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--- old/src/cpu/x86/vm/assembler_x86_32.cpp
+++ new/src/cpu/x86/vm/assembler_x86_32.cpp
1 1 /*
2 2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 21 * have any questions.
22 22 *
23 23 */
24 24
25 25 #include "incls/_precompiled.incl"
26 26 #include "incls/_assembler_x86_32.cpp.incl"
27 27
28 28 // Implementation of AddressLiteral
29 29
30 30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
31 31 _is_lval = false;
32 32 _target = target;
33 33 switch (rtype) {
34 34 case relocInfo::oop_type:
35 35 // Oops are a special case. Normally they would be their own section
36 36 // but in cases like icBuffer they are literals in the code stream that
37 37 // we don't have a section for. We use none so that we get a literal address
38 38 // which is always patchable.
39 39 break;
40 40 case relocInfo::external_word_type:
41 41 _rspec = external_word_Relocation::spec(target);
42 42 break;
43 43 case relocInfo::internal_word_type:
44 44 _rspec = internal_word_Relocation::spec(target);
45 45 break;
46 46 case relocInfo::opt_virtual_call_type:
47 47 _rspec = opt_virtual_call_Relocation::spec();
48 48 break;
49 49 case relocInfo::static_call_type:
50 50 _rspec = static_call_Relocation::spec();
51 51 break;
52 52 case relocInfo::runtime_call_type:
53 53 _rspec = runtime_call_Relocation::spec();
54 54 break;
55 55 case relocInfo::poll_type:
56 56 case relocInfo::poll_return_type:
57 57 _rspec = Relocation::spec_simple(rtype);
58 58 break;
59 59 case relocInfo::none:
60 60 break;
61 61 default:
62 62 ShouldNotReachHere();
63 63 break;
64 64 }
65 65 }
66 66
67 67 // Implementation of Address
68 68
69 69 Address Address::make_array(ArrayAddress adr) {
70 70 #ifdef _LP64
71 71 // Not implementable on 64bit machines
72 72 // Should have been handled higher up the call chain.
73 73 ShouldNotReachHere();
74 74 #else
75 75 AddressLiteral base = adr.base();
76 76 Address index = adr.index();
77 77 assert(index._disp == 0, "must not have disp"); // maybe it can?
78 78 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
79 79 array._rspec = base._rspec;
80 80 return array;
81 81 #endif // _LP64
82 82 }
83 83
84 84 #ifndef _LP64
85 85
86 86 // exceedingly dangerous constructor
87 87 Address::Address(address loc, RelocationHolder spec) {
88 88 _base = noreg;
89 89 _index = noreg;
90 90 _scale = no_scale;
91 91 _disp = (intptr_t) loc;
92 92 _rspec = spec;
93 93 }
94 94 #endif // _LP64
95 95
96 96 // Convert the raw encoding form into the form expected by the constructor for
97 97 // Address. An index of 4 (rsp) corresponds to having no index, so convert
98 98 // that to noreg for the Address constructor.
99 99 Address Address::make_raw(int base, int index, int scale, int disp) {
100 100 bool valid_index = index != rsp->encoding();
101 101 if (valid_index) {
102 102 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
103 103 return madr;
104 104 } else {
105 105 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
106 106 return madr;
107 107 }
108 108 }
109 109
110 110 // Implementation of Assembler
111 111
112 112 int AbstractAssembler::code_fill_byte() {
113 113 return (u_char)'\xF4'; // hlt
114 114 }
115 115
116 116 // make this go away someday
117 117 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
118 118 if (rtype == relocInfo::none)
119 119 emit_long(data);
120 120 else emit_data(data, Relocation::spec_simple(rtype), format);
121 121 }
122 122
123 123
124 124 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
125 125 assert(imm32_operand == 0, "default format must be imm32 in this file");
126 126 assert(inst_mark() != NULL, "must be inside InstructionMark");
127 127 if (rspec.type() != relocInfo::none) {
128 128 #ifdef ASSERT
129 129 check_relocation(rspec, format);
130 130 #endif
131 131 // Do not use AbstractAssembler::relocate, which is not intended for
132 132 // embedded words. Instead, relocate to the enclosing instruction.
133 133
134 134 // hack. call32 is too wide for mask so use disp32
135 135 if (format == call32_operand)
136 136 code_section()->relocate(inst_mark(), rspec, disp32_operand);
137 137 else
138 138 code_section()->relocate(inst_mark(), rspec, format);
139 139 }
140 140 emit_long(data);
141 141 }
142 142
143 143
144 144 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
145 145 assert(dst->has_byte_register(), "must have byte register");
146 146 assert(isByte(op1) && isByte(op2), "wrong opcode");
147 147 assert(isByte(imm8), "not a byte");
148 148 assert((op1 & 0x01) == 0, "should be 8bit operation");
149 149 emit_byte(op1);
150 150 emit_byte(op2 | dst->encoding());
151 151 emit_byte(imm8);
152 152 }
153 153
154 154
155 155 void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {
156 156 assert(isByte(op1) && isByte(op2), "wrong opcode");
157 157 assert((op1 & 0x01) == 1, "should be 32bit operation");
158 158 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
159 159 if (is8bit(imm32)) {
160 160 emit_byte(op1 | 0x02); // set sign bit
161 161 emit_byte(op2 | dst->encoding());
162 162 emit_byte(imm32 & 0xFF);
163 163 } else {
164 164 emit_byte(op1);
165 165 emit_byte(op2 | dst->encoding());
166 166 emit_long(imm32);
167 167 }
168 168 }
169 169
170 170 // immediate-to-memory forms
171 171 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) {
172 172 assert((op1 & 0x01) == 1, "should be 32bit operation");
173 173 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
174 174 if (is8bit(imm32)) {
175 175 emit_byte(op1 | 0x02); // set sign bit
176 176 emit_operand(rm,adr);
177 177 emit_byte(imm32 & 0xFF);
178 178 } else {
179 179 emit_byte(op1);
180 180 emit_operand(rm,adr);
181 181 emit_long(imm32);
182 182 }
183 183 }
184 184
185 185 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
186 186 assert(isByte(op1) && isByte(op2), "wrong opcode");
187 187 assert((op1 & 0x01) == 1, "should be 32bit operation");
188 188 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
189 189 InstructionMark im(this);
190 190 emit_byte(op1);
191 191 emit_byte(op2 | dst->encoding());
192 192 emit_data((int)obj, relocInfo::oop_type, 0);
193 193 }
194 194
195 195
196 196 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
197 197 assert(isByte(op1) && isByte(op2), "wrong opcode");
198 198 emit_byte(op1);
199 199 emit_byte(op2 | dst->encoding() << 3 | src->encoding());
200 200 }
201 201
202 202
203 203 void Assembler::emit_operand(Register reg,
204 204 Register base,
205 205 Register index,
206 206 Address::ScaleFactor scale,
207 207 int disp,
208 208 RelocationHolder const& rspec) {
209 209
210 210 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
211 211 if (base->is_valid()) {
212 212 if (index->is_valid()) {
213 213 assert(scale != Address::no_scale, "inconsistent address");
214 214 // [base + index*scale + disp]
215 215 if (disp == 0 && rtype == relocInfo::none && base != rbp) {
216 216 // [base + index*scale]
217 217 // [00 reg 100][ss index base]
218 218 assert(index != rsp, "illegal addressing mode");
219 219 emit_byte(0x04 | reg->encoding() << 3);
220 220 emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
221 221 } else if (is8bit(disp) && rtype == relocInfo::none) {
222 222 // [base + index*scale + imm8]
223 223 // [01 reg 100][ss index base] imm8
224 224 assert(index != rsp, "illegal addressing mode");
225 225 emit_byte(0x44 | reg->encoding() << 3);
226 226 emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
227 227 emit_byte(disp & 0xFF);
228 228 } else {
229 229 // [base + index*scale + imm32]
230 230 // [10 reg 100][ss index base] imm32
231 231 assert(index != rsp, "illegal addressing mode");
232 232 emit_byte(0x84 | reg->encoding() << 3);
233 233 emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
234 234 emit_data(disp, rspec, disp32_operand);
235 235 }
236 236 } else if (base == rsp) {
237 237 // [esp + disp]
238 238 if (disp == 0 && rtype == relocInfo::none) {
239 239 // [esp]
240 240 // [00 reg 100][00 100 100]
241 241 emit_byte(0x04 | reg->encoding() << 3);
242 242 emit_byte(0x24);
243 243 } else if (is8bit(disp) && rtype == relocInfo::none) {
244 244 // [esp + imm8]
245 245 // [01 reg 100][00 100 100] imm8
246 246 emit_byte(0x44 | reg->encoding() << 3);
247 247 emit_byte(0x24);
248 248 emit_byte(disp & 0xFF);
249 249 } else {
250 250 // [esp + imm32]
251 251 // [10 reg 100][00 100 100] imm32
252 252 emit_byte(0x84 | reg->encoding() << 3);
253 253 emit_byte(0x24);
254 254 emit_data(disp, rspec, disp32_operand);
255 255 }
256 256 } else {
257 257 // [base + disp]
258 258 assert(base != rsp, "illegal addressing mode");
259 259 if (disp == 0 && rtype == relocInfo::none && base != rbp) {
260 260 // [base]
261 261 // [00 reg base]
262 262 assert(base != rbp, "illegal addressing mode");
263 263 emit_byte(0x00 | reg->encoding() << 3 | base->encoding());
264 264 } else if (is8bit(disp) && rtype == relocInfo::none) {
265 265 // [base + imm8]
266 266 // [01 reg base] imm8
267 267 emit_byte(0x40 | reg->encoding() << 3 | base->encoding());
268 268 emit_byte(disp & 0xFF);
269 269 } else {
270 270 // [base + imm32]
271 271 // [10 reg base] imm32
272 272 emit_byte(0x80 | reg->encoding() << 3 | base->encoding());
273 273 emit_data(disp, rspec, disp32_operand);
274 274 }
275 275 }
276 276 } else {
277 277 if (index->is_valid()) {
278 278 assert(scale != Address::no_scale, "inconsistent address");
279 279 // [index*scale + disp]
280 280 // [00 reg 100][ss index 101] imm32
281 281 assert(index != rsp, "illegal addressing mode");
282 282 emit_byte(0x04 | reg->encoding() << 3);
283 283 emit_byte(scale << 6 | index->encoding() << 3 | 0x05);
284 284 emit_data(disp, rspec, disp32_operand);
285 285 } else {
286 286 // [disp]
287 287 // [00 reg 101] imm32
288 288 emit_byte(0x05 | reg->encoding() << 3);
289 289 emit_data(disp, rspec, disp32_operand);
290 290 }
291 291 }
292 292 }
293 293
294 294 // Secret local extension to Assembler::WhichOperand:
295 295 #define end_pc_operand (_WhichOperand_limit)
296 296
297 297 address Assembler::locate_operand(address inst, WhichOperand which) {
298 298 // Decode the given instruction, and return the address of
299 299 // an embedded 32-bit operand word.
300 300
301 301 // If "which" is disp32_operand, selects the displacement portion
302 302 // of an effective address specifier.
303 303 // If "which" is imm32_operand, selects the trailing immediate constant.
304 304 // If "which" is call32_operand, selects the displacement of a call or jump.
305 305 // Caller is responsible for ensuring that there is such an operand,
306 306 // and that it is 32 bits wide.
307 307
308 308 // If "which" is end_pc_operand, find the end of the instruction.
309 309
310 310 address ip = inst;
311 311
312 312 debug_only(bool has_imm32 = false);
313 313 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
314 314
315 315 again_after_prefix:
316 316 switch (0xFF & *ip++) {
317 317
318 318 // These convenience macros generate groups of "case" labels for the switch.
319 319 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
320 320 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
321 321 case (x)+4: case (x)+5: case (x)+6: case (x)+7
322 322 #define REP16(x) REP8((x)+0): \
323 323 case REP8((x)+8)
324 324
325 325 case CS_segment:
326 326 case SS_segment:
327 327 case DS_segment:
328 328 case ES_segment:
329 329 case FS_segment:
330 330 case GS_segment:
331 331 assert(ip == inst+1, "only one prefix allowed");
332 332 goto again_after_prefix;
333 333
334 334 case 0xFF: // pushl a; decl a; incl a; call a; jmp a
335 335 case 0x88: // movb a, r
336 336 case 0x89: // movl a, r
337 337 case 0x8A: // movb r, a
338 338 case 0x8B: // movl r, a
339 339 case 0x8F: // popl a
340 340 break;
341 341
342 342 case 0x68: // pushl #32(oop?)
343 343 if (which == end_pc_operand) return ip + 4;
344 344 assert(which == imm32_operand, "pushl has no disp32");
345 345 return ip; // not produced by emit_operand
346 346
347 347 case 0x66: // movw ... (size prefix)
348 348 switch (0xFF & *ip++) {
349 349 case 0x8B: // movw r, a
350 350 case 0x89: // movw a, r
351 351 break;
352 352 case 0xC7: // movw a, #16
353 353 tail_size = 2; // the imm16
354 354 break;
355 355 case 0x0F: // several SSE/SSE2 variants
356 356 ip--; // reparse the 0x0F
357 357 goto again_after_prefix;
358 358 default:
359 359 ShouldNotReachHere();
360 360 }
361 361 break;
362 362
363 363 case REP8(0xB8): // movl r, #32(oop?)
364 364 if (which == end_pc_operand) return ip + 4;
365 365 assert(which == imm32_operand || which == disp32_operand, "");
366 366 return ip;
367 367
368 368 case 0x69: // imul r, a, #32
369 369 case 0xC7: // movl a, #32(oop?)
370 370 tail_size = 4;
371 371 debug_only(has_imm32 = true); // has both kinds of operands!
372 372 break;
373 373
374 374 case 0x0F: // movx..., etc.
375 375 switch (0xFF & *ip++) {
376 376 case 0x12: // movlps
377 377 case 0x28: // movaps
378 378 case 0x2E: // ucomiss
379 379 case 0x2F: // comiss
380 380 case 0x54: // andps
381 381 case 0x55: // andnps
382 382 case 0x56: // orps
383 383 case 0x57: // xorps
384 384 case 0x6E: // movd
385 385 case 0x7E: // movd
386 386 case 0xAE: // ldmxcsr a
387 387 // amd side says it these have both operands but that doesn't
388 388 // appear to be true.
389 389 // debug_only(has_imm32 = true); // has both kinds of operands!
390 390 break;
391 391
392 392 case 0xAD: // shrd r, a, %cl
393 393 case 0xAF: // imul r, a
394 394 case 0xBE: // movsxb r, a
395 395 case 0xBF: // movsxw r, a
396 396 case 0xB6: // movzxb r, a
397 397 case 0xB7: // movzxw r, a
398 398 case REP16(0x40): // cmovl cc, r, a
399 399 case 0xB0: // cmpxchgb
400 400 case 0xB1: // cmpxchg
401 401 case 0xC1: // xaddl
402 402 case 0xC7: // cmpxchg8
403 403 case REP16(0x90): // setcc a
404 404 // fall out of the switch to decode the address
405 405 break;
406 406 case 0xAC: // shrd r, a, #8
407 407 tail_size = 1; // the imm8
408 408 break;
409 409 case REP16(0x80): // jcc rdisp32
410 410 if (which == end_pc_operand) return ip + 4;
411 411 assert(which == call32_operand, "jcc has no disp32 or imm32");
412 412 return ip;
413 413 default:
414 414 ShouldNotReachHere();
415 415 }
416 416 break;
417 417
418 418 case 0x81: // addl a, #32; addl r, #32
419 419 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
420 420 // in the case of cmpl, the imm32 might be an oop
421 421 tail_size = 4;
422 422 debug_only(has_imm32 = true); // has both kinds of operands!
423 423 break;
424 424
425 425 case 0x85: // test r/m, r
426 426 break;
427 427
428 428 case 0x83: // addl a, #8; addl r, #8
429 429 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
430 430 tail_size = 1;
431 431 break;
432 432
433 433 case 0x9B:
434 434 switch (0xFF & *ip++) {
435 435 case 0xD9: // fnstcw a
436 436 break;
437 437 default:
438 438 ShouldNotReachHere();
439 439 }
440 440 break;
441 441
442 442 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
443 443 case REP4(0x10): // adc...
444 444 case REP4(0x20): // and...
445 445 case REP4(0x30): // xor...
446 446 case REP4(0x08): // or...
447 447 case REP4(0x18): // sbb...
448 448 case REP4(0x28): // sub...
449 449 case REP4(0x38): // cmp...
450 450 case 0xF7: // mull a
451 451 case 0x8D: // leal r, a
452 452 case 0x87: // xchg r, a
453 453 break;
454 454
455 455 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
456 456 case 0xC6: // movb a, #8
457 457 case 0x80: // cmpb a, #8
458 458 case 0x6B: // imul r, a, #8
459 459 tail_size = 1; // the imm8
460 460 break;
461 461
462 462 case 0xE8: // call rdisp32
463 463 case 0xE9: // jmp rdisp32
464 464 if (which == end_pc_operand) return ip + 4;
465 465 assert(which == call32_operand, "call has no disp32 or imm32");
466 466 return ip;
467 467
468 468 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
469 469 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
470 470 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
471 471 case 0xDD: // fld_d a; fst_d a; fstp_d a
472 472 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
473 473 case 0xDF: // fild_d a; fistp_d a
474 474 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
475 475 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
476 476 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
477 477 break;
478 478
479 479 case 0xF3: // For SSE
480 480 case 0xF2: // For SSE2
481 481 ip++; ip++;
482 482 break;
483 483
484 484 default:
485 485 ShouldNotReachHere();
486 486
487 487 #undef REP8
488 488 #undef REP16
489 489 }
490 490
491 491 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
492 492 assert(which != imm32_operand || has_imm32, "instruction has no imm32 field");
493 493
494 494 // parse the output of emit_operand
495 495 int op2 = 0xFF & *ip++;
496 496 int base = op2 & 0x07;
497 497 int op3 = -1;
498 498 const int b100 = 4;
499 499 const int b101 = 5;
500 500 if (base == b100 && (op2 >> 6) != 3) {
501 501 op3 = 0xFF & *ip++;
502 502 base = op3 & 0x07; // refetch the base
503 503 }
504 504 // now ip points at the disp (if any)
505 505
506 506 switch (op2 >> 6) {
507 507 case 0:
508 508 // [00 reg 100][ss index base]
509 509 // [00 reg 100][00 100 rsp]
510 510 // [00 reg base]
511 511 // [00 reg 100][ss index 101][disp32]
512 512 // [00 reg 101] [disp32]
513 513
514 514 if (base == b101) {
515 515 if (which == disp32_operand)
516 516 return ip; // caller wants the disp32
517 517 ip += 4; // skip the disp32
518 518 }
519 519 break;
520 520
521 521 case 1:
522 522 // [01 reg 100][ss index base][disp8]
523 523 // [01 reg 100][00 100 rsp][disp8]
524 524 // [01 reg base] [disp8]
525 525 ip += 1; // skip the disp8
526 526 break;
527 527
528 528 case 2:
529 529 // [10 reg 100][ss index base][disp32]
530 530 // [10 reg 100][00 100 rsp][disp32]
531 531 // [10 reg base] [disp32]
532 532 if (which == disp32_operand)
533 533 return ip; // caller wants the disp32
534 534 ip += 4; // skip the disp32
535 535 break;
536 536
537 537 case 3:
538 538 // [11 reg base] (not a memory addressing mode)
539 539 break;
540 540 }
541 541
542 542 if (which == end_pc_operand) {
543 543 return ip + tail_size;
544 544 }
545 545
546 546 assert(which == imm32_operand, "instruction has only an imm32 field");
547 547 return ip;
548 548 }
549 549
550 550 address Assembler::locate_next_instruction(address inst) {
551 551 // Secretly share code with locate_operand:
552 552 return locate_operand(inst, end_pc_operand);
553 553 }
554 554
555 555
556 556 #ifdef ASSERT
557 557 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
558 558 address inst = inst_mark();
559 559 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
560 560 address opnd;
561 561
562 562 Relocation* r = rspec.reloc();
563 563 if (r->type() == relocInfo::none) {
564 564 return;
565 565 } else if (r->is_call() || format == call32_operand) {
566 566 // assert(format == imm32_operand, "cannot specify a nonzero format");
567 567 opnd = locate_operand(inst, call32_operand);
568 568 } else if (r->is_data()) {
569 569 assert(format == imm32_operand || format == disp32_operand, "format ok");
570 570 opnd = locate_operand(inst, (WhichOperand)format);
571 571 } else {
572 572 assert(format == imm32_operand, "cannot specify a format");
573 573 return;
574 574 }
575 575 assert(opnd == pc(), "must put operand where relocs can find it");
576 576 }
577 577 #endif
578 578
579 579
580 580
581 581 void Assembler::emit_operand(Register reg, Address adr) {
582 582 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
583 583 }
584 584
585 585
586 586 void Assembler::emit_farith(int b1, int b2, int i) {
587 587 assert(isByte(b1) && isByte(b2), "wrong opcode");
588 588 assert(0 <= i && i < 8, "illegal stack offset");
589 589 emit_byte(b1);
590 590 emit_byte(b2 + i);
591 591 }
592 592
593 593
594 594 void Assembler::pushad() {
595 595 emit_byte(0x60);
596 596 }
597 597
598 598 void Assembler::popad() {
599 599 emit_byte(0x61);
600 600 }
601 601
602 602 void Assembler::pushfd() {
603 603 emit_byte(0x9C);
604 604 }
605 605
606 606 void Assembler::popfd() {
607 607 emit_byte(0x9D);
608 608 }
609 609
610 610 void Assembler::pushl(int imm32) {
611 611 emit_byte(0x68);
612 612 emit_long(imm32);
613 613 }
614 614
615 615 #ifndef _LP64
616 616 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
617 617 InstructionMark im(this);
618 618 emit_byte(0x68);
619 619 emit_data(imm32, rspec, 0);
620 620 }
621 621 #endif // _LP64
622 622
623 623 void Assembler::pushl(Register src) {
624 624 emit_byte(0x50 | src->encoding());
625 625 }
626 626
627 627
628 628 void Assembler::pushl(Address src) {
629 629 InstructionMark im(this);
630 630 emit_byte(0xFF);
631 631 emit_operand(rsi, src);
632 632 }
633 633
634 634 void Assembler::popl(Register dst) {
635 635 emit_byte(0x58 | dst->encoding());
636 636 }
637 637
638 638
639 639 void Assembler::popl(Address dst) {
640 640 InstructionMark im(this);
641 641 emit_byte(0x8F);
642 642 emit_operand(rax, dst);
643 643 }
644 644
645 645
646 646 void Assembler::prefix(Prefix p) {
647 647 a_byte(p);
648 648 }
649 649
650 650
651 651 void Assembler::movb(Register dst, Address src) {
652 652 assert(dst->has_byte_register(), "must have byte register");
653 653 InstructionMark im(this);
654 654 emit_byte(0x8A);
655 655 emit_operand(dst, src);
656 656 }
657 657
658 658
659 659 void Assembler::movb(Address dst, int imm8) {
660 660 InstructionMark im(this);
661 661 emit_byte(0xC6);
662 662 emit_operand(rax, dst);
663 663 emit_byte(imm8);
664 664 }
665 665
666 666
667 667 void Assembler::movb(Address dst, Register src) {
668 668 assert(src->has_byte_register(), "must have byte register");
669 669 InstructionMark im(this);
670 670 emit_byte(0x88);
671 671 emit_operand(src, dst);
672 672 }
673 673
674 674
675 675 void Assembler::movw(Address dst, int imm16) {
676 676 InstructionMark im(this);
677 677
678 678 emit_byte(0x66); // switch to 16-bit mode
679 679 emit_byte(0xC7);
680 680 emit_operand(rax, dst);
681 681 emit_word(imm16);
682 682 }
683 683
684 684
685 685 void Assembler::movw(Register dst, Address src) {
686 686 InstructionMark im(this);
687 687 emit_byte(0x66);
688 688 emit_byte(0x8B);
689 689 emit_operand(dst, src);
690 690 }
691 691
692 692
693 693 void Assembler::movw(Address dst, Register src) {
694 694 InstructionMark im(this);
695 695 emit_byte(0x66);
696 696 emit_byte(0x89);
697 697 emit_operand(src, dst);
698 698 }
699 699
700 700
701 701 void Assembler::movl(Register dst, int imm32) {
702 702 emit_byte(0xB8 | dst->encoding());
703 703 emit_long(imm32);
704 704 }
705 705
706 706 #ifndef _LP64
707 707 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
708 708
709 709 InstructionMark im(this);
710 710 emit_byte(0xB8 | dst->encoding());
711 711 emit_data((int)imm32, rspec, 0);
712 712 }
713 713 #endif // _LP64
714 714
715 715 void Assembler::movl(Register dst, Register src) {
716 716 emit_byte(0x8B);
717 717 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
718 718 }
719 719
720 720
721 721 void Assembler::movl(Register dst, Address src) {
722 722 InstructionMark im(this);
723 723 emit_byte(0x8B);
724 724 emit_operand(dst, src);
725 725 }
726 726
727 727
728 728 void Assembler::movl(Address dst, int imm32) {
729 729 InstructionMark im(this);
730 730 emit_byte(0xC7);
731 731 emit_operand(rax, dst);
732 732 emit_long(imm32);
733 733 }
734 734
735 735 #ifndef _LP64
736 736 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
737 737 InstructionMark im(this);
738 738 emit_byte(0xC7);
739 739 emit_operand(rax, dst);
740 740 emit_data((int)imm32, rspec, 0);
741 741 }
742 742 #endif // _LP64
743 743
744 744 void Assembler::movl(Address dst, Register src) {
745 745 InstructionMark im(this);
746 746 emit_byte(0x89);
747 747 emit_operand(src, dst);
748 748 }
749 749
750 750 void Assembler::movsxb(Register dst, Address src) {
751 751 InstructionMark im(this);
752 752 emit_byte(0x0F);
753 753 emit_byte(0xBE);
754 754 emit_operand(dst, src);
755 755 }
756 756
757 757 void Assembler::movsxb(Register dst, Register src) {
758 758 assert(src->has_byte_register(), "must have byte register");
759 759 emit_byte(0x0F);
760 760 emit_byte(0xBE);
761 761 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
762 762 }
763 763
764 764
765 765 void Assembler::movsxw(Register dst, Address src) {
766 766 InstructionMark im(this);
767 767 emit_byte(0x0F);
768 768 emit_byte(0xBF);
769 769 emit_operand(dst, src);
770 770 }
771 771
772 772
773 773 void Assembler::movsxw(Register dst, Register src) {
774 774 emit_byte(0x0F);
775 775 emit_byte(0xBF);
776 776 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
777 777 }
778 778
779 779
780 780 void Assembler::movzxb(Register dst, Address src) {
781 781 InstructionMark im(this);
782 782 emit_byte(0x0F);
783 783 emit_byte(0xB6);
784 784 emit_operand(dst, src);
785 785 }
786 786
787 787
788 788 void Assembler::movzxb(Register dst, Register src) {
789 789 assert(src->has_byte_register(), "must have byte register");
790 790 emit_byte(0x0F);
791 791 emit_byte(0xB6);
792 792 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
793 793 }
794 794
795 795
796 796 void Assembler::movzxw(Register dst, Address src) {
797 797 InstructionMark im(this);
798 798 emit_byte(0x0F);
799 799 emit_byte(0xB7);
800 800 emit_operand(dst, src);
801 801 }
802 802
803 803
804 804 void Assembler::movzxw(Register dst, Register src) {
805 805 emit_byte(0x0F);
806 806 emit_byte(0xB7);
807 807 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
808 808 }
809 809
810 810
811 811 void Assembler::cmovl(Condition cc, Register dst, Register src) {
812 812 guarantee(VM_Version::supports_cmov(), "illegal instruction");
813 813 emit_byte(0x0F);
814 814 emit_byte(0x40 | cc);
815 815 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
816 816 }
817 817
818 818
819 819 void Assembler::cmovl(Condition cc, Register dst, Address src) {
820 820 guarantee(VM_Version::supports_cmov(), "illegal instruction");
821 821 // The code below seems to be wrong - however the manual is inconclusive
822 822 // do not use for now (remember to enable all callers when fixing this)
823 823 Unimplemented();
824 824 // wrong bytes?
825 825 InstructionMark im(this);
826 826 emit_byte(0x0F);
827 827 emit_byte(0x40 | cc);
828 828 emit_operand(dst, src);
829 829 }
830 830
831 831
832 832 void Assembler::prefetcht0(Address src) {
833 833 assert(VM_Version::supports_sse(), "must support");
834 834 InstructionMark im(this);
835 835 emit_byte(0x0F);
836 836 emit_byte(0x18);
837 837 emit_operand(rcx, src); // 1, src
838 838 }
839 839
840 840
841 841 void Assembler::prefetcht1(Address src) {
842 842 assert(VM_Version::supports_sse(), "must support");
843 843 InstructionMark im(this);
844 844 emit_byte(0x0F);
845 845 emit_byte(0x18);
846 846 emit_operand(rdx, src); // 2, src
847 847 }
848 848
849 849
850 850 void Assembler::prefetcht2(Address src) {
851 851 assert(VM_Version::supports_sse(), "must support");
852 852 InstructionMark im(this);
853 853 emit_byte(0x0F);
854 854 emit_byte(0x18);
855 855 emit_operand(rbx, src); // 3, src
856 856 }
857 857
858 858
859 859 void Assembler::prefetchnta(Address src) {
860 860 assert(VM_Version::supports_sse2(), "must support");
861 861 InstructionMark im(this);
862 862 emit_byte(0x0F);
863 863 emit_byte(0x18);
864 864 emit_operand(rax, src); // 0, src
865 865 }
866 866
867 867
868 868 void Assembler::prefetchw(Address src) {
869 869 assert(VM_Version::supports_3dnow(), "must support");
870 870 InstructionMark im(this);
871 871 emit_byte(0x0F);
872 872 emit_byte(0x0D);
873 873 emit_operand(rcx, src); // 1, src
874 874 }
875 875
876 876
877 877 void Assembler::prefetchr(Address src) {
878 878 assert(VM_Version::supports_3dnow(), "must support");
879 879 InstructionMark im(this);
880 880 emit_byte(0x0F);
881 881 emit_byte(0x0D);
882 882 emit_operand(rax, src); // 0, src
883 883 }
884 884
885 885
886 886 void Assembler::adcl(Register dst, int imm32) {
887 887 emit_arith(0x81, 0xD0, dst, imm32);
888 888 }
889 889
890 890
891 891 void Assembler::adcl(Register dst, Address src) {
892 892 InstructionMark im(this);
893 893 emit_byte(0x13);
894 894 emit_operand(dst, src);
895 895 }
896 896
897 897
898 898 void Assembler::adcl(Register dst, Register src) {
899 899 emit_arith(0x13, 0xC0, dst, src);
900 900 }
901 901
902 902
903 903 void Assembler::addl(Address dst, int imm32) {
904 904 InstructionMark im(this);
905 905 emit_arith_operand(0x81,rax,dst,imm32);
906 906 }
907 907
908 908
909 909 void Assembler::addl(Address dst, Register src) {
910 910 InstructionMark im(this);
911 911 emit_byte(0x01);
912 912 emit_operand(src, dst);
913 913 }
914 914
915 915
916 916 void Assembler::addl(Register dst, int imm32) {
917 917 emit_arith(0x81, 0xC0, dst, imm32);
918 918 }
919 919
920 920
921 921 void Assembler::addl(Register dst, Address src) {
922 922 InstructionMark im(this);
923 923 emit_byte(0x03);
924 924 emit_operand(dst, src);
925 925 }
926 926
927 927
928 928 void Assembler::addl(Register dst, Register src) {
929 929 emit_arith(0x03, 0xC0, dst, src);
930 930 }
931 931
932 932
933 933 void Assembler::andl(Register dst, int imm32) {
934 934 emit_arith(0x81, 0xE0, dst, imm32);
935 935 }
936 936
937 937
938 938 void Assembler::andl(Register dst, Address src) {
939 939 InstructionMark im(this);
940 940 emit_byte(0x23);
941 941 emit_operand(dst, src);
942 942 }
943 943
944 944
945 945 void Assembler::andl(Register dst, Register src) {
946 946 emit_arith(0x23, 0xC0, dst, src);
947 947 }
948 948
949 949
950 950 void Assembler::cmpb(Address dst, int imm8) {
951 951 InstructionMark im(this);
952 952 emit_byte(0x80);
953 953 emit_operand(rdi, dst);
954 954 emit_byte(imm8);
955 955 }
956 956
957 957 void Assembler::cmpw(Address dst, int imm16) {
958 958 InstructionMark im(this);
959 959 emit_byte(0x66);
960 960 emit_byte(0x81);
961 961 emit_operand(rdi, dst);
962 962 emit_word(imm16);
963 963 }
964 964
965 965 void Assembler::cmpl(Address dst, int imm32) {
966 966 InstructionMark im(this);
967 967 emit_byte(0x81);
968 968 emit_operand(rdi, dst);
969 969 emit_long(imm32);
970 970 }
971 971
972 972 #ifndef _LP64
973 973 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
974 974 InstructionMark im(this);
975 975 emit_byte(0x81);
976 976 emit_byte(0xF8 | src1->encoding());
977 977 emit_data(imm32, rspec, 0);
978 978 }
979 979
980 980 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
981 981 InstructionMark im(this);
982 982 emit_byte(0x81);
983 983 emit_operand(rdi, src1);
984 984 emit_data(imm32, rspec, 0);
985 985 }
986 986 #endif // _LP64
987 987
988 988
989 989 void Assembler::cmpl(Register dst, int imm32) {
990 990 emit_arith(0x81, 0xF8, dst, imm32);
991 991 }
992 992
993 993
994 994 void Assembler::cmpl(Register dst, Register src) {
995 995 emit_arith(0x3B, 0xC0, dst, src);
996 996 }
997 997
998 998
999 999 void Assembler::cmpl(Register dst, Address src) {
1000 1000 InstructionMark im(this);
1001 1001 emit_byte(0x3B);
1002 1002 emit_operand(dst, src);
1003 1003 }
1004 1004
1005 1005
1006 1006 void Assembler::decl(Register dst) {
1007 1007 // Don't use it directly. Use MacroAssembler::decrement() instead.
1008 1008 emit_byte(0x48 | dst->encoding());
1009 1009 }
1010 1010
1011 1011
1012 1012 void Assembler::decl(Address dst) {
1013 1013 // Don't use it directly. Use MacroAssembler::decrement() instead.
1014 1014 InstructionMark im(this);
1015 1015 emit_byte(0xFF);
1016 1016 emit_operand(rcx, dst);
1017 1017 }
1018 1018
1019 1019
1020 1020 void Assembler::idivl(Register src) {
1021 1021 emit_byte(0xF7);
1022 1022 emit_byte(0xF8 | src->encoding());
1023 1023 }
1024 1024
1025 1025
1026 1026 void Assembler::cdql() {
1027 1027 emit_byte(0x99);
1028 1028 }
1029 1029
1030 1030
1031 1031 void Assembler::imull(Register dst, Register src) {
1032 1032 emit_byte(0x0F);
1033 1033 emit_byte(0xAF);
1034 1034 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
1035 1035 }
1036 1036
1037 1037
1038 1038 void Assembler::imull(Register dst, Register src, int value) {
1039 1039 if (is8bit(value)) {
1040 1040 emit_byte(0x6B);
1041 1041 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
1042 1042 emit_byte(value);
1043 1043 } else {
1044 1044 emit_byte(0x69);
1045 1045 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
1046 1046 emit_long(value);
1047 1047 }
1048 1048 }
1049 1049
1050 1050
1051 1051 void Assembler::incl(Register dst) {
1052 1052 // Don't use it directly. Use MacroAssembler::increment() instead.
1053 1053 emit_byte(0x40 | dst->encoding());
1054 1054 }
1055 1055
1056 1056
1057 1057 void Assembler::incl(Address dst) {
1058 1058 // Don't use it directly. Use MacroAssembler::increment() instead.
1059 1059 InstructionMark im(this);
1060 1060 emit_byte(0xFF);
1061 1061 emit_operand(rax, dst);
1062 1062 }
1063 1063
1064 1064
1065 1065 void Assembler::leal(Register dst, Address src) {
1066 1066 InstructionMark im(this);
1067 1067 emit_byte(0x8D);
1068 1068 emit_operand(dst, src);
1069 1069 }
1070 1070
1071 1071 void Assembler::mull(Address src) {
1072 1072 InstructionMark im(this);
1073 1073 emit_byte(0xF7);
1074 1074 emit_operand(rsp, src);
1075 1075 }
1076 1076
1077 1077
1078 1078 void Assembler::mull(Register src) {
1079 1079 emit_byte(0xF7);
1080 1080 emit_byte(0xE0 | src->encoding());
1081 1081 }
1082 1082
1083 1083
1084 1084 void Assembler::negl(Register dst) {
1085 1085 emit_byte(0xF7);
1086 1086 emit_byte(0xD8 | dst->encoding());
1087 1087 }
1088 1088
1089 1089
1090 1090 void Assembler::notl(Register dst) {
1091 1091 emit_byte(0xF7);
1092 1092 emit_byte(0xD0 | dst->encoding());
1093 1093 }
1094 1094
1095 1095
1096 1096 void Assembler::orl(Address dst, int imm32) {
1097 1097 InstructionMark im(this);
1098 1098 emit_byte(0x81);
1099 1099 emit_operand(rcx, dst);
1100 1100 emit_long(imm32);
1101 1101 }
1102 1102
1103 1103 void Assembler::orl(Register dst, int imm32) {
1104 1104 emit_arith(0x81, 0xC8, dst, imm32);
1105 1105 }
1106 1106
1107 1107
1108 1108 void Assembler::orl(Register dst, Address src) {
1109 1109 InstructionMark im(this);
1110 1110 emit_byte(0x0B);
1111 1111 emit_operand(dst, src);
1112 1112 }
1113 1113
1114 1114
1115 1115 void Assembler::orl(Register dst, Register src) {
1116 1116 emit_arith(0x0B, 0xC0, dst, src);
1117 1117 }
1118 1118
1119 1119
1120 1120 void Assembler::rcll(Register dst, int imm8) {
1121 1121 assert(isShiftCount(imm8), "illegal shift count");
1122 1122 if (imm8 == 1) {
1123 1123 emit_byte(0xD1);
1124 1124 emit_byte(0xD0 | dst->encoding());
1125 1125 } else {
1126 1126 emit_byte(0xC1);
1127 1127 emit_byte(0xD0 | dst->encoding());
1128 1128 emit_byte(imm8);
1129 1129 }
1130 1130 }
1131 1131
1132 1132
1133 1133 void Assembler::sarl(Register dst, int imm8) {
1134 1134 assert(isShiftCount(imm8), "illegal shift count");
1135 1135 if (imm8 == 1) {
1136 1136 emit_byte(0xD1);
1137 1137 emit_byte(0xF8 | dst->encoding());
1138 1138 } else {
1139 1139 emit_byte(0xC1);
1140 1140 emit_byte(0xF8 | dst->encoding());
1141 1141 emit_byte(imm8);
1142 1142 }
1143 1143 }
1144 1144
1145 1145
1146 1146 void Assembler::sarl(Register dst) {
1147 1147 emit_byte(0xD3);
1148 1148 emit_byte(0xF8 | dst->encoding());
1149 1149 }
1150 1150
1151 1151
1152 1152 void Assembler::sbbl(Address dst, int imm32) {
1153 1153 InstructionMark im(this);
1154 1154 emit_arith_operand(0x81,rbx,dst,imm32);
1155 1155 }
1156 1156
1157 1157
1158 1158 void Assembler::sbbl(Register dst, int imm32) {
1159 1159 emit_arith(0x81, 0xD8, dst, imm32);
1160 1160 }
1161 1161
1162 1162
1163 1163 void Assembler::sbbl(Register dst, Address src) {
1164 1164 InstructionMark im(this);
1165 1165 emit_byte(0x1B);
1166 1166 emit_operand(dst, src);
1167 1167 }
1168 1168
1169 1169
1170 1170 void Assembler::sbbl(Register dst, Register src) {
1171 1171 emit_arith(0x1B, 0xC0, dst, src);
1172 1172 }
1173 1173
1174 1174
1175 1175 void Assembler::shldl(Register dst, Register src) {
1176 1176 emit_byte(0x0F);
1177 1177 emit_byte(0xA5);
1178 1178 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
1179 1179 }
1180 1180
1181 1181
1182 1182 void Assembler::shll(Register dst, int imm8) {
1183 1183 assert(isShiftCount(imm8), "illegal shift count");
1184 1184 if (imm8 == 1 ) {
1185 1185 emit_byte(0xD1);
1186 1186 emit_byte(0xE0 | dst->encoding());
1187 1187 } else {
1188 1188 emit_byte(0xC1);
1189 1189 emit_byte(0xE0 | dst->encoding());
1190 1190 emit_byte(imm8);
1191 1191 }
1192 1192 }
1193 1193
1194 1194
1195 1195 void Assembler::shll(Register dst) {
1196 1196 emit_byte(0xD3);
1197 1197 emit_byte(0xE0 | dst->encoding());
1198 1198 }
1199 1199
1200 1200
1201 1201 void Assembler::shrdl(Register dst, Register src) {
1202 1202 emit_byte(0x0F);
1203 1203 emit_byte(0xAD);
1204 1204 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
1205 1205 }
1206 1206
1207 1207
1208 1208 void Assembler::shrl(Register dst, int imm8) {
1209 1209 assert(isShiftCount(imm8), "illegal shift count");
1210 1210 emit_byte(0xC1);
1211 1211 emit_byte(0xE8 | dst->encoding());
1212 1212 emit_byte(imm8);
1213 1213 }
1214 1214
1215 1215
1216 1216 void Assembler::shrl(Register dst) {
1217 1217 emit_byte(0xD3);
1218 1218 emit_byte(0xE8 | dst->encoding());
1219 1219 }
1220 1220
1221 1221
1222 1222 void Assembler::subl(Address dst, int imm32) {
1223 1223 if (is8bit(imm32)) {
1224 1224 InstructionMark im(this);
1225 1225 emit_byte(0x83);
1226 1226 emit_operand(rbp, dst);
1227 1227 emit_byte(imm32 & 0xFF);
1228 1228 } else {
1229 1229 InstructionMark im(this);
1230 1230 emit_byte(0x81);
1231 1231 emit_operand(rbp, dst);
1232 1232 emit_long(imm32);
1233 1233 }
1234 1234 }
1235 1235
1236 1236
1237 1237 void Assembler::subl(Register dst, int imm32) {
1238 1238 emit_arith(0x81, 0xE8, dst, imm32);
1239 1239 }
1240 1240
1241 1241
1242 1242 void Assembler::subl(Address dst, Register src) {
1243 1243 InstructionMark im(this);
1244 1244 emit_byte(0x29);
1245 1245 emit_operand(src, dst);
1246 1246 }
1247 1247
1248 1248
1249 1249 void Assembler::subl(Register dst, Address src) {
1250 1250 InstructionMark im(this);
1251 1251 emit_byte(0x2B);
1252 1252 emit_operand(dst, src);
1253 1253 }
1254 1254
1255 1255
1256 1256 void Assembler::subl(Register dst, Register src) {
1257 1257 emit_arith(0x2B, 0xC0, dst, src);
1258 1258 }
1259 1259
1260 1260
1261 1261 void Assembler::testb(Register dst, int imm8) {
1262 1262 assert(dst->has_byte_register(), "must have byte register");
1263 1263 emit_arith_b(0xF6, 0xC0, dst, imm8);
1264 1264 }
1265 1265
1266 1266
1267 1267 void Assembler::testl(Register dst, int imm32) {
1268 1268 // not using emit_arith because test
1269 1269 // doesn't support sign-extension of
1270 1270 // 8bit operands
1271 1271 if (dst->encoding() == 0) {
1272 1272 emit_byte(0xA9);
1273 1273 } else {
1274 1274 emit_byte(0xF7);
1275 1275 emit_byte(0xC0 | dst->encoding());
1276 1276 }
1277 1277 emit_long(imm32);
1278 1278 }
1279 1279
1280 1280
1281 1281 void Assembler::testl(Register dst, Register src) {
1282 1282 emit_arith(0x85, 0xC0, dst, src);
1283 1283 }
1284 1284
1285 1285 void Assembler::testl(Register dst, Address src) {
1286 1286 InstructionMark im(this);
1287 1287 emit_byte(0x85);
1288 1288 emit_operand(dst, src);
1289 1289 }
1290 1290
1291 1291 void Assembler::xaddl(Address dst, Register src) {
1292 1292 InstructionMark im(this);
1293 1293 emit_byte(0x0F);
1294 1294 emit_byte(0xC1);
1295 1295 emit_operand(src, dst);
1296 1296 }
1297 1297
1298 1298 void Assembler::xorl(Register dst, int imm32) {
1299 1299 emit_arith(0x81, 0xF0, dst, imm32);
1300 1300 }
1301 1301
1302 1302
1303 1303 void Assembler::xorl(Register dst, Address src) {
1304 1304 InstructionMark im(this);
1305 1305 emit_byte(0x33);
1306 1306 emit_operand(dst, src);
1307 1307 }
1308 1308
1309 1309
1310 1310 void Assembler::xorl(Register dst, Register src) {
1311 1311 emit_arith(0x33, 0xC0, dst, src);
1312 1312 }
1313 1313
1314 1314
1315 1315 void Assembler::bswap(Register reg) {
1316 1316 emit_byte(0x0F);
1317 1317 emit_byte(0xC8 | reg->encoding());
1318 1318 }
1319 1319
1320 1320
1321 1321 void Assembler::lock() {
1322 1322 if (Atomics & 1) {
1323 1323 // Emit either nothing, a NOP, or a NOP: prefix
1324 1324 emit_byte(0x90) ;
1325 1325 } else {
1326 1326 emit_byte(0xF0);
1327 1327 }
1328 1328 }
1329 1329
1330 1330
1331 1331 void Assembler::xchg(Register reg, Address adr) {
1332 1332 InstructionMark im(this);
1333 1333 emit_byte(0x87);
1334 1334 emit_operand(reg, adr);
1335 1335 }
1336 1336
1337 1337
1338 1338 void Assembler::xchgl(Register dst, Register src) {
1339 1339 emit_byte(0x87);
1340 1340 emit_byte(0xc0 | dst->encoding() << 3 | src->encoding());
1341 1341 }
1342 1342
1343 1343
1344 1344 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1345 1345 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1346 1346 // The ZF is set if the compared values were equal, and cleared otherwise.
1347 1347 void Assembler::cmpxchg(Register reg, Address adr) {
1348 1348 if (Atomics & 2) {
1349 1349 // caveat: no instructionmark, so this isn't relocatable.
1350 1350 // Emit a synthetic, non-atomic, CAS equivalent.
1351 1351 // Beware. The synthetic form sets all ICCs, not just ZF.
1352 1352 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1353 1353 cmpl (rax, adr) ;
1354 1354 movl (rax, adr) ;
1355 1355 if (reg != rax) {
1356 1356 Label L ;
1357 1357 jcc (Assembler::notEqual, L) ;
1358 1358 movl (adr, reg) ;
1359 1359 bind (L) ;
1360 1360 }
1361 1361 } else {
1362 1362 InstructionMark im(this);
1363 1363 emit_byte(0x0F);
1364 1364 emit_byte(0xB1);
1365 1365 emit_operand(reg, adr);
1366 1366 }
1367 1367 }
1368 1368
1369 1369 // The 64-bit cmpxchg compares the value at adr with the contents of rdx:rax,
1370 1370 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
1371 1371 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
1372 1372 void Assembler::cmpxchg8(Address adr) {
1373 1373 InstructionMark im(this);
1374 1374 emit_byte(0x0F);
1375 1375 emit_byte(0xc7);
1376 1376 emit_operand(rcx, adr);
1377 1377 }
1378 1378
1379 1379 void Assembler::hlt() {
1380 1380 emit_byte(0xF4);
1381 1381 }
1382 1382
1383 1383
1384 1384 void Assembler::addr_nop_4() {
1385 1385 // 4 bytes: NOP DWORD PTR [EAX+0]
1386 1386 emit_byte(0x0F);
1387 1387 emit_byte(0x1F);
1388 1388 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1389 1389 emit_byte(0); // 8-bits offset (1 byte)
1390 1390 }
1391 1391
1392 1392 void Assembler::addr_nop_5() {
1393 1393 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1394 1394 emit_byte(0x0F);
1395 1395 emit_byte(0x1F);
1396 1396 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1397 1397 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1398 1398 emit_byte(0); // 8-bits offset (1 byte)
1399 1399 }
1400 1400
1401 1401 void Assembler::addr_nop_7() {
1402 1402 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1403 1403 emit_byte(0x0F);
1404 1404 emit_byte(0x1F);
1405 1405 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1406 1406 emit_long(0); // 32-bits offset (4 bytes)
1407 1407 }
1408 1408
1409 1409 void Assembler::addr_nop_8() {
1410 1410 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1411 1411 emit_byte(0x0F);
1412 1412 emit_byte(0x1F);
1413 1413 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1414 1414 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1415 1415 emit_long(0); // 32-bits offset (4 bytes)
1416 1416 }
1417 1417
1418 1418 void Assembler::nop(int i) {
1419 1419 assert(i > 0, " ");
1420 1420 if (UseAddressNop && VM_Version::is_intel()) {
1421 1421 //
1422 1422 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1423 1423 // 1: 0x90
1424 1424 // 2: 0x66 0x90
1425 1425 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1426 1426 // 4: 0x0F 0x1F 0x40 0x00
1427 1427 // 5: 0x0F 0x1F 0x44 0x00 0x00
1428 1428 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1429 1429 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1430 1430 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1431 1431 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1432 1432 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1433 1433 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1434 1434
1435 1435 // The rest coding is Intel specific - don't use consecutive address nops
1436 1436
1437 1437 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1438 1438 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1439 1439 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1440 1440 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1441 1441
1442 1442 while(i >= 15) {
1443 1443 // For Intel don't generate consecutive addess nops (mix with regular nops)
1444 1444 i -= 15;
1445 1445 emit_byte(0x66); // size prefix
1446 1446 emit_byte(0x66); // size prefix
1447 1447 emit_byte(0x66); // size prefix
1448 1448 addr_nop_8();
1449 1449 emit_byte(0x66); // size prefix
1450 1450 emit_byte(0x66); // size prefix
1451 1451 emit_byte(0x66); // size prefix
1452 1452 emit_byte(0x90); // nop
1453 1453 }
1454 1454 switch (i) {
1455 1455 case 14:
1456 1456 emit_byte(0x66); // size prefix
1457 1457 case 13:
1458 1458 emit_byte(0x66); // size prefix
1459 1459 case 12:
1460 1460 addr_nop_8();
1461 1461 emit_byte(0x66); // size prefix
1462 1462 emit_byte(0x66); // size prefix
1463 1463 emit_byte(0x66); // size prefix
1464 1464 emit_byte(0x90); // nop
1465 1465 break;
1466 1466 case 11:
1467 1467 emit_byte(0x66); // size prefix
1468 1468 case 10:
1469 1469 emit_byte(0x66); // size prefix
1470 1470 case 9:
1471 1471 emit_byte(0x66); // size prefix
1472 1472 case 8:
1473 1473 addr_nop_8();
1474 1474 break;
1475 1475 case 7:
1476 1476 addr_nop_7();
1477 1477 break;
1478 1478 case 6:
1479 1479 emit_byte(0x66); // size prefix
1480 1480 case 5:
1481 1481 addr_nop_5();
1482 1482 break;
1483 1483 case 4:
1484 1484 addr_nop_4();
1485 1485 break;
1486 1486 case 3:
1487 1487 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
1488 1488 emit_byte(0x66); // size prefix
1489 1489 case 2:
1490 1490 emit_byte(0x66); // size prefix
1491 1491 case 1:
1492 1492 emit_byte(0x90); // nop
1493 1493 break;
1494 1494 default:
1495 1495 assert(i == 0, " ");
1496 1496 }
1497 1497 return;
1498 1498 }
1499 1499 if (UseAddressNop && VM_Version::is_amd()) {
1500 1500 //
1501 1501 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
1502 1502 // 1: 0x90
1503 1503 // 2: 0x66 0x90
1504 1504 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1505 1505 // 4: 0x0F 0x1F 0x40 0x00
1506 1506 // 5: 0x0F 0x1F 0x44 0x00 0x00
1507 1507 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1508 1508 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1509 1509 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1510 1510 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1511 1511 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1512 1512 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1513 1513
1514 1514 // The rest coding is AMD specific - use consecutive address nops
1515 1515
1516 1516 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
1517 1517 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
1518 1518 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1519 1519 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1520 1520 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1521 1521 // Size prefixes (0x66) are added for larger sizes
1522 1522
1523 1523 while(i >= 22) {
1524 1524 i -= 11;
1525 1525 emit_byte(0x66); // size prefix
1526 1526 emit_byte(0x66); // size prefix
1527 1527 emit_byte(0x66); // size prefix
1528 1528 addr_nop_8();
1529 1529 }
1530 1530 // Generate first nop for size between 21-12
1531 1531 switch (i) {
1532 1532 case 21:
1533 1533 i -= 1;
1534 1534 emit_byte(0x66); // size prefix
1535 1535 case 20:
1536 1536 case 19:
1537 1537 i -= 1;
1538 1538 emit_byte(0x66); // size prefix
1539 1539 case 18:
1540 1540 case 17:
1541 1541 i -= 1;
1542 1542 emit_byte(0x66); // size prefix
1543 1543 case 16:
1544 1544 case 15:
1545 1545 i -= 8;
1546 1546 addr_nop_8();
1547 1547 break;
1548 1548 case 14:
1549 1549 case 13:
1550 1550 i -= 7;
1551 1551 addr_nop_7();
1552 1552 break;
1553 1553 case 12:
1554 1554 i -= 6;
1555 1555 emit_byte(0x66); // size prefix
1556 1556 addr_nop_5();
1557 1557 break;
1558 1558 default:
1559 1559 assert(i < 12, " ");
1560 1560 }
1561 1561
1562 1562 // Generate second nop for size between 11-1
1563 1563 switch (i) {
1564 1564 case 11:
1565 1565 emit_byte(0x66); // size prefix
1566 1566 case 10:
1567 1567 emit_byte(0x66); // size prefix
1568 1568 case 9:
1569 1569 emit_byte(0x66); // size prefix
1570 1570 case 8:
1571 1571 addr_nop_8();
1572 1572 break;
1573 1573 case 7:
1574 1574 addr_nop_7();
1575 1575 break;
1576 1576 case 6:
1577 1577 emit_byte(0x66); // size prefix
1578 1578 case 5:
1579 1579 addr_nop_5();
1580 1580 break;
1581 1581 case 4:
1582 1582 addr_nop_4();
1583 1583 break;
1584 1584 case 3:
1585 1585 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
1586 1586 emit_byte(0x66); // size prefix
1587 1587 case 2:
1588 1588 emit_byte(0x66); // size prefix
1589 1589 case 1:
1590 1590 emit_byte(0x90); // nop
1591 1591 break;
1592 1592 default:
1593 1593 assert(i == 0, " ");
1594 1594 }
1595 1595 return;
1596 1596 }
1597 1597
1598 1598 // Using nops with size prefixes "0x66 0x90".
1599 1599 // From AMD Optimization Guide:
1600 1600 // 1: 0x90
1601 1601 // 2: 0x66 0x90
1602 1602 // 3: 0x66 0x66 0x90
1603 1603 // 4: 0x66 0x66 0x66 0x90
1604 1604 // 5: 0x66 0x66 0x90 0x66 0x90
1605 1605 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
1606 1606 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
1607 1607 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
1608 1608 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
1609 1609 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
1610 1610 //
1611 1611 while(i > 12) {
1612 1612 i -= 4;
1613 1613 emit_byte(0x66); // size prefix
1614 1614 emit_byte(0x66);
1615 1615 emit_byte(0x66);
1616 1616 emit_byte(0x90); // nop
1617 1617 }
1618 1618 // 1 - 12 nops
1619 1619 if(i > 8) {
1620 1620 if(i > 9) {
1621 1621 i -= 1;
1622 1622 emit_byte(0x66);
1623 1623 }
1624 1624 i -= 3;
1625 1625 emit_byte(0x66);
1626 1626 emit_byte(0x66);
1627 1627 emit_byte(0x90);
1628 1628 }
1629 1629 // 1 - 8 nops
1630 1630 if(i > 4) {
1631 1631 if(i > 6) {
1632 1632 i -= 1;
1633 1633 emit_byte(0x66);
1634 1634 }
1635 1635 i -= 3;
1636 1636 emit_byte(0x66);
1637 1637 emit_byte(0x66);
1638 1638 emit_byte(0x90);
1639 1639 }
1640 1640 switch (i) {
1641 1641 case 4:
1642 1642 emit_byte(0x66);
1643 1643 case 3:
1644 1644 emit_byte(0x66);
1645 1645 case 2:
1646 1646 emit_byte(0x66);
1647 1647 case 1:
1648 1648 emit_byte(0x90);
1649 1649 break;
1650 1650 default:
1651 1651 assert(i == 0, " ");
1652 1652 }
1653 1653 }
1654 1654
1655 1655 void Assembler::ret(int imm16) {
1656 1656 if (imm16 == 0) {
1657 1657 emit_byte(0xC3);
1658 1658 } else {
1659 1659 emit_byte(0xC2);
1660 1660 emit_word(imm16);
1661 1661 }
1662 1662 }
1663 1663
1664 1664
1665 1665 void Assembler::set_byte_if_not_zero(Register dst) {
1666 1666 emit_byte(0x0F);
1667 1667 emit_byte(0x95);
1668 1668 emit_byte(0xE0 | dst->encoding());
1669 1669 }
1670 1670
1671 1671
1672 1672 // copies a single word from [esi] to [edi]
1673 1673 void Assembler::smovl() {
1674 1674 emit_byte(0xA5);
1675 1675 }
1676 1676
1677 1677 // copies data from [esi] to [edi] using rcx double words (m32)
1678 1678 void Assembler::rep_movl() {
1679 1679 emit_byte(0xF3);
1680 1680 emit_byte(0xA5);
1681 1681 }
1682 1682
1683 1683
1684 1684 // sets rcx double words (m32) with rax, value at [edi]
1685 1685 void Assembler::rep_set() {
1686 1686 emit_byte(0xF3);
1687 1687 emit_byte(0xAB);
1688 1688 }
1689 1689
1690 1690 // scans rcx double words (m32) at [edi] for occurance of rax,
1691 1691 void Assembler::repne_scan() {
1692 1692 emit_byte(0xF2);
1693 1693 emit_byte(0xAF);
1694 1694 }
1695 1695
1696 1696
1697 1697 void Assembler::setb(Condition cc, Register dst) {
1698 1698 assert(0 <= cc && cc < 16, "illegal cc");
1699 1699 emit_byte(0x0F);
1700 1700 emit_byte(0x90 | cc);
1701 1701 emit_byte(0xC0 | dst->encoding());
1702 1702 }
1703 1703
1704 1704 void Assembler::cld() {
1705 1705 emit_byte(0xfc);
1706 1706 }
1707 1707
1708 1708 void Assembler::std() {
1709 1709 emit_byte(0xfd);
1710 1710 }
1711 1711
1712 1712 void Assembler::emit_raw (unsigned char b) {
1713 1713 emit_byte (b) ;
1714 1714 }
1715 1715
1716 1716 // Serializes memory.
1717 1717 void Assembler::membar() {
1718 1718 // Memory barriers are only needed on multiprocessors
1719 1719 if (os::is_MP()) {
1720 1720 if( VM_Version::supports_sse2() ) {
1721 1721 emit_byte( 0x0F ); // MFENCE; faster blows no regs
1722 1722 emit_byte( 0xAE );
1723 1723 emit_byte( 0xF0 );
1724 1724 } else {
1725 1725 // All usable chips support "locked" instructions which suffice
1726 1726 // as barriers, and are much faster than the alternative of
1727 1727 // using cpuid instruction. We use here a locked add [esp],0.
1728 1728 // This is conveniently otherwise a no-op except for blowing
1729 1729 // flags (which we save and restore.)
1730 1730 pushfd(); // Save eflags register
1731 1731 lock();
1732 1732 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1733 1733 popfd(); // Restore eflags register
1734 1734 }
1735 1735 }
1736 1736 }
1737 1737
1738 1738 // Identify processor type and features
1739 1739 void Assembler::cpuid() {
1740 1740 // Note: we can't assert VM_Version::supports_cpuid() here
1741 1741 // because this instruction is used in the processor
1742 1742 // identification code.
1743 1743 emit_byte( 0x0F );
1744 1744 emit_byte( 0xA2 );
1745 1745 }
1746 1746
1747 1747 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1748 1748 if (L.is_bound()) {
1749 1749 const int long_size = 5;
1750 1750 int offs = target(L) - pc();
1751 1751 assert(offs <= 0, "assembler error");
1752 1752 InstructionMark im(this);
1753 1753 // 1110 1000 #32-bit disp
1754 1754 emit_byte(0xE8);
1755 1755 emit_data(offs - long_size, rtype, 0);
1756 1756 } else {
1757 1757 InstructionMark im(this);
1758 1758 // 1110 1000 #32-bit disp
1759 1759 L.add_patch_at(code(), locator());
1760 1760 emit_byte(0xE8);
1761 1761 emit_data(int(0), rtype, 0);
1762 1762 }
1763 1763 }
1764 1764
1765 1765 void Assembler::call(Register dst) {
1766 1766 emit_byte(0xFF);
1767 1767 emit_byte(0xD0 | dst->encoding());
1768 1768 }
1769 1769
1770 1770
1771 1771 void Assembler::call(Address adr) {
1772 1772 InstructionMark im(this);
1773 1773 relocInfo::relocType rtype = adr.reloc();
1774 1774 if (rtype != relocInfo::runtime_call_type) {
1775 1775 emit_byte(0xFF);
1776 1776 emit_operand(rdx, adr);
1777 1777 } else {
1778 1778 assert(false, "ack");
1779 1779 }
1780 1780
1781 1781 }
1782 1782
1783 1783 void Assembler::call_literal(address dest, RelocationHolder const& rspec) {
1784 1784 InstructionMark im(this);
1785 1785 emit_byte(0xE8);
1786 1786 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1787 1787 assert(dest != NULL, "must have a target");
1788 1788 emit_data(disp, rspec, call32_operand);
1789 1789
1790 1790 }
1791 1791
1792 1792 void Assembler::jmp(Register entry) {
1793 1793 emit_byte(0xFF);
1794 1794 emit_byte(0xE0 | entry->encoding());
1795 1795 }
1796 1796
1797 1797
1798 1798 void Assembler::jmp(Address adr) {
1799 1799 InstructionMark im(this);
1800 1800 emit_byte(0xFF);
1801 1801 emit_operand(rsp, adr);
1802 1802 }
1803 1803
1804 1804 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1805 1805 InstructionMark im(this);
1806 1806 emit_byte(0xE9);
1807 1807 assert(dest != NULL, "must have a target");
1808 1808 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1809 1809 emit_data(disp, rspec.reloc(), call32_operand);
1810 1810 }
1811 1811
1812 1812 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1813 1813 if (L.is_bound()) {
1814 1814 address entry = target(L);
1815 1815 assert(entry != NULL, "jmp most probably wrong");
1816 1816 InstructionMark im(this);
1817 1817 const int short_size = 2;
1818 1818 const int long_size = 5;
1819 1819 intptr_t offs = entry - _code_pos;
1820 1820 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1821 1821 emit_byte(0xEB);
1822 1822 emit_byte((offs - short_size) & 0xFF);
1823 1823 } else {
1824 1824 emit_byte(0xE9);
1825 1825 emit_long(offs - long_size);
1826 1826 }
1827 1827 } else {
1828 1828 // By default, forward jumps are always 32-bit displacements, since
1829 1829 // we can't yet know where the label will be bound. If you're sure that
1830 1830 // the forward jump will not run beyond 256 bytes, use jmpb to
1831 1831 // force an 8-bit displacement.
1832 1832 InstructionMark im(this);
1833 1833 relocate(rtype);
1834 1834 L.add_patch_at(code(), locator());
1835 1835 emit_byte(0xE9);
1836 1836 emit_long(0);
1837 1837 }
1838 1838 }
1839 1839
1840 1840 void Assembler::jmpb(Label& L) {
1841 1841 if (L.is_bound()) {
1842 1842 const int short_size = 2;
1843 1843 address entry = target(L);
1844 1844 assert(is8bit((entry - _code_pos) + short_size),
1845 1845 "Dispacement too large for a short jmp");
1846 1846 assert(entry != NULL, "jmp most probably wrong");
1847 1847 intptr_t offs = entry - _code_pos;
1848 1848 emit_byte(0xEB);
1849 1849 emit_byte((offs - short_size) & 0xFF);
1850 1850 } else {
1851 1851 InstructionMark im(this);
1852 1852 L.add_patch_at(code(), locator());
1853 1853 emit_byte(0xEB);
1854 1854 emit_byte(0);
1855 1855 }
1856 1856 }
1857 1857
1858 1858 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1859 1859 InstructionMark im(this);
1860 1860 relocate(rtype);
1861 1861 assert((0 <= cc) && (cc < 16), "illegal cc");
1862 1862 if (L.is_bound()) {
1863 1863 address dst = target(L);
1864 1864 assert(dst != NULL, "jcc most probably wrong");
1865 1865
1866 1866 const int short_size = 2;
1867 1867 const int long_size = 6;
1868 1868 int offs = (int)dst - ((int)_code_pos);
1869 1869 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1870 1870 // 0111 tttn #8-bit disp
1871 1871 emit_byte(0x70 | cc);
1872 1872 emit_byte((offs - short_size) & 0xFF);
1873 1873 } else {
1874 1874 // 0000 1111 1000 tttn #32-bit disp
1875 1875 emit_byte(0x0F);
1876 1876 emit_byte(0x80 | cc);
1877 1877 emit_long(offs - long_size);
1878 1878 }
1879 1879 } else {
1880 1880 // Note: could eliminate cond. jumps to this jump if condition
1881 1881 // is the same however, seems to be rather unlikely case.
1882 1882 // Note: use jccb() if label to be bound is very close to get
1883 1883 // an 8-bit displacement
1884 1884 L.add_patch_at(code(), locator());
1885 1885 emit_byte(0x0F);
1886 1886 emit_byte(0x80 | cc);
1887 1887 emit_long(0);
1888 1888 }
1889 1889 }
1890 1890
1891 1891 void Assembler::jccb(Condition cc, Label& L) {
1892 1892 if (L.is_bound()) {
1893 1893 const int short_size = 2;
1894 1894 address entry = target(L);
1895 1895 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1896 1896 "Dispacement too large for a short jmp");
1897 1897 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1898 1898 // 0111 tttn #8-bit disp
1899 1899 emit_byte(0x70 | cc);
1900 1900 emit_byte((offs - short_size) & 0xFF);
1901 1901 jcc(cc, L);
1902 1902 } else {
1903 1903 InstructionMark im(this);
1904 1904 L.add_patch_at(code(), locator());
1905 1905 emit_byte(0x70 | cc);
1906 1906 emit_byte(0);
1907 1907 }
1908 1908 }
1909 1909
1910 1910 // FPU instructions
1911 1911
1912 1912 void Assembler::fld1() {
1913 1913 emit_byte(0xD9);
1914 1914 emit_byte(0xE8);
1915 1915 }
1916 1916
1917 1917
1918 1918 void Assembler::fldz() {
1919 1919 emit_byte(0xD9);
1920 1920 emit_byte(0xEE);
1921 1921 }
1922 1922
1923 1923
1924 1924 void Assembler::fld_s(Address adr) {
1925 1925 InstructionMark im(this);
1926 1926 emit_byte(0xD9);
1927 1927 emit_operand(rax, adr);
1928 1928 }
1929 1929
1930 1930
1931 1931 void Assembler::fld_s (int index) {
1932 1932 emit_farith(0xD9, 0xC0, index);
1933 1933 }
1934 1934
1935 1935
1936 1936 void Assembler::fld_d(Address adr) {
1937 1937 InstructionMark im(this);
1938 1938 emit_byte(0xDD);
1939 1939 emit_operand(rax, adr);
1940 1940 }
1941 1941
1942 1942
1943 1943 void Assembler::fld_x(Address adr) {
1944 1944 InstructionMark im(this);
1945 1945 emit_byte(0xDB);
1946 1946 emit_operand(rbp, adr);
1947 1947 }
1948 1948
1949 1949
1950 1950 void Assembler::fst_s(Address adr) {
1951 1951 InstructionMark im(this);
1952 1952 emit_byte(0xD9);
1953 1953 emit_operand(rdx, adr);
1954 1954 }
1955 1955
1956 1956
1957 1957 void Assembler::fst_d(Address adr) {
1958 1958 InstructionMark im(this);
1959 1959 emit_byte(0xDD);
1960 1960 emit_operand(rdx, adr);
1961 1961 }
1962 1962
1963 1963
1964 1964 void Assembler::fstp_s(Address adr) {
1965 1965 InstructionMark im(this);
1966 1966 emit_byte(0xD9);
1967 1967 emit_operand(rbx, adr);
1968 1968 }
1969 1969
1970 1970
1971 1971 void Assembler::fstp_d(Address adr) {
1972 1972 InstructionMark im(this);
1973 1973 emit_byte(0xDD);
1974 1974 emit_operand(rbx, adr);
1975 1975 }
1976 1976
1977 1977
1978 1978 void Assembler::fstp_x(Address adr) {
1979 1979 InstructionMark im(this);
1980 1980 emit_byte(0xDB);
1981 1981 emit_operand(rdi, adr);
1982 1982 }
1983 1983
1984 1984
1985 1985 void Assembler::fstp_d(int index) {
1986 1986 emit_farith(0xDD, 0xD8, index);
1987 1987 }
1988 1988
1989 1989
1990 1990 void Assembler::fild_s(Address adr) {
1991 1991 InstructionMark im(this);
1992 1992 emit_byte(0xDB);
1993 1993 emit_operand(rax, adr);
1994 1994 }
1995 1995
1996 1996
1997 1997 void Assembler::fild_d(Address adr) {
1998 1998 InstructionMark im(this);
1999 1999 emit_byte(0xDF);
2000 2000 emit_operand(rbp, adr);
2001 2001 }
2002 2002
2003 2003
2004 2004 void Assembler::fistp_s(Address adr) {
2005 2005 InstructionMark im(this);
2006 2006 emit_byte(0xDB);
2007 2007 emit_operand(rbx, adr);
2008 2008 }
2009 2009
2010 2010
2011 2011 void Assembler::fistp_d(Address adr) {
2012 2012 InstructionMark im(this);
2013 2013 emit_byte(0xDF);
2014 2014 emit_operand(rdi, adr);
2015 2015 }
2016 2016
2017 2017
2018 2018 void Assembler::fist_s(Address adr) {
2019 2019 InstructionMark im(this);
2020 2020 emit_byte(0xDB);
2021 2021 emit_operand(rdx, adr);
2022 2022 }
2023 2023
2024 2024
2025 2025 void Assembler::fabs() {
2026 2026 emit_byte(0xD9);
2027 2027 emit_byte(0xE1);
2028 2028 }
2029 2029
2030 2030
2031 2031 void Assembler::fldln2() {
2032 2032 emit_byte(0xD9);
2033 2033 emit_byte(0xED);
2034 2034 }
2035 2035
2036 2036 void Assembler::fyl2x() {
2037 2037 emit_byte(0xD9);
2038 2038 emit_byte(0xF1);
2039 2039 }
2040 2040
2041 2041
2042 2042 void Assembler::fldlg2() {
2043 2043 emit_byte(0xD9);
2044 2044 emit_byte(0xEC);
2045 2045 }
2046 2046
2047 2047
2048 2048 void Assembler::flog() {
2049 2049 fldln2();
2050 2050 fxch();
2051 2051 fyl2x();
2052 2052 }
2053 2053
2054 2054
2055 2055 void Assembler::flog10() {
2056 2056 fldlg2();
2057 2057 fxch();
2058 2058 fyl2x();
2059 2059 }
2060 2060
2061 2061
2062 2062 void Assembler::fsin() {
2063 2063 emit_byte(0xD9);
2064 2064 emit_byte(0xFE);
2065 2065 }
2066 2066
2067 2067
2068 2068 void Assembler::fcos() {
2069 2069 emit_byte(0xD9);
2070 2070 emit_byte(0xFF);
2071 2071 }
2072 2072
2073 2073 void Assembler::ftan() {
2074 2074 emit_byte(0xD9);
2075 2075 emit_byte(0xF2);
2076 2076 emit_byte(0xDD);
2077 2077 emit_byte(0xD8);
2078 2078 }
2079 2079
2080 2080 void Assembler::fsqrt() {
2081 2081 emit_byte(0xD9);
2082 2082 emit_byte(0xFA);
2083 2083 }
2084 2084
2085 2085
2086 2086 void Assembler::fchs() {
2087 2087 emit_byte(0xD9);
2088 2088 emit_byte(0xE0);
2089 2089 }
2090 2090
2091 2091
2092 2092 void Assembler::fadd_s(Address src) {
2093 2093 InstructionMark im(this);
2094 2094 emit_byte(0xD8);
2095 2095 emit_operand(rax, src);
2096 2096 }
2097 2097
2098 2098
2099 2099 void Assembler::fadd_d(Address src) {
2100 2100 InstructionMark im(this);
2101 2101 emit_byte(0xDC);
2102 2102 emit_operand(rax, src);
2103 2103 }
2104 2104
2105 2105
2106 2106 void Assembler::fadd(int i) {
2107 2107 emit_farith(0xD8, 0xC0, i);
2108 2108 }
2109 2109
2110 2110
2111 2111 void Assembler::fadda(int i) {
2112 2112 emit_farith(0xDC, 0xC0, i);
2113 2113 }
2114 2114
2115 2115
2116 2116 void Assembler::fsub_d(Address src) {
2117 2117 InstructionMark im(this);
2118 2118 emit_byte(0xDC);
2119 2119 emit_operand(rsp, src);
2120 2120 }
2121 2121
2122 2122
2123 2123 void Assembler::fsub_s(Address src) {
2124 2124 InstructionMark im(this);
2125 2125 emit_byte(0xD8);
2126 2126 emit_operand(rsp, src);
2127 2127 }
2128 2128
2129 2129
2130 2130 void Assembler::fsubr_s(Address src) {
2131 2131 InstructionMark im(this);
2132 2132 emit_byte(0xD8);
2133 2133 emit_operand(rbp, src);
2134 2134 }
2135 2135
2136 2136
2137 2137 void Assembler::fsubr_d(Address src) {
2138 2138 InstructionMark im(this);
2139 2139 emit_byte(0xDC);
2140 2140 emit_operand(rbp, src);
2141 2141 }
2142 2142
2143 2143
2144 2144 void Assembler::fmul_s(Address src) {
2145 2145 InstructionMark im(this);
2146 2146 emit_byte(0xD8);
2147 2147 emit_operand(rcx, src);
2148 2148 }
2149 2149
2150 2150
2151 2151 void Assembler::fmul_d(Address src) {
2152 2152 InstructionMark im(this);
2153 2153 emit_byte(0xDC);
2154 2154 emit_operand(rcx, src);
2155 2155 }
2156 2156
2157 2157
2158 2158 void Assembler::fmul(int i) {
2159 2159 emit_farith(0xD8, 0xC8, i);
2160 2160 }
2161 2161
2162 2162
2163 2163 void Assembler::fmula(int i) {
2164 2164 emit_farith(0xDC, 0xC8, i);
2165 2165 }
2166 2166
2167 2167
2168 2168 void Assembler::fdiv_s(Address src) {
2169 2169 InstructionMark im(this);
2170 2170 emit_byte(0xD8);
2171 2171 emit_operand(rsi, src);
2172 2172 }
2173 2173
2174 2174
2175 2175 void Assembler::fdiv_d(Address src) {
2176 2176 InstructionMark im(this);
2177 2177 emit_byte(0xDC);
2178 2178 emit_operand(rsi, src);
2179 2179 }
2180 2180
2181 2181
2182 2182 void Assembler::fdivr_s(Address src) {
2183 2183 InstructionMark im(this);
2184 2184 emit_byte(0xD8);
2185 2185 emit_operand(rdi, src);
2186 2186 }
2187 2187
2188 2188
2189 2189 void Assembler::fdivr_d(Address src) {
2190 2190 InstructionMark im(this);
2191 2191 emit_byte(0xDC);
2192 2192 emit_operand(rdi, src);
2193 2193 }
2194 2194
2195 2195
2196 2196 void Assembler::fsub(int i) {
2197 2197 emit_farith(0xD8, 0xE0, i);
2198 2198 }
2199 2199
2200 2200
2201 2201 void Assembler::fsuba(int i) {
2202 2202 emit_farith(0xDC, 0xE8, i);
2203 2203 }
2204 2204
2205 2205
2206 2206 void Assembler::fsubr(int i) {
2207 2207 emit_farith(0xD8, 0xE8, i);
2208 2208 }
2209 2209
2210 2210
2211 2211 void Assembler::fsubra(int i) {
2212 2212 emit_farith(0xDC, 0xE0, i);
2213 2213 }
2214 2214
2215 2215
2216 2216 void Assembler::fdiv(int i) {
2217 2217 emit_farith(0xD8, 0xF0, i);
2218 2218 }
2219 2219
2220 2220
2221 2221 void Assembler::fdiva(int i) {
2222 2222 emit_farith(0xDC, 0xF8, i);
2223 2223 }
2224 2224
2225 2225
2226 2226 void Assembler::fdivr(int i) {
2227 2227 emit_farith(0xD8, 0xF8, i);
2228 2228 }
2229 2229
2230 2230
2231 2231 void Assembler::fdivra(int i) {
2232 2232 emit_farith(0xDC, 0xF0, i);
2233 2233 }
2234 2234
2235 2235
2236 2236 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
2237 2237 // is erroneous for some of the floating-point instructions below.
2238 2238
2239 2239 void Assembler::fdivp(int i) {
2240 2240 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
2241 2241 }
2242 2242
2243 2243
2244 2244 void Assembler::fdivrp(int i) {
2245 2245 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
2246 2246 }
2247 2247
2248 2248
2249 2249 void Assembler::fsubp(int i) {
2250 2250 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
2251 2251 }
2252 2252
2253 2253
2254 2254 void Assembler::fsubrp(int i) {
2255 2255 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
2256 2256 }
2257 2257
2258 2258
2259 2259 void Assembler::faddp(int i) {
2260 2260 emit_farith(0xDE, 0xC0, i);
2261 2261 }
2262 2262
2263 2263
2264 2264 void Assembler::fmulp(int i) {
2265 2265 emit_farith(0xDE, 0xC8, i);
2266 2266 }
2267 2267
2268 2268
2269 2269 void Assembler::fprem() {
2270 2270 emit_byte(0xD9);
2271 2271 emit_byte(0xF8);
2272 2272 }
2273 2273
2274 2274
2275 2275 void Assembler::fprem1() {
2276 2276 emit_byte(0xD9);
2277 2277 emit_byte(0xF5);
2278 2278 }
2279 2279
2280 2280
2281 2281 void Assembler::fxch(int i) {
2282 2282 emit_farith(0xD9, 0xC8, i);
2283 2283 }
2284 2284
2285 2285
2286 2286 void Assembler::fincstp() {
2287 2287 emit_byte(0xD9);
2288 2288 emit_byte(0xF7);
2289 2289 }
2290 2290
2291 2291
2292 2292 void Assembler::fdecstp() {
2293 2293 emit_byte(0xD9);
2294 2294 emit_byte(0xF6);
2295 2295 }
2296 2296
2297 2297
2298 2298 void Assembler::ffree(int i) {
2299 2299 emit_farith(0xDD, 0xC0, i);
2300 2300 }
2301 2301
2302 2302
2303 2303 void Assembler::fcomp_s(Address src) {
2304 2304 InstructionMark im(this);
2305 2305 emit_byte(0xD8);
2306 2306 emit_operand(rbx, src);
2307 2307 }
2308 2308
2309 2309
2310 2310 void Assembler::fcomp_d(Address src) {
2311 2311 InstructionMark im(this);
2312 2312 emit_byte(0xDC);
2313 2313 emit_operand(rbx, src);
2314 2314 }
2315 2315
2316 2316
2317 2317 void Assembler::fcom(int i) {
2318 2318 emit_farith(0xD8, 0xD0, i);
2319 2319 }
2320 2320
2321 2321
2322 2322 void Assembler::fcomp(int i) {
2323 2323 emit_farith(0xD8, 0xD8, i);
2324 2324 }
2325 2325
2326 2326
2327 2327 void Assembler::fcompp() {
2328 2328 emit_byte(0xDE);
2329 2329 emit_byte(0xD9);
2330 2330 }
2331 2331
2332 2332
2333 2333 void Assembler::fucomi(int i) {
2334 2334 // make sure the instruction is supported (introduced for P6, together with cmov)
2335 2335 guarantee(VM_Version::supports_cmov(), "illegal instruction");
2336 2336 emit_farith(0xDB, 0xE8, i);
2337 2337 }
2338 2338
2339 2339
2340 2340 void Assembler::fucomip(int i) {
2341 2341 // make sure the instruction is supported (introduced for P6, together with cmov)
2342 2342 guarantee(VM_Version::supports_cmov(), "illegal instruction");
2343 2343 emit_farith(0xDF, 0xE8, i);
2344 2344 }
2345 2345
2346 2346
2347 2347 void Assembler::ftst() {
2348 2348 emit_byte(0xD9);
2349 2349 emit_byte(0xE4);
2350 2350 }
2351 2351
2352 2352
2353 2353 void Assembler::fnstsw_ax() {
2354 2354 emit_byte(0xdF);
2355 2355 emit_byte(0xE0);
2356 2356 }
2357 2357
2358 2358
2359 2359 void Assembler::fwait() {
2360 2360 emit_byte(0x9B);
2361 2361 }
2362 2362
2363 2363
2364 2364 void Assembler::finit() {
2365 2365 emit_byte(0x9B);
2366 2366 emit_byte(0xDB);
2367 2367 emit_byte(0xE3);
2368 2368 }
2369 2369
2370 2370
2371 2371 void Assembler::fldcw(Address src) {
2372 2372 InstructionMark im(this);
2373 2373 emit_byte(0xd9);
2374 2374 emit_operand(rbp, src);
2375 2375 }
2376 2376
2377 2377
2378 2378 void Assembler::fnstcw(Address src) {
2379 2379 InstructionMark im(this);
2380 2380 emit_byte(0x9B);
2381 2381 emit_byte(0xD9);
2382 2382 emit_operand(rdi, src);
2383 2383 }
2384 2384
2385 2385 void Assembler::fnsave(Address dst) {
2386 2386 InstructionMark im(this);
2387 2387 emit_byte(0xDD);
2388 2388 emit_operand(rsi, dst);
2389 2389 }
2390 2390
2391 2391
2392 2392 void Assembler::frstor(Address src) {
2393 2393 InstructionMark im(this);
2394 2394 emit_byte(0xDD);
2395 2395 emit_operand(rsp, src);
2396 2396 }
2397 2397
2398 2398
2399 2399 void Assembler::fldenv(Address src) {
2400 2400 InstructionMark im(this);
2401 2401 emit_byte(0xD9);
2402 2402 emit_operand(rsp, src);
2403 2403 }
2404 2404
2405 2405
2406 2406 void Assembler::sahf() {
2407 2407 emit_byte(0x9E);
2408 2408 }
2409 2409
2410 2410 // MMX operations
2411 2411 void Assembler::emit_operand(MMXRegister reg, Address adr) {
2412 2412 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
2413 2413 }
2414 2414
2415 2415 void Assembler::movq( MMXRegister dst, Address src ) {
2416 2416 assert( VM_Version::supports_mmx(), "" );
2417 2417 emit_byte(0x0F);
2418 2418 emit_byte(0x6F);
2419 2419 emit_operand(dst,src);
2420 2420 }
2421 2421
2422 2422 void Assembler::movq( Address dst, MMXRegister src ) {
2423 2423 assert( VM_Version::supports_mmx(), "" );
2424 2424 emit_byte(0x0F);
2425 2425 emit_byte(0x7F);
2426 2426 emit_operand(src,dst);
2427 2427 }
2428 2428
2429 2429 void Assembler::emms() {
2430 2430 emit_byte(0x0F);
2431 2431 emit_byte(0x77);
2432 2432 }
2433 2433
2434 2434
2435 2435
2436 2436
2437 2437 // SSE and SSE2 instructions
2438 2438 inline void Assembler::emit_sse_operand(XMMRegister reg, Address adr) {
2439 2439 assert(((Register)reg)->encoding() == reg->encoding(), "otherwise typecast is invalid");
2440 2440 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
2441 2441 }
2442 2442 inline void Assembler::emit_sse_operand(Register reg, Address adr) {
2443 2443 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
2444 2444 }
2445 2445
2446 2446 inline void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2447 2447 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
2448 2448 }
2449 2449 inline void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2450 2450 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
2451 2451 }
2452 2452 inline void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2453 2453 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
2454 2454 }
2455 2455
2456 2456
2457 2457 // Macro for creation of SSE2 instructions
2458 2458 // The SSE2 instricution set is highly regular, so this macro saves
2459 2459 // a lot of cut&paste
2460 2460 // Each macro expansion creates two methods (same name with different
2461 2461 // parameter list)
2462 2462 //
2463 2463 // Macro parameters:
2464 2464 // * name: name of the created methods
2465 2465 // * sse_version: either sse or sse2 for the assertion if instruction supported by processor
2466 2466 // * prefix: first opcode byte of the instruction (or 0 if no prefix byte)
2467 2467 // * opcode: last opcode byte of the instruction
2468 2468 // * conversion instruction have parameters of type Register instead of XMMRegister,
2469 2469 // so this can also configured with macro parameters
2470 2470 #define emit_sse_instruction(name, sse_version, prefix, opcode, dst_register_type, src_register_type) \
2471 2471 \
2472 2472 void Assembler:: name (dst_register_type dst, Address src) { \
2473 2473 assert(VM_Version::supports_##sse_version(), ""); \
2474 2474 \
2475 2475 InstructionMark im(this); \
2476 2476 if (prefix != 0) emit_byte(prefix); \
2477 2477 emit_byte(0x0F); \
2478 2478 emit_byte(opcode); \
2479 2479 emit_sse_operand(dst, src); \
2480 2480 } \
2481 2481 \
2482 2482 void Assembler:: name (dst_register_type dst, src_register_type src) { \
2483 2483 assert(VM_Version::supports_##sse_version(), ""); \
2484 2484 \
2485 2485 if (prefix != 0) emit_byte(prefix); \
2486 2486 emit_byte(0x0F); \
2487 2487 emit_byte(opcode); \
2488 2488 emit_sse_operand(dst, src); \
2489 2489 } \
2490 2490
2491 2491 emit_sse_instruction(addss, sse, 0xF3, 0x58, XMMRegister, XMMRegister);
2492 2492 emit_sse_instruction(addsd, sse2, 0xF2, 0x58, XMMRegister, XMMRegister)
2493 2493 emit_sse_instruction(subss, sse, 0xF3, 0x5C, XMMRegister, XMMRegister)
2494 2494 emit_sse_instruction(subsd, sse2, 0xF2, 0x5C, XMMRegister, XMMRegister)
2495 2495 emit_sse_instruction(mulss, sse, 0xF3, 0x59, XMMRegister, XMMRegister)
2496 2496 emit_sse_instruction(mulsd, sse2, 0xF2, 0x59, XMMRegister, XMMRegister)
2497 2497 emit_sse_instruction(divss, sse, 0xF3, 0x5E, XMMRegister, XMMRegister)
2498 2498 emit_sse_instruction(divsd, sse2, 0xF2, 0x5E, XMMRegister, XMMRegister)
2499 2499 emit_sse_instruction(sqrtss, sse, 0xF3, 0x51, XMMRegister, XMMRegister)
2500 2500 emit_sse_instruction(sqrtsd, sse2, 0xF2, 0x51, XMMRegister, XMMRegister)
2501 2501
2502 2502 emit_sse_instruction(pxor, sse2, 0x66, 0xEF, XMMRegister, XMMRegister)
2503 2503
2504 2504 emit_sse_instruction(comiss, sse, 0, 0x2F, XMMRegister, XMMRegister)
2505 2505 emit_sse_instruction(comisd, sse2, 0x66, 0x2F, XMMRegister, XMMRegister)
2506 2506 emit_sse_instruction(ucomiss, sse, 0, 0x2E, XMMRegister, XMMRegister)
2507 2507 emit_sse_instruction(ucomisd, sse2, 0x66, 0x2E, XMMRegister, XMMRegister)
2508 2508
2509 2509 emit_sse_instruction(cvtss2sd, sse2, 0xF3, 0x5A, XMMRegister, XMMRegister);
2510 2510 emit_sse_instruction(cvtsd2ss, sse2, 0xF2, 0x5A, XMMRegister, XMMRegister)
2511 2511 emit_sse_instruction(cvtsi2ss, sse, 0xF3, 0x2A, XMMRegister, Register);
2512 2512 emit_sse_instruction(cvtsi2sd, sse2, 0xF2, 0x2A, XMMRegister, Register)
2513 2513 emit_sse_instruction(cvtss2si, sse, 0xF3, 0x2D, Register, XMMRegister);
2514 2514 emit_sse_instruction(cvtsd2si, sse2, 0xF2, 0x2D, Register, XMMRegister)
2515 2515 emit_sse_instruction(cvttss2si, sse, 0xF3, 0x2C, Register, XMMRegister);
2516 2516 emit_sse_instruction(cvttsd2si, sse2, 0xF2, 0x2C, Register, XMMRegister)
2517 2517
2518 2518 emit_sse_instruction(movss, sse, 0xF3, 0x10, XMMRegister, XMMRegister)
2519 2519 emit_sse_instruction(movsd, sse2, 0xF2, 0x10, XMMRegister, XMMRegister)
2520 2520
2521 2521 emit_sse_instruction(movq, sse2, 0xF3, 0x7E, XMMRegister, XMMRegister);
2522 2522 emit_sse_instruction(movd, sse2, 0x66, 0x6E, XMMRegister, Register);
2523 2523 emit_sse_instruction(movdqa, sse2, 0x66, 0x6F, XMMRegister, XMMRegister);
2524 2524
2525 2525 emit_sse_instruction(punpcklbw, sse2, 0x66, 0x60, XMMRegister, XMMRegister);
2526 2526
2527 2527
2528 2528 // Instruction not covered by macro
2529 2529 void Assembler::movq(Address dst, XMMRegister src) {
2530 2530 assert(VM_Version::supports_sse2(), "");
2531 2531
2532 2532 InstructionMark im(this);
2533 2533 emit_byte(0x66);
2534 2534 emit_byte(0x0F);
2535 2535 emit_byte(0xD6);
2536 2536 emit_sse_operand(src, dst);
2537 2537 }
2538 2538
2539 2539 void Assembler::movd(Address dst, XMMRegister src) {
2540 2540 assert(VM_Version::supports_sse2(), "");
2541 2541
2542 2542 InstructionMark im(this);
2543 2543 emit_byte(0x66);
2544 2544 emit_byte(0x0F);
2545 2545 emit_byte(0x7E);
2546 2546 emit_sse_operand(src, dst);
2547 2547 }
2548 2548
2549 2549 void Assembler::movd(Register dst, XMMRegister src) {
2550 2550 assert(VM_Version::supports_sse2(), "");
2551 2551
2552 2552 emit_byte(0x66);
2553 2553 emit_byte(0x0F);
2554 2554 emit_byte(0x7E);
2555 2555 emit_sse_operand(src, dst);
2556 2556 }
2557 2557
2558 2558 void Assembler::movdqa(Address dst, XMMRegister src) {
2559 2559 assert(VM_Version::supports_sse2(), "");
2560 2560
2561 2561 InstructionMark im(this);
2562 2562 emit_byte(0x66);
2563 2563 emit_byte(0x0F);
2564 2564 emit_byte(0x7F);
2565 2565 emit_sse_operand(src, dst);
2566 2566 }
2567 2567
2568 2568 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2569 2569 assert(isByte(mode), "invalid value");
2570 2570 assert(VM_Version::supports_sse2(), "");
2571 2571
2572 2572 emit_byte(0x66);
2573 2573 emit_byte(0x0F);
2574 2574 emit_byte(0x70);
2575 2575 emit_sse_operand(dst, src);
2576 2576 emit_byte(mode & 0xFF);
2577 2577 }
2578 2578
2579 2579 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2580 2580 assert(isByte(mode), "invalid value");
2581 2581 assert(VM_Version::supports_sse2(), "");
2582 2582
2583 2583 InstructionMark im(this);
2584 2584 emit_byte(0x66);
2585 2585 emit_byte(0x0F);
2586 2586 emit_byte(0x70);
2587 2587 emit_sse_operand(dst, src);
2588 2588 emit_byte(mode & 0xFF);
2589 2589 }
2590 2590
2591 2591 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2592 2592 assert(isByte(mode), "invalid value");
2593 2593 assert(VM_Version::supports_sse2(), "");
2594 2594
2595 2595 emit_byte(0xF2);
2596 2596 emit_byte(0x0F);
2597 2597 emit_byte(0x70);
2598 2598 emit_sse_operand(dst, src);
2599 2599 emit_byte(mode & 0xFF);
2600 2600 }
2601 2601
2602 2602 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2603 2603 assert(isByte(mode), "invalid value");
2604 2604 assert(VM_Version::supports_sse2(), "");
2605 2605
2606 2606 InstructionMark im(this);
2607 2607 emit_byte(0xF2);
2608 2608 emit_byte(0x0F);
2609 2609 emit_byte(0x70);
2610 2610 emit_sse_operand(dst, src);
2611 2611 emit_byte(mode & 0xFF);
2612 2612 }
2613 2613
2614 2614 void Assembler::psrlq(XMMRegister dst, int shift) {
2615 2615 assert(VM_Version::supports_sse2(), "");
2616 2616
2617 2617 emit_byte(0x66);
2618 2618 emit_byte(0x0F);
2619 2619 emit_byte(0x73);
2620 2620 emit_sse_operand(xmm2, dst);
2621 2621 emit_byte(shift);
2622 2622 }
2623 2623
2624 2624 void Assembler::movss( Address dst, XMMRegister src ) {
2625 2625 assert(VM_Version::supports_sse(), "");
2626 2626
2627 2627 InstructionMark im(this);
2628 2628 emit_byte(0xF3); // single
2629 2629 emit_byte(0x0F);
2630 2630 emit_byte(0x11); // store
2631 2631 emit_sse_operand(src, dst);
2632 2632 }
2633 2633
2634 2634 void Assembler::movsd( Address dst, XMMRegister src ) {
2635 2635 assert(VM_Version::supports_sse2(), "");
2636 2636
2637 2637 InstructionMark im(this);
2638 2638 emit_byte(0xF2); // double
2639 2639 emit_byte(0x0F);
2640 2640 emit_byte(0x11); // store
2641 2641 emit_sse_operand(src,dst);
2642 2642 }
2643 2643
2644 2644 // New cpus require to use movaps and movapd to avoid partial register stall
2645 2645 // when moving between registers.
2646 2646 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2647 2647 assert(VM_Version::supports_sse(), "");
2648 2648
2649 2649 emit_byte(0x0F);
2650 2650 emit_byte(0x28);
2651 2651 emit_sse_operand(dst, src);
2652 2652 }
2653 2653 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2654 2654 assert(VM_Version::supports_sse2(), "");
2655 2655
2656 2656 emit_byte(0x66);
2657 2657 emit_byte(0x0F);
2658 2658 emit_byte(0x28);
2659 2659 emit_sse_operand(dst, src);
2660 2660 }
2661 2661
2662 2662 // New cpus require to use movsd and movss to avoid partial register stall
2663 2663 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2664 2664 // The selection is done in MacroAssembler::movdbl() and movflt().
2665 2665 void Assembler::movlpd(XMMRegister dst, Address src) {
2666 2666 assert(VM_Version::supports_sse(), "");
2667 2667
2668 2668 InstructionMark im(this);
2669 2669 emit_byte(0x66);
2670 2670 emit_byte(0x0F);
2671 2671 emit_byte(0x12);
2672 2672 emit_sse_operand(dst, src);
2673 2673 }
2674 2674
2675 2675 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
2676 2676 assert(VM_Version::supports_sse2(), "");
2677 2677
2678 2678 emit_byte(0xF3);
2679 2679 emit_byte(0x0F);
2680 2680 emit_byte(0xE6);
2681 2681 emit_sse_operand(dst, src);
2682 2682 }
2683 2683
2684 2684 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
2685 2685 assert(VM_Version::supports_sse2(), "");
2686 2686
2687 2687 emit_byte(0x0F);
2688 2688 emit_byte(0x5B);
2689 2689 emit_sse_operand(dst, src);
2690 2690 }
2691 2691
2692 2692 emit_sse_instruction(andps, sse, 0, 0x54, XMMRegister, XMMRegister);
2693 2693 emit_sse_instruction(andpd, sse2, 0x66, 0x54, XMMRegister, XMMRegister);
2694 2694 emit_sse_instruction(andnps, sse, 0, 0x55, XMMRegister, XMMRegister);
2695 2695 emit_sse_instruction(andnpd, sse2, 0x66, 0x55, XMMRegister, XMMRegister);
2696 2696 emit_sse_instruction(orps, sse, 0, 0x56, XMMRegister, XMMRegister);
2697 2697 emit_sse_instruction(orpd, sse2, 0x66, 0x56, XMMRegister, XMMRegister);
2698 2698 emit_sse_instruction(xorps, sse, 0, 0x57, XMMRegister, XMMRegister);
2699 2699 emit_sse_instruction(xorpd, sse2, 0x66, 0x57, XMMRegister, XMMRegister);
2700 2700
2701 2701
2702 2702 void Assembler::ldmxcsr( Address src) {
2703 2703 InstructionMark im(this);
2704 2704 emit_byte(0x0F);
2705 2705 emit_byte(0xAE);
2706 2706 emit_operand(rdx /* 2 */, src);
2707 2707 }
2708 2708
2709 2709 void Assembler::stmxcsr( Address dst) {
2710 2710 InstructionMark im(this);
2711 2711 emit_byte(0x0F);
2712 2712 emit_byte(0xAE);
2713 2713 emit_operand(rbx /* 3 */, dst);
2714 2714 }
2715 2715
2716 2716 // Implementation of MacroAssembler
2717 2717
2718 2718 Address MacroAssembler::as_Address(AddressLiteral adr) {
2719 2719 // amd64 always does this as a pc-rel
2720 2720 // we can be absolute or disp based on the instruction type
2721 2721 // jmp/call are displacements others are absolute
2722 2722 assert(!adr.is_lval(), "must be rval");
2723 2723
2724 2724 return Address(adr.target(), adr.rspec());
2725 2725 }
2726 2726
2727 2727 Address MacroAssembler::as_Address(ArrayAddress adr) {
2728 2728 return Address::make_array(adr);
2729 2729 }
2730 2730
2731 2731 void MacroAssembler::fat_nop() {
2732 2732 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2733 2733 emit_byte(0x26); // es:
2734 2734 emit_byte(0x2e); // cs:
2735 2735 emit_byte(0x64); // fs:
2736 2736 emit_byte(0x65); // gs:
2737 2737 emit_byte(0x90);
2738 2738 }
2739 2739
2740 2740 // 32bit can do a case table jump in one instruction but we no longer allow the base
2741 2741 // to be installed in the Address class
2742 2742 void MacroAssembler::jump(ArrayAddress entry) {
2743 2743 jmp(as_Address(entry));
2744 2744 }
2745 2745
2746 2746 void MacroAssembler::jump(AddressLiteral dst) {
2747 2747 jmp_literal(dst.target(), dst.rspec());
2748 2748 }
2749 2749
2750 2750 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2751 2751 assert((0 <= cc) && (cc < 16), "illegal cc");
2752 2752
2753 2753 InstructionMark im(this);
2754 2754
2755 2755 relocInfo::relocType rtype = dst.reloc();
2756 2756 relocate(rtype);
2757 2757 const int short_size = 2;
2758 2758 const int long_size = 6;
2759 2759 int offs = (int)dst.target() - ((int)_code_pos);
2760 2760 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
2761 2761 // 0111 tttn #8-bit disp
2762 2762 emit_byte(0x70 | cc);
2763 2763 emit_byte((offs - short_size) & 0xFF);
2764 2764 } else {
2765 2765 // 0000 1111 1000 tttn #32-bit disp
2766 2766 emit_byte(0x0F);
2767 2767 emit_byte(0x80 | cc);
2768 2768 emit_long(offs - long_size);
2769 2769 }
2770 2770 }
2771 2771
2772 2772 // Calls
2773 2773 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2774 2774 Assembler::call(L, rtype);
2775 2775 }
2776 2776
2777 2777 void MacroAssembler::call(Register entry) {
2778 2778 Assembler::call(entry);
2779 2779 }
2780 2780
2781 2781 void MacroAssembler::call(AddressLiteral entry) {
2782 2782 Assembler::call_literal(entry.target(), entry.rspec());
2783 2783 }
2784 2784
2785 2785
2786 2786 void MacroAssembler::cmp8(AddressLiteral src1, int8_t imm) {
2787 2787 Assembler::cmpb(as_Address(src1), imm);
2788 2788 }
2789 2789
2790 2790 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2791 2791 Assembler::cmpl(as_Address(src1), imm);
2792 2792 }
2793 2793
2794 2794 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2795 2795 if (src2.is_lval()) {
2796 2796 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2797 2797 } else {
2798 2798 Assembler::cmpl(src1, as_Address(src2));
2799 2799 }
2800 2800 }
2801 2801
2802 2802 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2803 2803 Assembler::cmpl(src1, imm);
2804 2804 }
2805 2805
2806 2806 void MacroAssembler::cmp32(Register src1, Address src2) {
2807 2807 Assembler::cmpl(src1, src2);
2808 2808 }
2809 2809
2810 2810 void MacroAssembler::cmpoop(Address src1, jobject obj) {
2811 2811 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
2812 2812 }
2813 2813
2814 2814 void MacroAssembler::cmpoop(Register src1, jobject obj) {
2815 2815 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
2816 2816 }
2817 2817
2818 2818 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2819 2819 if (src2.is_lval()) {
2820 2820 // compare the effect address of src2 to src1
2821 2821 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
2822 2822 } else {
2823 2823 Assembler::cmpl(src1, as_Address(src2));
2824 2824 }
2825 2825 }
2826 2826
2827 2827 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2828 2828 assert(src2.is_lval(), "not a mem-mem compare");
2829 2829 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2830 2830 }
2831 2831
2832 2832
2833 2833 void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) {
2834 2834 cmpxchg(reg, as_Address(adr));
2835 2835 }
2836 2836
2837 2837 void MacroAssembler::increment(AddressLiteral dst) {
2838 2838 increment(as_Address(dst));
2839 2839 }
2840 2840
2841 2841 void MacroAssembler::increment(ArrayAddress dst) {
2842 2842 increment(as_Address(dst));
2843 2843 }
2844 2844
2845 2845 void MacroAssembler::lea(Register dst, AddressLiteral adr) {
2846 2846 // leal(dst, as_Address(adr));
2847 2847 // see note in movl as to why we musr use a move
2848 2848 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
2849 2849 }
2850 2850
2851 2851 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
2852 2852 // leal(dst, as_Address(adr));
2853 2853 // see note in movl as to why we musr use a move
2854 2854 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
2855 2855 }
2856 2856
2857 2857 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2858 2858 Assembler::movl(as_Address(dst), src);
2859 2859 }
2860 2860
2861 2861 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2862 2862 Assembler::movl(dst, as_Address(src));
2863 2863 }
2864 2864
2865 2865 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2866 2866 movb(as_Address(dst), src);
2867 2867 }
2868 2868
2869 2869 void MacroAssembler::movoop(Address dst, jobject obj) {
2870 2870 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
2871 2871 }
2872 2872
2873 2873 void MacroAssembler::movoop(Register dst, jobject obj) {
2874 2874 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
2875 2875 }
2876 2876
2877 2877 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
2878 2878 if (src.is_lval()) {
2879 2879 // essentially an lea
2880 2880 mov_literal32(dst, (int32_t) src.target(), src.rspec());
2881 2881 } else {
2882 2882 // mov 32bits from an absolute address
2883 2883 movl(dst, as_Address(src));
2884 2884 }
2885 2885 }
2886 2886
2887 2887 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
2888 2888 movl(as_Address(dst), src);
2889 2889 }
2890 2890
2891 2891 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
2892 2892 movl(dst, as_Address(src));
2893 2893 }
2894 2894
2895 2895 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2896 2896 movss(dst, as_Address(src));
2897 2897 }
2898 2898
2899 2899 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2900 2900 if (UseXmmLoadAndClearUpper) { movsd (dst, as_Address(src)); return; }
2901 2901 else { movlpd(dst, as_Address(src)); return; }
2902 2902 }
2903 2903
2904 2904 void Assembler::pushoop(jobject obj) {
2905 2905 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
2906 2906 }
2907 2907
2908 2908
2909 2909 void MacroAssembler::pushptr(AddressLiteral src) {
2910 2910 if (src.is_lval()) {
2911 2911 push_literal32((int32_t)src.target(), src.rspec());
2912 2912 } else {
2913 2913 pushl(as_Address(src));
2914 2914 }
2915 2915 }
2916 2916
2917 2917 void MacroAssembler::test32(Register src1, AddressLiteral src2) {
2918 2918 // src2 must be rval
2919 2919 testl(src1, as_Address(src2));
2920 2920 }
2921 2921
2922 2922 // FPU
2923 2923
2924 2924 void MacroAssembler::fld_x(AddressLiteral src) {
2925 2925 Assembler::fld_x(as_Address(src));
2926 2926 }
2927 2927
2928 2928 void MacroAssembler::fld_d(AddressLiteral src) {
2929 2929 fld_d(as_Address(src));
2930 2930 }
2931 2931
2932 2932 void MacroAssembler::fld_s(AddressLiteral src) {
2933 2933 fld_s(as_Address(src));
2934 2934 }
2935 2935
2936 2936 void MacroAssembler::fldcw(AddressLiteral src) {
2937 2937 Assembler::fldcw(as_Address(src));
2938 2938 }
2939 2939
2940 2940 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2941 2941 Assembler::ldmxcsr(as_Address(src));
2942 2942 }
2943 2943
2944 2944 // SSE
2945 2945
2946 2946 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
2947 2947 andpd(dst, as_Address(src));
2948 2948 }
2949 2949
2950 2950 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2951 2951 comisd(dst, as_Address(src));
2952 2952 }
2953 2953
2954 2954 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2955 2955 comiss(dst, as_Address(src));
2956 2956 }
2957 2957
2958 2958 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2959 2959 movsd(dst, as_Address(src));
2960 2960 }
2961 2961
2962 2962 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2963 2963 movss(dst, as_Address(src));
2964 2964 }
2965 2965
2966 2966 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
2967 2967 xorpd(dst, as_Address(src));
2968 2968 }
2969 2969
2970 2970 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
2971 2971 xorps(dst, as_Address(src));
2972 2972 }
2973 2973
2974 2974 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
2975 2975 ucomisd(dst, as_Address(src));
2976 2976 }
2977 2977
2978 2978 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
2979 2979 ucomiss(dst, as_Address(src));
2980 2980 }
2981 2981
2982 2982 void MacroAssembler::null_check(Register reg, int offset) {
2983 2983 if (needs_explicit_null_check(offset)) {
2984 2984 // provoke OS NULL exception if reg = NULL by
2985 2985 // accessing M[reg] w/o changing any (non-CC) registers
2986 2986 cmpl(rax, Address(reg, 0));
2987 2987 // Note: should probably use testl(rax, Address(reg, 0));
2988 2988 // may be shorter code (however, this version of
2989 2989 // testl needs to be implemented first)
2990 2990 } else {
2991 2991 // nothing to do, (later) access of M[reg + offset]
2992 2992 // will provoke OS NULL exception if reg = NULL
2993 2993 }
2994 2994 }
2995 2995
2996 2996
2997 2997 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2998 2998 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2999 2999 // and "3.9 Partial Register Penalties", p. 22).
3000 3000 int off;
3001 3001 if (VM_Version::is_P6() || src.uses(dst)) {
3002 3002 off = offset();
3003 3003 movzxb(dst, src);
3004 3004 } else {
3005 3005 xorl(dst, dst);
3006 3006 off = offset();
3007 3007 movb(dst, src);
3008 3008 }
3009 3009 return off;
3010 3010 }
3011 3011
3012 3012
3013 3013 int MacroAssembler::load_unsigned_word(Register dst, Address src) {
3014 3014 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3015 3015 // and "3.9 Partial Register Penalties", p. 22).
3016 3016 int off;
3017 3017 if (VM_Version::is_P6() || src.uses(dst)) {
3018 3018 off = offset();
3019 3019 movzxw(dst, src);
3020 3020 } else {
3021 3021 xorl(dst, dst);
3022 3022 off = offset();
3023 3023 movw(dst, src);
3024 3024 }
3025 3025 return off;
3026 3026 }
3027 3027
3028 3028
3029 3029 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3030 3030 int off;
3031 3031 if (VM_Version::is_P6()) {
3032 3032 off = offset();
3033 3033 movsxb(dst, src);
3034 3034 } else {
3035 3035 off = load_unsigned_byte(dst, src);
3036 3036 shll(dst, 24);
3037 3037 sarl(dst, 24);
3038 3038 }
3039 3039 return off;
3040 3040 }
3041 3041
3042 3042
3043 3043 int MacroAssembler::load_signed_word(Register dst, Address src) {
3044 3044 int off;
3045 3045 if (VM_Version::is_P6()) {
3046 3046 off = offset();
3047 3047 movsxw(dst, src);
3048 3048 } else {
3049 3049 off = load_unsigned_word(dst, src);
3050 3050 shll(dst, 16);
3051 3051 sarl(dst, 16);
3052 3052 }
3053 3053 return off;
3054 3054 }
3055 3055
3056 3056
3057 3057 void MacroAssembler::extend_sign(Register hi, Register lo) {
3058 3058 // According to Intel Doc. AP-526, "Integer Divide", p.18.
3059 3059 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
3060 3060 cdql();
3061 3061 } else {
3062 3062 movl(hi, lo);
3063 3063 sarl(hi, 31);
3064 3064 }
3065 3065 }
3066 3066
3067 3067
3068 3068 void MacroAssembler::increment(Register reg, int value) {
3069 3069 if (value == min_jint) {addl(reg, value); return; }
3070 3070 if (value < 0) { decrement(reg, -value); return; }
3071 3071 if (value == 0) { ; return; }
3072 3072 if (value == 1 && UseIncDec) { incl(reg); return; }
3073 3073 /* else */ { addl(reg, value) ; return; }
3074 3074 }
3075 3075
3076 3076 void MacroAssembler::increment(Address dst, int value) {
3077 3077 if (value == min_jint) {addl(dst, value); return; }
3078 3078 if (value < 0) { decrement(dst, -value); return; }
3079 3079 if (value == 0) { ; return; }
3080 3080 if (value == 1 && UseIncDec) { incl(dst); return; }
3081 3081 /* else */ { addl(dst, value) ; return; }
3082 3082 }
3083 3083
3084 3084 void MacroAssembler::decrement(Register reg, int value) {
3085 3085 if (value == min_jint) {subl(reg, value); return; }
3086 3086 if (value < 0) { increment(reg, -value); return; }
3087 3087 if (value == 0) { ; return; }
3088 3088 if (value == 1 && UseIncDec) { decl(reg); return; }
3089 3089 /* else */ { subl(reg, value) ; return; }
3090 3090 }
3091 3091
3092 3092 void MacroAssembler::decrement(Address dst, int value) {
3093 3093 if (value == min_jint) {subl(dst, value); return; }
3094 3094 if (value < 0) { increment(dst, -value); return; }
3095 3095 if (value == 0) { ; return; }
3096 3096 if (value == 1 && UseIncDec) { decl(dst); return; }
3097 3097 /* else */ { subl(dst, value) ; return; }
3098 3098 }
3099 3099
3100 3100 void MacroAssembler::align(int modulus) {
3101 3101 if (offset() % modulus != 0) nop(modulus - (offset() % modulus));
3102 3102 }
3103 3103
3104 3104
3105 3105 void MacroAssembler::enter() {
3106 3106 pushl(rbp);
3107 3107 movl(rbp, rsp);
3108 3108 }
3109 3109
3110 3110
3111 3111 void MacroAssembler::leave() {
3112 3112 movl(rsp, rbp);
3113 3113 popl(rbp);
3114 3114 }
3115 3115
3116 3116 void MacroAssembler::set_last_Java_frame(Register java_thread,
3117 3117 Register last_java_sp,
3118 3118 Register last_java_fp,
3119 3119 address last_java_pc) {
3120 3120 // determine java_thread register
3121 3121 if (!java_thread->is_valid()) {
3122 3122 java_thread = rdi;
3123 3123 get_thread(java_thread);
3124 3124 }
3125 3125 // determine last_java_sp register
3126 3126 if (!last_java_sp->is_valid()) {
3127 3127 last_java_sp = rsp;
3128 3128 }
3129 3129
3130 3130 // last_java_fp is optional
3131 3131
3132 3132 if (last_java_fp->is_valid()) {
3133 3133 movl(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3134 3134 }
3135 3135
3136 3136 // last_java_pc is optional
3137 3137
3138 3138 if (last_java_pc != NULL) {
3139 3139 lea(Address(java_thread,
3140 3140 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3141 3141 InternalAddress(last_java_pc));
3142 3142
3143 3143 }
3144 3144 movl(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3145 3145 }
3146 3146
3147 3147 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3148 3148 // determine java_thread register
3149 3149 if (!java_thread->is_valid()) {
3150 3150 java_thread = rdi;
3151 3151 get_thread(java_thread);
3152 3152 }
3153 3153 // we must set sp to zero to clear frame
3154 3154 movl(Address(java_thread, JavaThread::last_Java_sp_offset()), 0);
3155 3155 if (clear_fp) {
3156 3156 movl(Address(java_thread, JavaThread::last_Java_fp_offset()), 0);
3157 3157 }
3158 3158
3159 3159 if (clear_pc)
3160 3160 movl(Address(java_thread, JavaThread::last_Java_pc_offset()), 0);
3161 3161
3162 3162 }
3163 3163
3164 3164
3165 3165
3166 3166 // Implementation of call_VM versions
3167 3167
3168 3168 void MacroAssembler::call_VM_leaf_base(
3169 3169 address entry_point,
3170 3170 int number_of_arguments
3171 3171 ) {
3172 3172 call(RuntimeAddress(entry_point));
3173 3173 increment(rsp, number_of_arguments * wordSize);
3174 3174 }
3175 3175
3176 3176
3177 3177 void MacroAssembler::call_VM_base(
3178 3178 Register oop_result,
3179 3179 Register java_thread,
3180 3180 Register last_java_sp,
3181 3181 address entry_point,
3182 3182 int number_of_arguments,
3183 3183 bool check_exceptions
3184 3184 ) {
3185 3185 // determine java_thread register
3186 3186 if (!java_thread->is_valid()) {
3187 3187 java_thread = rdi;
3188 3188 get_thread(java_thread);
3189 3189 }
3190 3190 // determine last_java_sp register
3191 3191 if (!last_java_sp->is_valid()) {
3192 3192 last_java_sp = rsp;
3193 3193 }
3194 3194 // debugging support
3195 3195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
3196 3196 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
3197 3197 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
3198 3198 // push java thread (becomes first argument of C function)
3199 3199 pushl(java_thread);
3200 3200 // set last Java frame before call
3201 3201 assert(last_java_sp != rbp, "this code doesn't work for last_java_sp == rbp, which currently can't portably work anyway since C2 doesn't save rbp,");
3202 3202 // Only interpreter should have to set fp
3203 3203 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
3204 3204 // do the call
3205 3205 call(RuntimeAddress(entry_point));
3206 3206 // restore the thread (cannot use the pushed argument since arguments
3207 3207 // may be overwritten by C code generated by an optimizing compiler);
3208 3208 // however can use the register value directly if it is callee saved.
3209 3209 if (java_thread == rdi || java_thread == rsi) {
3210 3210 // rdi & rsi are callee saved -> nothing to do
3211 3211 #ifdef ASSERT
3212 3212 guarantee(java_thread != rax, "change this code");
3213 3213 pushl(rax);
3214 3214 { Label L;
3215 3215 get_thread(rax);
3216 3216 cmpl(java_thread, rax);
3217 3217 jcc(Assembler::equal, L);
3218 3218 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
3219 3219 bind(L);
3220 3220 }
3221 3221 popl(rax);
3222 3222 #endif
3223 3223 } else {
3224 3224 get_thread(java_thread);
3225 3225 }
3226 3226 // reset last Java frame
3227 3227 // Only interpreter should have to clear fp
3228 3228 reset_last_Java_frame(java_thread, true, false);
3229 3229 // discard thread and arguments
3230 3230 addl(rsp, (1 + number_of_arguments)*wordSize);
3231 3231
3232 3232 #ifndef CC_INTERP
3233 3233 // C++ interp handles this in the interpreter
3234 3234 check_and_handle_popframe(java_thread);
3235 3235 check_and_handle_earlyret(java_thread);
3236 3236 #endif /* CC_INTERP */
3237 3237
3238 3238 if (check_exceptions) {
3239 3239 // check for pending exceptions (java_thread is set upon return)
3240 3240 cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
3241 3241 jump_cc(Assembler::notEqual,
3242 3242 RuntimeAddress(StubRoutines::forward_exception_entry()));
3243 3243 }
3244 3244
3245 3245 // get oop result if there is one and reset the value in the thread
3246 3246 if (oop_result->is_valid()) {
3247 3247 movl(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
3248 3248 movl(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
3249 3249 verify_oop(oop_result);
3250 3250 }
3251 3251 }
3252 3252
3253 3253
3254 3254 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
3255 3255 }
3256 3256
3257 3257 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
3258 3258 }
3259 3259
3260 3260 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
3261 3261 leal(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
3262 3262 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
3263 3263 }
3264 3264
3265 3265
3266 3266 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
3267 3267 Label C, E;
3268 3268 call(C, relocInfo::none);
3269 3269 jmp(E);
3270 3270
3271 3271 bind(C);
3272 3272 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
3273 3273 ret(0);
3274 3274
3275 3275 bind(E);
3276 3276 }
3277 3277
3278 3278
3279 3279 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
3280 3280 Label C, E;
3281 3281 call(C, relocInfo::none);
3282 3282 jmp(E);
3283 3283
3284 3284 bind(C);
3285 3285 pushl(arg_1);
3286 3286 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
3287 3287 ret(0);
3288 3288
3289 3289 bind(E);
3290 3290 }
3291 3291
3292 3292
3293 3293 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
3294 3294 Label C, E;
3295 3295 call(C, relocInfo::none);
3296 3296 jmp(E);
3297 3297
3298 3298 bind(C);
3299 3299 pushl(arg_2);
3300 3300 pushl(arg_1);
3301 3301 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
3302 3302 ret(0);
3303 3303
3304 3304 bind(E);
3305 3305 }
3306 3306
3307 3307
3308 3308 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
3309 3309 Label C, E;
3310 3310 call(C, relocInfo::none);
3311 3311 jmp(E);
3312 3312
3313 3313 bind(C);
3314 3314 pushl(arg_3);
3315 3315 pushl(arg_2);
3316 3316 pushl(arg_1);
3317 3317 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
3318 3318 ret(0);
3319 3319
3320 3320 bind(E);
3321 3321 }
3322 3322
3323 3323
3324 3324 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
3325 3325 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
3326 3326 }
3327 3327
3328 3328
3329 3329 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
3330 3330 pushl(arg_1);
3331 3331 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
3332 3332 }
3333 3333
3334 3334
3335 3335 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
3336 3336 pushl(arg_2);
3337 3337 pushl(arg_1);
3338 3338 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
3339 3339 }
3340 3340
3341 3341
3342 3342 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
3343 3343 pushl(arg_3);
3344 3344 pushl(arg_2);
3345 3345 pushl(arg_1);
3346 3346 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
3347 3347 }
3348 3348
3349 3349
3350 3350 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
3351 3351 call_VM_leaf_base(entry_point, number_of_arguments);
3352 3352 }
3353 3353
3354 3354
3355 3355 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
3356 3356 pushl(arg_1);
3357 3357 call_VM_leaf(entry_point, 1);
3358 3358 }
3359 3359
3360 3360
3361 3361 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
3362 3362 pushl(arg_2);
3363 3363 pushl(arg_1);
3364 3364 call_VM_leaf(entry_point, 2);
3365 3365 }
3366 3366
3367 3367
3368 3368 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
3369 3369 pushl(arg_3);
3370 3370 pushl(arg_2);
3371 3371 pushl(arg_1);
3372 3372 call_VM_leaf(entry_point, 3);
3373 3373 }
3374 3374
3375 3375
3376 3376 // Calls to C land
3377 3377 //
3378 3378 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3379 3379 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3380 3380 // has to be reset to 0. This is required to allow proper stack traversal.
3381 3381
3382 3382 void MacroAssembler::store_check(Register obj) {
3383 3383 // Does a store check for the oop in register obj. The content of
3384 3384 // register obj is destroyed afterwards.
3385 3385 store_check_part_1(obj);
3386 3386 store_check_part_2(obj);
3387 3387 }
3388 3388
3389 3389
3390 3390 void MacroAssembler::store_check(Register obj, Address dst) {
3391 3391 store_check(obj);
3392 3392 }
3393 3393
3394 3394
3395 3395 // split the store check operation so that other instructions can be scheduled inbetween
3396 3396 void MacroAssembler::store_check_part_1(Register obj) {
3397 3397 BarrierSet* bs = Universe::heap()->barrier_set();
|
↓ open down ↓ |
3397 lines elided |
↑ open up ↑ |
3398 3398 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3399 3399 shrl(obj, CardTableModRefBS::card_shift);
3400 3400 }
3401 3401
3402 3402
3403 3403 void MacroAssembler::store_check_part_2(Register obj) {
3404 3404 BarrierSet* bs = Universe::heap()->barrier_set();
3405 3405 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3406 3406 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3407 3407 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3408 - ExternalAddress cardtable((address)ct->byte_map_base);
3409 - Address index(noreg, obj, Address::times_1);
3410 3408
3411 - movb(as_Address(ArrayAddress(cardtable, index)), 0);
3409 + // The calculation for byte_map_base is as follows:
3410 + // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
3411 + // So this essentially converts an address to a displacement and
3412 + // it will never need to be relocated. On 64bit however the value may be too
3413 + // large for a 32bit displacement
3414 +
3415 + intptr_t disp = (intptr_t) ct->byte_map_base;
3416 + Address cardtable(noreg, obj, Address::times_1, disp);
3417 + movb(cardtable, 0);
3412 3418 }
3413 3419
3414 3420
3415 3421 void MacroAssembler::c2bool(Register x) {
3416 3422 // implements x == 0 ? 0 : 1
3417 3423 // note: must only look at least-significant byte of x
3418 3424 // since C-style booleans are stored in one byte
3419 3425 // only! (was bug)
3420 3426 andl(x, 0xFF);
3421 3427 setb(Assembler::notZero, x);
3422 3428 }
3423 3429
3424 3430
3425 3431 int MacroAssembler::corrected_idivl(Register reg) {
3426 3432 // Full implementation of Java idiv and irem; checks for
3427 3433 // special case as described in JVM spec., p.243 & p.271.
3428 3434 // The function returns the (pc) offset of the idivl
3429 3435 // instruction - may be needed for implicit exceptions.
3430 3436 //
3431 3437 // normal case special case
3432 3438 //
3433 3439 // input : rax,: dividend min_int
3434 3440 // reg: divisor (may not be rax,/rdx) -1
3435 3441 //
3436 3442 // output: rax,: quotient (= rax, idiv reg) min_int
3437 3443 // rdx: remainder (= rax, irem reg) 0
3438 3444 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
3439 3445 const int min_int = 0x80000000;
3440 3446 Label normal_case, special_case;
3441 3447
3442 3448 // check for special case
3443 3449 cmpl(rax, min_int);
3444 3450 jcc(Assembler::notEqual, normal_case);
3445 3451 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
3446 3452 cmpl(reg, -1);
3447 3453 jcc(Assembler::equal, special_case);
3448 3454
3449 3455 // handle normal case
3450 3456 bind(normal_case);
3451 3457 cdql();
3452 3458 int idivl_offset = offset();
3453 3459 idivl(reg);
3454 3460
3455 3461 // normal and special case exit
3456 3462 bind(special_case);
3457 3463
3458 3464 return idivl_offset;
3459 3465 }
3460 3466
3461 3467
3462 3468 void MacroAssembler::lneg(Register hi, Register lo) {
3463 3469 negl(lo);
3464 3470 adcl(hi, 0);
3465 3471 negl(hi);
3466 3472 }
3467 3473
3468 3474
3469 3475 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
3470 3476 // Multiplication of two Java long values stored on the stack
3471 3477 // as illustrated below. Result is in rdx:rax.
3472 3478 //
3473 3479 // rsp ---> [ ?? ] \ \
3474 3480 // .... | y_rsp_offset |
3475 3481 // [ y_lo ] / (in bytes) | x_rsp_offset
3476 3482 // [ y_hi ] | (in bytes)
3477 3483 // .... |
3478 3484 // [ x_lo ] /
3479 3485 // [ x_hi ]
3480 3486 // ....
3481 3487 //
3482 3488 // Basic idea: lo(result) = lo(x_lo * y_lo)
3483 3489 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3484 3490 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
3485 3491 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
3486 3492 Label quick;
3487 3493 // load x_hi, y_hi and check if quick
3488 3494 // multiplication is possible
3489 3495 movl(rbx, x_hi);
3490 3496 movl(rcx, y_hi);
3491 3497 movl(rax, rbx);
3492 3498 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
3493 3499 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
3494 3500 // do full multiplication
3495 3501 // 1st step
3496 3502 mull(y_lo); // x_hi * y_lo
3497 3503 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
3498 3504 // 2nd step
3499 3505 movl(rax, x_lo);
3500 3506 mull(rcx); // x_lo * y_hi
3501 3507 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
3502 3508 // 3rd step
3503 3509 bind(quick); // note: rbx, = 0 if quick multiply!
3504 3510 movl(rax, x_lo);
3505 3511 mull(y_lo); // x_lo * y_lo
3506 3512 addl(rdx, rbx); // correct hi(x_lo * y_lo)
3507 3513 }
3508 3514
3509 3515
3510 3516 void MacroAssembler::lshl(Register hi, Register lo) {
3511 3517 // Java shift left long support (semantics as described in JVM spec., p.305)
3512 3518 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
3513 3519 // shift value is in rcx !
3514 3520 assert(hi != rcx, "must not use rcx");
3515 3521 assert(lo != rcx, "must not use rcx");
3516 3522 const Register s = rcx; // shift count
3517 3523 const int n = BitsPerWord;
3518 3524 Label L;
3519 3525 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
3520 3526 cmpl(s, n); // if (s < n)
3521 3527 jcc(Assembler::less, L); // else (s >= n)
3522 3528 movl(hi, lo); // x := x << n
3523 3529 xorl(lo, lo);
3524 3530 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
3525 3531 bind(L); // s (mod n) < n
3526 3532 shldl(hi, lo); // x := x << s
3527 3533 shll(lo);
3528 3534 }
3529 3535
3530 3536
3531 3537 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
3532 3538 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
3533 3539 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
3534 3540 assert(hi != rcx, "must not use rcx");
3535 3541 assert(lo != rcx, "must not use rcx");
3536 3542 const Register s = rcx; // shift count
3537 3543 const int n = BitsPerWord;
3538 3544 Label L;
3539 3545 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
3540 3546 cmpl(s, n); // if (s < n)
3541 3547 jcc(Assembler::less, L); // else (s >= n)
3542 3548 movl(lo, hi); // x := x >> n
3543 3549 if (sign_extension) sarl(hi, 31);
3544 3550 else xorl(hi, hi);
3545 3551 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
3546 3552 bind(L); // s (mod n) < n
3547 3553 shrdl(lo, hi); // x := x >> s
3548 3554 if (sign_extension) sarl(hi);
3549 3555 else shrl(hi);
3550 3556 }
3551 3557
3552 3558
3553 3559 // Note: y_lo will be destroyed
3554 3560 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
3555 3561 // Long compare for Java (semantics as described in JVM spec.)
3556 3562 Label high, low, done;
3557 3563
3558 3564 cmpl(x_hi, y_hi);
3559 3565 jcc(Assembler::less, low);
3560 3566 jcc(Assembler::greater, high);
3561 3567 // x_hi is the return register
3562 3568 xorl(x_hi, x_hi);
3563 3569 cmpl(x_lo, y_lo);
3564 3570 jcc(Assembler::below, low);
3565 3571 jcc(Assembler::equal, done);
3566 3572
3567 3573 bind(high);
3568 3574 xorl(x_hi, x_hi);
3569 3575 increment(x_hi);
3570 3576 jmp(done);
3571 3577
3572 3578 bind(low);
3573 3579 xorl(x_hi, x_hi);
3574 3580 decrement(x_hi);
3575 3581
3576 3582 bind(done);
3577 3583 }
3578 3584
3579 3585
3580 3586 void MacroAssembler::save_rax(Register tmp) {
3581 3587 if (tmp == noreg) pushl(rax);
3582 3588 else if (tmp != rax) movl(tmp, rax);
3583 3589 }
3584 3590
3585 3591
3586 3592 void MacroAssembler::restore_rax(Register tmp) {
3587 3593 if (tmp == noreg) popl(rax);
3588 3594 else if (tmp != rax) movl(rax, tmp);
3589 3595 }
3590 3596
3591 3597
3592 3598 void MacroAssembler::fremr(Register tmp) {
3593 3599 save_rax(tmp);
3594 3600 { Label L;
3595 3601 bind(L);
3596 3602 fprem();
3597 3603 fwait(); fnstsw_ax();
3598 3604 sahf();
3599 3605 jcc(Assembler::parity, L);
3600 3606 }
3601 3607 restore_rax(tmp);
3602 3608 // Result is in ST0.
3603 3609 // Note: fxch & fpop to get rid of ST1
3604 3610 // (otherwise FPU stack could overflow eventually)
3605 3611 fxch(1);
3606 3612 fpop();
3607 3613 }
3608 3614
3609 3615
3610 3616 static const double pi_4 = 0.7853981633974483;
3611 3617
3612 3618 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
3613 3619 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
3614 3620 // was attempted in this code; unfortunately it appears that the
3615 3621 // switch to 80-bit precision and back causes this to be
3616 3622 // unprofitable compared with simply performing a runtime call if
3617 3623 // the argument is out of the (-pi/4, pi/4) range.
3618 3624
3619 3625 Register tmp = noreg;
3620 3626 if (!VM_Version::supports_cmov()) {
3621 3627 // fcmp needs a temporary so preserve rbx,
3622 3628 tmp = rbx;
3623 3629 pushl(tmp);
3624 3630 }
3625 3631
3626 3632 Label slow_case, done;
3627 3633
3628 3634 // x ?<= pi/4
3629 3635 fld_d(ExternalAddress((address)&pi_4));
3630 3636 fld_s(1); // Stack: X PI/4 X
3631 3637 fabs(); // Stack: |X| PI/4 X
3632 3638 fcmp(tmp);
3633 3639 jcc(Assembler::above, slow_case);
3634 3640
3635 3641 // fastest case: -pi/4 <= x <= pi/4
3636 3642 switch(trig) {
3637 3643 case 's':
3638 3644 fsin();
3639 3645 break;
3640 3646 case 'c':
3641 3647 fcos();
3642 3648 break;
3643 3649 case 't':
3644 3650 ftan();
3645 3651 break;
3646 3652 default:
3647 3653 assert(false, "bad intrinsic");
3648 3654 break;
3649 3655 }
3650 3656 jmp(done);
3651 3657
3652 3658 // slow case: runtime call
3653 3659 bind(slow_case);
3654 3660 // Preserve registers across runtime call
3655 3661 pushad();
3656 3662 int incoming_argument_and_return_value_offset = -1;
3657 3663 if (num_fpu_regs_in_use > 1) {
3658 3664 // Must preserve all other FPU regs (could alternatively convert
3659 3665 // SharedRuntime::dsin and dcos into assembly routines known not to trash
3660 3666 // FPU state, but can not trust C compiler)
3661 3667 NEEDS_CLEANUP;
3662 3668 // NOTE that in this case we also push the incoming argument to
3663 3669 // the stack and restore it later; we also use this stack slot to
3664 3670 // hold the return value from dsin or dcos.
3665 3671 for (int i = 0; i < num_fpu_regs_in_use; i++) {
3666 3672 subl(rsp, wordSize*2);
3667 3673 fstp_d(Address(rsp, 0));
3668 3674 }
3669 3675 incoming_argument_and_return_value_offset = 2*wordSize*(num_fpu_regs_in_use-1);
3670 3676 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
3671 3677 }
3672 3678 subl(rsp, wordSize*2);
3673 3679 fstp_d(Address(rsp, 0));
3674 3680 // NOTE: we must not use call_VM_leaf here because that requires a
3675 3681 // complete interpreter frame in debug mode -- same bug as 4387334
3676 3682 NEEDS_CLEANUP;
3677 3683 // Need to add stack banging before this runtime call if it needs to
3678 3684 // be taken; however, there is no generic stack banging routine at
3679 3685 // the MacroAssembler level
3680 3686 switch(trig) {
3681 3687 case 's':
3682 3688 {
3683 3689 call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dsin)));
3684 3690 }
3685 3691 break;
3686 3692 case 'c':
3687 3693 {
3688 3694 call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dcos)));
3689 3695 }
3690 3696 break;
3691 3697 case 't':
3692 3698 {
3693 3699 call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtan)));
3694 3700 }
3695 3701 break;
3696 3702 default:
3697 3703 assert(false, "bad intrinsic");
3698 3704 break;
3699 3705 }
3700 3706 addl(rsp, wordSize * 2);
3701 3707 if (num_fpu_regs_in_use > 1) {
3702 3708 // Must save return value to stack and then restore entire FPU stack
3703 3709 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
3704 3710 for (int i = 0; i < num_fpu_regs_in_use; i++) {
3705 3711 fld_d(Address(rsp, 0));
3706 3712 addl(rsp, wordSize*2);
3707 3713 }
3708 3714 }
3709 3715 popad();
3710 3716
3711 3717 // Come here with result in F-TOS
3712 3718 bind(done);
3713 3719
3714 3720 if (tmp != noreg) {
3715 3721 popl(tmp);
3716 3722 }
3717 3723 }
3718 3724
3719 3725 void MacroAssembler::jC2(Register tmp, Label& L) {
3720 3726 // set parity bit if FPU flag C2 is set (via rax)
3721 3727 save_rax(tmp);
3722 3728 fwait(); fnstsw_ax();
3723 3729 sahf();
3724 3730 restore_rax(tmp);
3725 3731 // branch
3726 3732 jcc(Assembler::parity, L);
3727 3733 }
3728 3734
3729 3735
3730 3736 void MacroAssembler::jnC2(Register tmp, Label& L) {
3731 3737 // set parity bit if FPU flag C2 is set (via rax)
3732 3738 save_rax(tmp);
3733 3739 fwait(); fnstsw_ax();
3734 3740 sahf();
3735 3741 restore_rax(tmp);
3736 3742 // branch
3737 3743 jcc(Assembler::noParity, L);
3738 3744 }
3739 3745
3740 3746
3741 3747 void MacroAssembler::fcmp(Register tmp) {
3742 3748 fcmp(tmp, 1, true, true);
3743 3749 }
3744 3750
3745 3751
3746 3752 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3747 3753 assert(!pop_right || pop_left, "usage error");
3748 3754 if (VM_Version::supports_cmov()) {
3749 3755 assert(tmp == noreg, "unneeded temp");
3750 3756 if (pop_left) {
3751 3757 fucomip(index);
3752 3758 } else {
3753 3759 fucomi(index);
3754 3760 }
3755 3761 if (pop_right) {
3756 3762 fpop();
3757 3763 }
3758 3764 } else {
3759 3765 assert(tmp != noreg, "need temp");
3760 3766 if (pop_left) {
3761 3767 if (pop_right) {
3762 3768 fcompp();
3763 3769 } else {
3764 3770 fcomp(index);
3765 3771 }
3766 3772 } else {
3767 3773 fcom(index);
3768 3774 }
3769 3775 // convert FPU condition into eflags condition via rax,
3770 3776 save_rax(tmp);
3771 3777 fwait(); fnstsw_ax();
3772 3778 sahf();
3773 3779 restore_rax(tmp);
3774 3780 }
3775 3781 // condition codes set as follows:
3776 3782 //
3777 3783 // CF (corresponds to C0) if x < y
3778 3784 // PF (corresponds to C2) if unordered
3779 3785 // ZF (corresponds to C3) if x = y
3780 3786 }
3781 3787
3782 3788
3783 3789 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3784 3790 fcmp2int(dst, unordered_is_less, 1, true, true);
3785 3791 }
3786 3792
3787 3793
3788 3794 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3789 3795 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3790 3796 Label L;
3791 3797 if (unordered_is_less) {
3792 3798 movl(dst, -1);
3793 3799 jcc(Assembler::parity, L);
3794 3800 jcc(Assembler::below , L);
3795 3801 movl(dst, 0);
3796 3802 jcc(Assembler::equal , L);
3797 3803 increment(dst);
3798 3804 } else { // unordered is greater
3799 3805 movl(dst, 1);
3800 3806 jcc(Assembler::parity, L);
3801 3807 jcc(Assembler::above , L);
3802 3808 movl(dst, 0);
3803 3809 jcc(Assembler::equal , L);
3804 3810 decrement(dst);
3805 3811 }
3806 3812 bind(L);
3807 3813 }
3808 3814
3809 3815 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
3810 3816 ucomiss(opr1, opr2);
3811 3817
3812 3818 Label L;
3813 3819 if (unordered_is_less) {
3814 3820 movl(dst, -1);
3815 3821 jcc(Assembler::parity, L);
3816 3822 jcc(Assembler::below , L);
3817 3823 movl(dst, 0);
3818 3824 jcc(Assembler::equal , L);
3819 3825 increment(dst);
3820 3826 } else { // unordered is greater
3821 3827 movl(dst, 1);
3822 3828 jcc(Assembler::parity, L);
3823 3829 jcc(Assembler::above , L);
3824 3830 movl(dst, 0);
3825 3831 jcc(Assembler::equal , L);
3826 3832 decrement(dst);
3827 3833 }
3828 3834 bind(L);
3829 3835 }
3830 3836
3831 3837 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
3832 3838 ucomisd(opr1, opr2);
3833 3839
3834 3840 Label L;
3835 3841 if (unordered_is_less) {
3836 3842 movl(dst, -1);
3837 3843 jcc(Assembler::parity, L);
3838 3844 jcc(Assembler::below , L);
3839 3845 movl(dst, 0);
3840 3846 jcc(Assembler::equal , L);
3841 3847 increment(dst);
3842 3848 } else { // unordered is greater
3843 3849 movl(dst, 1);
3844 3850 jcc(Assembler::parity, L);
3845 3851 jcc(Assembler::above , L);
3846 3852 movl(dst, 0);
3847 3853 jcc(Assembler::equal , L);
3848 3854 decrement(dst);
3849 3855 }
3850 3856 bind(L);
3851 3857 }
3852 3858
3853 3859
3854 3860
3855 3861 void MacroAssembler::fpop() {
3856 3862 ffree();
3857 3863 fincstp();
3858 3864 }
3859 3865
3860 3866
3861 3867 void MacroAssembler::sign_extend_short(Register reg) {
3862 3868 if (VM_Version::is_P6()) {
3863 3869 movsxw(reg, reg);
3864 3870 } else {
3865 3871 shll(reg, 16);
3866 3872 sarl(reg, 16);
3867 3873 }
3868 3874 }
3869 3875
3870 3876
3871 3877 void MacroAssembler::sign_extend_byte(Register reg) {
3872 3878 if (VM_Version::is_P6() && reg->has_byte_register()) {
3873 3879 movsxb(reg, reg);
3874 3880 } else {
3875 3881 shll(reg, 24);
3876 3882 sarl(reg, 24);
3877 3883 }
3878 3884 }
3879 3885
3880 3886
3881 3887 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
3882 3888 assert (shift_value > 0, "illegal shift value");
3883 3889 Label _is_positive;
3884 3890 testl (reg, reg);
3885 3891 jcc (Assembler::positive, _is_positive);
3886 3892 int offset = (1 << shift_value) - 1 ;
3887 3893
3888 3894 increment(reg, offset);
3889 3895
3890 3896 bind (_is_positive);
3891 3897 sarl(reg, shift_value);
3892 3898 }
3893 3899
3894 3900
3895 3901 void MacroAssembler::round_to(Register reg, int modulus) {
3896 3902 addl(reg, modulus - 1);
3897 3903 andl(reg, -modulus);
3898 3904 }
3899 3905
3900 3906 // C++ bool manipulation
3901 3907
3902 3908 void MacroAssembler::movbool(Register dst, Address src) {
3903 3909 if(sizeof(bool) == 1)
3904 3910 movb(dst, src);
3905 3911 else if(sizeof(bool) == 2)
3906 3912 movw(dst, src);
3907 3913 else if(sizeof(bool) == 4)
3908 3914 movl(dst, src);
3909 3915 else
3910 3916 // unsupported
3911 3917 ShouldNotReachHere();
3912 3918 }
3913 3919
3914 3920 void MacroAssembler::movbool(Address dst, bool boolconst) {
3915 3921 if(sizeof(bool) == 1)
3916 3922 movb(dst, (int) boolconst);
3917 3923 else if(sizeof(bool) == 2)
3918 3924 movw(dst, (int) boolconst);
3919 3925 else if(sizeof(bool) == 4)
3920 3926 movl(dst, (int) boolconst);
3921 3927 else
3922 3928 // unsupported
3923 3929 ShouldNotReachHere();
3924 3930 }
3925 3931
3926 3932 void MacroAssembler::movbool(Address dst, Register src) {
3927 3933 if(sizeof(bool) == 1)
3928 3934 movb(dst, src);
3929 3935 else if(sizeof(bool) == 2)
3930 3936 movw(dst, src);
3931 3937 else if(sizeof(bool) == 4)
3932 3938 movl(dst, src);
3933 3939 else
3934 3940 // unsupported
3935 3941 ShouldNotReachHere();
3936 3942 }
3937 3943
3938 3944 void MacroAssembler::testbool(Register dst) {
3939 3945 if(sizeof(bool) == 1)
3940 3946 testb(dst, (int) 0xff);
3941 3947 else if(sizeof(bool) == 2) {
3942 3948 // testw implementation needed for two byte bools
3943 3949 ShouldNotReachHere();
3944 3950 } else if(sizeof(bool) == 4)
3945 3951 testl(dst, dst);
3946 3952 else
3947 3953 // unsupported
3948 3954 ShouldNotReachHere();
3949 3955 }
3950 3956
3951 3957 void MacroAssembler::verify_oop(Register reg, const char* s) {
3952 3958 if (!VerifyOops) return;
3953 3959 // Pass register number to verify_oop_subroutine
3954 3960 char* b = new char[strlen(s) + 50];
3955 3961 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
3956 3962 pushl(rax); // save rax,
3957 3963 pushl(reg); // pass register argument
3958 3964 ExternalAddress buffer((address) b);
3959 3965 pushptr(buffer.addr());
3960 3966 // call indirectly to solve generation ordering problem
3961 3967 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
3962 3968 call(rax);
3963 3969 }
3964 3970
3965 3971
3966 3972 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
3967 3973 if (!VerifyOops) return;
3968 3974 // QQQ fix this
3969 3975 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
3970 3976 // Pass register number to verify_oop_subroutine
3971 3977 char* b = new char[strlen(s) + 50];
3972 3978 sprintf(b, "verify_oop_addr: %s", s);
3973 3979 pushl(rax); // save rax,
3974 3980 // addr may contain rsp so we will have to adjust it based on the push
3975 3981 // we just did
3976 3982 if (addr.uses(rsp)) {
3977 3983 leal(rax, addr);
3978 3984 pushl(Address(rax, BytesPerWord));
3979 3985 } else {
3980 3986 pushl(addr);
3981 3987 }
3982 3988 ExternalAddress buffer((address) b);
3983 3989 // pass msg argument
3984 3990 pushptr(buffer.addr());
3985 3991 // call indirectly to solve generation ordering problem
3986 3992 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
3987 3993 call(rax);
3988 3994 // Caller pops the arguments and restores rax, from the stack
3989 3995 }
3990 3996
3991 3997
3992 3998 void MacroAssembler::stop(const char* msg) {
3993 3999 ExternalAddress message((address)msg);
3994 4000 // push address of message
3995 4001 pushptr(message.addr());
3996 4002 { Label L; call(L, relocInfo::none); bind(L); } // push eip
3997 4003 pushad(); // push registers
3998 4004 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
3999 4005 hlt();
4000 4006 }
4001 4007
4002 4008
4003 4009 void MacroAssembler::warn(const char* msg) {
4004 4010 push_CPU_state();
4005 4011
4006 4012 ExternalAddress message((address) msg);
4007 4013 // push address of message
4008 4014 pushptr(message.addr());
4009 4015
4010 4016 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
4011 4017 addl(rsp, wordSize); // discard argument
4012 4018 pop_CPU_state();
4013 4019 }
4014 4020
4015 4021
4016 4022 void MacroAssembler::debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
4017 4023 // In order to get locks to work, we need to fake a in_VM state
4018 4024 JavaThread* thread = JavaThread::current();
4019 4025 JavaThreadState saved_state = thread->thread_state();
4020 4026 thread->set_thread_state(_thread_in_vm);
4021 4027 if (ShowMessageBoxOnError) {
4022 4028 JavaThread* thread = JavaThread::current();
4023 4029 JavaThreadState saved_state = thread->thread_state();
4024 4030 thread->set_thread_state(_thread_in_vm);
4025 4031 ttyLocker ttyl;
4026 4032 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
4027 4033 BytecodeCounter::print();
4028 4034 }
4029 4035 // To see where a verify_oop failed, get $ebx+40/X for this frame.
4030 4036 // This is the value of eip which points to where verify_oop will return.
4031 4037 if (os::message_box(msg, "Execution stopped, print registers?")) {
4032 4038 tty->print_cr("eip = 0x%08x", eip);
4033 4039 tty->print_cr("rax, = 0x%08x", rax);
4034 4040 tty->print_cr("rbx, = 0x%08x", rbx);
4035 4041 tty->print_cr("rcx = 0x%08x", rcx);
4036 4042 tty->print_cr("rdx = 0x%08x", rdx);
4037 4043 tty->print_cr("rdi = 0x%08x", rdi);
4038 4044 tty->print_cr("rsi = 0x%08x", rsi);
4039 4045 tty->print_cr("rbp, = 0x%08x", rbp);
4040 4046 tty->print_cr("rsp = 0x%08x", rsp);
4041 4047 BREAKPOINT;
4042 4048 }
4043 4049 } else {
4044 4050 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
4045 4051 assert(false, "DEBUG MESSAGE");
4046 4052 }
4047 4053 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
4048 4054 }
4049 4055
4050 4056
4051 4057
4052 4058 void MacroAssembler::os_breakpoint() {
4053 4059 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
4054 4060 // (e.g., MSVC can't call ps() otherwise)
4055 4061 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
4056 4062 }
4057 4063
4058 4064
4059 4065 void MacroAssembler::push_fTOS() {
4060 4066 subl(rsp, 2 * wordSize);
4061 4067 fstp_d(Address(rsp, 0));
4062 4068 }
4063 4069
4064 4070
4065 4071 void MacroAssembler::pop_fTOS() {
4066 4072 fld_d(Address(rsp, 0));
4067 4073 addl(rsp, 2 * wordSize);
4068 4074 }
4069 4075
4070 4076
4071 4077 void MacroAssembler::empty_FPU_stack() {
4072 4078 if (VM_Version::supports_mmx()) {
4073 4079 emms();
4074 4080 } else {
4075 4081 for (int i = 8; i-- > 0; ) ffree(i);
4076 4082 }
4077 4083 }
4078 4084
4079 4085
4080 4086 class ControlWord {
4081 4087 public:
4082 4088 int32_t _value;
4083 4089
4084 4090 int rounding_control() const { return (_value >> 10) & 3 ; }
4085 4091 int precision_control() const { return (_value >> 8) & 3 ; }
4086 4092 bool precision() const { return ((_value >> 5) & 1) != 0; }
4087 4093 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4088 4094 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4089 4095 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4090 4096 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4091 4097 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4092 4098
4093 4099 void print() const {
4094 4100 // rounding control
4095 4101 const char* rc;
4096 4102 switch (rounding_control()) {
4097 4103 case 0: rc = "round near"; break;
4098 4104 case 1: rc = "round down"; break;
4099 4105 case 2: rc = "round up "; break;
4100 4106 case 3: rc = "chop "; break;
4101 4107 };
4102 4108 // precision control
4103 4109 const char* pc;
4104 4110 switch (precision_control()) {
4105 4111 case 0: pc = "24 bits "; break;
4106 4112 case 1: pc = "reserved"; break;
4107 4113 case 2: pc = "53 bits "; break;
4108 4114 case 3: pc = "64 bits "; break;
4109 4115 };
4110 4116 // flags
4111 4117 char f[9];
4112 4118 f[0] = ' ';
4113 4119 f[1] = ' ';
4114 4120 f[2] = (precision ()) ? 'P' : 'p';
4115 4121 f[3] = (underflow ()) ? 'U' : 'u';
4116 4122 f[4] = (overflow ()) ? 'O' : 'o';
4117 4123 f[5] = (zero_divide ()) ? 'Z' : 'z';
4118 4124 f[6] = (denormalized()) ? 'D' : 'd';
4119 4125 f[7] = (invalid ()) ? 'I' : 'i';
4120 4126 f[8] = '\x0';
4121 4127 // output
4122 4128 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4123 4129 }
4124 4130
4125 4131 };
4126 4132
4127 4133
4128 4134 class StatusWord {
4129 4135 public:
4130 4136 int32_t _value;
4131 4137
4132 4138 bool busy() const { return ((_value >> 15) & 1) != 0; }
4133 4139 bool C3() const { return ((_value >> 14) & 1) != 0; }
4134 4140 bool C2() const { return ((_value >> 10) & 1) != 0; }
4135 4141 bool C1() const { return ((_value >> 9) & 1) != 0; }
4136 4142 bool C0() const { return ((_value >> 8) & 1) != 0; }
4137 4143 int top() const { return (_value >> 11) & 7 ; }
4138 4144 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4139 4145 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4140 4146 bool precision() const { return ((_value >> 5) & 1) != 0; }
4141 4147 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4142 4148 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4143 4149 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4144 4150 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4145 4151 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4146 4152
4147 4153 void print() const {
4148 4154 // condition codes
4149 4155 char c[5];
4150 4156 c[0] = (C3()) ? '3' : '-';
4151 4157 c[1] = (C2()) ? '2' : '-';
4152 4158 c[2] = (C1()) ? '1' : '-';
4153 4159 c[3] = (C0()) ? '0' : '-';
4154 4160 c[4] = '\x0';
4155 4161 // flags
4156 4162 char f[9];
4157 4163 f[0] = (error_status()) ? 'E' : '-';
4158 4164 f[1] = (stack_fault ()) ? 'S' : '-';
4159 4165 f[2] = (precision ()) ? 'P' : '-';
4160 4166 f[3] = (underflow ()) ? 'U' : '-';
4161 4167 f[4] = (overflow ()) ? 'O' : '-';
4162 4168 f[5] = (zero_divide ()) ? 'Z' : '-';
4163 4169 f[6] = (denormalized()) ? 'D' : '-';
4164 4170 f[7] = (invalid ()) ? 'I' : '-';
4165 4171 f[8] = '\x0';
4166 4172 // output
4167 4173 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4168 4174 }
4169 4175
4170 4176 };
4171 4177
4172 4178
4173 4179 class TagWord {
4174 4180 public:
4175 4181 int32_t _value;
4176 4182
4177 4183 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4178 4184
4179 4185 void print() const {
4180 4186 printf("%04x", _value & 0xFFFF);
4181 4187 }
4182 4188
4183 4189 };
4184 4190
4185 4191
4186 4192 class FPU_Register {
4187 4193 public:
4188 4194 int32_t _m0;
4189 4195 int32_t _m1;
4190 4196 int16_t _ex;
4191 4197
4192 4198 bool is_indefinite() const {
4193 4199 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4194 4200 }
4195 4201
4196 4202 void print() const {
4197 4203 char sign = (_ex < 0) ? '-' : '+';
4198 4204 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4199 4205 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4200 4206 };
4201 4207
4202 4208 };
4203 4209
4204 4210
4205 4211 class FPU_State {
4206 4212 public:
4207 4213 enum {
4208 4214 register_size = 10,
4209 4215 number_of_registers = 8,
4210 4216 register_mask = 7
4211 4217 };
4212 4218
4213 4219 ControlWord _control_word;
4214 4220 StatusWord _status_word;
4215 4221 TagWord _tag_word;
4216 4222 int32_t _error_offset;
4217 4223 int32_t _error_selector;
4218 4224 int32_t _data_offset;
4219 4225 int32_t _data_selector;
4220 4226 int8_t _register[register_size * number_of_registers];
4221 4227
4222 4228 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4223 4229 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4224 4230
4225 4231 const char* tag_as_string(int tag) const {
4226 4232 switch (tag) {
4227 4233 case 0: return "valid";
4228 4234 case 1: return "zero";
4229 4235 case 2: return "special";
4230 4236 case 3: return "empty";
4231 4237 }
4232 4238 ShouldNotReachHere()
4233 4239 return NULL;
4234 4240 }
4235 4241
4236 4242 void print() const {
4237 4243 // print computation registers
4238 4244 { int t = _status_word.top();
4239 4245 for (int i = 0; i < number_of_registers; i++) {
4240 4246 int j = (i - t) & register_mask;
4241 4247 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4242 4248 st(j)->print();
4243 4249 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4244 4250 }
4245 4251 }
4246 4252 printf("\n");
4247 4253 // print control registers
4248 4254 printf("ctrl = "); _control_word.print(); printf("\n");
4249 4255 printf("stat = "); _status_word .print(); printf("\n");
4250 4256 printf("tags = "); _tag_word .print(); printf("\n");
4251 4257 }
4252 4258
4253 4259 };
4254 4260
4255 4261
4256 4262 class Flag_Register {
4257 4263 public:
4258 4264 int32_t _value;
4259 4265
4260 4266 bool overflow() const { return ((_value >> 11) & 1) != 0; }
4261 4267 bool direction() const { return ((_value >> 10) & 1) != 0; }
4262 4268 bool sign() const { return ((_value >> 7) & 1) != 0; }
4263 4269 bool zero() const { return ((_value >> 6) & 1) != 0; }
4264 4270 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
4265 4271 bool parity() const { return ((_value >> 2) & 1) != 0; }
4266 4272 bool carry() const { return ((_value >> 0) & 1) != 0; }
4267 4273
4268 4274 void print() const {
4269 4275 // flags
4270 4276 char f[8];
4271 4277 f[0] = (overflow ()) ? 'O' : '-';
4272 4278 f[1] = (direction ()) ? 'D' : '-';
4273 4279 f[2] = (sign ()) ? 'S' : '-';
4274 4280 f[3] = (zero ()) ? 'Z' : '-';
4275 4281 f[4] = (auxiliary_carry()) ? 'A' : '-';
4276 4282 f[5] = (parity ()) ? 'P' : '-';
4277 4283 f[6] = (carry ()) ? 'C' : '-';
4278 4284 f[7] = '\x0';
4279 4285 // output
4280 4286 printf("%08x flags = %s", _value, f);
4281 4287 }
4282 4288
4283 4289 };
4284 4290
4285 4291
4286 4292 class IU_Register {
4287 4293 public:
4288 4294 int32_t _value;
4289 4295
4290 4296 void print() const {
4291 4297 printf("%08x %11d", _value, _value);
4292 4298 }
4293 4299
4294 4300 };
4295 4301
4296 4302
4297 4303 class IU_State {
4298 4304 public:
4299 4305 Flag_Register _eflags;
4300 4306 IU_Register _rdi;
4301 4307 IU_Register _rsi;
4302 4308 IU_Register _rbp;
4303 4309 IU_Register _rsp;
4304 4310 IU_Register _rbx;
4305 4311 IU_Register _rdx;
4306 4312 IU_Register _rcx;
4307 4313 IU_Register _rax;
4308 4314
4309 4315 void print() const {
4310 4316 // computation registers
4311 4317 printf("rax, = "); _rax.print(); printf("\n");
4312 4318 printf("rbx, = "); _rbx.print(); printf("\n");
4313 4319 printf("rcx = "); _rcx.print(); printf("\n");
4314 4320 printf("rdx = "); _rdx.print(); printf("\n");
4315 4321 printf("rdi = "); _rdi.print(); printf("\n");
4316 4322 printf("rsi = "); _rsi.print(); printf("\n");
4317 4323 printf("rbp, = "); _rbp.print(); printf("\n");
4318 4324 printf("rsp = "); _rsp.print(); printf("\n");
4319 4325 printf("\n");
4320 4326 // control registers
4321 4327 printf("flgs = "); _eflags.print(); printf("\n");
4322 4328 }
4323 4329 };
4324 4330
4325 4331
4326 4332 class CPU_State {
4327 4333 public:
4328 4334 FPU_State _fpu_state;
4329 4335 IU_State _iu_state;
4330 4336
4331 4337 void print() const {
4332 4338 printf("--------------------------------------------------\n");
4333 4339 _iu_state .print();
4334 4340 printf("\n");
4335 4341 _fpu_state.print();
4336 4342 printf("--------------------------------------------------\n");
4337 4343 }
4338 4344
4339 4345 };
4340 4346
4341 4347
4342 4348 static void _print_CPU_state(CPU_State* state) {
4343 4349 state->print();
4344 4350 };
4345 4351
4346 4352
4347 4353 void MacroAssembler::print_CPU_state() {
4348 4354 push_CPU_state();
4349 4355 pushl(rsp); // pass CPU state
4350 4356 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4351 4357 addl(rsp, wordSize); // discard argument
4352 4358 pop_CPU_state();
4353 4359 }
4354 4360
4355 4361
4356 4362 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4357 4363 static int counter = 0;
4358 4364 FPU_State* fs = &state->_fpu_state;
4359 4365 counter++;
4360 4366 // For leaf calls, only verify that the top few elements remain empty.
4361 4367 // We only need 1 empty at the top for C2 code.
4362 4368 if( stack_depth < 0 ) {
4363 4369 if( fs->tag_for_st(7) != 3 ) {
4364 4370 printf("FPR7 not empty\n");
4365 4371 state->print();
4366 4372 assert(false, "error");
4367 4373 return false;
4368 4374 }
4369 4375 return true; // All other stack states do not matter
4370 4376 }
4371 4377
4372 4378 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
4373 4379 "bad FPU control word");
4374 4380
4375 4381 // compute stack depth
4376 4382 int i = 0;
4377 4383 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
4378 4384 int d = i;
4379 4385 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4380 4386 // verify findings
4381 4387 if (i != FPU_State::number_of_registers) {
4382 4388 // stack not contiguous
4383 4389 printf("%s: stack not contiguous at ST%d\n", s, i);
4384 4390 state->print();
4385 4391 assert(false, "error");
4386 4392 return false;
4387 4393 }
4388 4394 // check if computed stack depth corresponds to expected stack depth
4389 4395 if (stack_depth < 0) {
4390 4396 // expected stack depth is -stack_depth or less
4391 4397 if (d > -stack_depth) {
4392 4398 // too many elements on the stack
4393 4399 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4394 4400 state->print();
4395 4401 assert(false, "error");
4396 4402 return false;
4397 4403 }
4398 4404 } else {
4399 4405 // expected stack depth is stack_depth
4400 4406 if (d != stack_depth) {
4401 4407 // wrong stack depth
4402 4408 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4403 4409 state->print();
4404 4410 assert(false, "error");
4405 4411 return false;
4406 4412 }
4407 4413 }
4408 4414 // everything is cool
4409 4415 return true;
4410 4416 }
4411 4417
4412 4418
4413 4419 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4414 4420 if (!VerifyFPU) return;
4415 4421 push_CPU_state();
4416 4422 pushl(rsp); // pass CPU state
4417 4423 ExternalAddress msg((address) s);
4418 4424 // pass message string s
4419 4425 pushptr(msg.addr());
4420 4426 pushl(stack_depth); // pass stack depth
4421 4427 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4422 4428 addl(rsp, 3 * wordSize); // discard arguments
4423 4429 // check for error
4424 4430 { Label L;
4425 4431 testl(rax, rax);
4426 4432 jcc(Assembler::notZero, L);
4427 4433 int3(); // break if error condition
4428 4434 bind(L);
4429 4435 }
4430 4436 pop_CPU_state();
4431 4437 }
4432 4438
4433 4439
4434 4440 void MacroAssembler::push_IU_state() {
4435 4441 pushad();
4436 4442 pushfd();
4437 4443 }
4438 4444
4439 4445
4440 4446 void MacroAssembler::pop_IU_state() {
4441 4447 popfd();
4442 4448 popad();
4443 4449 }
4444 4450
4445 4451
4446 4452 void MacroAssembler::push_FPU_state() {
4447 4453 subl(rsp, FPUStateSizeInWords * wordSize);
4448 4454 fnsave(Address(rsp, 0));
4449 4455 fwait();
4450 4456 }
4451 4457
4452 4458
4453 4459 void MacroAssembler::pop_FPU_state() {
4454 4460 frstor(Address(rsp, 0));
4455 4461 addl(rsp, FPUStateSizeInWords * wordSize);
4456 4462 }
4457 4463
4458 4464
4459 4465 void MacroAssembler::push_CPU_state() {
4460 4466 push_IU_state();
4461 4467 push_FPU_state();
4462 4468 }
4463 4469
4464 4470
4465 4471 void MacroAssembler::pop_CPU_state() {
4466 4472 pop_FPU_state();
4467 4473 pop_IU_state();
4468 4474 }
4469 4475
4470 4476
4471 4477 void MacroAssembler::push_callee_saved_registers() {
4472 4478 pushl(rsi);
4473 4479 pushl(rdi);
4474 4480 pushl(rdx);
4475 4481 pushl(rcx);
4476 4482 }
4477 4483
4478 4484
4479 4485 void MacroAssembler::pop_callee_saved_registers() {
4480 4486 popl(rcx);
4481 4487 popl(rdx);
4482 4488 popl(rdi);
4483 4489 popl(rsi);
4484 4490 }
4485 4491
4486 4492
4487 4493 void MacroAssembler::set_word_if_not_zero(Register dst) {
4488 4494 xorl(dst, dst);
4489 4495 set_byte_if_not_zero(dst);
4490 4496 }
4491 4497
4492 4498 // Write serialization page so VM thread can do a pseudo remote membar.
4493 4499 // We use the current thread pointer to calculate a thread specific
4494 4500 // offset to write to within the page. This minimizes bus traffic
4495 4501 // due to cache line collision.
4496 4502 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
4497 4503 movl(tmp, thread);
4498 4504 shrl(tmp, os::get_serialize_page_shift_count());
4499 4505 andl(tmp, (os::vm_page_size() - sizeof(int)));
4500 4506
4501 4507 Address index(noreg, tmp, Address::times_1);
4502 4508 ExternalAddress page(os::get_memory_serialize_page());
4503 4509
4504 4510 movptr(ArrayAddress(page, index), tmp);
4505 4511 }
4506 4512
4507 4513
4508 4514 void MacroAssembler::verify_tlab() {
4509 4515 #ifdef ASSERT
4510 4516 if (UseTLAB && VerifyOops) {
4511 4517 Label next, ok;
4512 4518 Register t1 = rsi;
4513 4519 Register thread_reg = rbx;
4514 4520
4515 4521 pushl(t1);
4516 4522 pushl(thread_reg);
4517 4523 get_thread(thread_reg);
4518 4524
4519 4525 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4520 4526 cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4521 4527 jcc(Assembler::aboveEqual, next);
4522 4528 stop("assert(top >= start)");
4523 4529 should_not_reach_here();
4524 4530
4525 4531 bind(next);
4526 4532 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4527 4533 cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4528 4534 jcc(Assembler::aboveEqual, ok);
4529 4535 stop("assert(top <= end)");
4530 4536 should_not_reach_here();
4531 4537
4532 4538 bind(ok);
4533 4539 popl(thread_reg);
4534 4540 popl(t1);
4535 4541 }
4536 4542 #endif
4537 4543 }
4538 4544
4539 4545
4540 4546 // Defines obj, preserves var_size_in_bytes
4541 4547 void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
4542 4548 Register t1, Label& slow_case) {
4543 4549 assert(obj == rax, "obj must be in rax, for cmpxchg");
4544 4550 assert_different_registers(obj, var_size_in_bytes, t1);
4545 4551 Register end = t1;
4546 4552 Label retry;
4547 4553 bind(retry);
4548 4554 ExternalAddress heap_top((address) Universe::heap()->top_addr());
4549 4555 movptr(obj, heap_top);
4550 4556 if (var_size_in_bytes == noreg) {
4551 4557 leal(end, Address(obj, con_size_in_bytes));
4552 4558 } else {
4553 4559 leal(end, Address(obj, var_size_in_bytes, Address::times_1));
4554 4560 }
4555 4561 // if end < obj then we wrapped around => object too long => slow case
4556 4562 cmpl(end, obj);
4557 4563 jcc(Assembler::below, slow_case);
4558 4564 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
4559 4565 jcc(Assembler::above, slow_case);
4560 4566 // Compare obj with the top addr, and if still equal, store the new top addr in
4561 4567 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
4562 4568 // it otherwise. Use lock prefix for atomicity on MPs.
4563 4569 if (os::is_MP()) {
4564 4570 lock();
4565 4571 }
4566 4572 cmpxchgptr(end, heap_top);
4567 4573 jcc(Assembler::notEqual, retry);
4568 4574 }
4569 4575
4570 4576
4571 4577 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4572 4578 void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
4573 4579 Register t1, Register t2, Label& slow_case) {
4574 4580 assert_different_registers(obj, t1, t2);
4575 4581 assert_different_registers(obj, var_size_in_bytes, t1);
4576 4582 Register end = t2;
4577 4583 Register thread = t1;
4578 4584
4579 4585 verify_tlab();
4580 4586
4581 4587 get_thread(thread);
4582 4588
4583 4589 movl(obj, Address(thread, JavaThread::tlab_top_offset()));
4584 4590 if (var_size_in_bytes == noreg) {
4585 4591 leal(end, Address(obj, con_size_in_bytes));
4586 4592 } else {
4587 4593 leal(end, Address(obj, var_size_in_bytes, Address::times_1));
4588 4594 }
4589 4595 cmpl(end, Address(thread, JavaThread::tlab_end_offset()));
4590 4596 jcc(Assembler::above, slow_case);
4591 4597
4592 4598 // update the tlab top pointer
4593 4599 movl(Address(thread, JavaThread::tlab_top_offset()), end);
4594 4600
4595 4601 // recover var_size_in_bytes if necessary
4596 4602 if (var_size_in_bytes == end) {
4597 4603 subl(var_size_in_bytes, obj);
4598 4604 }
4599 4605 verify_tlab();
4600 4606 }
4601 4607
4602 4608 // Preserves rbx, and rdx.
4603 4609 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
4604 4610 Register top = rax;
4605 4611 Register t1 = rcx;
4606 4612 Register t2 = rsi;
4607 4613 Register thread_reg = rdi;
4608 4614 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4609 4615 Label do_refill, discard_tlab;
4610 4616
4611 4617 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4612 4618 // No allocation in the shared eden.
4613 4619 jmp(slow_case);
4614 4620 }
4615 4621
4616 4622 get_thread(thread_reg);
4617 4623
4618 4624 movl(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4619 4625 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4620 4626
4621 4627 // calculate amount of free space
4622 4628 subl(t1, top);
4623 4629 shrl(t1, LogHeapWordSize);
4624 4630
4625 4631 // Retain tlab and allocate object in shared space if
4626 4632 // the amount free in the tlab is too large to discard.
4627 4633 cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4628 4634 jcc(Assembler::lessEqual, discard_tlab);
4629 4635
4630 4636 // Retain
4631 4637 movl(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment());
4632 4638 addl(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4633 4639 if (TLABStats) {
4634 4640 // increment number of slow_allocations
4635 4641 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4636 4642 }
4637 4643 jmp(try_eden);
4638 4644
4639 4645 bind(discard_tlab);
4640 4646 if (TLABStats) {
4641 4647 // increment number of refills
4642 4648 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4643 4649 // accumulate wastage -- t1 is amount free in tlab
4644 4650 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4645 4651 }
4646 4652
4647 4653 // if tlab is currently allocated (top or end != null) then
4648 4654 // fill [top, end + alignment_reserve) with array object
4649 4655 testl (top, top);
4650 4656 jcc(Assembler::zero, do_refill);
4651 4657
4652 4658 // set up the mark word
4653 4659 movl(Address(top, oopDesc::mark_offset_in_bytes()), (int)markOopDesc::prototype()->copy_set_hash(0x2));
4654 4660 // set the length to the remaining space
4655 4661 subl(t1, typeArrayOopDesc::header_size(T_INT));
4656 4662 addl(t1, ThreadLocalAllocBuffer::alignment_reserve());
4657 4663 shll(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4658 4664 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4659 4665 // set klass to intArrayKlass
4660 4666 // dubious reloc why not an oop reloc?
4661 4667 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
4662 4668 movl(Address(top, oopDesc::klass_offset_in_bytes()), t1);
4663 4669
4664 4670 // refill the tlab with an eden allocation
4665 4671 bind(do_refill);
4666 4672 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4667 4673 shll(t1, LogHeapWordSize);
4668 4674 // add object_size ??
4669 4675 eden_allocate(top, t1, 0, t2, slow_case);
4670 4676
4671 4677 // Check that t1 was preserved in eden_allocate.
4672 4678 #ifdef ASSERT
4673 4679 if (UseTLAB) {
4674 4680 Label ok;
4675 4681 Register tsize = rsi;
4676 4682 assert_different_registers(tsize, thread_reg, t1);
4677 4683 pushl(tsize);
4678 4684 movl(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4679 4685 shll(tsize, LogHeapWordSize);
4680 4686 cmpl(t1, tsize);
4681 4687 jcc(Assembler::equal, ok);
4682 4688 stop("assert(t1 != tlab size)");
4683 4689 should_not_reach_here();
4684 4690
4685 4691 bind(ok);
4686 4692 popl(tsize);
4687 4693 }
4688 4694 #endif
4689 4695 movl(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4690 4696 movl(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4691 4697 addl(top, t1);
4692 4698 subl(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4693 4699 movl(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4694 4700 verify_tlab();
4695 4701 jmp(retry);
4696 4702 }
4697 4703
4698 4704
4699 4705 int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
4700 4706 bool swap_reg_contains_mark,
4701 4707 Label& done, Label* slow_case,
4702 4708 BiasedLockingCounters* counters) {
4703 4709 assert(UseBiasedLocking, "why call this otherwise?");
4704 4710 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4705 4711 assert_different_registers(lock_reg, obj_reg, swap_reg);
4706 4712
4707 4713 if (PrintBiasedLockingStatistics && counters == NULL)
4708 4714 counters = BiasedLocking::counters();
4709 4715
4710 4716 bool need_tmp_reg = false;
4711 4717 if (tmp_reg == noreg) {
4712 4718 need_tmp_reg = true;
4713 4719 tmp_reg = lock_reg;
4714 4720 } else {
4715 4721 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4716 4722 }
4717 4723 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4718 4724 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4719 4725 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4720 4726 Address saved_mark_addr(lock_reg, 0);
4721 4727
4722 4728 // Biased locking
4723 4729 // See whether the lock is currently biased toward our thread and
4724 4730 // whether the epoch is still valid
4725 4731 // Note that the runtime guarantees sufficient alignment of JavaThread
4726 4732 // pointers to allow age to be placed into low bits
4727 4733 // First check to see whether biasing is even enabled for this object
4728 4734 Label cas_label;
4729 4735 int null_check_offset = -1;
4730 4736 if (!swap_reg_contains_mark) {
4731 4737 null_check_offset = offset();
4732 4738 movl(swap_reg, mark_addr);
4733 4739 }
4734 4740 if (need_tmp_reg) {
4735 4741 pushl(tmp_reg);
4736 4742 }
4737 4743 movl(tmp_reg, swap_reg);
4738 4744 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4739 4745 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4740 4746 if (need_tmp_reg) {
4741 4747 popl(tmp_reg);
4742 4748 }
4743 4749 jcc(Assembler::notEqual, cas_label);
4744 4750 // The bias pattern is present in the object's header. Need to check
4745 4751 // whether the bias owner and the epoch are both still current.
4746 4752 // Note that because there is no current thread register on x86 we
4747 4753 // need to store off the mark word we read out of the object to
4748 4754 // avoid reloading it and needing to recheck invariants below. This
4749 4755 // store is unfortunate but it makes the overall code shorter and
4750 4756 // simpler.
4751 4757 movl(saved_mark_addr, swap_reg);
4752 4758 if (need_tmp_reg) {
4753 4759 pushl(tmp_reg);
4754 4760 }
4755 4761 get_thread(tmp_reg);
4756 4762 xorl(swap_reg, tmp_reg);
4757 4763 if (swap_reg_contains_mark) {
4758 4764 null_check_offset = offset();
4759 4765 }
4760 4766 movl(tmp_reg, klass_addr);
4761 4767 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4762 4768 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4763 4769 if (need_tmp_reg) {
4764 4770 popl(tmp_reg);
4765 4771 }
4766 4772 if (counters != NULL) {
4767 4773 cond_inc32(Assembler::zero,
4768 4774 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4769 4775 }
4770 4776 jcc(Assembler::equal, done);
4771 4777
4772 4778 Label try_revoke_bias;
4773 4779 Label try_rebias;
4774 4780
4775 4781 // At this point we know that the header has the bias pattern and
4776 4782 // that we are not the bias owner in the current epoch. We need to
4777 4783 // figure out more details about the state of the header in order to
4778 4784 // know what operations can be legally performed on the object's
4779 4785 // header.
4780 4786
4781 4787 // If the low three bits in the xor result aren't clear, that means
4782 4788 // the prototype header is no longer biased and we have to revoke
4783 4789 // the bias on this object.
4784 4790 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4785 4791 jcc(Assembler::notZero, try_revoke_bias);
4786 4792
4787 4793 // Biasing is still enabled for this data type. See whether the
4788 4794 // epoch of the current bias is still valid, meaning that the epoch
4789 4795 // bits of the mark word are equal to the epoch bits of the
4790 4796 // prototype header. (Note that the prototype header's epoch bits
4791 4797 // only change at a safepoint.) If not, attempt to rebias the object
4792 4798 // toward the current thread. Note that we must be absolutely sure
4793 4799 // that the current epoch is invalid in order to do this because
4794 4800 // otherwise the manipulations it performs on the mark word are
4795 4801 // illegal.
4796 4802 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4797 4803 jcc(Assembler::notZero, try_rebias);
4798 4804
4799 4805 // The epoch of the current bias is still valid but we know nothing
4800 4806 // about the owner; it might be set or it might be clear. Try to
4801 4807 // acquire the bias of the object using an atomic operation. If this
4802 4808 // fails we will go in to the runtime to revoke the object's bias.
4803 4809 // Note that we first construct the presumed unbiased header so we
4804 4810 // don't accidentally blow away another thread's valid bias.
4805 4811 movl(swap_reg, saved_mark_addr);
4806 4812 andl(swap_reg,
4807 4813 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4808 4814 if (need_tmp_reg) {
4809 4815 pushl(tmp_reg);
4810 4816 }
4811 4817 get_thread(tmp_reg);
4812 4818 orl(tmp_reg, swap_reg);
4813 4819 if (os::is_MP()) {
4814 4820 lock();
4815 4821 }
4816 4822 cmpxchg(tmp_reg, Address(obj_reg, 0));
4817 4823 if (need_tmp_reg) {
4818 4824 popl(tmp_reg);
4819 4825 }
4820 4826 // If the biasing toward our thread failed, this means that
4821 4827 // another thread succeeded in biasing it toward itself and we
4822 4828 // need to revoke that bias. The revocation will occur in the
4823 4829 // interpreter runtime in the slow case.
4824 4830 if (counters != NULL) {
4825 4831 cond_inc32(Assembler::zero,
4826 4832 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4827 4833 }
4828 4834 if (slow_case != NULL) {
4829 4835 jcc(Assembler::notZero, *slow_case);
4830 4836 }
4831 4837 jmp(done);
4832 4838
4833 4839 bind(try_rebias);
4834 4840 // At this point we know the epoch has expired, meaning that the
4835 4841 // current "bias owner", if any, is actually invalid. Under these
4836 4842 // circumstances _only_, we are allowed to use the current header's
4837 4843 // value as the comparison value when doing the cas to acquire the
4838 4844 // bias in the current epoch. In other words, we allow transfer of
4839 4845 // the bias from one thread to another directly in this situation.
4840 4846 //
4841 4847 // FIXME: due to a lack of registers we currently blow away the age
4842 4848 // bits in this situation. Should attempt to preserve them.
4843 4849 if (need_tmp_reg) {
4844 4850 pushl(tmp_reg);
4845 4851 }
4846 4852 get_thread(tmp_reg);
4847 4853 movl(swap_reg, klass_addr);
4848 4854 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4849 4855 movl(swap_reg, saved_mark_addr);
4850 4856 if (os::is_MP()) {
4851 4857 lock();
4852 4858 }
4853 4859 cmpxchg(tmp_reg, Address(obj_reg, 0));
4854 4860 if (need_tmp_reg) {
4855 4861 popl(tmp_reg);
4856 4862 }
4857 4863 // If the biasing toward our thread failed, then another thread
4858 4864 // succeeded in biasing it toward itself and we need to revoke that
4859 4865 // bias. The revocation will occur in the runtime in the slow case.
4860 4866 if (counters != NULL) {
4861 4867 cond_inc32(Assembler::zero,
4862 4868 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4863 4869 }
4864 4870 if (slow_case != NULL) {
4865 4871 jcc(Assembler::notZero, *slow_case);
4866 4872 }
4867 4873 jmp(done);
4868 4874
4869 4875 bind(try_revoke_bias);
4870 4876 // The prototype mark in the klass doesn't have the bias bit set any
4871 4877 // more, indicating that objects of this data type are not supposed
4872 4878 // to be biased any more. We are going to try to reset the mark of
4873 4879 // this object to the prototype value and fall through to the
4874 4880 // CAS-based locking scheme. Note that if our CAS fails, it means
4875 4881 // that another thread raced us for the privilege of revoking the
4876 4882 // bias of this particular object, so it's okay to continue in the
4877 4883 // normal locking code.
4878 4884 //
4879 4885 // FIXME: due to a lack of registers we currently blow away the age
4880 4886 // bits in this situation. Should attempt to preserve them.
4881 4887 movl(swap_reg, saved_mark_addr);
4882 4888 if (need_tmp_reg) {
4883 4889 pushl(tmp_reg);
4884 4890 }
4885 4891 movl(tmp_reg, klass_addr);
4886 4892 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4887 4893 if (os::is_MP()) {
4888 4894 lock();
4889 4895 }
4890 4896 cmpxchg(tmp_reg, Address(obj_reg, 0));
4891 4897 if (need_tmp_reg) {
4892 4898 popl(tmp_reg);
4893 4899 }
4894 4900 // Fall through to the normal CAS-based lock, because no matter what
4895 4901 // the result of the above CAS, some thread must have succeeded in
4896 4902 // removing the bias bit from the object's header.
4897 4903 if (counters != NULL) {
4898 4904 cond_inc32(Assembler::zero,
4899 4905 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4900 4906 }
4901 4907
4902 4908 bind(cas_label);
4903 4909
4904 4910 return null_check_offset;
4905 4911 }
4906 4912
4907 4913
4908 4914 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
4909 4915 assert(UseBiasedLocking, "why call this otherwise?");
4910 4916
4911 4917 // Check for biased locking unlock case, which is a no-op
4912 4918 // Note: we do not have to check the thread ID for two reasons.
4913 4919 // First, the interpreter checks for IllegalMonitorStateException at
4914 4920 // a higher level. Second, if the bias was revoked while we held the
4915 4921 // lock, the object could not be rebiased toward another thread, so
4916 4922 // the bias bit would be clear.
4917 4923 movl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
4918 4924 andl(temp_reg, markOopDesc::biased_lock_mask_in_place);
4919 4925 cmpl(temp_reg, markOopDesc::biased_lock_pattern);
4920 4926 jcc(Assembler::equal, done);
4921 4927 }
4922 4928
4923 4929
4924 4930 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
4925 4931 switch (cond) {
4926 4932 // Note some conditions are synonyms for others
4927 4933 case Assembler::zero: return Assembler::notZero;
4928 4934 case Assembler::notZero: return Assembler::zero;
4929 4935 case Assembler::less: return Assembler::greaterEqual;
4930 4936 case Assembler::lessEqual: return Assembler::greater;
4931 4937 case Assembler::greater: return Assembler::lessEqual;
4932 4938 case Assembler::greaterEqual: return Assembler::less;
4933 4939 case Assembler::below: return Assembler::aboveEqual;
4934 4940 case Assembler::belowEqual: return Assembler::above;
4935 4941 case Assembler::above: return Assembler::belowEqual;
4936 4942 case Assembler::aboveEqual: return Assembler::below;
4937 4943 case Assembler::overflow: return Assembler::noOverflow;
4938 4944 case Assembler::noOverflow: return Assembler::overflow;
4939 4945 case Assembler::negative: return Assembler::positive;
4940 4946 case Assembler::positive: return Assembler::negative;
4941 4947 case Assembler::parity: return Assembler::noParity;
4942 4948 case Assembler::noParity: return Assembler::parity;
4943 4949 }
4944 4950 ShouldNotReachHere(); return Assembler::overflow;
4945 4951 }
4946 4952
4947 4953
4948 4954 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
4949 4955 Condition negated_cond = negate_condition(cond);
4950 4956 Label L;
4951 4957 jcc(negated_cond, L);
4952 4958 atomic_incl(counter_addr);
4953 4959 bind(L);
4954 4960 }
4955 4961
4956 4962 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
4957 4963 pushfd();
4958 4964 if (os::is_MP())
4959 4965 lock();
4960 4966 increment(counter_addr);
4961 4967 popfd();
4962 4968 }
4963 4969
4964 4970 SkipIfEqual::SkipIfEqual(
4965 4971 MacroAssembler* masm, const bool* flag_addr, bool value) {
4966 4972 _masm = masm;
4967 4973 _masm->cmp8(ExternalAddress((address)flag_addr), value);
4968 4974 _masm->jcc(Assembler::equal, _label);
4969 4975 }
4970 4976
4971 4977 SkipIfEqual::~SkipIfEqual() {
4972 4978 _masm->bind(_label);
4973 4979 }
4974 4980
4975 4981
4976 4982 // Writes to stack successive pages until offset reached to check for
4977 4983 // stack overflow + shadow pages. This clobbers tmp.
4978 4984 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4979 4985 movl(tmp, rsp);
4980 4986 // Bang stack for total size given plus shadow page size.
4981 4987 // Bang one page at a time because large size can bang beyond yellow and
4982 4988 // red zones.
4983 4989 Label loop;
4984 4990 bind(loop);
4985 4991 movl(Address(tmp, (-os::vm_page_size())), size );
4986 4992 subl(tmp, os::vm_page_size());
4987 4993 subl(size, os::vm_page_size());
4988 4994 jcc(Assembler::greater, loop);
4989 4995
4990 4996 // Bang down shadow pages too.
4991 4997 // The -1 because we already subtracted 1 page.
4992 4998 for (int i = 0; i< StackShadowPages-1; i++) {
4993 4999 movl(Address(tmp, (-i*os::vm_page_size())), size );
4994 5000 }
4995 5001 }
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