1 /*
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_assembler_x86_32.cpp.incl"
27
28 // Implementation of AddressLiteral
29
30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
31 _is_lval = false;
32 _target = target;
33 switch (rtype) {
34 case relocInfo::oop_type:
35 // Oops are a special case. Normally they would be their own section
36 // but in cases like icBuffer they are literals in the code stream that
37 // we don't have a section for. We use none so that we get a literal address
38 // which is always patchable.
39 break;
40 case relocInfo::external_word_type:
41 _rspec = external_word_Relocation::spec(target);
42 break;
43 case relocInfo::internal_word_type:
44 _rspec = internal_word_Relocation::spec(target);
45 break;
46 case relocInfo::opt_virtual_call_type:
47 _rspec = opt_virtual_call_Relocation::spec();
48 break;
49 case relocInfo::static_call_type:
50 _rspec = static_call_Relocation::spec();
51 break;
52 case relocInfo::runtime_call_type:
53 _rspec = runtime_call_Relocation::spec();
54 break;
55 case relocInfo::poll_type:
56 case relocInfo::poll_return_type:
57 _rspec = Relocation::spec_simple(rtype);
58 break;
59 case relocInfo::none:
60 break;
61 default:
62 ShouldNotReachHere();
63 break;
64 }
65 }
66
67 // Implementation of Address
68
69 Address Address::make_array(ArrayAddress adr) {
70 #ifdef _LP64
71 // Not implementable on 64bit machines
72 // Should have been handled higher up the call chain.
73 ShouldNotReachHere();
74 #else
75 AddressLiteral base = adr.base();
76 Address index = adr.index();
77 assert(index._disp == 0, "must not have disp"); // maybe it can?
78 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
79 array._rspec = base._rspec;
80 return array;
81 #endif // _LP64
82 }
83
84 #ifndef _LP64
85
86 // exceedingly dangerous constructor
87 Address::Address(address loc, RelocationHolder spec) {
88 _base = noreg;
89 _index = noreg;
90 _scale = no_scale;
91 _disp = (intptr_t) loc;
92 _rspec = spec;
93 }
94 #endif // _LP64
95
96 // Convert the raw encoding form into the form expected by the constructor for
97 // Address. An index of 4 (rsp) corresponds to having no index, so convert
98 // that to noreg for the Address constructor.
99 Address Address::make_raw(int base, int index, int scale, int disp) {
100 bool valid_index = index != rsp->encoding();
101 if (valid_index) {
102 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
103 return madr;
104 } else {
105 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
106 return madr;
107 }
108 }
109
110 // Implementation of Assembler
111
112 int AbstractAssembler::code_fill_byte() {
113 return (u_char)'\xF4'; // hlt
114 }
115
116 // make this go away someday
117 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
118 if (rtype == relocInfo::none)
119 emit_long(data);
120 else emit_data(data, Relocation::spec_simple(rtype), format);
121 }
122
123
124 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
125 assert(imm32_operand == 0, "default format must be imm32 in this file");
126 assert(inst_mark() != NULL, "must be inside InstructionMark");
127 if (rspec.type() != relocInfo::none) {
128 #ifdef ASSERT
129 check_relocation(rspec, format);
130 #endif
131 // Do not use AbstractAssembler::relocate, which is not intended for
132 // embedded words. Instead, relocate to the enclosing instruction.
133
134 // hack. call32 is too wide for mask so use disp32
135 if (format == call32_operand)
136 code_section()->relocate(inst_mark(), rspec, disp32_operand);
137 else
138 code_section()->relocate(inst_mark(), rspec, format);
139 }
140 emit_long(data);
141 }
142
143
144 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
145 assert(dst->has_byte_register(), "must have byte register");
146 assert(isByte(op1) && isByte(op2), "wrong opcode");
147 assert(isByte(imm8), "not a byte");
148 assert((op1 & 0x01) == 0, "should be 8bit operation");
149 emit_byte(op1);
150 emit_byte(op2 | dst->encoding());
151 emit_byte(imm8);
152 }
153
154
155 void Assembler::emit_arith(int op1, int op2, Register dst, int imm32) {
156 assert(isByte(op1) && isByte(op2), "wrong opcode");
157 assert((op1 & 0x01) == 1, "should be 32bit operation");
158 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
159 if (is8bit(imm32)) {
160 emit_byte(op1 | 0x02); // set sign bit
161 emit_byte(op2 | dst->encoding());
162 emit_byte(imm32 & 0xFF);
163 } else {
164 emit_byte(op1);
165 emit_byte(op2 | dst->encoding());
166 emit_long(imm32);
167 }
168 }
169
170 // immediate-to-memory forms
171 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int imm32) {
172 assert((op1 & 0x01) == 1, "should be 32bit operation");
173 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
174 if (is8bit(imm32)) {
175 emit_byte(op1 | 0x02); // set sign bit
176 emit_operand(rm,adr);
177 emit_byte(imm32 & 0xFF);
178 } else {
179 emit_byte(op1);
180 emit_operand(rm,adr);
181 emit_long(imm32);
182 }
183 }
184
185 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) {
186 assert(isByte(op1) && isByte(op2), "wrong opcode");
187 assert((op1 & 0x01) == 1, "should be 32bit operation");
188 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
189 InstructionMark im(this);
190 emit_byte(op1);
191 emit_byte(op2 | dst->encoding());
192 emit_data((int)obj, relocInfo::oop_type, 0);
193 }
194
195
196 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
197 assert(isByte(op1) && isByte(op2), "wrong opcode");
198 emit_byte(op1);
199 emit_byte(op2 | dst->encoding() << 3 | src->encoding());
200 }
201
202
203 void Assembler::emit_operand(Register reg,
204 Register base,
205 Register index,
206 Address::ScaleFactor scale,
207 int disp,
208 RelocationHolder const& rspec) {
209
210 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
211 if (base->is_valid()) {
212 if (index->is_valid()) {
213 assert(scale != Address::no_scale, "inconsistent address");
214 // [base + index*scale + disp]
215 if (disp == 0 && rtype == relocInfo::none && base != rbp) {
216 // [base + index*scale]
217 // [00 reg 100][ss index base]
218 assert(index != rsp, "illegal addressing mode");
219 emit_byte(0x04 | reg->encoding() << 3);
220 emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
221 } else if (is8bit(disp) && rtype == relocInfo::none) {
222 // [base + index*scale + imm8]
223 // [01 reg 100][ss index base] imm8
224 assert(index != rsp, "illegal addressing mode");
225 emit_byte(0x44 | reg->encoding() << 3);
226 emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
227 emit_byte(disp & 0xFF);
228 } else {
229 // [base + index*scale + imm32]
230 // [10 reg 100][ss index base] imm32
231 assert(index != rsp, "illegal addressing mode");
232 emit_byte(0x84 | reg->encoding() << 3);
233 emit_byte(scale << 6 | index->encoding() << 3 | base->encoding());
234 emit_data(disp, rspec, disp32_operand);
235 }
236 } else if (base == rsp) {
237 // [esp + disp]
238 if (disp == 0 && rtype == relocInfo::none) {
239 // [esp]
240 // [00 reg 100][00 100 100]
241 emit_byte(0x04 | reg->encoding() << 3);
242 emit_byte(0x24);
243 } else if (is8bit(disp) && rtype == relocInfo::none) {
244 // [esp + imm8]
245 // [01 reg 100][00 100 100] imm8
246 emit_byte(0x44 | reg->encoding() << 3);
247 emit_byte(0x24);
248 emit_byte(disp & 0xFF);
249 } else {
250 // [esp + imm32]
251 // [10 reg 100][00 100 100] imm32
252 emit_byte(0x84 | reg->encoding() << 3);
253 emit_byte(0x24);
254 emit_data(disp, rspec, disp32_operand);
255 }
256 } else {
257 // [base + disp]
258 assert(base != rsp, "illegal addressing mode");
259 if (disp == 0 && rtype == relocInfo::none && base != rbp) {
260 // [base]
261 // [00 reg base]
262 assert(base != rbp, "illegal addressing mode");
263 emit_byte(0x00 | reg->encoding() << 3 | base->encoding());
264 } else if (is8bit(disp) && rtype == relocInfo::none) {
265 // [base + imm8]
266 // [01 reg base] imm8
267 emit_byte(0x40 | reg->encoding() << 3 | base->encoding());
268 emit_byte(disp & 0xFF);
269 } else {
270 // [base + imm32]
271 // [10 reg base] imm32
272 emit_byte(0x80 | reg->encoding() << 3 | base->encoding());
273 emit_data(disp, rspec, disp32_operand);
274 }
275 }
276 } else {
277 if (index->is_valid()) {
278 assert(scale != Address::no_scale, "inconsistent address");
279 // [index*scale + disp]
280 // [00 reg 100][ss index 101] imm32
281 assert(index != rsp, "illegal addressing mode");
282 emit_byte(0x04 | reg->encoding() << 3);
283 emit_byte(scale << 6 | index->encoding() << 3 | 0x05);
284 emit_data(disp, rspec, disp32_operand);
285 } else {
286 // [disp]
287 // [00 reg 101] imm32
288 emit_byte(0x05 | reg->encoding() << 3);
289 emit_data(disp, rspec, disp32_operand);
290 }
291 }
292 }
293
294 // Secret local extension to Assembler::WhichOperand:
295 #define end_pc_operand (_WhichOperand_limit)
296
297 address Assembler::locate_operand(address inst, WhichOperand which) {
298 // Decode the given instruction, and return the address of
299 // an embedded 32-bit operand word.
300
301 // If "which" is disp32_operand, selects the displacement portion
302 // of an effective address specifier.
303 // If "which" is imm32_operand, selects the trailing immediate constant.
304 // If "which" is call32_operand, selects the displacement of a call or jump.
305 // Caller is responsible for ensuring that there is such an operand,
306 // and that it is 32 bits wide.
307
308 // If "which" is end_pc_operand, find the end of the instruction.
309
310 address ip = inst;
311
312 debug_only(bool has_imm32 = false);
313 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
314
315 again_after_prefix:
316 switch (0xFF & *ip++) {
317
318 // These convenience macros generate groups of "case" labels for the switch.
319 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
320 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
321 case (x)+4: case (x)+5: case (x)+6: case (x)+7
322 #define REP16(x) REP8((x)+0): \
323 case REP8((x)+8)
324
325 case CS_segment:
326 case SS_segment:
327 case DS_segment:
328 case ES_segment:
329 case FS_segment:
330 case GS_segment:
331 assert(ip == inst+1, "only one prefix allowed");
332 goto again_after_prefix;
333
334 case 0xFF: // pushl a; decl a; incl a; call a; jmp a
335 case 0x88: // movb a, r
336 case 0x89: // movl a, r
337 case 0x8A: // movb r, a
338 case 0x8B: // movl r, a
339 case 0x8F: // popl a
340 break;
341
342 case 0x68: // pushl #32(oop?)
343 if (which == end_pc_operand) return ip + 4;
344 assert(which == imm32_operand, "pushl has no disp32");
345 return ip; // not produced by emit_operand
346
347 case 0x66: // movw ... (size prefix)
348 switch (0xFF & *ip++) {
349 case 0x8B: // movw r, a
350 case 0x89: // movw a, r
351 break;
352 case 0xC7: // movw a, #16
353 tail_size = 2; // the imm16
354 break;
355 case 0x0F: // several SSE/SSE2 variants
356 ip--; // reparse the 0x0F
357 goto again_after_prefix;
358 default:
359 ShouldNotReachHere();
360 }
361 break;
362
363 case REP8(0xB8): // movl r, #32(oop?)
364 if (which == end_pc_operand) return ip + 4;
365 assert(which == imm32_operand || which == disp32_operand, "");
366 return ip;
367
368 case 0x69: // imul r, a, #32
369 case 0xC7: // movl a, #32(oop?)
370 tail_size = 4;
371 debug_only(has_imm32 = true); // has both kinds of operands!
372 break;
373
374 case 0x0F: // movx..., etc.
375 switch (0xFF & *ip++) {
376 case 0x12: // movlps
377 case 0x28: // movaps
378 case 0x2E: // ucomiss
379 case 0x2F: // comiss
380 case 0x54: // andps
381 case 0x55: // andnps
382 case 0x56: // orps
383 case 0x57: // xorps
384 case 0x6E: // movd
385 case 0x7E: // movd
386 case 0xAE: // ldmxcsr a
387 // amd side says it these have both operands but that doesn't
388 // appear to be true.
389 // debug_only(has_imm32 = true); // has both kinds of operands!
390 break;
391
392 case 0xAD: // shrd r, a, %cl
393 case 0xAF: // imul r, a
394 case 0xBE: // movsxb r, a
395 case 0xBF: // movsxw r, a
396 case 0xB6: // movzxb r, a
397 case 0xB7: // movzxw r, a
398 case REP16(0x40): // cmovl cc, r, a
399 case 0xB0: // cmpxchgb
400 case 0xB1: // cmpxchg
401 case 0xC1: // xaddl
402 case 0xC7: // cmpxchg8
403 case REP16(0x90): // setcc a
404 // fall out of the switch to decode the address
405 break;
406 case 0xAC: // shrd r, a, #8
407 tail_size = 1; // the imm8
408 break;
409 case REP16(0x80): // jcc rdisp32
410 if (which == end_pc_operand) return ip + 4;
411 assert(which == call32_operand, "jcc has no disp32 or imm32");
412 return ip;
413 default:
414 ShouldNotReachHere();
415 }
416 break;
417
418 case 0x81: // addl a, #32; addl r, #32
419 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
420 // in the case of cmpl, the imm32 might be an oop
421 tail_size = 4;
422 debug_only(has_imm32 = true); // has both kinds of operands!
423 break;
424
425 case 0x85: // test r/m, r
426 break;
427
428 case 0x83: // addl a, #8; addl r, #8
429 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
430 tail_size = 1;
431 break;
432
433 case 0x9B:
434 switch (0xFF & *ip++) {
435 case 0xD9: // fnstcw a
436 break;
437 default:
438 ShouldNotReachHere();
439 }
440 break;
441
442 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
443 case REP4(0x10): // adc...
444 case REP4(0x20): // and...
445 case REP4(0x30): // xor...
446 case REP4(0x08): // or...
447 case REP4(0x18): // sbb...
448 case REP4(0x28): // sub...
449 case REP4(0x38): // cmp...
450 case 0xF7: // mull a
451 case 0x8D: // leal r, a
452 case 0x87: // xchg r, a
453 break;
454
455 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
456 case 0xC6: // movb a, #8
457 case 0x80: // cmpb a, #8
458 case 0x6B: // imul r, a, #8
459 tail_size = 1; // the imm8
460 break;
461
462 case 0xE8: // call rdisp32
463 case 0xE9: // jmp rdisp32
464 if (which == end_pc_operand) return ip + 4;
465 assert(which == call32_operand, "call has no disp32 or imm32");
466 return ip;
467
468 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
469 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
470 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
471 case 0xDD: // fld_d a; fst_d a; fstp_d a
472 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
473 case 0xDF: // fild_d a; fistp_d a
474 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
475 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
476 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
477 break;
478
479 case 0xF3: // For SSE
480 case 0xF2: // For SSE2
481 ip++; ip++;
482 break;
483
484 default:
485 ShouldNotReachHere();
486
487 #undef REP8
488 #undef REP16
489 }
490
491 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
492 assert(which != imm32_operand || has_imm32, "instruction has no imm32 field");
493
494 // parse the output of emit_operand
495 int op2 = 0xFF & *ip++;
496 int base = op2 & 0x07;
497 int op3 = -1;
498 const int b100 = 4;
499 const int b101 = 5;
500 if (base == b100 && (op2 >> 6) != 3) {
501 op3 = 0xFF & *ip++;
502 base = op3 & 0x07; // refetch the base
503 }
504 // now ip points at the disp (if any)
505
506 switch (op2 >> 6) {
507 case 0:
508 // [00 reg 100][ss index base]
509 // [00 reg 100][00 100 rsp]
510 // [00 reg base]
511 // [00 reg 100][ss index 101][disp32]
512 // [00 reg 101] [disp32]
513
514 if (base == b101) {
515 if (which == disp32_operand)
516 return ip; // caller wants the disp32
517 ip += 4; // skip the disp32
518 }
519 break;
520
521 case 1:
522 // [01 reg 100][ss index base][disp8]
523 // [01 reg 100][00 100 rsp][disp8]
524 // [01 reg base] [disp8]
525 ip += 1; // skip the disp8
526 break;
527
528 case 2:
529 // [10 reg 100][ss index base][disp32]
530 // [10 reg 100][00 100 rsp][disp32]
531 // [10 reg base] [disp32]
532 if (which == disp32_operand)
533 return ip; // caller wants the disp32
534 ip += 4; // skip the disp32
535 break;
536
537 case 3:
538 // [11 reg base] (not a memory addressing mode)
539 break;
540 }
541
542 if (which == end_pc_operand) {
543 return ip + tail_size;
544 }
545
546 assert(which == imm32_operand, "instruction has only an imm32 field");
547 return ip;
548 }
549
550 address Assembler::locate_next_instruction(address inst) {
551 // Secretly share code with locate_operand:
552 return locate_operand(inst, end_pc_operand);
553 }
554
555
556 #ifdef ASSERT
557 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
558 address inst = inst_mark();
559 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
560 address opnd;
561
562 Relocation* r = rspec.reloc();
563 if (r->type() == relocInfo::none) {
564 return;
565 } else if (r->is_call() || format == call32_operand) {
566 // assert(format == imm32_operand, "cannot specify a nonzero format");
567 opnd = locate_operand(inst, call32_operand);
568 } else if (r->is_data()) {
569 assert(format == imm32_operand || format == disp32_operand, "format ok");
570 opnd = locate_operand(inst, (WhichOperand)format);
571 } else {
572 assert(format == imm32_operand, "cannot specify a format");
573 return;
574 }
575 assert(opnd == pc(), "must put operand where relocs can find it");
576 }
577 #endif
578
579
580
581 void Assembler::emit_operand(Register reg, Address adr) {
582 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
583 }
584
585
586 void Assembler::emit_farith(int b1, int b2, int i) {
587 assert(isByte(b1) && isByte(b2), "wrong opcode");
588 assert(0 <= i && i < 8, "illegal stack offset");
589 emit_byte(b1);
590 emit_byte(b2 + i);
591 }
592
593
594 void Assembler::pushad() {
595 emit_byte(0x60);
596 }
597
598 void Assembler::popad() {
599 emit_byte(0x61);
600 }
601
602 void Assembler::pushfd() {
603 emit_byte(0x9C);
604 }
605
606 void Assembler::popfd() {
607 emit_byte(0x9D);
608 }
609
610 void Assembler::pushl(int imm32) {
611 emit_byte(0x68);
612 emit_long(imm32);
613 }
614
615 #ifndef _LP64
616 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
617 InstructionMark im(this);
618 emit_byte(0x68);
619 emit_data(imm32, rspec, 0);
620 }
621 #endif // _LP64
622
623 void Assembler::pushl(Register src) {
624 emit_byte(0x50 | src->encoding());
625 }
626
627
628 void Assembler::pushl(Address src) {
629 InstructionMark im(this);
630 emit_byte(0xFF);
631 emit_operand(rsi, src);
632 }
633
634 void Assembler::popl(Register dst) {
635 emit_byte(0x58 | dst->encoding());
636 }
637
638
639 void Assembler::popl(Address dst) {
640 InstructionMark im(this);
641 emit_byte(0x8F);
642 emit_operand(rax, dst);
643 }
644
645
646 void Assembler::prefix(Prefix p) {
647 a_byte(p);
648 }
649
650
651 void Assembler::movb(Register dst, Address src) {
652 assert(dst->has_byte_register(), "must have byte register");
653 InstructionMark im(this);
654 emit_byte(0x8A);
655 emit_operand(dst, src);
656 }
657
658
659 void Assembler::movb(Address dst, int imm8) {
660 InstructionMark im(this);
661 emit_byte(0xC6);
662 emit_operand(rax, dst);
663 emit_byte(imm8);
664 }
665
666
667 void Assembler::movb(Address dst, Register src) {
668 assert(src->has_byte_register(), "must have byte register");
669 InstructionMark im(this);
670 emit_byte(0x88);
671 emit_operand(src, dst);
672 }
673
674
675 void Assembler::movw(Address dst, int imm16) {
676 InstructionMark im(this);
677
678 emit_byte(0x66); // switch to 16-bit mode
679 emit_byte(0xC7);
680 emit_operand(rax, dst);
681 emit_word(imm16);
682 }
683
684
685 void Assembler::movw(Register dst, Address src) {
686 InstructionMark im(this);
687 emit_byte(0x66);
688 emit_byte(0x8B);
689 emit_operand(dst, src);
690 }
691
692
693 void Assembler::movw(Address dst, Register src) {
694 InstructionMark im(this);
695 emit_byte(0x66);
696 emit_byte(0x89);
697 emit_operand(src, dst);
698 }
699
700
701 void Assembler::movl(Register dst, int imm32) {
702 emit_byte(0xB8 | dst->encoding());
703 emit_long(imm32);
704 }
705
706 #ifndef _LP64
707 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
708
709 InstructionMark im(this);
710 emit_byte(0xB8 | dst->encoding());
711 emit_data((int)imm32, rspec, 0);
712 }
713 #endif // _LP64
714
715 void Assembler::movl(Register dst, Register src) {
716 emit_byte(0x8B);
717 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
718 }
719
720
721 void Assembler::movl(Register dst, Address src) {
722 InstructionMark im(this);
723 emit_byte(0x8B);
724 emit_operand(dst, src);
725 }
726
727
728 void Assembler::movl(Address dst, int imm32) {
729 InstructionMark im(this);
730 emit_byte(0xC7);
731 emit_operand(rax, dst);
732 emit_long(imm32);
733 }
734
735 #ifndef _LP64
736 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
737 InstructionMark im(this);
738 emit_byte(0xC7);
739 emit_operand(rax, dst);
740 emit_data((int)imm32, rspec, 0);
741 }
742 #endif // _LP64
743
744 void Assembler::movl(Address dst, Register src) {
745 InstructionMark im(this);
746 emit_byte(0x89);
747 emit_operand(src, dst);
748 }
749
750 void Assembler::movsxb(Register dst, Address src) {
751 InstructionMark im(this);
752 emit_byte(0x0F);
753 emit_byte(0xBE);
754 emit_operand(dst, src);
755 }
756
757 void Assembler::movsxb(Register dst, Register src) {
758 assert(src->has_byte_register(), "must have byte register");
759 emit_byte(0x0F);
760 emit_byte(0xBE);
761 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
762 }
763
764
765 void Assembler::movsxw(Register dst, Address src) {
766 InstructionMark im(this);
767 emit_byte(0x0F);
768 emit_byte(0xBF);
769 emit_operand(dst, src);
770 }
771
772
773 void Assembler::movsxw(Register dst, Register src) {
774 emit_byte(0x0F);
775 emit_byte(0xBF);
776 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
777 }
778
779
780 void Assembler::movzxb(Register dst, Address src) {
781 InstructionMark im(this);
782 emit_byte(0x0F);
783 emit_byte(0xB6);
784 emit_operand(dst, src);
785 }
786
787
788 void Assembler::movzxb(Register dst, Register src) {
789 assert(src->has_byte_register(), "must have byte register");
790 emit_byte(0x0F);
791 emit_byte(0xB6);
792 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
793 }
794
795
796 void Assembler::movzxw(Register dst, Address src) {
797 InstructionMark im(this);
798 emit_byte(0x0F);
799 emit_byte(0xB7);
800 emit_operand(dst, src);
801 }
802
803
804 void Assembler::movzxw(Register dst, Register src) {
805 emit_byte(0x0F);
806 emit_byte(0xB7);
807 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
808 }
809
810
811 void Assembler::cmovl(Condition cc, Register dst, Register src) {
812 guarantee(VM_Version::supports_cmov(), "illegal instruction");
813 emit_byte(0x0F);
814 emit_byte(0x40 | cc);
815 emit_byte(0xC0 | (dst->encoding() << 3) | src->encoding());
816 }
817
818
819 void Assembler::cmovl(Condition cc, Register dst, Address src) {
820 guarantee(VM_Version::supports_cmov(), "illegal instruction");
821 // The code below seems to be wrong - however the manual is inconclusive
822 // do not use for now (remember to enable all callers when fixing this)
823 Unimplemented();
824 // wrong bytes?
825 InstructionMark im(this);
826 emit_byte(0x0F);
827 emit_byte(0x40 | cc);
828 emit_operand(dst, src);
829 }
830
831
832 void Assembler::prefetcht0(Address src) {
833 assert(VM_Version::supports_sse(), "must support");
834 InstructionMark im(this);
835 emit_byte(0x0F);
836 emit_byte(0x18);
837 emit_operand(rcx, src); // 1, src
838 }
839
840
841 void Assembler::prefetcht1(Address src) {
842 assert(VM_Version::supports_sse(), "must support");
843 InstructionMark im(this);
844 emit_byte(0x0F);
845 emit_byte(0x18);
846 emit_operand(rdx, src); // 2, src
847 }
848
849
850 void Assembler::prefetcht2(Address src) {
851 assert(VM_Version::supports_sse(), "must support");
852 InstructionMark im(this);
853 emit_byte(0x0F);
854 emit_byte(0x18);
855 emit_operand(rbx, src); // 3, src
856 }
857
858
859 void Assembler::prefetchnta(Address src) {
860 assert(VM_Version::supports_sse2(), "must support");
861 InstructionMark im(this);
862 emit_byte(0x0F);
863 emit_byte(0x18);
864 emit_operand(rax, src); // 0, src
865 }
866
867
868 void Assembler::prefetchw(Address src) {
869 assert(VM_Version::supports_3dnow(), "must support");
870 InstructionMark im(this);
871 emit_byte(0x0F);
872 emit_byte(0x0D);
873 emit_operand(rcx, src); // 1, src
874 }
875
876
877 void Assembler::prefetchr(Address src) {
878 assert(VM_Version::supports_3dnow(), "must support");
879 InstructionMark im(this);
880 emit_byte(0x0F);
881 emit_byte(0x0D);
882 emit_operand(rax, src); // 0, src
883 }
884
885
886 void Assembler::adcl(Register dst, int imm32) {
887 emit_arith(0x81, 0xD0, dst, imm32);
888 }
889
890
891 void Assembler::adcl(Register dst, Address src) {
892 InstructionMark im(this);
893 emit_byte(0x13);
894 emit_operand(dst, src);
895 }
896
897
898 void Assembler::adcl(Register dst, Register src) {
899 emit_arith(0x13, 0xC0, dst, src);
900 }
901
902
903 void Assembler::addl(Address dst, int imm32) {
904 InstructionMark im(this);
905 emit_arith_operand(0x81,rax,dst,imm32);
906 }
907
908
909 void Assembler::addl(Address dst, Register src) {
910 InstructionMark im(this);
911 emit_byte(0x01);
912 emit_operand(src, dst);
913 }
914
915
916 void Assembler::addl(Register dst, int imm32) {
917 emit_arith(0x81, 0xC0, dst, imm32);
918 }
919
920
921 void Assembler::addl(Register dst, Address src) {
922 InstructionMark im(this);
923 emit_byte(0x03);
924 emit_operand(dst, src);
925 }
926
927
928 void Assembler::addl(Register dst, Register src) {
929 emit_arith(0x03, 0xC0, dst, src);
930 }
931
932
933 void Assembler::andl(Register dst, int imm32) {
934 emit_arith(0x81, 0xE0, dst, imm32);
935 }
936
937
938 void Assembler::andl(Register dst, Address src) {
939 InstructionMark im(this);
940 emit_byte(0x23);
941 emit_operand(dst, src);
942 }
943
944
945 void Assembler::andl(Register dst, Register src) {
946 emit_arith(0x23, 0xC0, dst, src);
947 }
948
949
950 void Assembler::cmpb(Address dst, int imm8) {
951 InstructionMark im(this);
952 emit_byte(0x80);
953 emit_operand(rdi, dst);
954 emit_byte(imm8);
955 }
956
957 void Assembler::cmpw(Address dst, int imm16) {
958 InstructionMark im(this);
959 emit_byte(0x66);
960 emit_byte(0x81);
961 emit_operand(rdi, dst);
962 emit_word(imm16);
963 }
964
965 void Assembler::cmpl(Address dst, int imm32) {
966 InstructionMark im(this);
967 emit_byte(0x81);
968 emit_operand(rdi, dst);
969 emit_long(imm32);
970 }
971
972 #ifndef _LP64
973 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
974 InstructionMark im(this);
975 emit_byte(0x81);
976 emit_byte(0xF8 | src1->encoding());
977 emit_data(imm32, rspec, 0);
978 }
979
980 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
981 InstructionMark im(this);
982 emit_byte(0x81);
983 emit_operand(rdi, src1);
984 emit_data(imm32, rspec, 0);
985 }
986 #endif // _LP64
987
988
989 void Assembler::cmpl(Register dst, int imm32) {
990 emit_arith(0x81, 0xF8, dst, imm32);
991 }
992
993
994 void Assembler::cmpl(Register dst, Register src) {
995 emit_arith(0x3B, 0xC0, dst, src);
996 }
997
998
999 void Assembler::cmpl(Register dst, Address src) {
1000 InstructionMark im(this);
1001 emit_byte(0x3B);
1002 emit_operand(dst, src);
1003 }
1004
1005
1006 void Assembler::decl(Register dst) {
1007 // Don't use it directly. Use MacroAssembler::decrement() instead.
1008 emit_byte(0x48 | dst->encoding());
1009 }
1010
1011
1012 void Assembler::decl(Address dst) {
1013 // Don't use it directly. Use MacroAssembler::decrement() instead.
1014 InstructionMark im(this);
1015 emit_byte(0xFF);
1016 emit_operand(rcx, dst);
1017 }
1018
1019
1020 void Assembler::idivl(Register src) {
1021 emit_byte(0xF7);
1022 emit_byte(0xF8 | src->encoding());
1023 }
1024
1025
1026 void Assembler::cdql() {
1027 emit_byte(0x99);
1028 }
1029
1030
1031 void Assembler::imull(Register dst, Register src) {
1032 emit_byte(0x0F);
1033 emit_byte(0xAF);
1034 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
1035 }
1036
1037
1038 void Assembler::imull(Register dst, Register src, int value) {
1039 if (is8bit(value)) {
1040 emit_byte(0x6B);
1041 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
1042 emit_byte(value);
1043 } else {
1044 emit_byte(0x69);
1045 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
1046 emit_long(value);
1047 }
1048 }
1049
1050
1051 void Assembler::incl(Register dst) {
1052 // Don't use it directly. Use MacroAssembler::increment() instead.
1053 emit_byte(0x40 | dst->encoding());
1054 }
1055
1056
1057 void Assembler::incl(Address dst) {
1058 // Don't use it directly. Use MacroAssembler::increment() instead.
1059 InstructionMark im(this);
1060 emit_byte(0xFF);
1061 emit_operand(rax, dst);
1062 }
1063
1064
1065 void Assembler::leal(Register dst, Address src) {
1066 InstructionMark im(this);
1067 emit_byte(0x8D);
1068 emit_operand(dst, src);
1069 }
1070
1071 void Assembler::mull(Address src) {
1072 InstructionMark im(this);
1073 emit_byte(0xF7);
1074 emit_operand(rsp, src);
1075 }
1076
1077
1078 void Assembler::mull(Register src) {
1079 emit_byte(0xF7);
1080 emit_byte(0xE0 | src->encoding());
1081 }
1082
1083
1084 void Assembler::negl(Register dst) {
1085 emit_byte(0xF7);
1086 emit_byte(0xD8 | dst->encoding());
1087 }
1088
1089
1090 void Assembler::notl(Register dst) {
1091 emit_byte(0xF7);
1092 emit_byte(0xD0 | dst->encoding());
1093 }
1094
1095
1096 void Assembler::orl(Address dst, int imm32) {
1097 InstructionMark im(this);
1098 emit_byte(0x81);
1099 emit_operand(rcx, dst);
1100 emit_long(imm32);
1101 }
1102
1103 void Assembler::orl(Register dst, int imm32) {
1104 emit_arith(0x81, 0xC8, dst, imm32);
1105 }
1106
1107
1108 void Assembler::orl(Register dst, Address src) {
1109 InstructionMark im(this);
1110 emit_byte(0x0B);
1111 emit_operand(dst, src);
1112 }
1113
1114
1115 void Assembler::orl(Register dst, Register src) {
1116 emit_arith(0x0B, 0xC0, dst, src);
1117 }
1118
1119
1120 void Assembler::rcll(Register dst, int imm8) {
1121 assert(isShiftCount(imm8), "illegal shift count");
1122 if (imm8 == 1) {
1123 emit_byte(0xD1);
1124 emit_byte(0xD0 | dst->encoding());
1125 } else {
1126 emit_byte(0xC1);
1127 emit_byte(0xD0 | dst->encoding());
1128 emit_byte(imm8);
1129 }
1130 }
1131
1132
1133 void Assembler::sarl(Register dst, int imm8) {
1134 assert(isShiftCount(imm8), "illegal shift count");
1135 if (imm8 == 1) {
1136 emit_byte(0xD1);
1137 emit_byte(0xF8 | dst->encoding());
1138 } else {
1139 emit_byte(0xC1);
1140 emit_byte(0xF8 | dst->encoding());
1141 emit_byte(imm8);
1142 }
1143 }
1144
1145
1146 void Assembler::sarl(Register dst) {
1147 emit_byte(0xD3);
1148 emit_byte(0xF8 | dst->encoding());
1149 }
1150
1151
1152 void Assembler::sbbl(Address dst, int imm32) {
1153 InstructionMark im(this);
1154 emit_arith_operand(0x81,rbx,dst,imm32);
1155 }
1156
1157
1158 void Assembler::sbbl(Register dst, int imm32) {
1159 emit_arith(0x81, 0xD8, dst, imm32);
1160 }
1161
1162
1163 void Assembler::sbbl(Register dst, Address src) {
1164 InstructionMark im(this);
1165 emit_byte(0x1B);
1166 emit_operand(dst, src);
1167 }
1168
1169
1170 void Assembler::sbbl(Register dst, Register src) {
1171 emit_arith(0x1B, 0xC0, dst, src);
1172 }
1173
1174
1175 void Assembler::shldl(Register dst, Register src) {
1176 emit_byte(0x0F);
1177 emit_byte(0xA5);
1178 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
1179 }
1180
1181
1182 void Assembler::shll(Register dst, int imm8) {
1183 assert(isShiftCount(imm8), "illegal shift count");
1184 if (imm8 == 1 ) {
1185 emit_byte(0xD1);
1186 emit_byte(0xE0 | dst->encoding());
1187 } else {
1188 emit_byte(0xC1);
1189 emit_byte(0xE0 | dst->encoding());
1190 emit_byte(imm8);
1191 }
1192 }
1193
1194
1195 void Assembler::shll(Register dst) {
1196 emit_byte(0xD3);
1197 emit_byte(0xE0 | dst->encoding());
1198 }
1199
1200
1201 void Assembler::shrdl(Register dst, Register src) {
1202 emit_byte(0x0F);
1203 emit_byte(0xAD);
1204 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding());
1205 }
1206
1207
1208 void Assembler::shrl(Register dst, int imm8) {
1209 assert(isShiftCount(imm8), "illegal shift count");
1210 emit_byte(0xC1);
1211 emit_byte(0xE8 | dst->encoding());
1212 emit_byte(imm8);
1213 }
1214
1215
1216 void Assembler::shrl(Register dst) {
1217 emit_byte(0xD3);
1218 emit_byte(0xE8 | dst->encoding());
1219 }
1220
1221
1222 void Assembler::subl(Address dst, int imm32) {
1223 if (is8bit(imm32)) {
1224 InstructionMark im(this);
1225 emit_byte(0x83);
1226 emit_operand(rbp, dst);
1227 emit_byte(imm32 & 0xFF);
1228 } else {
1229 InstructionMark im(this);
1230 emit_byte(0x81);
1231 emit_operand(rbp, dst);
1232 emit_long(imm32);
1233 }
1234 }
1235
1236
1237 void Assembler::subl(Register dst, int imm32) {
1238 emit_arith(0x81, 0xE8, dst, imm32);
1239 }
1240
1241
1242 void Assembler::subl(Address dst, Register src) {
1243 InstructionMark im(this);
1244 emit_byte(0x29);
1245 emit_operand(src, dst);
1246 }
1247
1248
1249 void Assembler::subl(Register dst, Address src) {
1250 InstructionMark im(this);
1251 emit_byte(0x2B);
1252 emit_operand(dst, src);
1253 }
1254
1255
1256 void Assembler::subl(Register dst, Register src) {
1257 emit_arith(0x2B, 0xC0, dst, src);
1258 }
1259
1260
1261 void Assembler::testb(Register dst, int imm8) {
1262 assert(dst->has_byte_register(), "must have byte register");
1263 emit_arith_b(0xF6, 0xC0, dst, imm8);
1264 }
1265
1266
1267 void Assembler::testl(Register dst, int imm32) {
1268 // not using emit_arith because test
1269 // doesn't support sign-extension of
1270 // 8bit operands
1271 if (dst->encoding() == 0) {
1272 emit_byte(0xA9);
1273 } else {
1274 emit_byte(0xF7);
1275 emit_byte(0xC0 | dst->encoding());
1276 }
1277 emit_long(imm32);
1278 }
1279
1280
1281 void Assembler::testl(Register dst, Register src) {
1282 emit_arith(0x85, 0xC0, dst, src);
1283 }
1284
1285 void Assembler::testl(Register dst, Address src) {
1286 InstructionMark im(this);
1287 emit_byte(0x85);
1288 emit_operand(dst, src);
1289 }
1290
1291 void Assembler::xaddl(Address dst, Register src) {
1292 InstructionMark im(this);
1293 emit_byte(0x0F);
1294 emit_byte(0xC1);
1295 emit_operand(src, dst);
1296 }
1297
1298 void Assembler::xorl(Register dst, int imm32) {
1299 emit_arith(0x81, 0xF0, dst, imm32);
1300 }
1301
1302
1303 void Assembler::xorl(Register dst, Address src) {
1304 InstructionMark im(this);
1305 emit_byte(0x33);
1306 emit_operand(dst, src);
1307 }
1308
1309
1310 void Assembler::xorl(Register dst, Register src) {
1311 emit_arith(0x33, 0xC0, dst, src);
1312 }
1313
1314
1315 void Assembler::bswap(Register reg) {
1316 emit_byte(0x0F);
1317 emit_byte(0xC8 | reg->encoding());
1318 }
1319
1320
1321 void Assembler::lock() {
1322 if (Atomics & 1) {
1323 // Emit either nothing, a NOP, or a NOP: prefix
1324 emit_byte(0x90) ;
1325 } else {
1326 emit_byte(0xF0);
1327 }
1328 }
1329
1330
1331 void Assembler::xchg(Register reg, Address adr) {
1332 InstructionMark im(this);
1333 emit_byte(0x87);
1334 emit_operand(reg, adr);
1335 }
1336
1337
1338 void Assembler::xchgl(Register dst, Register src) {
1339 emit_byte(0x87);
1340 emit_byte(0xc0 | dst->encoding() << 3 | src->encoding());
1341 }
1342
1343
1344 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1345 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1346 // The ZF is set if the compared values were equal, and cleared otherwise.
1347 void Assembler::cmpxchg(Register reg, Address adr) {
1348 if (Atomics & 2) {
1349 // caveat: no instructionmark, so this isn't relocatable.
1350 // Emit a synthetic, non-atomic, CAS equivalent.
1351 // Beware. The synthetic form sets all ICCs, not just ZF.
1352 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r)
1353 cmpl (rax, adr) ;
1354 movl (rax, adr) ;
1355 if (reg != rax) {
1356 Label L ;
1357 jcc (Assembler::notEqual, L) ;
1358 movl (adr, reg) ;
1359 bind (L) ;
1360 }
1361 } else {
1362 InstructionMark im(this);
1363 emit_byte(0x0F);
1364 emit_byte(0xB1);
1365 emit_operand(reg, adr);
1366 }
1367 }
1368
1369 // The 64-bit cmpxchg compares the value at adr with the contents of rdx:rax,
1370 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
1371 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
1372 void Assembler::cmpxchg8(Address adr) {
1373 InstructionMark im(this);
1374 emit_byte(0x0F);
1375 emit_byte(0xc7);
1376 emit_operand(rcx, adr);
1377 }
1378
1379 void Assembler::hlt() {
1380 emit_byte(0xF4);
1381 }
1382
1383
1384 void Assembler::addr_nop_4() {
1385 // 4 bytes: NOP DWORD PTR [EAX+0]
1386 emit_byte(0x0F);
1387 emit_byte(0x1F);
1388 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1389 emit_byte(0); // 8-bits offset (1 byte)
1390 }
1391
1392 void Assembler::addr_nop_5() {
1393 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1394 emit_byte(0x0F);
1395 emit_byte(0x1F);
1396 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1397 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1398 emit_byte(0); // 8-bits offset (1 byte)
1399 }
1400
1401 void Assembler::addr_nop_7() {
1402 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1403 emit_byte(0x0F);
1404 emit_byte(0x1F);
1405 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1406 emit_long(0); // 32-bits offset (4 bytes)
1407 }
1408
1409 void Assembler::addr_nop_8() {
1410 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1411 emit_byte(0x0F);
1412 emit_byte(0x1F);
1413 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1414 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1415 emit_long(0); // 32-bits offset (4 bytes)
1416 }
1417
1418 void Assembler::nop(int i) {
1419 assert(i > 0, " ");
1420 if (UseAddressNop && VM_Version::is_intel()) {
1421 //
1422 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
1423 // 1: 0x90
1424 // 2: 0x66 0x90
1425 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1426 // 4: 0x0F 0x1F 0x40 0x00
1427 // 5: 0x0F 0x1F 0x44 0x00 0x00
1428 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1429 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1430 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1431 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1432 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1433 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1434
1435 // The rest coding is Intel specific - don't use consecutive address nops
1436
1437 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1438 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1439 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1440 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
1441
1442 while(i >= 15) {
1443 // For Intel don't generate consecutive addess nops (mix with regular nops)
1444 i -= 15;
1445 emit_byte(0x66); // size prefix
1446 emit_byte(0x66); // size prefix
1447 emit_byte(0x66); // size prefix
1448 addr_nop_8();
1449 emit_byte(0x66); // size prefix
1450 emit_byte(0x66); // size prefix
1451 emit_byte(0x66); // size prefix
1452 emit_byte(0x90); // nop
1453 }
1454 switch (i) {
1455 case 14:
1456 emit_byte(0x66); // size prefix
1457 case 13:
1458 emit_byte(0x66); // size prefix
1459 case 12:
1460 addr_nop_8();
1461 emit_byte(0x66); // size prefix
1462 emit_byte(0x66); // size prefix
1463 emit_byte(0x66); // size prefix
1464 emit_byte(0x90); // nop
1465 break;
1466 case 11:
1467 emit_byte(0x66); // size prefix
1468 case 10:
1469 emit_byte(0x66); // size prefix
1470 case 9:
1471 emit_byte(0x66); // size prefix
1472 case 8:
1473 addr_nop_8();
1474 break;
1475 case 7:
1476 addr_nop_7();
1477 break;
1478 case 6:
1479 emit_byte(0x66); // size prefix
1480 case 5:
1481 addr_nop_5();
1482 break;
1483 case 4:
1484 addr_nop_4();
1485 break;
1486 case 3:
1487 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
1488 emit_byte(0x66); // size prefix
1489 case 2:
1490 emit_byte(0x66); // size prefix
1491 case 1:
1492 emit_byte(0x90); // nop
1493 break;
1494 default:
1495 assert(i == 0, " ");
1496 }
1497 return;
1498 }
1499 if (UseAddressNop && VM_Version::is_amd()) {
1500 //
1501 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
1502 // 1: 0x90
1503 // 2: 0x66 0x90
1504 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
1505 // 4: 0x0F 0x1F 0x40 0x00
1506 // 5: 0x0F 0x1F 0x44 0x00 0x00
1507 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
1508 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1509 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1510 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1511 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1512 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1513
1514 // The rest coding is AMD specific - use consecutive address nops
1515
1516 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
1517 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
1518 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1519 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
1520 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
1521 // Size prefixes (0x66) are added for larger sizes
1522
1523 while(i >= 22) {
1524 i -= 11;
1525 emit_byte(0x66); // size prefix
1526 emit_byte(0x66); // size prefix
1527 emit_byte(0x66); // size prefix
1528 addr_nop_8();
1529 }
1530 // Generate first nop for size between 21-12
1531 switch (i) {
1532 case 21:
1533 i -= 1;
1534 emit_byte(0x66); // size prefix
1535 case 20:
1536 case 19:
1537 i -= 1;
1538 emit_byte(0x66); // size prefix
1539 case 18:
1540 case 17:
1541 i -= 1;
1542 emit_byte(0x66); // size prefix
1543 case 16:
1544 case 15:
1545 i -= 8;
1546 addr_nop_8();
1547 break;
1548 case 14:
1549 case 13:
1550 i -= 7;
1551 addr_nop_7();
1552 break;
1553 case 12:
1554 i -= 6;
1555 emit_byte(0x66); // size prefix
1556 addr_nop_5();
1557 break;
1558 default:
1559 assert(i < 12, " ");
1560 }
1561
1562 // Generate second nop for size between 11-1
1563 switch (i) {
1564 case 11:
1565 emit_byte(0x66); // size prefix
1566 case 10:
1567 emit_byte(0x66); // size prefix
1568 case 9:
1569 emit_byte(0x66); // size prefix
1570 case 8:
1571 addr_nop_8();
1572 break;
1573 case 7:
1574 addr_nop_7();
1575 break;
1576 case 6:
1577 emit_byte(0x66); // size prefix
1578 case 5:
1579 addr_nop_5();
1580 break;
1581 case 4:
1582 addr_nop_4();
1583 break;
1584 case 3:
1585 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
1586 emit_byte(0x66); // size prefix
1587 case 2:
1588 emit_byte(0x66); // size prefix
1589 case 1:
1590 emit_byte(0x90); // nop
1591 break;
1592 default:
1593 assert(i == 0, " ");
1594 }
1595 return;
1596 }
1597
1598 // Using nops with size prefixes "0x66 0x90".
1599 // From AMD Optimization Guide:
1600 // 1: 0x90
1601 // 2: 0x66 0x90
1602 // 3: 0x66 0x66 0x90
1603 // 4: 0x66 0x66 0x66 0x90
1604 // 5: 0x66 0x66 0x90 0x66 0x90
1605 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
1606 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
1607 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
1608 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
1609 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
1610 //
1611 while(i > 12) {
1612 i -= 4;
1613 emit_byte(0x66); // size prefix
1614 emit_byte(0x66);
1615 emit_byte(0x66);
1616 emit_byte(0x90); // nop
1617 }
1618 // 1 - 12 nops
1619 if(i > 8) {
1620 if(i > 9) {
1621 i -= 1;
1622 emit_byte(0x66);
1623 }
1624 i -= 3;
1625 emit_byte(0x66);
1626 emit_byte(0x66);
1627 emit_byte(0x90);
1628 }
1629 // 1 - 8 nops
1630 if(i > 4) {
1631 if(i > 6) {
1632 i -= 1;
1633 emit_byte(0x66);
1634 }
1635 i -= 3;
1636 emit_byte(0x66);
1637 emit_byte(0x66);
1638 emit_byte(0x90);
1639 }
1640 switch (i) {
1641 case 4:
1642 emit_byte(0x66);
1643 case 3:
1644 emit_byte(0x66);
1645 case 2:
1646 emit_byte(0x66);
1647 case 1:
1648 emit_byte(0x90);
1649 break;
1650 default:
1651 assert(i == 0, " ");
1652 }
1653 }
1654
1655 void Assembler::ret(int imm16) {
1656 if (imm16 == 0) {
1657 emit_byte(0xC3);
1658 } else {
1659 emit_byte(0xC2);
1660 emit_word(imm16);
1661 }
1662 }
1663
1664
1665 void Assembler::set_byte_if_not_zero(Register dst) {
1666 emit_byte(0x0F);
1667 emit_byte(0x95);
1668 emit_byte(0xE0 | dst->encoding());
1669 }
1670
1671
1672 // copies a single word from [esi] to [edi]
1673 void Assembler::smovl() {
1674 emit_byte(0xA5);
1675 }
1676
1677 // copies data from [esi] to [edi] using rcx double words (m32)
1678 void Assembler::rep_movl() {
1679 emit_byte(0xF3);
1680 emit_byte(0xA5);
1681 }
1682
1683
1684 // sets rcx double words (m32) with rax, value at [edi]
1685 void Assembler::rep_set() {
1686 emit_byte(0xF3);
1687 emit_byte(0xAB);
1688 }
1689
1690 // scans rcx double words (m32) at [edi] for occurance of rax,
1691 void Assembler::repne_scan() {
1692 emit_byte(0xF2);
1693 emit_byte(0xAF);
1694 }
1695
1696
1697 void Assembler::setb(Condition cc, Register dst) {
1698 assert(0 <= cc && cc < 16, "illegal cc");
1699 emit_byte(0x0F);
1700 emit_byte(0x90 | cc);
1701 emit_byte(0xC0 | dst->encoding());
1702 }
1703
1704 void Assembler::cld() {
1705 emit_byte(0xfc);
1706 }
1707
1708 void Assembler::std() {
1709 emit_byte(0xfd);
1710 }
1711
1712 void Assembler::emit_raw (unsigned char b) {
1713 emit_byte (b) ;
1714 }
1715
1716 // Serializes memory.
1717 void Assembler::membar() {
1718 // Memory barriers are only needed on multiprocessors
1719 if (os::is_MP()) {
1720 if( VM_Version::supports_sse2() ) {
1721 emit_byte( 0x0F ); // MFENCE; faster blows no regs
1722 emit_byte( 0xAE );
1723 emit_byte( 0xF0 );
1724 } else {
1725 // All usable chips support "locked" instructions which suffice
1726 // as barriers, and are much faster than the alternative of
1727 // using cpuid instruction. We use here a locked add [esp],0.
1728 // This is conveniently otherwise a no-op except for blowing
1729 // flags (which we save and restore.)
1730 pushfd(); // Save eflags register
1731 lock();
1732 addl(Address(rsp, 0), 0);// Assert the lock# signal here
1733 popfd(); // Restore eflags register
1734 }
1735 }
1736 }
1737
1738 // Identify processor type and features
1739 void Assembler::cpuid() {
1740 // Note: we can't assert VM_Version::supports_cpuid() here
1741 // because this instruction is used in the processor
1742 // identification code.
1743 emit_byte( 0x0F );
1744 emit_byte( 0xA2 );
1745 }
1746
1747 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1748 if (L.is_bound()) {
1749 const int long_size = 5;
1750 int offs = target(L) - pc();
1751 assert(offs <= 0, "assembler error");
1752 InstructionMark im(this);
1753 // 1110 1000 #32-bit disp
1754 emit_byte(0xE8);
1755 emit_data(offs - long_size, rtype, 0);
1756 } else {
1757 InstructionMark im(this);
1758 // 1110 1000 #32-bit disp
1759 L.add_patch_at(code(), locator());
1760 emit_byte(0xE8);
1761 emit_data(int(0), rtype, 0);
1762 }
1763 }
1764
1765 void Assembler::call(Register dst) {
1766 emit_byte(0xFF);
1767 emit_byte(0xD0 | dst->encoding());
1768 }
1769
1770
1771 void Assembler::call(Address adr) {
1772 InstructionMark im(this);
1773 relocInfo::relocType rtype = adr.reloc();
1774 if (rtype != relocInfo::runtime_call_type) {
1775 emit_byte(0xFF);
1776 emit_operand(rdx, adr);
1777 } else {
1778 assert(false, "ack");
1779 }
1780
1781 }
1782
1783 void Assembler::call_literal(address dest, RelocationHolder const& rspec) {
1784 InstructionMark im(this);
1785 emit_byte(0xE8);
1786 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1787 assert(dest != NULL, "must have a target");
1788 emit_data(disp, rspec, call32_operand);
1789
1790 }
1791
1792 void Assembler::jmp(Register entry) {
1793 emit_byte(0xFF);
1794 emit_byte(0xE0 | entry->encoding());
1795 }
1796
1797
1798 void Assembler::jmp(Address adr) {
1799 InstructionMark im(this);
1800 emit_byte(0xFF);
1801 emit_operand(rsp, adr);
1802 }
1803
1804 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1805 InstructionMark im(this);
1806 emit_byte(0xE9);
1807 assert(dest != NULL, "must have a target");
1808 intptr_t disp = dest - (_code_pos + sizeof(int32_t));
1809 emit_data(disp, rspec.reloc(), call32_operand);
1810 }
1811
1812 void Assembler::jmp(Label& L, relocInfo::relocType rtype) {
1813 if (L.is_bound()) {
1814 address entry = target(L);
1815 assert(entry != NULL, "jmp most probably wrong");
1816 InstructionMark im(this);
1817 const int short_size = 2;
1818 const int long_size = 5;
1819 intptr_t offs = entry - _code_pos;
1820 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1821 emit_byte(0xEB);
1822 emit_byte((offs - short_size) & 0xFF);
1823 } else {
1824 emit_byte(0xE9);
1825 emit_long(offs - long_size);
1826 }
1827 } else {
1828 // By default, forward jumps are always 32-bit displacements, since
1829 // we can't yet know where the label will be bound. If you're sure that
1830 // the forward jump will not run beyond 256 bytes, use jmpb to
1831 // force an 8-bit displacement.
1832 InstructionMark im(this);
1833 relocate(rtype);
1834 L.add_patch_at(code(), locator());
1835 emit_byte(0xE9);
1836 emit_long(0);
1837 }
1838 }
1839
1840 void Assembler::jmpb(Label& L) {
1841 if (L.is_bound()) {
1842 const int short_size = 2;
1843 address entry = target(L);
1844 assert(is8bit((entry - _code_pos) + short_size),
1845 "Dispacement too large for a short jmp");
1846 assert(entry != NULL, "jmp most probably wrong");
1847 intptr_t offs = entry - _code_pos;
1848 emit_byte(0xEB);
1849 emit_byte((offs - short_size) & 0xFF);
1850 } else {
1851 InstructionMark im(this);
1852 L.add_patch_at(code(), locator());
1853 emit_byte(0xEB);
1854 emit_byte(0);
1855 }
1856 }
1857
1858 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) {
1859 InstructionMark im(this);
1860 relocate(rtype);
1861 assert((0 <= cc) && (cc < 16), "illegal cc");
1862 if (L.is_bound()) {
1863 address dst = target(L);
1864 assert(dst != NULL, "jcc most probably wrong");
1865
1866 const int short_size = 2;
1867 const int long_size = 6;
1868 int offs = (int)dst - ((int)_code_pos);
1869 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
1870 // 0111 tttn #8-bit disp
1871 emit_byte(0x70 | cc);
1872 emit_byte((offs - short_size) & 0xFF);
1873 } else {
1874 // 0000 1111 1000 tttn #32-bit disp
1875 emit_byte(0x0F);
1876 emit_byte(0x80 | cc);
1877 emit_long(offs - long_size);
1878 }
1879 } else {
1880 // Note: could eliminate cond. jumps to this jump if condition
1881 // is the same however, seems to be rather unlikely case.
1882 // Note: use jccb() if label to be bound is very close to get
1883 // an 8-bit displacement
1884 L.add_patch_at(code(), locator());
1885 emit_byte(0x0F);
1886 emit_byte(0x80 | cc);
1887 emit_long(0);
1888 }
1889 }
1890
1891 void Assembler::jccb(Condition cc, Label& L) {
1892 if (L.is_bound()) {
1893 const int short_size = 2;
1894 address entry = target(L);
1895 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)),
1896 "Dispacement too large for a short jmp");
1897 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos;
1898 // 0111 tttn #8-bit disp
1899 emit_byte(0x70 | cc);
1900 emit_byte((offs - short_size) & 0xFF);
1901 jcc(cc, L);
1902 } else {
1903 InstructionMark im(this);
1904 L.add_patch_at(code(), locator());
1905 emit_byte(0x70 | cc);
1906 emit_byte(0);
1907 }
1908 }
1909
1910 // FPU instructions
1911
1912 void Assembler::fld1() {
1913 emit_byte(0xD9);
1914 emit_byte(0xE8);
1915 }
1916
1917
1918 void Assembler::fldz() {
1919 emit_byte(0xD9);
1920 emit_byte(0xEE);
1921 }
1922
1923
1924 void Assembler::fld_s(Address adr) {
1925 InstructionMark im(this);
1926 emit_byte(0xD9);
1927 emit_operand(rax, adr);
1928 }
1929
1930
1931 void Assembler::fld_s (int index) {
1932 emit_farith(0xD9, 0xC0, index);
1933 }
1934
1935
1936 void Assembler::fld_d(Address adr) {
1937 InstructionMark im(this);
1938 emit_byte(0xDD);
1939 emit_operand(rax, adr);
1940 }
1941
1942
1943 void Assembler::fld_x(Address adr) {
1944 InstructionMark im(this);
1945 emit_byte(0xDB);
1946 emit_operand(rbp, adr);
1947 }
1948
1949
1950 void Assembler::fst_s(Address adr) {
1951 InstructionMark im(this);
1952 emit_byte(0xD9);
1953 emit_operand(rdx, adr);
1954 }
1955
1956
1957 void Assembler::fst_d(Address adr) {
1958 InstructionMark im(this);
1959 emit_byte(0xDD);
1960 emit_operand(rdx, adr);
1961 }
1962
1963
1964 void Assembler::fstp_s(Address adr) {
1965 InstructionMark im(this);
1966 emit_byte(0xD9);
1967 emit_operand(rbx, adr);
1968 }
1969
1970
1971 void Assembler::fstp_d(Address adr) {
1972 InstructionMark im(this);
1973 emit_byte(0xDD);
1974 emit_operand(rbx, adr);
1975 }
1976
1977
1978 void Assembler::fstp_x(Address adr) {
1979 InstructionMark im(this);
1980 emit_byte(0xDB);
1981 emit_operand(rdi, adr);
1982 }
1983
1984
1985 void Assembler::fstp_d(int index) {
1986 emit_farith(0xDD, 0xD8, index);
1987 }
1988
1989
1990 void Assembler::fild_s(Address adr) {
1991 InstructionMark im(this);
1992 emit_byte(0xDB);
1993 emit_operand(rax, adr);
1994 }
1995
1996
1997 void Assembler::fild_d(Address adr) {
1998 InstructionMark im(this);
1999 emit_byte(0xDF);
2000 emit_operand(rbp, adr);
2001 }
2002
2003
2004 void Assembler::fistp_s(Address adr) {
2005 InstructionMark im(this);
2006 emit_byte(0xDB);
2007 emit_operand(rbx, adr);
2008 }
2009
2010
2011 void Assembler::fistp_d(Address adr) {
2012 InstructionMark im(this);
2013 emit_byte(0xDF);
2014 emit_operand(rdi, adr);
2015 }
2016
2017
2018 void Assembler::fist_s(Address adr) {
2019 InstructionMark im(this);
2020 emit_byte(0xDB);
2021 emit_operand(rdx, adr);
2022 }
2023
2024
2025 void Assembler::fabs() {
2026 emit_byte(0xD9);
2027 emit_byte(0xE1);
2028 }
2029
2030
2031 void Assembler::fldln2() {
2032 emit_byte(0xD9);
2033 emit_byte(0xED);
2034 }
2035
2036 void Assembler::fyl2x() {
2037 emit_byte(0xD9);
2038 emit_byte(0xF1);
2039 }
2040
2041
2042 void Assembler::fldlg2() {
2043 emit_byte(0xD9);
2044 emit_byte(0xEC);
2045 }
2046
2047
2048 void Assembler::flog() {
2049 fldln2();
2050 fxch();
2051 fyl2x();
2052 }
2053
2054
2055 void Assembler::flog10() {
2056 fldlg2();
2057 fxch();
2058 fyl2x();
2059 }
2060
2061
2062 void Assembler::fsin() {
2063 emit_byte(0xD9);
2064 emit_byte(0xFE);
2065 }
2066
2067
2068 void Assembler::fcos() {
2069 emit_byte(0xD9);
2070 emit_byte(0xFF);
2071 }
2072
2073 void Assembler::ftan() {
2074 emit_byte(0xD9);
2075 emit_byte(0xF2);
2076 emit_byte(0xDD);
2077 emit_byte(0xD8);
2078 }
2079
2080 void Assembler::fsqrt() {
2081 emit_byte(0xD9);
2082 emit_byte(0xFA);
2083 }
2084
2085
2086 void Assembler::fchs() {
2087 emit_byte(0xD9);
2088 emit_byte(0xE0);
2089 }
2090
2091
2092 void Assembler::fadd_s(Address src) {
2093 InstructionMark im(this);
2094 emit_byte(0xD8);
2095 emit_operand(rax, src);
2096 }
2097
2098
2099 void Assembler::fadd_d(Address src) {
2100 InstructionMark im(this);
2101 emit_byte(0xDC);
2102 emit_operand(rax, src);
2103 }
2104
2105
2106 void Assembler::fadd(int i) {
2107 emit_farith(0xD8, 0xC0, i);
2108 }
2109
2110
2111 void Assembler::fadda(int i) {
2112 emit_farith(0xDC, 0xC0, i);
2113 }
2114
2115
2116 void Assembler::fsub_d(Address src) {
2117 InstructionMark im(this);
2118 emit_byte(0xDC);
2119 emit_operand(rsp, src);
2120 }
2121
2122
2123 void Assembler::fsub_s(Address src) {
2124 InstructionMark im(this);
2125 emit_byte(0xD8);
2126 emit_operand(rsp, src);
2127 }
2128
2129
2130 void Assembler::fsubr_s(Address src) {
2131 InstructionMark im(this);
2132 emit_byte(0xD8);
2133 emit_operand(rbp, src);
2134 }
2135
2136
2137 void Assembler::fsubr_d(Address src) {
2138 InstructionMark im(this);
2139 emit_byte(0xDC);
2140 emit_operand(rbp, src);
2141 }
2142
2143
2144 void Assembler::fmul_s(Address src) {
2145 InstructionMark im(this);
2146 emit_byte(0xD8);
2147 emit_operand(rcx, src);
2148 }
2149
2150
2151 void Assembler::fmul_d(Address src) {
2152 InstructionMark im(this);
2153 emit_byte(0xDC);
2154 emit_operand(rcx, src);
2155 }
2156
2157
2158 void Assembler::fmul(int i) {
2159 emit_farith(0xD8, 0xC8, i);
2160 }
2161
2162
2163 void Assembler::fmula(int i) {
2164 emit_farith(0xDC, 0xC8, i);
2165 }
2166
2167
2168 void Assembler::fdiv_s(Address src) {
2169 InstructionMark im(this);
2170 emit_byte(0xD8);
2171 emit_operand(rsi, src);
2172 }
2173
2174
2175 void Assembler::fdiv_d(Address src) {
2176 InstructionMark im(this);
2177 emit_byte(0xDC);
2178 emit_operand(rsi, src);
2179 }
2180
2181
2182 void Assembler::fdivr_s(Address src) {
2183 InstructionMark im(this);
2184 emit_byte(0xD8);
2185 emit_operand(rdi, src);
2186 }
2187
2188
2189 void Assembler::fdivr_d(Address src) {
2190 InstructionMark im(this);
2191 emit_byte(0xDC);
2192 emit_operand(rdi, src);
2193 }
2194
2195
2196 void Assembler::fsub(int i) {
2197 emit_farith(0xD8, 0xE0, i);
2198 }
2199
2200
2201 void Assembler::fsuba(int i) {
2202 emit_farith(0xDC, 0xE8, i);
2203 }
2204
2205
2206 void Assembler::fsubr(int i) {
2207 emit_farith(0xD8, 0xE8, i);
2208 }
2209
2210
2211 void Assembler::fsubra(int i) {
2212 emit_farith(0xDC, 0xE0, i);
2213 }
2214
2215
2216 void Assembler::fdiv(int i) {
2217 emit_farith(0xD8, 0xF0, i);
2218 }
2219
2220
2221 void Assembler::fdiva(int i) {
2222 emit_farith(0xDC, 0xF8, i);
2223 }
2224
2225
2226 void Assembler::fdivr(int i) {
2227 emit_farith(0xD8, 0xF8, i);
2228 }
2229
2230
2231 void Assembler::fdivra(int i) {
2232 emit_farith(0xDC, 0xF0, i);
2233 }
2234
2235
2236 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
2237 // is erroneous for some of the floating-point instructions below.
2238
2239 void Assembler::fdivp(int i) {
2240 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
2241 }
2242
2243
2244 void Assembler::fdivrp(int i) {
2245 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
2246 }
2247
2248
2249 void Assembler::fsubp(int i) {
2250 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
2251 }
2252
2253
2254 void Assembler::fsubrp(int i) {
2255 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
2256 }
2257
2258
2259 void Assembler::faddp(int i) {
2260 emit_farith(0xDE, 0xC0, i);
2261 }
2262
2263
2264 void Assembler::fmulp(int i) {
2265 emit_farith(0xDE, 0xC8, i);
2266 }
2267
2268
2269 void Assembler::fprem() {
2270 emit_byte(0xD9);
2271 emit_byte(0xF8);
2272 }
2273
2274
2275 void Assembler::fprem1() {
2276 emit_byte(0xD9);
2277 emit_byte(0xF5);
2278 }
2279
2280
2281 void Assembler::fxch(int i) {
2282 emit_farith(0xD9, 0xC8, i);
2283 }
2284
2285
2286 void Assembler::fincstp() {
2287 emit_byte(0xD9);
2288 emit_byte(0xF7);
2289 }
2290
2291
2292 void Assembler::fdecstp() {
2293 emit_byte(0xD9);
2294 emit_byte(0xF6);
2295 }
2296
2297
2298 void Assembler::ffree(int i) {
2299 emit_farith(0xDD, 0xC0, i);
2300 }
2301
2302
2303 void Assembler::fcomp_s(Address src) {
2304 InstructionMark im(this);
2305 emit_byte(0xD8);
2306 emit_operand(rbx, src);
2307 }
2308
2309
2310 void Assembler::fcomp_d(Address src) {
2311 InstructionMark im(this);
2312 emit_byte(0xDC);
2313 emit_operand(rbx, src);
2314 }
2315
2316
2317 void Assembler::fcom(int i) {
2318 emit_farith(0xD8, 0xD0, i);
2319 }
2320
2321
2322 void Assembler::fcomp(int i) {
2323 emit_farith(0xD8, 0xD8, i);
2324 }
2325
2326
2327 void Assembler::fcompp() {
2328 emit_byte(0xDE);
2329 emit_byte(0xD9);
2330 }
2331
2332
2333 void Assembler::fucomi(int i) {
2334 // make sure the instruction is supported (introduced for P6, together with cmov)
2335 guarantee(VM_Version::supports_cmov(), "illegal instruction");
2336 emit_farith(0xDB, 0xE8, i);
2337 }
2338
2339
2340 void Assembler::fucomip(int i) {
2341 // make sure the instruction is supported (introduced for P6, together with cmov)
2342 guarantee(VM_Version::supports_cmov(), "illegal instruction");
2343 emit_farith(0xDF, 0xE8, i);
2344 }
2345
2346
2347 void Assembler::ftst() {
2348 emit_byte(0xD9);
2349 emit_byte(0xE4);
2350 }
2351
2352
2353 void Assembler::fnstsw_ax() {
2354 emit_byte(0xdF);
2355 emit_byte(0xE0);
2356 }
2357
2358
2359 void Assembler::fwait() {
2360 emit_byte(0x9B);
2361 }
2362
2363
2364 void Assembler::finit() {
2365 emit_byte(0x9B);
2366 emit_byte(0xDB);
2367 emit_byte(0xE3);
2368 }
2369
2370
2371 void Assembler::fldcw(Address src) {
2372 InstructionMark im(this);
2373 emit_byte(0xd9);
2374 emit_operand(rbp, src);
2375 }
2376
2377
2378 void Assembler::fnstcw(Address src) {
2379 InstructionMark im(this);
2380 emit_byte(0x9B);
2381 emit_byte(0xD9);
2382 emit_operand(rdi, src);
2383 }
2384
2385 void Assembler::fnsave(Address dst) {
2386 InstructionMark im(this);
2387 emit_byte(0xDD);
2388 emit_operand(rsi, dst);
2389 }
2390
2391
2392 void Assembler::frstor(Address src) {
2393 InstructionMark im(this);
2394 emit_byte(0xDD);
2395 emit_operand(rsp, src);
2396 }
2397
2398
2399 void Assembler::fldenv(Address src) {
2400 InstructionMark im(this);
2401 emit_byte(0xD9);
2402 emit_operand(rsp, src);
2403 }
2404
2405
2406 void Assembler::sahf() {
2407 emit_byte(0x9E);
2408 }
2409
2410 // MMX operations
2411 void Assembler::emit_operand(MMXRegister reg, Address adr) {
2412 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
2413 }
2414
2415 void Assembler::movq( MMXRegister dst, Address src ) {
2416 assert( VM_Version::supports_mmx(), "" );
2417 emit_byte(0x0F);
2418 emit_byte(0x6F);
2419 emit_operand(dst,src);
2420 }
2421
2422 void Assembler::movq( Address dst, MMXRegister src ) {
2423 assert( VM_Version::supports_mmx(), "" );
2424 emit_byte(0x0F);
2425 emit_byte(0x7F);
2426 emit_operand(src,dst);
2427 }
2428
2429 void Assembler::emms() {
2430 emit_byte(0x0F);
2431 emit_byte(0x77);
2432 }
2433
2434
2435
2436
2437 // SSE and SSE2 instructions
2438 inline void Assembler::emit_sse_operand(XMMRegister reg, Address adr) {
2439 assert(((Register)reg)->encoding() == reg->encoding(), "otherwise typecast is invalid");
2440 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
2441 }
2442 inline void Assembler::emit_sse_operand(Register reg, Address adr) {
2443 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
2444 }
2445
2446 inline void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2447 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
2448 }
2449 inline void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2450 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
2451 }
2452 inline void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2453 emit_byte(0xC0 | dst->encoding() << 3 | src->encoding());
2454 }
2455
2456
2457 // Macro for creation of SSE2 instructions
2458 // The SSE2 instricution set is highly regular, so this macro saves
2459 // a lot of cut&paste
2460 // Each macro expansion creates two methods (same name with different
2461 // parameter list)
2462 //
2463 // Macro parameters:
2464 // * name: name of the created methods
2465 // * sse_version: either sse or sse2 for the assertion if instruction supported by processor
2466 // * prefix: first opcode byte of the instruction (or 0 if no prefix byte)
2467 // * opcode: last opcode byte of the instruction
2468 // * conversion instruction have parameters of type Register instead of XMMRegister,
2469 // so this can also configured with macro parameters
2470 #define emit_sse_instruction(name, sse_version, prefix, opcode, dst_register_type, src_register_type) \
2471 \
2472 void Assembler:: name (dst_register_type dst, Address src) { \
2473 assert(VM_Version::supports_##sse_version(), ""); \
2474 \
2475 InstructionMark im(this); \
2476 if (prefix != 0) emit_byte(prefix); \
2477 emit_byte(0x0F); \
2478 emit_byte(opcode); \
2479 emit_sse_operand(dst, src); \
2480 } \
2481 \
2482 void Assembler:: name (dst_register_type dst, src_register_type src) { \
2483 assert(VM_Version::supports_##sse_version(), ""); \
2484 \
2485 if (prefix != 0) emit_byte(prefix); \
2486 emit_byte(0x0F); \
2487 emit_byte(opcode); \
2488 emit_sse_operand(dst, src); \
2489 } \
2490
2491 emit_sse_instruction(addss, sse, 0xF3, 0x58, XMMRegister, XMMRegister);
2492 emit_sse_instruction(addsd, sse2, 0xF2, 0x58, XMMRegister, XMMRegister)
2493 emit_sse_instruction(subss, sse, 0xF3, 0x5C, XMMRegister, XMMRegister)
2494 emit_sse_instruction(subsd, sse2, 0xF2, 0x5C, XMMRegister, XMMRegister)
2495 emit_sse_instruction(mulss, sse, 0xF3, 0x59, XMMRegister, XMMRegister)
2496 emit_sse_instruction(mulsd, sse2, 0xF2, 0x59, XMMRegister, XMMRegister)
2497 emit_sse_instruction(divss, sse, 0xF3, 0x5E, XMMRegister, XMMRegister)
2498 emit_sse_instruction(divsd, sse2, 0xF2, 0x5E, XMMRegister, XMMRegister)
2499 emit_sse_instruction(sqrtss, sse, 0xF3, 0x51, XMMRegister, XMMRegister)
2500 emit_sse_instruction(sqrtsd, sse2, 0xF2, 0x51, XMMRegister, XMMRegister)
2501
2502 emit_sse_instruction(pxor, sse2, 0x66, 0xEF, XMMRegister, XMMRegister)
2503
2504 emit_sse_instruction(comiss, sse, 0, 0x2F, XMMRegister, XMMRegister)
2505 emit_sse_instruction(comisd, sse2, 0x66, 0x2F, XMMRegister, XMMRegister)
2506 emit_sse_instruction(ucomiss, sse, 0, 0x2E, XMMRegister, XMMRegister)
2507 emit_sse_instruction(ucomisd, sse2, 0x66, 0x2E, XMMRegister, XMMRegister)
2508
2509 emit_sse_instruction(cvtss2sd, sse2, 0xF3, 0x5A, XMMRegister, XMMRegister);
2510 emit_sse_instruction(cvtsd2ss, sse2, 0xF2, 0x5A, XMMRegister, XMMRegister)
2511 emit_sse_instruction(cvtsi2ss, sse, 0xF3, 0x2A, XMMRegister, Register);
2512 emit_sse_instruction(cvtsi2sd, sse2, 0xF2, 0x2A, XMMRegister, Register)
2513 emit_sse_instruction(cvtss2si, sse, 0xF3, 0x2D, Register, XMMRegister);
2514 emit_sse_instruction(cvtsd2si, sse2, 0xF2, 0x2D, Register, XMMRegister)
2515 emit_sse_instruction(cvttss2si, sse, 0xF3, 0x2C, Register, XMMRegister);
2516 emit_sse_instruction(cvttsd2si, sse2, 0xF2, 0x2C, Register, XMMRegister)
2517
2518 emit_sse_instruction(movss, sse, 0xF3, 0x10, XMMRegister, XMMRegister)
2519 emit_sse_instruction(movsd, sse2, 0xF2, 0x10, XMMRegister, XMMRegister)
2520
2521 emit_sse_instruction(movq, sse2, 0xF3, 0x7E, XMMRegister, XMMRegister);
2522 emit_sse_instruction(movd, sse2, 0x66, 0x6E, XMMRegister, Register);
2523 emit_sse_instruction(movdqa, sse2, 0x66, 0x6F, XMMRegister, XMMRegister);
2524
2525 emit_sse_instruction(punpcklbw, sse2, 0x66, 0x60, XMMRegister, XMMRegister);
2526
2527
2528 // Instruction not covered by macro
2529 void Assembler::movq(Address dst, XMMRegister src) {
2530 assert(VM_Version::supports_sse2(), "");
2531
2532 InstructionMark im(this);
2533 emit_byte(0x66);
2534 emit_byte(0x0F);
2535 emit_byte(0xD6);
2536 emit_sse_operand(src, dst);
2537 }
2538
2539 void Assembler::movd(Address dst, XMMRegister src) {
2540 assert(VM_Version::supports_sse2(), "");
2541
2542 InstructionMark im(this);
2543 emit_byte(0x66);
2544 emit_byte(0x0F);
2545 emit_byte(0x7E);
2546 emit_sse_operand(src, dst);
2547 }
2548
2549 void Assembler::movd(Register dst, XMMRegister src) {
2550 assert(VM_Version::supports_sse2(), "");
2551
2552 emit_byte(0x66);
2553 emit_byte(0x0F);
2554 emit_byte(0x7E);
2555 emit_sse_operand(src, dst);
2556 }
2557
2558 void Assembler::movdqa(Address dst, XMMRegister src) {
2559 assert(VM_Version::supports_sse2(), "");
2560
2561 InstructionMark im(this);
2562 emit_byte(0x66);
2563 emit_byte(0x0F);
2564 emit_byte(0x7F);
2565 emit_sse_operand(src, dst);
2566 }
2567
2568 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2569 assert(isByte(mode), "invalid value");
2570 assert(VM_Version::supports_sse2(), "");
2571
2572 emit_byte(0x66);
2573 emit_byte(0x0F);
2574 emit_byte(0x70);
2575 emit_sse_operand(dst, src);
2576 emit_byte(mode & 0xFF);
2577 }
2578
2579 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2580 assert(isByte(mode), "invalid value");
2581 assert(VM_Version::supports_sse2(), "");
2582
2583 InstructionMark im(this);
2584 emit_byte(0x66);
2585 emit_byte(0x0F);
2586 emit_byte(0x70);
2587 emit_sse_operand(dst, src);
2588 emit_byte(mode & 0xFF);
2589 }
2590
2591 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2592 assert(isByte(mode), "invalid value");
2593 assert(VM_Version::supports_sse2(), "");
2594
2595 emit_byte(0xF2);
2596 emit_byte(0x0F);
2597 emit_byte(0x70);
2598 emit_sse_operand(dst, src);
2599 emit_byte(mode & 0xFF);
2600 }
2601
2602 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2603 assert(isByte(mode), "invalid value");
2604 assert(VM_Version::supports_sse2(), "");
2605
2606 InstructionMark im(this);
2607 emit_byte(0xF2);
2608 emit_byte(0x0F);
2609 emit_byte(0x70);
2610 emit_sse_operand(dst, src);
2611 emit_byte(mode & 0xFF);
2612 }
2613
2614 void Assembler::psrlq(XMMRegister dst, int shift) {
2615 assert(VM_Version::supports_sse2(), "");
2616
2617 emit_byte(0x66);
2618 emit_byte(0x0F);
2619 emit_byte(0x73);
2620 emit_sse_operand(xmm2, dst);
2621 emit_byte(shift);
2622 }
2623
2624 void Assembler::movss( Address dst, XMMRegister src ) {
2625 assert(VM_Version::supports_sse(), "");
2626
2627 InstructionMark im(this);
2628 emit_byte(0xF3); // single
2629 emit_byte(0x0F);
2630 emit_byte(0x11); // store
2631 emit_sse_operand(src, dst);
2632 }
2633
2634 void Assembler::movsd( Address dst, XMMRegister src ) {
2635 assert(VM_Version::supports_sse2(), "");
2636
2637 InstructionMark im(this);
2638 emit_byte(0xF2); // double
2639 emit_byte(0x0F);
2640 emit_byte(0x11); // store
2641 emit_sse_operand(src,dst);
2642 }
2643
2644 // New cpus require to use movaps and movapd to avoid partial register stall
2645 // when moving between registers.
2646 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2647 assert(VM_Version::supports_sse(), "");
2648
2649 emit_byte(0x0F);
2650 emit_byte(0x28);
2651 emit_sse_operand(dst, src);
2652 }
2653 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2654 assert(VM_Version::supports_sse2(), "");
2655
2656 emit_byte(0x66);
2657 emit_byte(0x0F);
2658 emit_byte(0x28);
2659 emit_sse_operand(dst, src);
2660 }
2661
2662 // New cpus require to use movsd and movss to avoid partial register stall
2663 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2664 // The selection is done in MacroAssembler::movdbl() and movflt().
2665 void Assembler::movlpd(XMMRegister dst, Address src) {
2666 assert(VM_Version::supports_sse(), "");
2667
2668 InstructionMark im(this);
2669 emit_byte(0x66);
2670 emit_byte(0x0F);
2671 emit_byte(0x12);
2672 emit_sse_operand(dst, src);
2673 }
2674
2675 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
2676 assert(VM_Version::supports_sse2(), "");
2677
2678 emit_byte(0xF3);
2679 emit_byte(0x0F);
2680 emit_byte(0xE6);
2681 emit_sse_operand(dst, src);
2682 }
2683
2684 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
2685 assert(VM_Version::supports_sse2(), "");
2686
2687 emit_byte(0x0F);
2688 emit_byte(0x5B);
2689 emit_sse_operand(dst, src);
2690 }
2691
2692 emit_sse_instruction(andps, sse, 0, 0x54, XMMRegister, XMMRegister);
2693 emit_sse_instruction(andpd, sse2, 0x66, 0x54, XMMRegister, XMMRegister);
2694 emit_sse_instruction(andnps, sse, 0, 0x55, XMMRegister, XMMRegister);
2695 emit_sse_instruction(andnpd, sse2, 0x66, 0x55, XMMRegister, XMMRegister);
2696 emit_sse_instruction(orps, sse, 0, 0x56, XMMRegister, XMMRegister);
2697 emit_sse_instruction(orpd, sse2, 0x66, 0x56, XMMRegister, XMMRegister);
2698 emit_sse_instruction(xorps, sse, 0, 0x57, XMMRegister, XMMRegister);
2699 emit_sse_instruction(xorpd, sse2, 0x66, 0x57, XMMRegister, XMMRegister);
2700
2701
2702 void Assembler::ldmxcsr( Address src) {
2703 InstructionMark im(this);
2704 emit_byte(0x0F);
2705 emit_byte(0xAE);
2706 emit_operand(rdx /* 2 */, src);
2707 }
2708
2709 void Assembler::stmxcsr( Address dst) {
2710 InstructionMark im(this);
2711 emit_byte(0x0F);
2712 emit_byte(0xAE);
2713 emit_operand(rbx /* 3 */, dst);
2714 }
2715
2716 // Implementation of MacroAssembler
2717
2718 Address MacroAssembler::as_Address(AddressLiteral adr) {
2719 // amd64 always does this as a pc-rel
2720 // we can be absolute or disp based on the instruction type
2721 // jmp/call are displacements others are absolute
2722 assert(!adr.is_lval(), "must be rval");
2723
2724 return Address(adr.target(), adr.rspec());
2725 }
2726
2727 Address MacroAssembler::as_Address(ArrayAddress adr) {
2728 return Address::make_array(adr);
2729 }
2730
2731 void MacroAssembler::fat_nop() {
2732 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2733 emit_byte(0x26); // es:
2734 emit_byte(0x2e); // cs:
2735 emit_byte(0x64); // fs:
2736 emit_byte(0x65); // gs:
2737 emit_byte(0x90);
2738 }
2739
2740 // 32bit can do a case table jump in one instruction but we no longer allow the base
2741 // to be installed in the Address class
2742 void MacroAssembler::jump(ArrayAddress entry) {
2743 jmp(as_Address(entry));
2744 }
2745
2746 void MacroAssembler::jump(AddressLiteral dst) {
2747 jmp_literal(dst.target(), dst.rspec());
2748 }
2749
2750 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2751 assert((0 <= cc) && (cc < 16), "illegal cc");
2752
2753 InstructionMark im(this);
2754
2755 relocInfo::relocType rtype = dst.reloc();
2756 relocate(rtype);
2757 const int short_size = 2;
2758 const int long_size = 6;
2759 int offs = (int)dst.target() - ((int)_code_pos);
2760 if (rtype == relocInfo::none && is8bit(offs - short_size)) {
2761 // 0111 tttn #8-bit disp
2762 emit_byte(0x70 | cc);
2763 emit_byte((offs - short_size) & 0xFF);
2764 } else {
2765 // 0000 1111 1000 tttn #32-bit disp
2766 emit_byte(0x0F);
2767 emit_byte(0x80 | cc);
2768 emit_long(offs - long_size);
2769 }
2770 }
2771
2772 // Calls
2773 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2774 Assembler::call(L, rtype);
2775 }
2776
2777 void MacroAssembler::call(Register entry) {
2778 Assembler::call(entry);
2779 }
2780
2781 void MacroAssembler::call(AddressLiteral entry) {
2782 Assembler::call_literal(entry.target(), entry.rspec());
2783 }
2784
2785
2786 void MacroAssembler::cmp8(AddressLiteral src1, int8_t imm) {
2787 Assembler::cmpb(as_Address(src1), imm);
2788 }
2789
2790 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2791 Assembler::cmpl(as_Address(src1), imm);
2792 }
2793
2794 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2795 if (src2.is_lval()) {
2796 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2797 } else {
2798 Assembler::cmpl(src1, as_Address(src2));
2799 }
2800 }
2801
2802 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2803 Assembler::cmpl(src1, imm);
2804 }
2805
2806 void MacroAssembler::cmp32(Register src1, Address src2) {
2807 Assembler::cmpl(src1, src2);
2808 }
2809
2810 void MacroAssembler::cmpoop(Address src1, jobject obj) {
2811 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
2812 }
2813
2814 void MacroAssembler::cmpoop(Register src1, jobject obj) {
2815 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
2816 }
2817
2818 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2819 if (src2.is_lval()) {
2820 // compare the effect address of src2 to src1
2821 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
2822 } else {
2823 Assembler::cmpl(src1, as_Address(src2));
2824 }
2825 }
2826
2827 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2828 assert(src2.is_lval(), "not a mem-mem compare");
2829 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2830 }
2831
2832
2833 void MacroAssembler::cmpxchgptr(Register reg, AddressLiteral adr) {
2834 cmpxchg(reg, as_Address(adr));
2835 }
2836
2837 void MacroAssembler::increment(AddressLiteral dst) {
2838 increment(as_Address(dst));
2839 }
2840
2841 void MacroAssembler::increment(ArrayAddress dst) {
2842 increment(as_Address(dst));
2843 }
2844
2845 void MacroAssembler::lea(Register dst, AddressLiteral adr) {
2846 // leal(dst, as_Address(adr));
2847 // see note in movl as to why we musr use a move
2848 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
2849 }
2850
2851 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
2852 // leal(dst, as_Address(adr));
2853 // see note in movl as to why we musr use a move
2854 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
2855 }
2856
2857 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2858 Assembler::movl(as_Address(dst), src);
2859 }
2860
2861 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2862 Assembler::movl(dst, as_Address(src));
2863 }
2864
2865 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2866 movb(as_Address(dst), src);
2867 }
2868
2869 void MacroAssembler::movoop(Address dst, jobject obj) {
2870 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
2871 }
2872
2873 void MacroAssembler::movoop(Register dst, jobject obj) {
2874 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
2875 }
2876
2877 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
2878 if (src.is_lval()) {
2879 // essentially an lea
2880 mov_literal32(dst, (int32_t) src.target(), src.rspec());
2881 } else {
2882 // mov 32bits from an absolute address
2883 movl(dst, as_Address(src));
2884 }
2885 }
2886
2887 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
2888 movl(as_Address(dst), src);
2889 }
2890
2891 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
2892 movl(dst, as_Address(src));
2893 }
2894
2895 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2896 movss(dst, as_Address(src));
2897 }
2898
2899 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2900 if (UseXmmLoadAndClearUpper) { movsd (dst, as_Address(src)); return; }
2901 else { movlpd(dst, as_Address(src)); return; }
2902 }
2903
2904 void Assembler::pushoop(jobject obj) {
2905 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
2906 }
2907
2908
2909 void MacroAssembler::pushptr(AddressLiteral src) {
2910 if (src.is_lval()) {
2911 push_literal32((int32_t)src.target(), src.rspec());
2912 } else {
2913 pushl(as_Address(src));
2914 }
2915 }
2916
2917 void MacroAssembler::test32(Register src1, AddressLiteral src2) {
2918 // src2 must be rval
2919 testl(src1, as_Address(src2));
2920 }
2921
2922 // FPU
2923
2924 void MacroAssembler::fld_x(AddressLiteral src) {
2925 Assembler::fld_x(as_Address(src));
2926 }
2927
2928 void MacroAssembler::fld_d(AddressLiteral src) {
2929 fld_d(as_Address(src));
2930 }
2931
2932 void MacroAssembler::fld_s(AddressLiteral src) {
2933 fld_s(as_Address(src));
2934 }
2935
2936 void MacroAssembler::fldcw(AddressLiteral src) {
2937 Assembler::fldcw(as_Address(src));
2938 }
2939
2940 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2941 Assembler::ldmxcsr(as_Address(src));
2942 }
2943
2944 // SSE
2945
2946 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
2947 andpd(dst, as_Address(src));
2948 }
2949
2950 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2951 comisd(dst, as_Address(src));
2952 }
2953
2954 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2955 comiss(dst, as_Address(src));
2956 }
2957
2958 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2959 movsd(dst, as_Address(src));
2960 }
2961
2962 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2963 movss(dst, as_Address(src));
2964 }
2965
2966 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
2967 xorpd(dst, as_Address(src));
2968 }
2969
2970 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
2971 xorps(dst, as_Address(src));
2972 }
2973
2974 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
2975 ucomisd(dst, as_Address(src));
2976 }
2977
2978 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
2979 ucomiss(dst, as_Address(src));
2980 }
2981
2982 void MacroAssembler::null_check(Register reg, int offset) {
2983 if (needs_explicit_null_check(offset)) {
2984 // provoke OS NULL exception if reg = NULL by
2985 // accessing M[reg] w/o changing any (non-CC) registers
2986 cmpl(rax, Address(reg, 0));
2987 // Note: should probably use testl(rax, Address(reg, 0));
2988 // may be shorter code (however, this version of
2989 // testl needs to be implemented first)
2990 } else {
2991 // nothing to do, (later) access of M[reg + offset]
2992 // will provoke OS NULL exception if reg = NULL
2993 }
2994 }
2995
2996
2997 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2998 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2999 // and "3.9 Partial Register Penalties", p. 22).
3000 int off;
3001 if (VM_Version::is_P6() || src.uses(dst)) {
3002 off = offset();
3003 movzxb(dst, src);
3004 } else {
3005 xorl(dst, dst);
3006 off = offset();
3007 movb(dst, src);
3008 }
3009 return off;
3010 }
3011
3012
3013 int MacroAssembler::load_unsigned_word(Register dst, Address src) {
3014 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3015 // and "3.9 Partial Register Penalties", p. 22).
3016 int off;
3017 if (VM_Version::is_P6() || src.uses(dst)) {
3018 off = offset();
3019 movzxw(dst, src);
3020 } else {
3021 xorl(dst, dst);
3022 off = offset();
3023 movw(dst, src);
3024 }
3025 return off;
3026 }
3027
3028
3029 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3030 int off;
3031 if (VM_Version::is_P6()) {
3032 off = offset();
3033 movsxb(dst, src);
3034 } else {
3035 off = load_unsigned_byte(dst, src);
3036 shll(dst, 24);
3037 sarl(dst, 24);
3038 }
3039 return off;
3040 }
3041
3042
3043 int MacroAssembler::load_signed_word(Register dst, Address src) {
3044 int off;
3045 if (VM_Version::is_P6()) {
3046 off = offset();
3047 movsxw(dst, src);
3048 } else {
3049 off = load_unsigned_word(dst, src);
3050 shll(dst, 16);
3051 sarl(dst, 16);
3052 }
3053 return off;
3054 }
3055
3056
3057 void MacroAssembler::extend_sign(Register hi, Register lo) {
3058 // According to Intel Doc. AP-526, "Integer Divide", p.18.
3059 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
3060 cdql();
3061 } else {
3062 movl(hi, lo);
3063 sarl(hi, 31);
3064 }
3065 }
3066
3067
3068 void MacroAssembler::increment(Register reg, int value) {
3069 if (value == min_jint) {addl(reg, value); return; }
3070 if (value < 0) { decrement(reg, -value); return; }
3071 if (value == 0) { ; return; }
3072 if (value == 1 && UseIncDec) { incl(reg); return; }
3073 /* else */ { addl(reg, value) ; return; }
3074 }
3075
3076 void MacroAssembler::increment(Address dst, int value) {
3077 if (value == min_jint) {addl(dst, value); return; }
3078 if (value < 0) { decrement(dst, -value); return; }
3079 if (value == 0) { ; return; }
3080 if (value == 1 && UseIncDec) { incl(dst); return; }
3081 /* else */ { addl(dst, value) ; return; }
3082 }
3083
3084 void MacroAssembler::decrement(Register reg, int value) {
3085 if (value == min_jint) {subl(reg, value); return; }
3086 if (value < 0) { increment(reg, -value); return; }
3087 if (value == 0) { ; return; }
3088 if (value == 1 && UseIncDec) { decl(reg); return; }
3089 /* else */ { subl(reg, value) ; return; }
3090 }
3091
3092 void MacroAssembler::decrement(Address dst, int value) {
3093 if (value == min_jint) {subl(dst, value); return; }
3094 if (value < 0) { increment(dst, -value); return; }
3095 if (value == 0) { ; return; }
3096 if (value == 1 && UseIncDec) { decl(dst); return; }
3097 /* else */ { subl(dst, value) ; return; }
3098 }
3099
3100 void MacroAssembler::align(int modulus) {
3101 if (offset() % modulus != 0) nop(modulus - (offset() % modulus));
3102 }
3103
3104
3105 void MacroAssembler::enter() {
3106 pushl(rbp);
3107 movl(rbp, rsp);
3108 }
3109
3110
3111 void MacroAssembler::leave() {
3112 movl(rsp, rbp);
3113 popl(rbp);
3114 }
3115
3116 void MacroAssembler::set_last_Java_frame(Register java_thread,
3117 Register last_java_sp,
3118 Register last_java_fp,
3119 address last_java_pc) {
3120 // determine java_thread register
3121 if (!java_thread->is_valid()) {
3122 java_thread = rdi;
3123 get_thread(java_thread);
3124 }
3125 // determine last_java_sp register
3126 if (!last_java_sp->is_valid()) {
3127 last_java_sp = rsp;
3128 }
3129
3130 // last_java_fp is optional
3131
3132 if (last_java_fp->is_valid()) {
3133 movl(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3134 }
3135
3136 // last_java_pc is optional
3137
3138 if (last_java_pc != NULL) {
3139 lea(Address(java_thread,
3140 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3141 InternalAddress(last_java_pc));
3142
3143 }
3144 movl(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3145 }
3146
3147 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3148 // determine java_thread register
3149 if (!java_thread->is_valid()) {
3150 java_thread = rdi;
3151 get_thread(java_thread);
3152 }
3153 // we must set sp to zero to clear frame
3154 movl(Address(java_thread, JavaThread::last_Java_sp_offset()), 0);
3155 if (clear_fp) {
3156 movl(Address(java_thread, JavaThread::last_Java_fp_offset()), 0);
3157 }
3158
3159 if (clear_pc)
3160 movl(Address(java_thread, JavaThread::last_Java_pc_offset()), 0);
3161
3162 }
3163
3164
3165
3166 // Implementation of call_VM versions
3167
3168 void MacroAssembler::call_VM_leaf_base(
3169 address entry_point,
3170 int number_of_arguments
3171 ) {
3172 call(RuntimeAddress(entry_point));
3173 increment(rsp, number_of_arguments * wordSize);
3174 }
3175
3176
3177 void MacroAssembler::call_VM_base(
3178 Register oop_result,
3179 Register java_thread,
3180 Register last_java_sp,
3181 address entry_point,
3182 int number_of_arguments,
3183 bool check_exceptions
3184 ) {
3185 // determine java_thread register
3186 if (!java_thread->is_valid()) {
3187 java_thread = rdi;
3188 get_thread(java_thread);
3189 }
3190 // determine last_java_sp register
3191 if (!last_java_sp->is_valid()) {
3192 last_java_sp = rsp;
3193 }
3194 // debugging support
3195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
3196 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
3197 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
3198 // push java thread (becomes first argument of C function)
3199 pushl(java_thread);
3200 // set last Java frame before call
3201 assert(last_java_sp != rbp, "this code doesn't work for last_java_sp == rbp, which currently can't portably work anyway since C2 doesn't save rbp,");
3202 // Only interpreter should have to set fp
3203 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
3204 // do the call
3205 call(RuntimeAddress(entry_point));
3206 // restore the thread (cannot use the pushed argument since arguments
3207 // may be overwritten by C code generated by an optimizing compiler);
3208 // however can use the register value directly if it is callee saved.
3209 if (java_thread == rdi || java_thread == rsi) {
3210 // rdi & rsi are callee saved -> nothing to do
3211 #ifdef ASSERT
3212 guarantee(java_thread != rax, "change this code");
3213 pushl(rax);
3214 { Label L;
3215 get_thread(rax);
3216 cmpl(java_thread, rax);
3217 jcc(Assembler::equal, L);
3218 stop("MacroAssembler::call_VM_base: rdi not callee saved?");
3219 bind(L);
3220 }
3221 popl(rax);
3222 #endif
3223 } else {
3224 get_thread(java_thread);
3225 }
3226 // reset last Java frame
3227 // Only interpreter should have to clear fp
3228 reset_last_Java_frame(java_thread, true, false);
3229 // discard thread and arguments
3230 addl(rsp, (1 + number_of_arguments)*wordSize);
3231
3232 #ifndef CC_INTERP
3233 // C++ interp handles this in the interpreter
3234 check_and_handle_popframe(java_thread);
3235 check_and_handle_earlyret(java_thread);
3236 #endif /* CC_INTERP */
3237
3238 if (check_exceptions) {
3239 // check for pending exceptions (java_thread is set upon return)
3240 cmpl(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
3241 jump_cc(Assembler::notEqual,
3242 RuntimeAddress(StubRoutines::forward_exception_entry()));
3243 }
3244
3245 // get oop result if there is one and reset the value in the thread
3246 if (oop_result->is_valid()) {
3247 movl(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
3248 movl(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
3249 verify_oop(oop_result);
3250 }
3251 }
3252
3253
3254 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
3255 }
3256
3257 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
3258 }
3259
3260 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
3261 leal(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
3262 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
3263 }
3264
3265
3266 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
3267 Label C, E;
3268 call(C, relocInfo::none);
3269 jmp(E);
3270
3271 bind(C);
3272 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
3273 ret(0);
3274
3275 bind(E);
3276 }
3277
3278
3279 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
3280 Label C, E;
3281 call(C, relocInfo::none);
3282 jmp(E);
3283
3284 bind(C);
3285 pushl(arg_1);
3286 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
3287 ret(0);
3288
3289 bind(E);
3290 }
3291
3292
3293 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
3294 Label C, E;
3295 call(C, relocInfo::none);
3296 jmp(E);
3297
3298 bind(C);
3299 pushl(arg_2);
3300 pushl(arg_1);
3301 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
3302 ret(0);
3303
3304 bind(E);
3305 }
3306
3307
3308 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
3309 Label C, E;
3310 call(C, relocInfo::none);
3311 jmp(E);
3312
3313 bind(C);
3314 pushl(arg_3);
3315 pushl(arg_2);
3316 pushl(arg_1);
3317 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
3318 ret(0);
3319
3320 bind(E);
3321 }
3322
3323
3324 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) {
3325 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions);
3326 }
3327
3328
3329 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
3330 pushl(arg_1);
3331 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
3332 }
3333
3334
3335 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
3336 pushl(arg_2);
3337 pushl(arg_1);
3338 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
3339 }
3340
3341
3342 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) {
3343 pushl(arg_3);
3344 pushl(arg_2);
3345 pushl(arg_1);
3346 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
3347 }
3348
3349
3350 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
3351 call_VM_leaf_base(entry_point, number_of_arguments);
3352 }
3353
3354
3355 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
3356 pushl(arg_1);
3357 call_VM_leaf(entry_point, 1);
3358 }
3359
3360
3361 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
3362 pushl(arg_2);
3363 pushl(arg_1);
3364 call_VM_leaf(entry_point, 2);
3365 }
3366
3367
3368 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
3369 pushl(arg_3);
3370 pushl(arg_2);
3371 pushl(arg_1);
3372 call_VM_leaf(entry_point, 3);
3373 }
3374
3375
3376 // Calls to C land
3377 //
3378 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3379 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3380 // has to be reset to 0. This is required to allow proper stack traversal.
3381
3382 void MacroAssembler::store_check(Register obj) {
3383 // Does a store check for the oop in register obj. The content of
3384 // register obj is destroyed afterwards.
3385 store_check_part_1(obj);
3386 store_check_part_2(obj);
3387 }
3388
3389
3390 void MacroAssembler::store_check(Register obj, Address dst) {
3391 store_check(obj);
3392 }
3393
3394
3395 // split the store check operation so that other instructions can be scheduled inbetween
3396 void MacroAssembler::store_check_part_1(Register obj) {
3397 BarrierSet* bs = Universe::heap()->barrier_set();
3398 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3399 shrl(obj, CardTableModRefBS::card_shift);
3400 }
3401
3402
3403 void MacroAssembler::store_check_part_2(Register obj) {
3404 BarrierSet* bs = Universe::heap()->barrier_set();
3405 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind");
3406 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
3407 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
3408 ExternalAddress cardtable((address)ct->byte_map_base);
3409 Address index(noreg, obj, Address::times_1);
3410
3411 movb(as_Address(ArrayAddress(cardtable, index)), 0);
3412 }
3413
3414
3415 void MacroAssembler::c2bool(Register x) {
3416 // implements x == 0 ? 0 : 1
3417 // note: must only look at least-significant byte of x
3418 // since C-style booleans are stored in one byte
3419 // only! (was bug)
3420 andl(x, 0xFF);
3421 setb(Assembler::notZero, x);
3422 }
3423
3424
3425 int MacroAssembler::corrected_idivl(Register reg) {
3426 // Full implementation of Java idiv and irem; checks for
3427 // special case as described in JVM spec., p.243 & p.271.
3428 // The function returns the (pc) offset of the idivl
3429 // instruction - may be needed for implicit exceptions.
3430 //
3431 // normal case special case
3432 //
3433 // input : rax,: dividend min_int
3434 // reg: divisor (may not be rax,/rdx) -1
3435 //
3436 // output: rax,: quotient (= rax, idiv reg) min_int
3437 // rdx: remainder (= rax, irem reg) 0
3438 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
3439 const int min_int = 0x80000000;
3440 Label normal_case, special_case;
3441
3442 // check for special case
3443 cmpl(rax, min_int);
3444 jcc(Assembler::notEqual, normal_case);
3445 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
3446 cmpl(reg, -1);
3447 jcc(Assembler::equal, special_case);
3448
3449 // handle normal case
3450 bind(normal_case);
3451 cdql();
3452 int idivl_offset = offset();
3453 idivl(reg);
3454
3455 // normal and special case exit
3456 bind(special_case);
3457
3458 return idivl_offset;
3459 }
3460
3461
3462 void MacroAssembler::lneg(Register hi, Register lo) {
3463 negl(lo);
3464 adcl(hi, 0);
3465 negl(hi);
3466 }
3467
3468
3469 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
3470 // Multiplication of two Java long values stored on the stack
3471 // as illustrated below. Result is in rdx:rax.
3472 //
3473 // rsp ---> [ ?? ] \ \
3474 // .... | y_rsp_offset |
3475 // [ y_lo ] / (in bytes) | x_rsp_offset
3476 // [ y_hi ] | (in bytes)
3477 // .... |
3478 // [ x_lo ] /
3479 // [ x_hi ]
3480 // ....
3481 //
3482 // Basic idea: lo(result) = lo(x_lo * y_lo)
3483 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
3484 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
3485 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
3486 Label quick;
3487 // load x_hi, y_hi and check if quick
3488 // multiplication is possible
3489 movl(rbx, x_hi);
3490 movl(rcx, y_hi);
3491 movl(rax, rbx);
3492 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
3493 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
3494 // do full multiplication
3495 // 1st step
3496 mull(y_lo); // x_hi * y_lo
3497 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
3498 // 2nd step
3499 movl(rax, x_lo);
3500 mull(rcx); // x_lo * y_hi
3501 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
3502 // 3rd step
3503 bind(quick); // note: rbx, = 0 if quick multiply!
3504 movl(rax, x_lo);
3505 mull(y_lo); // x_lo * y_lo
3506 addl(rdx, rbx); // correct hi(x_lo * y_lo)
3507 }
3508
3509
3510 void MacroAssembler::lshl(Register hi, Register lo) {
3511 // Java shift left long support (semantics as described in JVM spec., p.305)
3512 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
3513 // shift value is in rcx !
3514 assert(hi != rcx, "must not use rcx");
3515 assert(lo != rcx, "must not use rcx");
3516 const Register s = rcx; // shift count
3517 const int n = BitsPerWord;
3518 Label L;
3519 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
3520 cmpl(s, n); // if (s < n)
3521 jcc(Assembler::less, L); // else (s >= n)
3522 movl(hi, lo); // x := x << n
3523 xorl(lo, lo);
3524 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
3525 bind(L); // s (mod n) < n
3526 shldl(hi, lo); // x := x << s
3527 shll(lo);
3528 }
3529
3530
3531 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
3532 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
3533 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
3534 assert(hi != rcx, "must not use rcx");
3535 assert(lo != rcx, "must not use rcx");
3536 const Register s = rcx; // shift count
3537 const int n = BitsPerWord;
3538 Label L;
3539 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
3540 cmpl(s, n); // if (s < n)
3541 jcc(Assembler::less, L); // else (s >= n)
3542 movl(lo, hi); // x := x >> n
3543 if (sign_extension) sarl(hi, 31);
3544 else xorl(hi, hi);
3545 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
3546 bind(L); // s (mod n) < n
3547 shrdl(lo, hi); // x := x >> s
3548 if (sign_extension) sarl(hi);
3549 else shrl(hi);
3550 }
3551
3552
3553 // Note: y_lo will be destroyed
3554 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
3555 // Long compare for Java (semantics as described in JVM spec.)
3556 Label high, low, done;
3557
3558 cmpl(x_hi, y_hi);
3559 jcc(Assembler::less, low);
3560 jcc(Assembler::greater, high);
3561 // x_hi is the return register
3562 xorl(x_hi, x_hi);
3563 cmpl(x_lo, y_lo);
3564 jcc(Assembler::below, low);
3565 jcc(Assembler::equal, done);
3566
3567 bind(high);
3568 xorl(x_hi, x_hi);
3569 increment(x_hi);
3570 jmp(done);
3571
3572 bind(low);
3573 xorl(x_hi, x_hi);
3574 decrement(x_hi);
3575
3576 bind(done);
3577 }
3578
3579
3580 void MacroAssembler::save_rax(Register tmp) {
3581 if (tmp == noreg) pushl(rax);
3582 else if (tmp != rax) movl(tmp, rax);
3583 }
3584
3585
3586 void MacroAssembler::restore_rax(Register tmp) {
3587 if (tmp == noreg) popl(rax);
3588 else if (tmp != rax) movl(rax, tmp);
3589 }
3590
3591
3592 void MacroAssembler::fremr(Register tmp) {
3593 save_rax(tmp);
3594 { Label L;
3595 bind(L);
3596 fprem();
3597 fwait(); fnstsw_ax();
3598 sahf();
3599 jcc(Assembler::parity, L);
3600 }
3601 restore_rax(tmp);
3602 // Result is in ST0.
3603 // Note: fxch & fpop to get rid of ST1
3604 // (otherwise FPU stack could overflow eventually)
3605 fxch(1);
3606 fpop();
3607 }
3608
3609
3610 static const double pi_4 = 0.7853981633974483;
3611
3612 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
3613 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
3614 // was attempted in this code; unfortunately it appears that the
3615 // switch to 80-bit precision and back causes this to be
3616 // unprofitable compared with simply performing a runtime call if
3617 // the argument is out of the (-pi/4, pi/4) range.
3618
3619 Register tmp = noreg;
3620 if (!VM_Version::supports_cmov()) {
3621 // fcmp needs a temporary so preserve rbx,
3622 tmp = rbx;
3623 pushl(tmp);
3624 }
3625
3626 Label slow_case, done;
3627
3628 // x ?<= pi/4
3629 fld_d(ExternalAddress((address)&pi_4));
3630 fld_s(1); // Stack: X PI/4 X
3631 fabs(); // Stack: |X| PI/4 X
3632 fcmp(tmp);
3633 jcc(Assembler::above, slow_case);
3634
3635 // fastest case: -pi/4 <= x <= pi/4
3636 switch(trig) {
3637 case 's':
3638 fsin();
3639 break;
3640 case 'c':
3641 fcos();
3642 break;
3643 case 't':
3644 ftan();
3645 break;
3646 default:
3647 assert(false, "bad intrinsic");
3648 break;
3649 }
3650 jmp(done);
3651
3652 // slow case: runtime call
3653 bind(slow_case);
3654 // Preserve registers across runtime call
3655 pushad();
3656 int incoming_argument_and_return_value_offset = -1;
3657 if (num_fpu_regs_in_use > 1) {
3658 // Must preserve all other FPU regs (could alternatively convert
3659 // SharedRuntime::dsin and dcos into assembly routines known not to trash
3660 // FPU state, but can not trust C compiler)
3661 NEEDS_CLEANUP;
3662 // NOTE that in this case we also push the incoming argument to
3663 // the stack and restore it later; we also use this stack slot to
3664 // hold the return value from dsin or dcos.
3665 for (int i = 0; i < num_fpu_regs_in_use; i++) {
3666 subl(rsp, wordSize*2);
3667 fstp_d(Address(rsp, 0));
3668 }
3669 incoming_argument_and_return_value_offset = 2*wordSize*(num_fpu_regs_in_use-1);
3670 fld_d(Address(rsp, incoming_argument_and_return_value_offset));
3671 }
3672 subl(rsp, wordSize*2);
3673 fstp_d(Address(rsp, 0));
3674 // NOTE: we must not use call_VM_leaf here because that requires a
3675 // complete interpreter frame in debug mode -- same bug as 4387334
3676 NEEDS_CLEANUP;
3677 // Need to add stack banging before this runtime call if it needs to
3678 // be taken; however, there is no generic stack banging routine at
3679 // the MacroAssembler level
3680 switch(trig) {
3681 case 's':
3682 {
3683 call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dsin)));
3684 }
3685 break;
3686 case 'c':
3687 {
3688 call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dcos)));
3689 }
3690 break;
3691 case 't':
3692 {
3693 call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtan)));
3694 }
3695 break;
3696 default:
3697 assert(false, "bad intrinsic");
3698 break;
3699 }
3700 addl(rsp, wordSize * 2);
3701 if (num_fpu_regs_in_use > 1) {
3702 // Must save return value to stack and then restore entire FPU stack
3703 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
3704 for (int i = 0; i < num_fpu_regs_in_use; i++) {
3705 fld_d(Address(rsp, 0));
3706 addl(rsp, wordSize*2);
3707 }
3708 }
3709 popad();
3710
3711 // Come here with result in F-TOS
3712 bind(done);
3713
3714 if (tmp != noreg) {
3715 popl(tmp);
3716 }
3717 }
3718
3719 void MacroAssembler::jC2(Register tmp, Label& L) {
3720 // set parity bit if FPU flag C2 is set (via rax)
3721 save_rax(tmp);
3722 fwait(); fnstsw_ax();
3723 sahf();
3724 restore_rax(tmp);
3725 // branch
3726 jcc(Assembler::parity, L);
3727 }
3728
3729
3730 void MacroAssembler::jnC2(Register tmp, Label& L) {
3731 // set parity bit if FPU flag C2 is set (via rax)
3732 save_rax(tmp);
3733 fwait(); fnstsw_ax();
3734 sahf();
3735 restore_rax(tmp);
3736 // branch
3737 jcc(Assembler::noParity, L);
3738 }
3739
3740
3741 void MacroAssembler::fcmp(Register tmp) {
3742 fcmp(tmp, 1, true, true);
3743 }
3744
3745
3746 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
3747 assert(!pop_right || pop_left, "usage error");
3748 if (VM_Version::supports_cmov()) {
3749 assert(tmp == noreg, "unneeded temp");
3750 if (pop_left) {
3751 fucomip(index);
3752 } else {
3753 fucomi(index);
3754 }
3755 if (pop_right) {
3756 fpop();
3757 }
3758 } else {
3759 assert(tmp != noreg, "need temp");
3760 if (pop_left) {
3761 if (pop_right) {
3762 fcompp();
3763 } else {
3764 fcomp(index);
3765 }
3766 } else {
3767 fcom(index);
3768 }
3769 // convert FPU condition into eflags condition via rax,
3770 save_rax(tmp);
3771 fwait(); fnstsw_ax();
3772 sahf();
3773 restore_rax(tmp);
3774 }
3775 // condition codes set as follows:
3776 //
3777 // CF (corresponds to C0) if x < y
3778 // PF (corresponds to C2) if unordered
3779 // ZF (corresponds to C3) if x = y
3780 }
3781
3782
3783 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3784 fcmp2int(dst, unordered_is_less, 1, true, true);
3785 }
3786
3787
3788 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3789 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3790 Label L;
3791 if (unordered_is_less) {
3792 movl(dst, -1);
3793 jcc(Assembler::parity, L);
3794 jcc(Assembler::below , L);
3795 movl(dst, 0);
3796 jcc(Assembler::equal , L);
3797 increment(dst);
3798 } else { // unordered is greater
3799 movl(dst, 1);
3800 jcc(Assembler::parity, L);
3801 jcc(Assembler::above , L);
3802 movl(dst, 0);
3803 jcc(Assembler::equal , L);
3804 decrement(dst);
3805 }
3806 bind(L);
3807 }
3808
3809 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
3810 ucomiss(opr1, opr2);
3811
3812 Label L;
3813 if (unordered_is_less) {
3814 movl(dst, -1);
3815 jcc(Assembler::parity, L);
3816 jcc(Assembler::below , L);
3817 movl(dst, 0);
3818 jcc(Assembler::equal , L);
3819 increment(dst);
3820 } else { // unordered is greater
3821 movl(dst, 1);
3822 jcc(Assembler::parity, L);
3823 jcc(Assembler::above , L);
3824 movl(dst, 0);
3825 jcc(Assembler::equal , L);
3826 decrement(dst);
3827 }
3828 bind(L);
3829 }
3830
3831 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
3832 ucomisd(opr1, opr2);
3833
3834 Label L;
3835 if (unordered_is_less) {
3836 movl(dst, -1);
3837 jcc(Assembler::parity, L);
3838 jcc(Assembler::below , L);
3839 movl(dst, 0);
3840 jcc(Assembler::equal , L);
3841 increment(dst);
3842 } else { // unordered is greater
3843 movl(dst, 1);
3844 jcc(Assembler::parity, L);
3845 jcc(Assembler::above , L);
3846 movl(dst, 0);
3847 jcc(Assembler::equal , L);
3848 decrement(dst);
3849 }
3850 bind(L);
3851 }
3852
3853
3854
3855 void MacroAssembler::fpop() {
3856 ffree();
3857 fincstp();
3858 }
3859
3860
3861 void MacroAssembler::sign_extend_short(Register reg) {
3862 if (VM_Version::is_P6()) {
3863 movsxw(reg, reg);
3864 } else {
3865 shll(reg, 16);
3866 sarl(reg, 16);
3867 }
3868 }
3869
3870
3871 void MacroAssembler::sign_extend_byte(Register reg) {
3872 if (VM_Version::is_P6() && reg->has_byte_register()) {
3873 movsxb(reg, reg);
3874 } else {
3875 shll(reg, 24);
3876 sarl(reg, 24);
3877 }
3878 }
3879
3880
3881 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
3882 assert (shift_value > 0, "illegal shift value");
3883 Label _is_positive;
3884 testl (reg, reg);
3885 jcc (Assembler::positive, _is_positive);
3886 int offset = (1 << shift_value) - 1 ;
3887
3888 increment(reg, offset);
3889
3890 bind (_is_positive);
3891 sarl(reg, shift_value);
3892 }
3893
3894
3895 void MacroAssembler::round_to(Register reg, int modulus) {
3896 addl(reg, modulus - 1);
3897 andl(reg, -modulus);
3898 }
3899
3900 // C++ bool manipulation
3901
3902 void MacroAssembler::movbool(Register dst, Address src) {
3903 if(sizeof(bool) == 1)
3904 movb(dst, src);
3905 else if(sizeof(bool) == 2)
3906 movw(dst, src);
3907 else if(sizeof(bool) == 4)
3908 movl(dst, src);
3909 else
3910 // unsupported
3911 ShouldNotReachHere();
3912 }
3913
3914 void MacroAssembler::movbool(Address dst, bool boolconst) {
3915 if(sizeof(bool) == 1)
3916 movb(dst, (int) boolconst);
3917 else if(sizeof(bool) == 2)
3918 movw(dst, (int) boolconst);
3919 else if(sizeof(bool) == 4)
3920 movl(dst, (int) boolconst);
3921 else
3922 // unsupported
3923 ShouldNotReachHere();
3924 }
3925
3926 void MacroAssembler::movbool(Address dst, Register src) {
3927 if(sizeof(bool) == 1)
3928 movb(dst, src);
3929 else if(sizeof(bool) == 2)
3930 movw(dst, src);
3931 else if(sizeof(bool) == 4)
3932 movl(dst, src);
3933 else
3934 // unsupported
3935 ShouldNotReachHere();
3936 }
3937
3938 void MacroAssembler::testbool(Register dst) {
3939 if(sizeof(bool) == 1)
3940 testb(dst, (int) 0xff);
3941 else if(sizeof(bool) == 2) {
3942 // testw implementation needed for two byte bools
3943 ShouldNotReachHere();
3944 } else if(sizeof(bool) == 4)
3945 testl(dst, dst);
3946 else
3947 // unsupported
3948 ShouldNotReachHere();
3949 }
3950
3951 void MacroAssembler::verify_oop(Register reg, const char* s) {
3952 if (!VerifyOops) return;
3953 // Pass register number to verify_oop_subroutine
3954 char* b = new char[strlen(s) + 50];
3955 sprintf(b, "verify_oop: %s: %s", reg->name(), s);
3956 pushl(rax); // save rax,
3957 pushl(reg); // pass register argument
3958 ExternalAddress buffer((address) b);
3959 pushptr(buffer.addr());
3960 // call indirectly to solve generation ordering problem
3961 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
3962 call(rax);
3963 }
3964
3965
3966 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
3967 if (!VerifyOops) return;
3968 // QQQ fix this
3969 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
3970 // Pass register number to verify_oop_subroutine
3971 char* b = new char[strlen(s) + 50];
3972 sprintf(b, "verify_oop_addr: %s", s);
3973 pushl(rax); // save rax,
3974 // addr may contain rsp so we will have to adjust it based on the push
3975 // we just did
3976 if (addr.uses(rsp)) {
3977 leal(rax, addr);
3978 pushl(Address(rax, BytesPerWord));
3979 } else {
3980 pushl(addr);
3981 }
3982 ExternalAddress buffer((address) b);
3983 // pass msg argument
3984 pushptr(buffer.addr());
3985 // call indirectly to solve generation ordering problem
3986 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
3987 call(rax);
3988 // Caller pops the arguments and restores rax, from the stack
3989 }
3990
3991
3992 void MacroAssembler::stop(const char* msg) {
3993 ExternalAddress message((address)msg);
3994 // push address of message
3995 pushptr(message.addr());
3996 { Label L; call(L, relocInfo::none); bind(L); } // push eip
3997 pushad(); // push registers
3998 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug)));
3999 hlt();
4000 }
4001
4002
4003 void MacroAssembler::warn(const char* msg) {
4004 push_CPU_state();
4005
4006 ExternalAddress message((address) msg);
4007 // push address of message
4008 pushptr(message.addr());
4009
4010 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
4011 addl(rsp, wordSize); // discard argument
4012 pop_CPU_state();
4013 }
4014
4015
4016 void MacroAssembler::debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
4017 // In order to get locks to work, we need to fake a in_VM state
4018 JavaThread* thread = JavaThread::current();
4019 JavaThreadState saved_state = thread->thread_state();
4020 thread->set_thread_state(_thread_in_vm);
4021 if (ShowMessageBoxOnError) {
4022 JavaThread* thread = JavaThread::current();
4023 JavaThreadState saved_state = thread->thread_state();
4024 thread->set_thread_state(_thread_in_vm);
4025 ttyLocker ttyl;
4026 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
4027 BytecodeCounter::print();
4028 }
4029 // To see where a verify_oop failed, get $ebx+40/X for this frame.
4030 // This is the value of eip which points to where verify_oop will return.
4031 if (os::message_box(msg, "Execution stopped, print registers?")) {
4032 tty->print_cr("eip = 0x%08x", eip);
4033 tty->print_cr("rax, = 0x%08x", rax);
4034 tty->print_cr("rbx, = 0x%08x", rbx);
4035 tty->print_cr("rcx = 0x%08x", rcx);
4036 tty->print_cr("rdx = 0x%08x", rdx);
4037 tty->print_cr("rdi = 0x%08x", rdi);
4038 tty->print_cr("rsi = 0x%08x", rsi);
4039 tty->print_cr("rbp, = 0x%08x", rbp);
4040 tty->print_cr("rsp = 0x%08x", rsp);
4041 BREAKPOINT;
4042 }
4043 } else {
4044 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
4045 assert(false, "DEBUG MESSAGE");
4046 }
4047 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
4048 }
4049
4050
4051
4052 void MacroAssembler::os_breakpoint() {
4053 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
4054 // (e.g., MSVC can't call ps() otherwise)
4055 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
4056 }
4057
4058
4059 void MacroAssembler::push_fTOS() {
4060 subl(rsp, 2 * wordSize);
4061 fstp_d(Address(rsp, 0));
4062 }
4063
4064
4065 void MacroAssembler::pop_fTOS() {
4066 fld_d(Address(rsp, 0));
4067 addl(rsp, 2 * wordSize);
4068 }
4069
4070
4071 void MacroAssembler::empty_FPU_stack() {
4072 if (VM_Version::supports_mmx()) {
4073 emms();
4074 } else {
4075 for (int i = 8; i-- > 0; ) ffree(i);
4076 }
4077 }
4078
4079
4080 class ControlWord {
4081 public:
4082 int32_t _value;
4083
4084 int rounding_control() const { return (_value >> 10) & 3 ; }
4085 int precision_control() const { return (_value >> 8) & 3 ; }
4086 bool precision() const { return ((_value >> 5) & 1) != 0; }
4087 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4088 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4089 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4090 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4091 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4092
4093 void print() const {
4094 // rounding control
4095 const char* rc;
4096 switch (rounding_control()) {
4097 case 0: rc = "round near"; break;
4098 case 1: rc = "round down"; break;
4099 case 2: rc = "round up "; break;
4100 case 3: rc = "chop "; break;
4101 };
4102 // precision control
4103 const char* pc;
4104 switch (precision_control()) {
4105 case 0: pc = "24 bits "; break;
4106 case 1: pc = "reserved"; break;
4107 case 2: pc = "53 bits "; break;
4108 case 3: pc = "64 bits "; break;
4109 };
4110 // flags
4111 char f[9];
4112 f[0] = ' ';
4113 f[1] = ' ';
4114 f[2] = (precision ()) ? 'P' : 'p';
4115 f[3] = (underflow ()) ? 'U' : 'u';
4116 f[4] = (overflow ()) ? 'O' : 'o';
4117 f[5] = (zero_divide ()) ? 'Z' : 'z';
4118 f[6] = (denormalized()) ? 'D' : 'd';
4119 f[7] = (invalid ()) ? 'I' : 'i';
4120 f[8] = '\x0';
4121 // output
4122 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4123 }
4124
4125 };
4126
4127
4128 class StatusWord {
4129 public:
4130 int32_t _value;
4131
4132 bool busy() const { return ((_value >> 15) & 1) != 0; }
4133 bool C3() const { return ((_value >> 14) & 1) != 0; }
4134 bool C2() const { return ((_value >> 10) & 1) != 0; }
4135 bool C1() const { return ((_value >> 9) & 1) != 0; }
4136 bool C0() const { return ((_value >> 8) & 1) != 0; }
4137 int top() const { return (_value >> 11) & 7 ; }
4138 bool error_status() const { return ((_value >> 7) & 1) != 0; }
4139 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
4140 bool precision() const { return ((_value >> 5) & 1) != 0; }
4141 bool underflow() const { return ((_value >> 4) & 1) != 0; }
4142 bool overflow() const { return ((_value >> 3) & 1) != 0; }
4143 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
4144 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
4145 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4146
4147 void print() const {
4148 // condition codes
4149 char c[5];
4150 c[0] = (C3()) ? '3' : '-';
4151 c[1] = (C2()) ? '2' : '-';
4152 c[2] = (C1()) ? '1' : '-';
4153 c[3] = (C0()) ? '0' : '-';
4154 c[4] = '\x0';
4155 // flags
4156 char f[9];
4157 f[0] = (error_status()) ? 'E' : '-';
4158 f[1] = (stack_fault ()) ? 'S' : '-';
4159 f[2] = (precision ()) ? 'P' : '-';
4160 f[3] = (underflow ()) ? 'U' : '-';
4161 f[4] = (overflow ()) ? 'O' : '-';
4162 f[5] = (zero_divide ()) ? 'Z' : '-';
4163 f[6] = (denormalized()) ? 'D' : '-';
4164 f[7] = (invalid ()) ? 'I' : '-';
4165 f[8] = '\x0';
4166 // output
4167 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4168 }
4169
4170 };
4171
4172
4173 class TagWord {
4174 public:
4175 int32_t _value;
4176
4177 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4178
4179 void print() const {
4180 printf("%04x", _value & 0xFFFF);
4181 }
4182
4183 };
4184
4185
4186 class FPU_Register {
4187 public:
4188 int32_t _m0;
4189 int32_t _m1;
4190 int16_t _ex;
4191
4192 bool is_indefinite() const {
4193 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4194 }
4195
4196 void print() const {
4197 char sign = (_ex < 0) ? '-' : '+';
4198 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4199 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4200 };
4201
4202 };
4203
4204
4205 class FPU_State {
4206 public:
4207 enum {
4208 register_size = 10,
4209 number_of_registers = 8,
4210 register_mask = 7
4211 };
4212
4213 ControlWord _control_word;
4214 StatusWord _status_word;
4215 TagWord _tag_word;
4216 int32_t _error_offset;
4217 int32_t _error_selector;
4218 int32_t _data_offset;
4219 int32_t _data_selector;
4220 int8_t _register[register_size * number_of_registers];
4221
4222 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4223 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4224
4225 const char* tag_as_string(int tag) const {
4226 switch (tag) {
4227 case 0: return "valid";
4228 case 1: return "zero";
4229 case 2: return "special";
4230 case 3: return "empty";
4231 }
4232 ShouldNotReachHere()
4233 return NULL;
4234 }
4235
4236 void print() const {
4237 // print computation registers
4238 { int t = _status_word.top();
4239 for (int i = 0; i < number_of_registers; i++) {
4240 int j = (i - t) & register_mask;
4241 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4242 st(j)->print();
4243 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4244 }
4245 }
4246 printf("\n");
4247 // print control registers
4248 printf("ctrl = "); _control_word.print(); printf("\n");
4249 printf("stat = "); _status_word .print(); printf("\n");
4250 printf("tags = "); _tag_word .print(); printf("\n");
4251 }
4252
4253 };
4254
4255
4256 class Flag_Register {
4257 public:
4258 int32_t _value;
4259
4260 bool overflow() const { return ((_value >> 11) & 1) != 0; }
4261 bool direction() const { return ((_value >> 10) & 1) != 0; }
4262 bool sign() const { return ((_value >> 7) & 1) != 0; }
4263 bool zero() const { return ((_value >> 6) & 1) != 0; }
4264 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
4265 bool parity() const { return ((_value >> 2) & 1) != 0; }
4266 bool carry() const { return ((_value >> 0) & 1) != 0; }
4267
4268 void print() const {
4269 // flags
4270 char f[8];
4271 f[0] = (overflow ()) ? 'O' : '-';
4272 f[1] = (direction ()) ? 'D' : '-';
4273 f[2] = (sign ()) ? 'S' : '-';
4274 f[3] = (zero ()) ? 'Z' : '-';
4275 f[4] = (auxiliary_carry()) ? 'A' : '-';
4276 f[5] = (parity ()) ? 'P' : '-';
4277 f[6] = (carry ()) ? 'C' : '-';
4278 f[7] = '\x0';
4279 // output
4280 printf("%08x flags = %s", _value, f);
4281 }
4282
4283 };
4284
4285
4286 class IU_Register {
4287 public:
4288 int32_t _value;
4289
4290 void print() const {
4291 printf("%08x %11d", _value, _value);
4292 }
4293
4294 };
4295
4296
4297 class IU_State {
4298 public:
4299 Flag_Register _eflags;
4300 IU_Register _rdi;
4301 IU_Register _rsi;
4302 IU_Register _rbp;
4303 IU_Register _rsp;
4304 IU_Register _rbx;
4305 IU_Register _rdx;
4306 IU_Register _rcx;
4307 IU_Register _rax;
4308
4309 void print() const {
4310 // computation registers
4311 printf("rax, = "); _rax.print(); printf("\n");
4312 printf("rbx, = "); _rbx.print(); printf("\n");
4313 printf("rcx = "); _rcx.print(); printf("\n");
4314 printf("rdx = "); _rdx.print(); printf("\n");
4315 printf("rdi = "); _rdi.print(); printf("\n");
4316 printf("rsi = "); _rsi.print(); printf("\n");
4317 printf("rbp, = "); _rbp.print(); printf("\n");
4318 printf("rsp = "); _rsp.print(); printf("\n");
4319 printf("\n");
4320 // control registers
4321 printf("flgs = "); _eflags.print(); printf("\n");
4322 }
4323 };
4324
4325
4326 class CPU_State {
4327 public:
4328 FPU_State _fpu_state;
4329 IU_State _iu_state;
4330
4331 void print() const {
4332 printf("--------------------------------------------------\n");
4333 _iu_state .print();
4334 printf("\n");
4335 _fpu_state.print();
4336 printf("--------------------------------------------------\n");
4337 }
4338
4339 };
4340
4341
4342 static void _print_CPU_state(CPU_State* state) {
4343 state->print();
4344 };
4345
4346
4347 void MacroAssembler::print_CPU_state() {
4348 push_CPU_state();
4349 pushl(rsp); // pass CPU state
4350 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4351 addl(rsp, wordSize); // discard argument
4352 pop_CPU_state();
4353 }
4354
4355
4356 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4357 static int counter = 0;
4358 FPU_State* fs = &state->_fpu_state;
4359 counter++;
4360 // For leaf calls, only verify that the top few elements remain empty.
4361 // We only need 1 empty at the top for C2 code.
4362 if( stack_depth < 0 ) {
4363 if( fs->tag_for_st(7) != 3 ) {
4364 printf("FPR7 not empty\n");
4365 state->print();
4366 assert(false, "error");
4367 return false;
4368 }
4369 return true; // All other stack states do not matter
4370 }
4371
4372 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
4373 "bad FPU control word");
4374
4375 // compute stack depth
4376 int i = 0;
4377 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
4378 int d = i;
4379 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4380 // verify findings
4381 if (i != FPU_State::number_of_registers) {
4382 // stack not contiguous
4383 printf("%s: stack not contiguous at ST%d\n", s, i);
4384 state->print();
4385 assert(false, "error");
4386 return false;
4387 }
4388 // check if computed stack depth corresponds to expected stack depth
4389 if (stack_depth < 0) {
4390 // expected stack depth is -stack_depth or less
4391 if (d > -stack_depth) {
4392 // too many elements on the stack
4393 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4394 state->print();
4395 assert(false, "error");
4396 return false;
4397 }
4398 } else {
4399 // expected stack depth is stack_depth
4400 if (d != stack_depth) {
4401 // wrong stack depth
4402 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4403 state->print();
4404 assert(false, "error");
4405 return false;
4406 }
4407 }
4408 // everything is cool
4409 return true;
4410 }
4411
4412
4413 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4414 if (!VerifyFPU) return;
4415 push_CPU_state();
4416 pushl(rsp); // pass CPU state
4417 ExternalAddress msg((address) s);
4418 // pass message string s
4419 pushptr(msg.addr());
4420 pushl(stack_depth); // pass stack depth
4421 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4422 addl(rsp, 3 * wordSize); // discard arguments
4423 // check for error
4424 { Label L;
4425 testl(rax, rax);
4426 jcc(Assembler::notZero, L);
4427 int3(); // break if error condition
4428 bind(L);
4429 }
4430 pop_CPU_state();
4431 }
4432
4433
4434 void MacroAssembler::push_IU_state() {
4435 pushad();
4436 pushfd();
4437 }
4438
4439
4440 void MacroAssembler::pop_IU_state() {
4441 popfd();
4442 popad();
4443 }
4444
4445
4446 void MacroAssembler::push_FPU_state() {
4447 subl(rsp, FPUStateSizeInWords * wordSize);
4448 fnsave(Address(rsp, 0));
4449 fwait();
4450 }
4451
4452
4453 void MacroAssembler::pop_FPU_state() {
4454 frstor(Address(rsp, 0));
4455 addl(rsp, FPUStateSizeInWords * wordSize);
4456 }
4457
4458
4459 void MacroAssembler::push_CPU_state() {
4460 push_IU_state();
4461 push_FPU_state();
4462 }
4463
4464
4465 void MacroAssembler::pop_CPU_state() {
4466 pop_FPU_state();
4467 pop_IU_state();
4468 }
4469
4470
4471 void MacroAssembler::push_callee_saved_registers() {
4472 pushl(rsi);
4473 pushl(rdi);
4474 pushl(rdx);
4475 pushl(rcx);
4476 }
4477
4478
4479 void MacroAssembler::pop_callee_saved_registers() {
4480 popl(rcx);
4481 popl(rdx);
4482 popl(rdi);
4483 popl(rsi);
4484 }
4485
4486
4487 void MacroAssembler::set_word_if_not_zero(Register dst) {
4488 xorl(dst, dst);
4489 set_byte_if_not_zero(dst);
4490 }
4491
4492 // Write serialization page so VM thread can do a pseudo remote membar.
4493 // We use the current thread pointer to calculate a thread specific
4494 // offset to write to within the page. This minimizes bus traffic
4495 // due to cache line collision.
4496 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
4497 movl(tmp, thread);
4498 shrl(tmp, os::get_serialize_page_shift_count());
4499 andl(tmp, (os::vm_page_size() - sizeof(int)));
4500
4501 Address index(noreg, tmp, Address::times_1);
4502 ExternalAddress page(os::get_memory_serialize_page());
4503
4504 movptr(ArrayAddress(page, index), tmp);
4505 }
4506
4507
4508 void MacroAssembler::verify_tlab() {
4509 #ifdef ASSERT
4510 if (UseTLAB && VerifyOops) {
4511 Label next, ok;
4512 Register t1 = rsi;
4513 Register thread_reg = rbx;
4514
4515 pushl(t1);
4516 pushl(thread_reg);
4517 get_thread(thread_reg);
4518
4519 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4520 cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4521 jcc(Assembler::aboveEqual, next);
4522 stop("assert(top >= start)");
4523 should_not_reach_here();
4524
4525 bind(next);
4526 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4527 cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4528 jcc(Assembler::aboveEqual, ok);
4529 stop("assert(top <= end)");
4530 should_not_reach_here();
4531
4532 bind(ok);
4533 popl(thread_reg);
4534 popl(t1);
4535 }
4536 #endif
4537 }
4538
4539
4540 // Defines obj, preserves var_size_in_bytes
4541 void MacroAssembler::eden_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
4542 Register t1, Label& slow_case) {
4543 assert(obj == rax, "obj must be in rax, for cmpxchg");
4544 assert_different_registers(obj, var_size_in_bytes, t1);
4545 Register end = t1;
4546 Label retry;
4547 bind(retry);
4548 ExternalAddress heap_top((address) Universe::heap()->top_addr());
4549 movptr(obj, heap_top);
4550 if (var_size_in_bytes == noreg) {
4551 leal(end, Address(obj, con_size_in_bytes));
4552 } else {
4553 leal(end, Address(obj, var_size_in_bytes, Address::times_1));
4554 }
4555 // if end < obj then we wrapped around => object too long => slow case
4556 cmpl(end, obj);
4557 jcc(Assembler::below, slow_case);
4558 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
4559 jcc(Assembler::above, slow_case);
4560 // Compare obj with the top addr, and if still equal, store the new top addr in
4561 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
4562 // it otherwise. Use lock prefix for atomicity on MPs.
4563 if (os::is_MP()) {
4564 lock();
4565 }
4566 cmpxchgptr(end, heap_top);
4567 jcc(Assembler::notEqual, retry);
4568 }
4569
4570
4571 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4572 void MacroAssembler::tlab_allocate(Register obj, Register var_size_in_bytes, int con_size_in_bytes,
4573 Register t1, Register t2, Label& slow_case) {
4574 assert_different_registers(obj, t1, t2);
4575 assert_different_registers(obj, var_size_in_bytes, t1);
4576 Register end = t2;
4577 Register thread = t1;
4578
4579 verify_tlab();
4580
4581 get_thread(thread);
4582
4583 movl(obj, Address(thread, JavaThread::tlab_top_offset()));
4584 if (var_size_in_bytes == noreg) {
4585 leal(end, Address(obj, con_size_in_bytes));
4586 } else {
4587 leal(end, Address(obj, var_size_in_bytes, Address::times_1));
4588 }
4589 cmpl(end, Address(thread, JavaThread::tlab_end_offset()));
4590 jcc(Assembler::above, slow_case);
4591
4592 // update the tlab top pointer
4593 movl(Address(thread, JavaThread::tlab_top_offset()), end);
4594
4595 // recover var_size_in_bytes if necessary
4596 if (var_size_in_bytes == end) {
4597 subl(var_size_in_bytes, obj);
4598 }
4599 verify_tlab();
4600 }
4601
4602 // Preserves rbx, and rdx.
4603 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) {
4604 Register top = rax;
4605 Register t1 = rcx;
4606 Register t2 = rsi;
4607 Register thread_reg = rdi;
4608 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4609 Label do_refill, discard_tlab;
4610
4611 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) {
4612 // No allocation in the shared eden.
4613 jmp(slow_case);
4614 }
4615
4616 get_thread(thread_reg);
4617
4618 movl(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4619 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4620
4621 // calculate amount of free space
4622 subl(t1, top);
4623 shrl(t1, LogHeapWordSize);
4624
4625 // Retain tlab and allocate object in shared space if
4626 // the amount free in the tlab is too large to discard.
4627 cmpl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4628 jcc(Assembler::lessEqual, discard_tlab);
4629
4630 // Retain
4631 movl(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment());
4632 addl(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4633 if (TLABStats) {
4634 // increment number of slow_allocations
4635 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4636 }
4637 jmp(try_eden);
4638
4639 bind(discard_tlab);
4640 if (TLABStats) {
4641 // increment number of refills
4642 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4643 // accumulate wastage -- t1 is amount free in tlab
4644 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4645 }
4646
4647 // if tlab is currently allocated (top or end != null) then
4648 // fill [top, end + alignment_reserve) with array object
4649 testl (top, top);
4650 jcc(Assembler::zero, do_refill);
4651
4652 // set up the mark word
4653 movl(Address(top, oopDesc::mark_offset_in_bytes()), (int)markOopDesc::prototype()->copy_set_hash(0x2));
4654 // set the length to the remaining space
4655 subl(t1, typeArrayOopDesc::header_size(T_INT));
4656 addl(t1, ThreadLocalAllocBuffer::alignment_reserve());
4657 shll(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4658 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4659 // set klass to intArrayKlass
4660 // dubious reloc why not an oop reloc?
4661 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr()));
4662 movl(Address(top, oopDesc::klass_offset_in_bytes()), t1);
4663
4664 // refill the tlab with an eden allocation
4665 bind(do_refill);
4666 movl(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4667 shll(t1, LogHeapWordSize);
4668 // add object_size ??
4669 eden_allocate(top, t1, 0, t2, slow_case);
4670
4671 // Check that t1 was preserved in eden_allocate.
4672 #ifdef ASSERT
4673 if (UseTLAB) {
4674 Label ok;
4675 Register tsize = rsi;
4676 assert_different_registers(tsize, thread_reg, t1);
4677 pushl(tsize);
4678 movl(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4679 shll(tsize, LogHeapWordSize);
4680 cmpl(t1, tsize);
4681 jcc(Assembler::equal, ok);
4682 stop("assert(t1 != tlab size)");
4683 should_not_reach_here();
4684
4685 bind(ok);
4686 popl(tsize);
4687 }
4688 #endif
4689 movl(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4690 movl(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4691 addl(top, t1);
4692 subl(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4693 movl(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4694 verify_tlab();
4695 jmp(retry);
4696 }
4697
4698
4699 int MacroAssembler::biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
4700 bool swap_reg_contains_mark,
4701 Label& done, Label* slow_case,
4702 BiasedLockingCounters* counters) {
4703 assert(UseBiasedLocking, "why call this otherwise?");
4704 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg");
4705 assert_different_registers(lock_reg, obj_reg, swap_reg);
4706
4707 if (PrintBiasedLockingStatistics && counters == NULL)
4708 counters = BiasedLocking::counters();
4709
4710 bool need_tmp_reg = false;
4711 if (tmp_reg == noreg) {
4712 need_tmp_reg = true;
4713 tmp_reg = lock_reg;
4714 } else {
4715 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
4716 }
4717 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
4718 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
4719 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes());
4720 Address saved_mark_addr(lock_reg, 0);
4721
4722 // Biased locking
4723 // See whether the lock is currently biased toward our thread and
4724 // whether the epoch is still valid
4725 // Note that the runtime guarantees sufficient alignment of JavaThread
4726 // pointers to allow age to be placed into low bits
4727 // First check to see whether biasing is even enabled for this object
4728 Label cas_label;
4729 int null_check_offset = -1;
4730 if (!swap_reg_contains_mark) {
4731 null_check_offset = offset();
4732 movl(swap_reg, mark_addr);
4733 }
4734 if (need_tmp_reg) {
4735 pushl(tmp_reg);
4736 }
4737 movl(tmp_reg, swap_reg);
4738 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place);
4739 cmpl(tmp_reg, markOopDesc::biased_lock_pattern);
4740 if (need_tmp_reg) {
4741 popl(tmp_reg);
4742 }
4743 jcc(Assembler::notEqual, cas_label);
4744 // The bias pattern is present in the object's header. Need to check
4745 // whether the bias owner and the epoch are both still current.
4746 // Note that because there is no current thread register on x86 we
4747 // need to store off the mark word we read out of the object to
4748 // avoid reloading it and needing to recheck invariants below. This
4749 // store is unfortunate but it makes the overall code shorter and
4750 // simpler.
4751 movl(saved_mark_addr, swap_reg);
4752 if (need_tmp_reg) {
4753 pushl(tmp_reg);
4754 }
4755 get_thread(tmp_reg);
4756 xorl(swap_reg, tmp_reg);
4757 if (swap_reg_contains_mark) {
4758 null_check_offset = offset();
4759 }
4760 movl(tmp_reg, klass_addr);
4761 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4762 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place));
4763 if (need_tmp_reg) {
4764 popl(tmp_reg);
4765 }
4766 if (counters != NULL) {
4767 cond_inc32(Assembler::zero,
4768 ExternalAddress((address)counters->biased_lock_entry_count_addr()));
4769 }
4770 jcc(Assembler::equal, done);
4771
4772 Label try_revoke_bias;
4773 Label try_rebias;
4774
4775 // At this point we know that the header has the bias pattern and
4776 // that we are not the bias owner in the current epoch. We need to
4777 // figure out more details about the state of the header in order to
4778 // know what operations can be legally performed on the object's
4779 // header.
4780
4781 // If the low three bits in the xor result aren't clear, that means
4782 // the prototype header is no longer biased and we have to revoke
4783 // the bias on this object.
4784 testl(swap_reg, markOopDesc::biased_lock_mask_in_place);
4785 jcc(Assembler::notZero, try_revoke_bias);
4786
4787 // Biasing is still enabled for this data type. See whether the
4788 // epoch of the current bias is still valid, meaning that the epoch
4789 // bits of the mark word are equal to the epoch bits of the
4790 // prototype header. (Note that the prototype header's epoch bits
4791 // only change at a safepoint.) If not, attempt to rebias the object
4792 // toward the current thread. Note that we must be absolutely sure
4793 // that the current epoch is invalid in order to do this because
4794 // otherwise the manipulations it performs on the mark word are
4795 // illegal.
4796 testl(swap_reg, markOopDesc::epoch_mask_in_place);
4797 jcc(Assembler::notZero, try_rebias);
4798
4799 // The epoch of the current bias is still valid but we know nothing
4800 // about the owner; it might be set or it might be clear. Try to
4801 // acquire the bias of the object using an atomic operation. If this
4802 // fails we will go in to the runtime to revoke the object's bias.
4803 // Note that we first construct the presumed unbiased header so we
4804 // don't accidentally blow away another thread's valid bias.
4805 movl(swap_reg, saved_mark_addr);
4806 andl(swap_reg,
4807 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
4808 if (need_tmp_reg) {
4809 pushl(tmp_reg);
4810 }
4811 get_thread(tmp_reg);
4812 orl(tmp_reg, swap_reg);
4813 if (os::is_MP()) {
4814 lock();
4815 }
4816 cmpxchg(tmp_reg, Address(obj_reg, 0));
4817 if (need_tmp_reg) {
4818 popl(tmp_reg);
4819 }
4820 // If the biasing toward our thread failed, this means that
4821 // another thread succeeded in biasing it toward itself and we
4822 // need to revoke that bias. The revocation will occur in the
4823 // interpreter runtime in the slow case.
4824 if (counters != NULL) {
4825 cond_inc32(Assembler::zero,
4826 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr()));
4827 }
4828 if (slow_case != NULL) {
4829 jcc(Assembler::notZero, *slow_case);
4830 }
4831 jmp(done);
4832
4833 bind(try_rebias);
4834 // At this point we know the epoch has expired, meaning that the
4835 // current "bias owner", if any, is actually invalid. Under these
4836 // circumstances _only_, we are allowed to use the current header's
4837 // value as the comparison value when doing the cas to acquire the
4838 // bias in the current epoch. In other words, we allow transfer of
4839 // the bias from one thread to another directly in this situation.
4840 //
4841 // FIXME: due to a lack of registers we currently blow away the age
4842 // bits in this situation. Should attempt to preserve them.
4843 if (need_tmp_reg) {
4844 pushl(tmp_reg);
4845 }
4846 get_thread(tmp_reg);
4847 movl(swap_reg, klass_addr);
4848 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4849 movl(swap_reg, saved_mark_addr);
4850 if (os::is_MP()) {
4851 lock();
4852 }
4853 cmpxchg(tmp_reg, Address(obj_reg, 0));
4854 if (need_tmp_reg) {
4855 popl(tmp_reg);
4856 }
4857 // If the biasing toward our thread failed, then another thread
4858 // succeeded in biasing it toward itself and we need to revoke that
4859 // bias. The revocation will occur in the runtime in the slow case.
4860 if (counters != NULL) {
4861 cond_inc32(Assembler::zero,
4862 ExternalAddress((address)counters->rebiased_lock_entry_count_addr()));
4863 }
4864 if (slow_case != NULL) {
4865 jcc(Assembler::notZero, *slow_case);
4866 }
4867 jmp(done);
4868
4869 bind(try_revoke_bias);
4870 // The prototype mark in the klass doesn't have the bias bit set any
4871 // more, indicating that objects of this data type are not supposed
4872 // to be biased any more. We are going to try to reset the mark of
4873 // this object to the prototype value and fall through to the
4874 // CAS-based locking scheme. Note that if our CAS fails, it means
4875 // that another thread raced us for the privilege of revoking the
4876 // bias of this particular object, so it's okay to continue in the
4877 // normal locking code.
4878 //
4879 // FIXME: due to a lack of registers we currently blow away the age
4880 // bits in this situation. Should attempt to preserve them.
4881 movl(swap_reg, saved_mark_addr);
4882 if (need_tmp_reg) {
4883 pushl(tmp_reg);
4884 }
4885 movl(tmp_reg, klass_addr);
4886 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()));
4887 if (os::is_MP()) {
4888 lock();
4889 }
4890 cmpxchg(tmp_reg, Address(obj_reg, 0));
4891 if (need_tmp_reg) {
4892 popl(tmp_reg);
4893 }
4894 // Fall through to the normal CAS-based lock, because no matter what
4895 // the result of the above CAS, some thread must have succeeded in
4896 // removing the bias bit from the object's header.
4897 if (counters != NULL) {
4898 cond_inc32(Assembler::zero,
4899 ExternalAddress((address)counters->revoked_lock_entry_count_addr()));
4900 }
4901
4902 bind(cas_label);
4903
4904 return null_check_offset;
4905 }
4906
4907
4908 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
4909 assert(UseBiasedLocking, "why call this otherwise?");
4910
4911 // Check for biased locking unlock case, which is a no-op
4912 // Note: we do not have to check the thread ID for two reasons.
4913 // First, the interpreter checks for IllegalMonitorStateException at
4914 // a higher level. Second, if the bias was revoked while we held the
4915 // lock, the object could not be rebiased toward another thread, so
4916 // the bias bit would be clear.
4917 movl(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
4918 andl(temp_reg, markOopDesc::biased_lock_mask_in_place);
4919 cmpl(temp_reg, markOopDesc::biased_lock_pattern);
4920 jcc(Assembler::equal, done);
4921 }
4922
4923
4924 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
4925 switch (cond) {
4926 // Note some conditions are synonyms for others
4927 case Assembler::zero: return Assembler::notZero;
4928 case Assembler::notZero: return Assembler::zero;
4929 case Assembler::less: return Assembler::greaterEqual;
4930 case Assembler::lessEqual: return Assembler::greater;
4931 case Assembler::greater: return Assembler::lessEqual;
4932 case Assembler::greaterEqual: return Assembler::less;
4933 case Assembler::below: return Assembler::aboveEqual;
4934 case Assembler::belowEqual: return Assembler::above;
4935 case Assembler::above: return Assembler::belowEqual;
4936 case Assembler::aboveEqual: return Assembler::below;
4937 case Assembler::overflow: return Assembler::noOverflow;
4938 case Assembler::noOverflow: return Assembler::overflow;
4939 case Assembler::negative: return Assembler::positive;
4940 case Assembler::positive: return Assembler::negative;
4941 case Assembler::parity: return Assembler::noParity;
4942 case Assembler::noParity: return Assembler::parity;
4943 }
4944 ShouldNotReachHere(); return Assembler::overflow;
4945 }
4946
4947
4948 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
4949 Condition negated_cond = negate_condition(cond);
4950 Label L;
4951 jcc(negated_cond, L);
4952 atomic_incl(counter_addr);
4953 bind(L);
4954 }
4955
4956 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) {
4957 pushfd();
4958 if (os::is_MP())
4959 lock();
4960 increment(counter_addr);
4961 popfd();
4962 }
4963
4964 SkipIfEqual::SkipIfEqual(
4965 MacroAssembler* masm, const bool* flag_addr, bool value) {
4966 _masm = masm;
4967 _masm->cmp8(ExternalAddress((address)flag_addr), value);
4968 _masm->jcc(Assembler::equal, _label);
4969 }
4970
4971 SkipIfEqual::~SkipIfEqual() {
4972 _masm->bind(_label);
4973 }
4974
4975
4976 // Writes to stack successive pages until offset reached to check for
4977 // stack overflow + shadow pages. This clobbers tmp.
4978 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4979 movl(tmp, rsp);
4980 // Bang stack for total size given plus shadow page size.
4981 // Bang one page at a time because large size can bang beyond yellow and
4982 // red zones.
4983 Label loop;
4984 bind(loop);
4985 movl(Address(tmp, (-os::vm_page_size())), size );
4986 subl(tmp, os::vm_page_size());
4987 subl(size, os::vm_page_size());
4988 jcc(Assembler::greater, loop);
4989
4990 // Bang down shadow pages too.
4991 // The -1 because we already subtracted 1 page.
4992 for (int i = 0; i< StackShadowPages-1; i++) {
4993 movl(Address(tmp, (-i*os::vm_page_size())), size );
4994 }
4995 }