1 //
2 // Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundry (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 tty->print("FLDCW 24 bit fpu control word");
499 tty->print_cr(""); tty->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 tty->print_cr("# stack bang"); tty->print("\t");
514 }
515 tty->print_cr("PUSHL EBP"); tty->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 tty->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 tty->print_cr(""); tty->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 tty->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 tty->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size ) {
729 if( cbuf ) {
730 emit_opcode (*cbuf, opcode );
731 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
732 #ifndef PRODUCT
733 } else if( !do_size ) {
734 if( size != 0 ) tty->print("\n\t");
735 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
736 if( is_load ) tty->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
737 else tty->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
738 } else { // FLD, FST, PUSH, POP
739 tty->print("%s [ESP + #%d]",op_str,offset);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 return size+3+offset_size;
745 }
746
747 // Helper for XMM registers. Extra opcode bits, limited syntax.
748 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
749 int offset, int reg_lo, int reg_hi, int size ) {
750 if( cbuf ) {
751 if( reg_lo+1 == reg_hi ) { // double move?
752 if( is_load && !UseXmmLoadAndClearUpper )
753 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
754 else
755 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
756 } else {
757 emit_opcode(*cbuf, 0xF3 );
758 }
759 emit_opcode(*cbuf, 0x0F );
760 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
761 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
762 else
763 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
764 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
765 #ifndef PRODUCT
766 } else if( !do_size ) {
767 if( size != 0 ) tty->print("\n\t");
768 if( reg_lo+1 == reg_hi ) { // double move?
769 if( is_load ) tty->print("%s %s,[ESP + #%d]",
770 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
771 Matcher::regName[reg_lo], offset);
772 else tty->print("MOVSD [ESP + #%d],%s",
773 offset, Matcher::regName[reg_lo]);
774 } else {
775 if( is_load ) tty->print("MOVSS %s,[ESP + #%d]",
776 Matcher::regName[reg_lo], offset);
777 else tty->print("MOVSS [ESP + #%d],%s",
778 offset, Matcher::regName[reg_lo]);
779 }
780 #endif
781 }
782 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
783 return size+5+offset_size;
784 }
785
786
787 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
788 int src_hi, int dst_hi, int size ) {
789 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
790 if( cbuf ) {
791 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
792 emit_opcode(*cbuf, 0x66 );
793 }
794 emit_opcode(*cbuf, 0x0F );
795 emit_opcode(*cbuf, 0x28 );
796 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
797 #ifndef PRODUCT
798 } else if( !do_size ) {
799 if( size != 0 ) tty->print("\n\t");
800 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
801 tty->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
802 } else {
803 tty->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
804 }
805 #endif
806 }
807 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
808 } else {
809 if( cbuf ) {
810 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
811 emit_opcode(*cbuf, 0x0F );
812 emit_opcode(*cbuf, 0x10 );
813 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
814 #ifndef PRODUCT
815 } else if( !do_size ) {
816 if( size != 0 ) tty->print("\n\t");
817 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
818 tty->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
819 } else {
820 tty->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
821 }
822 #endif
823 }
824 return size+4;
825 }
826 }
827
828 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size ) {
829 if( cbuf ) {
830 emit_opcode(*cbuf, 0x8B );
831 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
832 #ifndef PRODUCT
833 } else if( !do_size ) {
834 if( size != 0 ) tty->print("\n\t");
835 tty->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
836 #endif
837 }
838 return size+2;
839 }
840
841 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, int offset, int size ) {
842 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
843 if( cbuf ) {
844 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
845 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
846 #ifndef PRODUCT
847 } else if( !do_size ) {
848 if( size != 0 ) tty->print("\n\t");
849 tty->print("FLD %s",Matcher::regName[src_lo]);
850 #endif
851 }
852 size += 2;
853 }
854
855 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
856 const char *op_str;
857 int op;
858 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
859 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
860 op = 0xDD;
861 } else { // 32-bit store
862 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
863 op = 0xD9;
864 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
865 }
866
867 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size);
868 }
869
870 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
871 // Get registers to move
872 OptoReg::Name src_second = ra_->get_reg_second(in(1));
873 OptoReg::Name src_first = ra_->get_reg_first(in(1));
874 OptoReg::Name dst_second = ra_->get_reg_second(this );
875 OptoReg::Name dst_first = ra_->get_reg_first(this );
876
877 enum RC src_second_rc = rc_class(src_second);
878 enum RC src_first_rc = rc_class(src_first);
879 enum RC dst_second_rc = rc_class(dst_second);
880 enum RC dst_first_rc = rc_class(dst_first);
881
882 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
883
884 // Generate spill code!
885 int size = 0;
886
887 if( src_first == dst_first && src_second == dst_second )
888 return size; // Self copy, no move
889
890 // --------------------------------------
891 // Check for mem-mem move. push/pop to move.
892 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
893 if( src_second == dst_first ) { // overlapping stack copy ranges
894 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
895 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size);
896 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size);
897 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
898 }
899 // move low bits
900 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size);
901 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size);
902 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
903 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size);
904 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size);
905 }
906 return size;
907 }
908
909 // --------------------------------------
910 // Check for integer reg-reg copy
911 if( src_first_rc == rc_int && dst_first_rc == rc_int )
912 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size);
913
914 // Check for integer store
915 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
916 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size);
917
918 // Check for integer load
919 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
920 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size);
921
922 // --------------------------------------
923 // Check for float reg-reg copy
924 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
925 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
926 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
927 if( cbuf ) {
928
929 // Note the mucking with the register encode to compensate for the 0/1
930 // indexing issue mentioned in a comment in the reg_def sections
931 // for FPR registers many lines above here.
932
933 if( src_first != FPR1L_num ) {
934 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
935 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
936 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
937 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
938 } else {
939 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
940 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
941 }
942 #ifndef PRODUCT
943 } else if( !do_size ) {
944 if( size != 0 ) st->print("\n\t");
945 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
946 else st->print( "FST %s", Matcher::regName[dst_first]);
947 #endif
948 }
949 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
950 }
951
952 // Check for float store
953 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
954 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size);
955 }
956
957 // Check for float load
958 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
959 int offset = ra_->reg2offset(src_first);
960 const char *op_str;
961 int op;
962 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
963 op_str = "FLD_D";
964 op = 0xDD;
965 } else { // 32-bit load
966 op_str = "FLD_S";
967 op = 0xD9;
968 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
969 }
970 if( cbuf ) {
971 emit_opcode (*cbuf, op );
972 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
973 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
974 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
975 #ifndef PRODUCT
976 } else if( !do_size ) {
977 if( size != 0 ) st->print("\n\t");
978 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
979 #endif
980 }
981 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
982 return size + 3+offset_size+2;
983 }
984
985 // Check for xmm reg-reg copy
986 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
987 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
988 (src_first+1 == src_second && dst_first+1 == dst_second),
989 "no non-adjacent float-moves" );
990 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size);
991 }
992
993 // Check for xmm store
994 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size);
996 }
997
998 // Check for float xmm load
999 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1000 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size);
1001 }
1002
1003 // Copy from float reg to xmm reg
1004 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1005 // copy to the top of stack from floating point reg
1006 // and use LEA to preserve flags
1007 if( cbuf ) {
1008 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1009 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1010 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1011 emit_d8(*cbuf,0xF8);
1012 #ifndef PRODUCT
1013 } else if( !do_size ) {
1014 if( size != 0 ) st->print("\n\t");
1015 st->print("LEA ESP,[ESP-8]");
1016 #endif
1017 }
1018 size += 4;
1019
1020 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size);
1021
1022 // Copy from the temp memory to the xmm reg.
1023 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size);
1024
1025 if( cbuf ) {
1026 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1027 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1028 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1029 emit_d8(*cbuf,0x08);
1030 #ifndef PRODUCT
1031 } else if( !do_size ) {
1032 if( size != 0 ) st->print("\n\t");
1033 st->print("LEA ESP,[ESP+8]");
1034 #endif
1035 }
1036 size += 4;
1037 return size;
1038 }
1039
1040 assert( size > 0, "missed a case" );
1041
1042 // --------------------------------------------------------------------
1043 // Check for second bits still needing moving.
1044 if( src_second == dst_second )
1045 return size; // Self copy; no move
1046 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1047
1048 // Check for second word int-int move
1049 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1050 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size);
1051
1052 // Check for second word integer store
1053 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1054 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size);
1055
1056 // Check for second word integer load
1057 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1058 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size);
1059
1060
1061 Unimplemented();
1062 }
1063
1064 #ifndef PRODUCT
1065 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1066 implementation( NULL, ra_, false, st );
1067 }
1068 #endif
1069
1070 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1071 implementation( &cbuf, ra_, false, NULL );
1072 }
1073
1074 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1075 return implementation( NULL, ra_, true, NULL );
1076 }
1077
1078 //=============================================================================
1079 #ifndef PRODUCT
1080 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1081 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1082 }
1083 #endif
1084
1085 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1086 MacroAssembler _masm(&cbuf);
1087 __ nop(_count);
1088 }
1089
1090 uint MachNopNode::size(PhaseRegAlloc *) const {
1091 return _count;
1092 }
1093
1094
1095 //=============================================================================
1096 #ifndef PRODUCT
1097 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1098 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1099 int reg = ra_->get_reg_first(this);
1100 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1101 }
1102 #endif
1103
1104 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1105 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1106 int reg = ra_->get_encode(this);
1107 if( offset >= 128 ) {
1108 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1109 emit_rm(cbuf, 0x2, reg, 0x04);
1110 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1111 emit_d32(cbuf, offset);
1112 }
1113 else {
1114 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1115 emit_rm(cbuf, 0x1, reg, 0x04);
1116 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1117 emit_d8(cbuf, offset);
1118 }
1119 }
1120
1121 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1122 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1123 if( offset >= 128 ) {
1124 return 7;
1125 }
1126 else {
1127 return 4;
1128 }
1129 }
1130
1131 //=============================================================================
1132
1133 // emit call stub, compiled java to interpreter
1134 void emit_java_to_interp(CodeBuffer &cbuf ) {
1135 // Stub is fixed up when the corresponding call is converted from calling
1136 // compiled code to calling interpreted code.
1137 // mov rbx,0
1138 // jmp -1
1139
1140 address mark = cbuf.inst_mark(); // get mark within main instrs section
1141
1142 // Note that the code buffer's inst_mark is always relative to insts.
1143 // That's why we must use the macroassembler to generate a stub.
1144 MacroAssembler _masm(&cbuf);
1145
1146 address base =
1147 __ start_a_stub(Compile::MAX_stubs_size);
1148 if (base == NULL) return; // CodeBuffer::expand failed
1149 // static stub relocation stores the instruction address of the call
1150 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1151 // static stub relocation also tags the methodOop in the code-stream.
1152 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1153 // This is recognized as unresolved by relocs/nativeInst/ic code
1154 __ jump(RuntimeAddress(__ pc()));
1155
1156 __ end_a_stub();
1157 // Update current stubs pointer and restore code_end.
1158 }
1159 // size of call stub, compiled java to interpretor
1160 uint size_java_to_interp() {
1161 return 10; // movl; jmp
1162 }
1163 // relocation entries for call stub, compiled java to interpretor
1164 uint reloc_java_to_interp() {
1165 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1166 }
1167
1168 //=============================================================================
1169 #ifndef PRODUCT
1170 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1171 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1172 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1173 st->print_cr("\tNOP");
1174 st->print_cr("\tNOP");
1175 if( !OptoBreakpoint )
1176 st->print_cr("\tNOP");
1177 }
1178 #endif
1179
1180 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1181 MacroAssembler masm(&cbuf);
1182 #ifdef ASSERT
1183 uint code_size = cbuf.code_size();
1184 #endif
1185 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1186 masm.jump_cc(Assembler::notEqual,
1187 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1188 /* WARNING these NOPs are critical so that verified entry point is properly
1189 aligned for patching by NativeJump::patch_verified_entry() */
1190 int nops_cnt = 2;
1191 if( !OptoBreakpoint ) // Leave space for int3
1192 nops_cnt += 1;
1193 masm.nop(nops_cnt);
1194
1195 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1196 }
1197
1198 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1199 return OptoBreakpoint ? 11 : 12;
1200 }
1201
1202
1203 //=============================================================================
1204 uint size_exception_handler() {
1205 // NativeCall instruction size is the same as NativeJump.
1206 // exception handler starts out as jump and can be patched to
1207 // a call be deoptimization. (4932387)
1208 // Note that this value is also credited (in output.cpp) to
1209 // the size of the code section.
1210 return NativeJump::instruction_size;
1211 }
1212
1213 // Emit exception handler code. Stuff framesize into a register
1214 // and call a VM stub routine.
1215 int emit_exception_handler(CodeBuffer& cbuf) {
1216
1217 // Note that the code buffer's inst_mark is always relative to insts.
1218 // That's why we must use the macroassembler to generate a handler.
1219 MacroAssembler _masm(&cbuf);
1220 address base =
1221 __ start_a_stub(size_exception_handler());
1222 if (base == NULL) return 0; // CodeBuffer::expand failed
1223 int offset = __ offset();
1224 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1225 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1226 __ end_a_stub();
1227 return offset;
1228 }
1229
1230 uint size_deopt_handler() {
1231 // NativeCall instruction size is the same as NativeJump.
1232 // exception handler starts out as jump and can be patched to
1233 // a call be deoptimization. (4932387)
1234 // Note that this value is also credited (in output.cpp) to
1235 // the size of the code section.
1236 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1237 }
1238
1239 // Emit deopt handler code.
1240 int emit_deopt_handler(CodeBuffer& cbuf) {
1241
1242 // Note that the code buffer's inst_mark is always relative to insts.
1243 // That's why we must use the macroassembler to generate a handler.
1244 MacroAssembler _masm(&cbuf);
1245 address base =
1246 __ start_a_stub(size_exception_handler());
1247 if (base == NULL) return 0; // CodeBuffer::expand failed
1248 int offset = __ offset();
1249 InternalAddress here(__ pc());
1250 __ pushptr(here.addr());
1251
1252 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1253 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1254 __ end_a_stub();
1255 return offset;
1256 }
1257
1258
1259 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1260 int mark = cbuf.insts()->mark_off();
1261 MacroAssembler _masm(&cbuf);
1262 address double_address = __ double_constant(x);
1263 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1264 emit_d32_reloc(cbuf,
1265 (int)double_address,
1266 internal_word_Relocation::spec(double_address),
1267 RELOC_DISP32);
1268 }
1269
1270 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1271 int mark = cbuf.insts()->mark_off();
1272 MacroAssembler _masm(&cbuf);
1273 address float_address = __ float_constant(x);
1274 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1275 emit_d32_reloc(cbuf,
1276 (int)float_address,
1277 internal_word_Relocation::spec(float_address),
1278 RELOC_DISP32);
1279 }
1280
1281
1282 int Matcher::regnum_to_fpu_offset(int regnum) {
1283 return regnum - 32; // The FP registers are in the second chunk
1284 }
1285
1286 bool is_positive_zero_float(jfloat f) {
1287 return jint_cast(f) == jint_cast(0.0F);
1288 }
1289
1290 bool is_positive_one_float(jfloat f) {
1291 return jint_cast(f) == jint_cast(1.0F);
1292 }
1293
1294 bool is_positive_zero_double(jdouble d) {
1295 return jlong_cast(d) == jlong_cast(0.0);
1296 }
1297
1298 bool is_positive_one_double(jdouble d) {
1299 return jlong_cast(d) == jlong_cast(1.0);
1300 }
1301
1302 // This is UltraSparc specific, true just means we have fast l2f conversion
1303 const bool Matcher::convL2FSupported(void) {
1304 return true;
1305 }
1306
1307 // Vector width in bytes
1308 const uint Matcher::vector_width_in_bytes(void) {
1309 return UseSSE >= 2 ? 8 : 0;
1310 }
1311
1312 // Vector ideal reg
1313 const uint Matcher::vector_ideal_reg(void) {
1314 return Op_RegD;
1315 }
1316
1317 // Is this branch offset short enough that a short branch can be used?
1318 //
1319 // NOTE: If the platform does not provide any short branch variants, then
1320 // this method should return false for offset 0.
1321 bool Matcher::is_short_branch_offset(int offset) {
1322 return (-128 <= offset && offset <= 127);
1323 }
1324
1325 const bool Matcher::isSimpleConstant64(jlong value) {
1326 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1327 return false;
1328 }
1329
1330 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1331 const bool Matcher::init_array_count_is_in_bytes = false;
1332
1333 // Threshold size for cleararray.
1334 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1335
1336 // Should the Matcher clone shifts on addressing modes, expecting them to
1337 // be subsumed into complex addressing expressions or compute them into
1338 // registers? True for Intel but false for most RISCs
1339 const bool Matcher::clone_shift_expressions = true;
1340
1341 // Is it better to copy float constants, or load them directly from memory?
1342 // Intel can load a float constant from a direct address, requiring no
1343 // extra registers. Most RISCs will have to materialize an address into a
1344 // register first, so they would do better to copy the constant from stack.
1345 const bool Matcher::rematerialize_float_constants = true;
1346
1347 // If CPU can load and store mis-aligned doubles directly then no fixup is
1348 // needed. Else we split the double into 2 integer pieces and move it
1349 // piece-by-piece. Only happens when passing doubles into C code as the
1350 // Java calling convention forces doubles to be aligned.
1351 const bool Matcher::misaligned_doubles_ok = true;
1352
1353
1354 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1355 // Get the memory operand from the node
1356 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1357 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1358 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1359 uint opcnt = 1; // First operand
1360 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1361 while( idx >= skipped+num_edges ) {
1362 skipped += num_edges;
1363 opcnt++; // Bump operand count
1364 assert( opcnt < numopnds, "Accessing non-existent operand" );
1365 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1366 }
1367
1368 MachOper *memory = node->_opnds[opcnt];
1369 MachOper *new_memory = NULL;
1370 switch (memory->opcode()) {
1371 case DIRECT:
1372 case INDOFFSET32X:
1373 // No transformation necessary.
1374 return;
1375 case INDIRECT:
1376 new_memory = new (C) indirect_win95_safeOper( );
1377 break;
1378 case INDOFFSET8:
1379 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1380 break;
1381 case INDOFFSET32:
1382 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1383 break;
1384 case INDINDEXOFFSET:
1385 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1386 break;
1387 case INDINDEXSCALE:
1388 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1389 break;
1390 case INDINDEXSCALEOFFSET:
1391 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1392 break;
1393 case LOAD_LONG_INDIRECT:
1394 case LOAD_LONG_INDOFFSET32:
1395 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1396 return;
1397 default:
1398 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1399 return;
1400 }
1401 node->_opnds[opcnt] = new_memory;
1402 }
1403
1404 // Advertise here if the CPU requires explicit rounding operations
1405 // to implement the UseStrictFP mode.
1406 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1407
1408 // Do floats take an entire double register or just half?
1409 const bool Matcher::float_in_double = true;
1410 // Do ints take an entire long register or just half?
1411 const bool Matcher::int_in_long = false;
1412
1413 // Return whether or not this register is ever used as an argument. This
1414 // function is used on startup to build the trampoline stubs in generateOptoStub.
1415 // Registers not mentioned will be killed by the VM call in the trampoline, and
1416 // arguments in those registers not be available to the callee.
1417 bool Matcher::can_be_java_arg( int reg ) {
1418 if( reg == ECX_num || reg == EDX_num ) return true;
1419 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1420 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1421 return false;
1422 }
1423
1424 bool Matcher::is_spillable_arg( int reg ) {
1425 return can_be_java_arg(reg);
1426 }
1427
1428 // Register for DIVI projection of divmodI
1429 RegMask Matcher::divI_proj_mask() {
1430 return EAX_REG_mask;
1431 }
1432
1433 // Register for MODI projection of divmodI
1434 RegMask Matcher::modI_proj_mask() {
1435 return EDX_REG_mask;
1436 }
1437
1438 // Register for DIVL projection of divmodL
1439 RegMask Matcher::divL_proj_mask() {
1440 ShouldNotReachHere();
1441 return RegMask();
1442 }
1443
1444 // Register for MODL projection of divmodL
1445 RegMask Matcher::modL_proj_mask() {
1446 ShouldNotReachHere();
1447 return RegMask();
1448 }
1449
1450 %}
1451
1452 //----------ENCODING BLOCK-----------------------------------------------------
1453 // This block specifies the encoding classes used by the compiler to output
1454 // byte streams. Encoding classes generate functions which are called by
1455 // Machine Instruction Nodes in order to generate the bit encoding of the
1456 // instruction. Operands specify their base encoding interface with the
1457 // interface keyword. There are currently supported four interfaces,
1458 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1459 // operand to generate a function which returns its register number when
1460 // queried. CONST_INTER causes an operand to generate a function which
1461 // returns the value of the constant when queried. MEMORY_INTER causes an
1462 // operand to generate four functions which return the Base Register, the
1463 // Index Register, the Scale Value, and the Offset Value of the operand when
1464 // queried. COND_INTER causes an operand to generate six functions which
1465 // return the encoding code (ie - encoding bits for the instruction)
1466 // associated with each basic boolean condition for a conditional instruction.
1467 // Instructions specify two basic values for encoding. They use the
1468 // ins_encode keyword to specify their encoding class (which must be one of
1469 // the class names specified in the encoding block), and they use the
1470 // opcode keyword to specify, in order, their primary, secondary, and
1471 // tertiary opcode. Only the opcode sections which a particular instruction
1472 // needs for encoding need to be specified.
1473 encode %{
1474 // Build emit functions for each basic byte or larger field in the intel
1475 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1476 // code in the enc_class source block. Emit functions will live in the
1477 // main source block for now. In future, we can generalize this by
1478 // adding a syntax that specifies the sizes of fields in an order,
1479 // so that the adlc can build the emit functions automagically
1480 enc_class OpcP %{ // Emit opcode
1481 emit_opcode(cbuf,$primary);
1482 %}
1483
1484 enc_class OpcS %{ // Emit opcode
1485 emit_opcode(cbuf,$secondary);
1486 %}
1487
1488 enc_class Opcode(immI d8 ) %{ // Emit opcode
1489 emit_opcode(cbuf,$d8$$constant);
1490 %}
1491
1492 enc_class SizePrefix %{
1493 emit_opcode(cbuf,0x66);
1494 %}
1495
1496 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1497 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1498 %}
1499
1500 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1501 emit_opcode(cbuf,$opcode$$constant);
1502 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1503 %}
1504
1505 enc_class mov_r32_imm0( eRegI dst ) %{
1506 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1507 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1508 %}
1509
1510 enc_class cdq_enc %{
1511 // Full implementation of Java idiv and irem; checks for
1512 // special case as described in JVM spec., p.243 & p.271.
1513 //
1514 // normal case special case
1515 //
1516 // input : rax,: dividend min_int
1517 // reg: divisor -1
1518 //
1519 // output: rax,: quotient (= rax, idiv reg) min_int
1520 // rdx: remainder (= rax, irem reg) 0
1521 //
1522 // Code sequnce:
1523 //
1524 // 81 F8 00 00 00 80 cmp rax,80000000h
1525 // 0F 85 0B 00 00 00 jne normal_case
1526 // 33 D2 xor rdx,edx
1527 // 83 F9 FF cmp rcx,0FFh
1528 // 0F 84 03 00 00 00 je done
1529 // normal_case:
1530 // 99 cdq
1531 // F7 F9 idiv rax,ecx
1532 // done:
1533 //
1534 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1535 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1536 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1537 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1538 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1539 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1540 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1541 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1542 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1543 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1544 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1545 // normal_case:
1546 emit_opcode(cbuf,0x99); // cdq
1547 // idiv (note: must be emitted by the user of this rule)
1548 // normal:
1549 %}
1550
1551 // Dense encoding for older common ops
1552 enc_class Opc_plus(immI opcode, eRegI reg) %{
1553 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1554 %}
1555
1556
1557 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1558 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1559 // Check for 8-bit immediate, and set sign extend bit in opcode
1560 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1561 emit_opcode(cbuf, $primary | 0x02);
1562 }
1563 else { // If 32-bit immediate
1564 emit_opcode(cbuf, $primary);
1565 }
1566 %}
1567
1568 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1569 // Emit primary opcode and set sign-extend bit
1570 // Check for 8-bit immediate, and set sign extend bit in opcode
1571 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1572 emit_opcode(cbuf, $primary | 0x02); }
1573 else { // If 32-bit immediate
1574 emit_opcode(cbuf, $primary);
1575 }
1576 // Emit r/m byte with secondary opcode, after primary opcode.
1577 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1578 %}
1579
1580 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1581 // Check for 8-bit immediate, and set sign extend bit in opcode
1582 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1583 $$$emit8$imm$$constant;
1584 }
1585 else { // If 32-bit immediate
1586 // Output immediate
1587 $$$emit32$imm$$constant;
1588 }
1589 %}
1590
1591 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1592 // Emit primary opcode and set sign-extend bit
1593 // Check for 8-bit immediate, and set sign extend bit in opcode
1594 int con = (int)$imm$$constant; // Throw away top bits
1595 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1596 // Emit r/m byte with secondary opcode, after primary opcode.
1597 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1598 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1599 else emit_d32(cbuf,con);
1600 %}
1601
1602 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1603 // Emit primary opcode and set sign-extend bit
1604 // Check for 8-bit immediate, and set sign extend bit in opcode
1605 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1606 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1607 // Emit r/m byte with tertiary opcode, after primary opcode.
1608 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1609 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1610 else emit_d32(cbuf,con);
1611 %}
1612
1613 enc_class Lbl (label labl) %{ // JMP, CALL
1614 Label *l = $labl$$label;
1615 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1616 %}
1617
1618 enc_class LblShort (label labl) %{ // JMP, CALL
1619 Label *l = $labl$$label;
1620 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1621 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1622 emit_d8(cbuf, disp);
1623 %}
1624
1625 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1626 emit_cc(cbuf, $secondary, $dst$$reg );
1627 %}
1628
1629 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1630 int destlo = $dst$$reg;
1631 int desthi = HIGH_FROM_LOW(destlo);
1632 // bswap lo
1633 emit_opcode(cbuf, 0x0F);
1634 emit_cc(cbuf, 0xC8, destlo);
1635 // bswap hi
1636 emit_opcode(cbuf, 0x0F);
1637 emit_cc(cbuf, 0xC8, desthi);
1638 // xchg lo and hi
1639 emit_opcode(cbuf, 0x87);
1640 emit_rm(cbuf, 0x3, destlo, desthi);
1641 %}
1642
1643 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1644 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1645 %}
1646
1647 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1648 Label *l = $labl$$label;
1649 $$$emit8$primary;
1650 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1651 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1652 %}
1653
1654 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1655 Label *l = $labl$$label;
1656 emit_cc(cbuf, $primary, $cop$$cmpcode);
1657 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1658 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1659 emit_d8(cbuf, disp);
1660 %}
1661
1662 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1663 $$$emit8$primary;
1664 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1665 %}
1666
1667 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1668 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1669 emit_d8(cbuf, op >> 8 );
1670 emit_d8(cbuf, op & 255);
1671 %}
1672
1673 // emulate a CMOV with a conditional branch around a MOV
1674 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1675 // Invert sense of branch from sense of CMOV
1676 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1677 emit_d8( cbuf, $brOffs$$constant );
1678 %}
1679
1680 enc_class enc_PartialSubtypeCheck( ) %{
1681 Register Redi = as_Register(EDI_enc); // result register
1682 Register Reax = as_Register(EAX_enc); // super class
1683 Register Recx = as_Register(ECX_enc); // killed
1684 Register Resi = as_Register(ESI_enc); // sub class
1685 Label hit, miss;
1686
1687 MacroAssembler _masm(&cbuf);
1688 // Compare super with sub directly, since super is not in its own SSA.
1689 // The compiler used to emit this test, but we fold it in here,
1690 // to allow platform-specific tweaking on sparc.
1691 __ cmpptr(Reax, Resi);
1692 __ jcc(Assembler::equal, hit);
1693 #ifndef PRODUCT
1694 __ incrementl(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1695 #endif //PRODUCT
1696 __ movptr(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
1697 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes()));
1698 __ addptr(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
1699 __ repne_scan();
1700 __ jcc(Assembler::notEqual, miss);
1701 __ movptr(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax);
1702 __ bind(hit);
1703 if( $primary )
1704 __ xorptr(Redi,Redi);
1705 __ bind(miss);
1706 %}
1707
1708 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1709 MacroAssembler masm(&cbuf);
1710 int start = masm.offset();
1711 if (UseSSE >= 2) {
1712 if (VerifyFPU) {
1713 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1714 }
1715 } else {
1716 // External c_calling_convention expects the FPU stack to be 'clean'.
1717 // Compiled code leaves it dirty. Do cleanup now.
1718 masm.empty_FPU_stack();
1719 }
1720 if (sizeof_FFree_Float_Stack_All == -1) {
1721 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1722 } else {
1723 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1724 }
1725 %}
1726
1727 enc_class Verify_FPU_For_Leaf %{
1728 if( VerifyFPU ) {
1729 MacroAssembler masm(&cbuf);
1730 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1731 }
1732 %}
1733
1734 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1735 // This is the instruction starting address for relocation info.
1736 cbuf.set_inst_mark();
1737 $$$emit8$primary;
1738 // CALL directly to the runtime
1739 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1740 runtime_call_Relocation::spec(), RELOC_IMM32 );
1741
1742 if (UseSSE >= 2) {
1743 MacroAssembler _masm(&cbuf);
1744 BasicType rt = tf()->return_type();
1745
1746 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1747 // A C runtime call where the return value is unused. In SSE2+
1748 // mode the result needs to be removed from the FPU stack. It's
1749 // likely that this function call could be removed by the
1750 // optimizer if the C function is a pure function.
1751 __ ffree(0);
1752 } else if (rt == T_FLOAT) {
1753 __ lea(rsp, Address(rsp, -4));
1754 __ fstp_s(Address(rsp, 0));
1755 __ movflt(xmm0, Address(rsp, 0));
1756 __ lea(rsp, Address(rsp, 4));
1757 } else if (rt == T_DOUBLE) {
1758 __ lea(rsp, Address(rsp, -8));
1759 __ fstp_d(Address(rsp, 0));
1760 __ movdbl(xmm0, Address(rsp, 0));
1761 __ lea(rsp, Address(rsp, 8));
1762 }
1763 }
1764 %}
1765
1766
1767 enc_class pre_call_FPU %{
1768 // If method sets FPU control word restore it here
1769 if( Compile::current()->in_24_bit_fp_mode() ) {
1770 MacroAssembler masm(&cbuf);
1771 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1772 }
1773 %}
1774
1775 enc_class post_call_FPU %{
1776 // If method sets FPU control word do it here also
1777 if( Compile::current()->in_24_bit_fp_mode() ) {
1778 MacroAssembler masm(&cbuf);
1779 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1780 }
1781 %}
1782
1783 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1784 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1785 // who we intended to call.
1786 cbuf.set_inst_mark();
1787 $$$emit8$primary;
1788 if ( !_method ) {
1789 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1790 runtime_call_Relocation::spec(), RELOC_IMM32 );
1791 } else if(_optimized_virtual) {
1792 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1793 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1794 } else {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 static_call_Relocation::spec(), RELOC_IMM32 );
1797 }
1798 if( _method ) { // Emit stub for static call
1799 emit_java_to_interp(cbuf);
1800 }
1801 %}
1802
1803 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1804 // !!!!!
1805 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1806 // emit_call_dynamic_prologue( cbuf );
1807 cbuf.set_inst_mark();
1808 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1809 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1810 address virtual_call_oop_addr = cbuf.inst_mark();
1811 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1812 // who we intended to call.
1813 cbuf.set_inst_mark();
1814 $$$emit8$primary;
1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1816 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1817 %}
1818
1819 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1820 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1821 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1822
1823 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1824 cbuf.set_inst_mark();
1825 $$$emit8$primary;
1826 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1827 emit_d8(cbuf, disp); // Displacement
1828
1829 %}
1830
1831 enc_class Xor_Reg (eRegI dst) %{
1832 emit_opcode(cbuf, 0x33);
1833 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1834 %}
1835
1836 // Following encoding is no longer used, but may be restored if calling
1837 // convention changes significantly.
1838 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1839 //
1840 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1841 // // int ic_reg = Matcher::inline_cache_reg();
1842 // // int ic_encode = Matcher::_regEncode[ic_reg];
1843 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1844 // // int imo_encode = Matcher::_regEncode[imo_reg];
1845 //
1846 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1847 // // // so we load it immediately before the call
1848 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1849 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1850 //
1851 // // xor rbp,ebp
1852 // emit_opcode(cbuf, 0x33);
1853 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1854 //
1855 // // CALL to interpreter.
1856 // cbuf.set_inst_mark();
1857 // $$$emit8$primary;
1858 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1859 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1860 // %}
1861
1862 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1863 $$$emit8$primary;
1864 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1865 $$$emit8$shift$$constant;
1866 %}
1867
1868 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1869 // Load immediate does not have a zero or sign extended version
1870 // for 8-bit immediates
1871 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1872 $$$emit32$src$$constant;
1873 %}
1874
1875 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1876 // Load immediate does not have a zero or sign extended version
1877 // for 8-bit immediates
1878 emit_opcode(cbuf, $primary + $dst$$reg);
1879 $$$emit32$src$$constant;
1880 %}
1881
1882 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1883 // Load immediate does not have a zero or sign extended version
1884 // for 8-bit immediates
1885 int dst_enc = $dst$$reg;
1886 int src_con = $src$$constant & 0x0FFFFFFFFL;
1887 if (src_con == 0) {
1888 // xor dst, dst
1889 emit_opcode(cbuf, 0x33);
1890 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1891 } else {
1892 emit_opcode(cbuf, $primary + dst_enc);
1893 emit_d32(cbuf, src_con);
1894 }
1895 %}
1896
1897 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1898 // Load immediate does not have a zero or sign extended version
1899 // for 8-bit immediates
1900 int dst_enc = $dst$$reg + 2;
1901 int src_con = ((julong)($src$$constant)) >> 32;
1902 if (src_con == 0) {
1903 // xor dst, dst
1904 emit_opcode(cbuf, 0x33);
1905 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1906 } else {
1907 emit_opcode(cbuf, $primary + dst_enc);
1908 emit_d32(cbuf, src_con);
1909 }
1910 %}
1911
1912
1913 enc_class LdImmD (immD src) %{ // Load Immediate
1914 if( is_positive_zero_double($src$$constant)) {
1915 // FLDZ
1916 emit_opcode(cbuf,0xD9);
1917 emit_opcode(cbuf,0xEE);
1918 } else if( is_positive_one_double($src$$constant)) {
1919 // FLD1
1920 emit_opcode(cbuf,0xD9);
1921 emit_opcode(cbuf,0xE8);
1922 } else {
1923 emit_opcode(cbuf,0xDD);
1924 emit_rm(cbuf, 0x0, 0x0, 0x5);
1925 emit_double_constant(cbuf, $src$$constant);
1926 }
1927 %}
1928
1929
1930 enc_class LdImmF (immF src) %{ // Load Immediate
1931 if( is_positive_zero_float($src$$constant)) {
1932 emit_opcode(cbuf,0xD9);
1933 emit_opcode(cbuf,0xEE);
1934 } else if( is_positive_one_float($src$$constant)) {
1935 emit_opcode(cbuf,0xD9);
1936 emit_opcode(cbuf,0xE8);
1937 } else {
1938 $$$emit8$primary;
1939 // Load immediate does not have a zero or sign extended version
1940 // for 8-bit immediates
1941 // First load to TOS, then move to dst
1942 emit_rm(cbuf, 0x0, 0x0, 0x5);
1943 emit_float_constant(cbuf, $src$$constant);
1944 }
1945 %}
1946
1947 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1948 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1949 emit_float_constant(cbuf, $con$$constant);
1950 %}
1951
1952 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1953 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1954 emit_double_constant(cbuf, $con$$constant);
1955 %}
1956
1957 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1958 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1959 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1960 emit_opcode(cbuf, 0x0F);
1961 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1962 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1963 emit_double_constant(cbuf, $con$$constant);
1964 %}
1965
1966 enc_class Opc_MemImm_F(immF src) %{
1967 cbuf.set_inst_mark();
1968 $$$emit8$primary;
1969 emit_rm(cbuf, 0x0, $secondary, 0x5);
1970 emit_float_constant(cbuf, $src$$constant);
1971 %}
1972
1973
1974 enc_class MovI2X_reg(regX dst, eRegI src) %{
1975 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1976 emit_opcode(cbuf, 0x0F );
1977 emit_opcode(cbuf, 0x6E );
1978 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1979 %}
1980
1981 enc_class MovX2I_reg(eRegI dst, regX src) %{
1982 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1983 emit_opcode(cbuf, 0x0F );
1984 emit_opcode(cbuf, 0x7E );
1985 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1986 %}
1987
1988 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1989 { // MOVD $dst,$src.lo
1990 emit_opcode(cbuf,0x66);
1991 emit_opcode(cbuf,0x0F);
1992 emit_opcode(cbuf,0x6E);
1993 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1994 }
1995 { // MOVD $tmp,$src.hi
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2000 }
2001 { // PUNPCKLDQ $dst,$tmp
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x62);
2005 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2006 }
2007 %}
2008
2009 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2010 { // MOVD $dst.lo,$src
2011 emit_opcode(cbuf,0x66);
2012 emit_opcode(cbuf,0x0F);
2013 emit_opcode(cbuf,0x7E);
2014 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2015 }
2016 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2017 emit_opcode(cbuf,0xF2);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x70);
2020 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2021 emit_d8(cbuf, 0x4E);
2022 }
2023 { // MOVD $dst.hi,$tmp
2024 emit_opcode(cbuf,0x66);
2025 emit_opcode(cbuf,0x0F);
2026 emit_opcode(cbuf,0x7E);
2027 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2028 }
2029 %}
2030
2031
2032 // Encode a reg-reg copy. If it is useless, then empty encoding.
2033 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2034 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2035 %}
2036
2037 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2038 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2039 %}
2040
2041 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2042 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2043 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2044 %}
2045
2046 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2047 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2048 %}
2049
2050 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2051 $$$emit8$primary;
2052 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2053 %}
2054
2055 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2056 $$$emit8$secondary;
2057 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2058 %}
2059
2060 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2061 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2062 %}
2063
2064 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2065 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2066 %}
2067
2068 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2069 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2070 %}
2071
2072 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2073 // Output immediate
2074 $$$emit32$src$$constant;
2075 %}
2076
2077 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2078 // Output Float immediate bits
2079 jfloat jf = $src$$constant;
2080 int jf_as_bits = jint_cast( jf );
2081 emit_d32(cbuf, jf_as_bits);
2082 %}
2083
2084 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2085 // Output Float immediate bits
2086 jfloat jf = $src$$constant;
2087 int jf_as_bits = jint_cast( jf );
2088 emit_d32(cbuf, jf_as_bits);
2089 %}
2090
2091 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2092 // Output immediate
2093 $$$emit16$src$$constant;
2094 %}
2095
2096 enc_class Con_d32(immI src) %{
2097 emit_d32(cbuf,$src$$constant);
2098 %}
2099
2100 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2101 // Output immediate memory reference
2102 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2103 emit_d32(cbuf, 0x00);
2104 %}
2105
2106 enc_class lock_prefix( ) %{
2107 if( os::is_MP() )
2108 emit_opcode(cbuf,0xF0); // [Lock]
2109 %}
2110
2111 // Cmp-xchg long value.
2112 // Note: we need to swap rbx, and rcx before and after the
2113 // cmpxchg8 instruction because the instruction uses
2114 // rcx as the high order word of the new value to store but
2115 // our register encoding uses rbx,.
2116 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2117
2118 // XCHG rbx,ecx
2119 emit_opcode(cbuf,0x87);
2120 emit_opcode(cbuf,0xD9);
2121 // [Lock]
2122 if( os::is_MP() )
2123 emit_opcode(cbuf,0xF0);
2124 // CMPXCHG8 [Eptr]
2125 emit_opcode(cbuf,0x0F);
2126 emit_opcode(cbuf,0xC7);
2127 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2128 // XCHG rbx,ecx
2129 emit_opcode(cbuf,0x87);
2130 emit_opcode(cbuf,0xD9);
2131 %}
2132
2133 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2134 // [Lock]
2135 if( os::is_MP() )
2136 emit_opcode(cbuf,0xF0);
2137
2138 // CMPXCHG [Eptr]
2139 emit_opcode(cbuf,0x0F);
2140 emit_opcode(cbuf,0xB1);
2141 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2142 %}
2143
2144 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2145 int res_encoding = $res$$reg;
2146
2147 // MOV res,0
2148 emit_opcode( cbuf, 0xB8 + res_encoding);
2149 emit_d32( cbuf, 0 );
2150 // JNE,s fail
2151 emit_opcode(cbuf,0x75);
2152 emit_d8(cbuf, 5 );
2153 // MOV res,1
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 1 );
2156 // fail:
2157 %}
2158
2159 enc_class set_instruction_start( ) %{
2160 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2161 %}
2162
2163 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2164 int reg_encoding = $ereg$$reg;
2165 int base = $mem$$base;
2166 int index = $mem$$index;
2167 int scale = $mem$$scale;
2168 int displace = $mem$$disp;
2169 bool disp_is_oop = $mem->disp_is_oop();
2170 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2171 %}
2172
2173 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2174 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2175 int base = $mem$$base;
2176 int index = $mem$$index;
2177 int scale = $mem$$scale;
2178 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2179 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2181 %}
2182
2183 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2184 int r1, r2;
2185 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2186 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2187 emit_opcode(cbuf,0x0F);
2188 emit_opcode(cbuf,$tertiary);
2189 emit_rm(cbuf, 0x3, r1, r2);
2190 emit_d8(cbuf,$cnt$$constant);
2191 emit_d8(cbuf,$primary);
2192 emit_rm(cbuf, 0x3, $secondary, r1);
2193 emit_d8(cbuf,$cnt$$constant);
2194 %}
2195
2196 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2197 emit_opcode( cbuf, 0x8B ); // Move
2198 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2199 emit_d8(cbuf,$primary);
2200 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2201 emit_d8(cbuf,$cnt$$constant-32);
2202 emit_d8(cbuf,$primary);
2203 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2204 emit_d8(cbuf,31);
2205 %}
2206
2207 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2208 int r1, r2;
2209 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2210 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2211
2212 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2213 emit_rm(cbuf, 0x3, r1, r2);
2214 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2215 emit_opcode(cbuf,$primary);
2216 emit_rm(cbuf, 0x3, $secondary, r1);
2217 emit_d8(cbuf,$cnt$$constant-32);
2218 }
2219 emit_opcode(cbuf,0x33); // XOR r2,r2
2220 emit_rm(cbuf, 0x3, r2, r2);
2221 %}
2222
2223 // Clone of RegMem but accepts an extra parameter to access each
2224 // half of a double in memory; it never needs relocation info.
2225 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2226 emit_opcode(cbuf,$opcode$$constant);
2227 int reg_encoding = $rm_reg$$reg;
2228 int base = $mem$$base;
2229 int index = $mem$$index;
2230 int scale = $mem$$scale;
2231 int displace = $mem$$disp + $disp_for_half$$constant;
2232 bool disp_is_oop = false;
2233 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2234 %}
2235
2236 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2237 //
2238 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2239 // and it never needs relocation information.
2240 // Frequently used to move data between FPU's Stack Top and memory.
2241 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2242 int rm_byte_opcode = $rm_opcode$$constant;
2243 int base = $mem$$base;
2244 int index = $mem$$index;
2245 int scale = $mem$$scale;
2246 int displace = $mem$$disp;
2247 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2248 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2249 %}
2250
2251 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2252 int rm_byte_opcode = $rm_opcode$$constant;
2253 int base = $mem$$base;
2254 int index = $mem$$index;
2255 int scale = $mem$$scale;
2256 int displace = $mem$$disp;
2257 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2258 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2259 %}
2260
2261 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2262 int reg_encoding = $dst$$reg;
2263 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2264 int index = 0x04; // 0x04 indicates no index
2265 int scale = 0x00; // 0x00 indicates no scale
2266 int displace = $src1$$constant; // 0x00 indicates no displacement
2267 bool disp_is_oop = false;
2268 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2269 %}
2270
2271 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2272 // Compare dst,src
2273 emit_opcode(cbuf,0x3B);
2274 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2275 // jmp dst < src around move
2276 emit_opcode(cbuf,0x7C);
2277 emit_d8(cbuf,2);
2278 // move dst,src
2279 emit_opcode(cbuf,0x8B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 %}
2282
2283 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2284 // Compare dst,src
2285 emit_opcode(cbuf,0x3B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 // jmp dst > src around move
2288 emit_opcode(cbuf,0x7F);
2289 emit_d8(cbuf,2);
2290 // move dst,src
2291 emit_opcode(cbuf,0x8B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 %}
2294
2295 enc_class enc_FP_store(memory mem, regD src) %{
2296 // If src is FPR1, we can just FST to store it.
2297 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2298 int reg_encoding = 0x2; // Just store
2299 int base = $mem$$base;
2300 int index = $mem$$index;
2301 int scale = $mem$$scale;
2302 int displace = $mem$$disp;
2303 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2304 if( $src$$reg != FPR1L_enc ) {
2305 reg_encoding = 0x3; // Store & pop
2306 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2307 emit_d8( cbuf, 0xC0-1+$src$$reg );
2308 }
2309 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2310 emit_opcode(cbuf,$primary);
2311 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2312 %}
2313
2314 enc_class neg_reg(eRegI dst) %{
2315 // NEG $dst
2316 emit_opcode(cbuf,0xF7);
2317 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2318 %}
2319
2320 enc_class setLT_reg(eCXRegI dst) %{
2321 // SETLT $dst
2322 emit_opcode(cbuf,0x0F);
2323 emit_opcode(cbuf,0x9C);
2324 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2325 %}
2326
2327 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2328 int tmpReg = $tmp$$reg;
2329
2330 // SUB $p,$q
2331 emit_opcode(cbuf,0x2B);
2332 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2333 // SBB $tmp,$tmp
2334 emit_opcode(cbuf,0x1B);
2335 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2336 // AND $tmp,$y
2337 emit_opcode(cbuf,0x23);
2338 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2339 // ADD $p,$tmp
2340 emit_opcode(cbuf,0x03);
2341 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2342 %}
2343
2344 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2345 int tmpReg = $tmp$$reg;
2346
2347 // SUB $p,$q
2348 emit_opcode(cbuf,0x2B);
2349 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2350 // SBB $tmp,$tmp
2351 emit_opcode(cbuf,0x1B);
2352 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2353 // AND $tmp,$y
2354 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2355 emit_opcode(cbuf,0x23);
2356 int reg_encoding = tmpReg;
2357 int base = $mem$$base;
2358 int index = $mem$$index;
2359 int scale = $mem$$scale;
2360 int displace = $mem$$disp;
2361 bool disp_is_oop = $mem->disp_is_oop();
2362 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2363 // ADD $p,$tmp
2364 emit_opcode(cbuf,0x03);
2365 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2366 %}
2367
2368 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2369 // TEST shift,32
2370 emit_opcode(cbuf,0xF7);
2371 emit_rm(cbuf, 0x3, 0, ECX_enc);
2372 emit_d32(cbuf,0x20);
2373 // JEQ,s small
2374 emit_opcode(cbuf, 0x74);
2375 emit_d8(cbuf, 0x04);
2376 // MOV $dst.hi,$dst.lo
2377 emit_opcode( cbuf, 0x8B );
2378 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2379 // CLR $dst.lo
2380 emit_opcode(cbuf, 0x33);
2381 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2382 // small:
2383 // SHLD $dst.hi,$dst.lo,$shift
2384 emit_opcode(cbuf,0x0F);
2385 emit_opcode(cbuf,0xA5);
2386 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2387 // SHL $dst.lo,$shift"
2388 emit_opcode(cbuf,0xD3);
2389 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2390 %}
2391
2392 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2393 // TEST shift,32
2394 emit_opcode(cbuf,0xF7);
2395 emit_rm(cbuf, 0x3, 0, ECX_enc);
2396 emit_d32(cbuf,0x20);
2397 // JEQ,s small
2398 emit_opcode(cbuf, 0x74);
2399 emit_d8(cbuf, 0x04);
2400 // MOV $dst.lo,$dst.hi
2401 emit_opcode( cbuf, 0x8B );
2402 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2403 // CLR $dst.hi
2404 emit_opcode(cbuf, 0x33);
2405 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2406 // small:
2407 // SHRD $dst.lo,$dst.hi,$shift
2408 emit_opcode(cbuf,0x0F);
2409 emit_opcode(cbuf,0xAD);
2410 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2411 // SHR $dst.hi,$shift"
2412 emit_opcode(cbuf,0xD3);
2413 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2414 %}
2415
2416 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2417 // TEST shift,32
2418 emit_opcode(cbuf,0xF7);
2419 emit_rm(cbuf, 0x3, 0, ECX_enc);
2420 emit_d32(cbuf,0x20);
2421 // JEQ,s small
2422 emit_opcode(cbuf, 0x74);
2423 emit_d8(cbuf, 0x05);
2424 // MOV $dst.lo,$dst.hi
2425 emit_opcode( cbuf, 0x8B );
2426 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2427 // SAR $dst.hi,31
2428 emit_opcode(cbuf, 0xC1);
2429 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2430 emit_d8(cbuf, 0x1F );
2431 // small:
2432 // SHRD $dst.lo,$dst.hi,$shift
2433 emit_opcode(cbuf,0x0F);
2434 emit_opcode(cbuf,0xAD);
2435 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2436 // SAR $dst.hi,$shift"
2437 emit_opcode(cbuf,0xD3);
2438 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2439 %}
2440
2441
2442 // ----------------- Encodings for floating point unit -----------------
2443 // May leave result in FPU-TOS or FPU reg depending on opcodes
2444 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2445 $$$emit8$primary;
2446 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2447 %}
2448
2449 // Pop argument in FPR0 with FSTP ST(0)
2450 enc_class PopFPU() %{
2451 emit_opcode( cbuf, 0xDD );
2452 emit_d8( cbuf, 0xD8 );
2453 %}
2454
2455 // !!!!! equivalent to Pop_Reg_F
2456 enc_class Pop_Reg_D( regD dst ) %{
2457 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2458 emit_d8( cbuf, 0xD8+$dst$$reg );
2459 %}
2460
2461 enc_class Push_Reg_D( regD dst ) %{
2462 emit_opcode( cbuf, 0xD9 );
2463 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2464 %}
2465
2466 enc_class strictfp_bias1( regD dst ) %{
2467 emit_opcode( cbuf, 0xDB ); // FLD m80real
2468 emit_opcode( cbuf, 0x2D );
2469 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2470 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2471 emit_opcode( cbuf, 0xC8+$dst$$reg );
2472 %}
2473
2474 enc_class strictfp_bias2( regD dst ) %{
2475 emit_opcode( cbuf, 0xDB ); // FLD m80real
2476 emit_opcode( cbuf, 0x2D );
2477 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2478 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2479 emit_opcode( cbuf, 0xC8+$dst$$reg );
2480 %}
2481
2482 // Special case for moving an integer register to a stack slot.
2483 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2484 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2485 %}
2486
2487 // Special case for moving a register to a stack slot.
2488 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2489 // Opcode already emitted
2490 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2491 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2492 emit_d32(cbuf, $dst$$disp); // Displacement
2493 %}
2494
2495 // Push the integer in stackSlot 'src' onto FP-stack
2496 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2497 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2498 %}
2499
2500 // Push the float in stackSlot 'src' onto FP-stack
2501 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2502 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2503 %}
2504
2505 // Push the double in stackSlot 'src' onto FP-stack
2506 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2507 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2508 %}
2509
2510 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2511 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2512 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2513 %}
2514
2515 // Same as Pop_Mem_F except for opcode
2516 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2518 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2519 %}
2520
2521 enc_class Pop_Reg_F( regF dst ) %{
2522 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2523 emit_d8( cbuf, 0xD8+$dst$$reg );
2524 %}
2525
2526 enc_class Push_Reg_F( regF dst ) %{
2527 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2528 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2529 %}
2530
2531 // Push FPU's float to a stack-slot, and pop FPU-stack
2532 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2533 int pop = 0x02;
2534 if ($src$$reg != FPR1L_enc) {
2535 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2536 emit_d8( cbuf, 0xC0-1+$src$$reg );
2537 pop = 0x03;
2538 }
2539 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2540 %}
2541
2542 // Push FPU's double to a stack-slot, and pop FPU-stack
2543 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2544 int pop = 0x02;
2545 if ($src$$reg != FPR1L_enc) {
2546 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2547 emit_d8( cbuf, 0xC0-1+$src$$reg );
2548 pop = 0x03;
2549 }
2550 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2551 %}
2552
2553 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2554 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2555 int pop = 0xD0 - 1; // -1 since we skip FLD
2556 if ($src$$reg != FPR1L_enc) {
2557 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2558 emit_d8( cbuf, 0xC0-1+$src$$reg );
2559 pop = 0xD8;
2560 }
2561 emit_opcode( cbuf, 0xDD );
2562 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2563 %}
2564
2565
2566 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2567 MacroAssembler masm(&cbuf);
2568 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2569 masm.fmul( $src2$$reg+0); // value at TOS
2570 masm.fadd( $src$$reg+0); // value at TOS
2571 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2572 %}
2573
2574
2575 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2576 // load dst in FPR0
2577 emit_opcode( cbuf, 0xD9 );
2578 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2579 if ($src$$reg != FPR1L_enc) {
2580 // fincstp
2581 emit_opcode (cbuf, 0xD9);
2582 emit_opcode (cbuf, 0xF7);
2583 // swap src with FPR1:
2584 // FXCH FPR1 with src
2585 emit_opcode(cbuf, 0xD9);
2586 emit_d8(cbuf, 0xC8-1+$src$$reg );
2587 // fdecstp
2588 emit_opcode (cbuf, 0xD9);
2589 emit_opcode (cbuf, 0xF6);
2590 }
2591 %}
2592
2593 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2594 // Allocate a word
2595 emit_opcode(cbuf,0x83); // SUB ESP,8
2596 emit_opcode(cbuf,0xEC);
2597 emit_d8(cbuf,0x08);
2598
2599 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2600 emit_opcode (cbuf, 0x0F );
2601 emit_opcode (cbuf, 0x11 );
2602 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2603
2604 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2605 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2606
2607 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2608 emit_opcode (cbuf, 0x0F );
2609 emit_opcode (cbuf, 0x11 );
2610 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2611
2612 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2613 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2614
2615 %}
2616
2617 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2618 // Allocate a word
2619 emit_opcode(cbuf,0x83); // SUB ESP,4
2620 emit_opcode(cbuf,0xEC);
2621 emit_d8(cbuf,0x04);
2622
2623 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2624 emit_opcode (cbuf, 0x0F );
2625 emit_opcode (cbuf, 0x11 );
2626 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2627
2628 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2629 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2630
2631 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2632 emit_opcode (cbuf, 0x0F );
2633 emit_opcode (cbuf, 0x11 );
2634 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2635
2636 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2637 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2638
2639 %}
2640
2641 enc_class Push_ResultXD(regXD dst) %{
2642 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2643
2644 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2645 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2646 emit_opcode (cbuf, 0x0F );
2647 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2648 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2649
2650 emit_opcode(cbuf,0x83); // ADD ESP,8
2651 emit_opcode(cbuf,0xC4);
2652 emit_d8(cbuf,0x08);
2653 %}
2654
2655 enc_class Push_ResultX(regX dst, immI d8) %{
2656 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2657
2658 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2659 emit_opcode (cbuf, 0x0F );
2660 emit_opcode (cbuf, 0x10 );
2661 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2662
2663 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2664 emit_opcode(cbuf,0xC4);
2665 emit_d8(cbuf,$d8$$constant);
2666 %}
2667
2668 enc_class Push_SrcXD(regXD src) %{
2669 // Allocate a word
2670 emit_opcode(cbuf,0x83); // SUB ESP,8
2671 emit_opcode(cbuf,0xEC);
2672 emit_d8(cbuf,0x08);
2673
2674 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2675 emit_opcode (cbuf, 0x0F );
2676 emit_opcode (cbuf, 0x11 );
2677 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2678
2679 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2680 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2681 %}
2682
2683 enc_class push_stack_temp_qword() %{
2684 emit_opcode(cbuf,0x83); // SUB ESP,8
2685 emit_opcode(cbuf,0xEC);
2686 emit_d8 (cbuf,0x08);
2687 %}
2688
2689 enc_class pop_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // ADD ESP,8
2691 emit_opcode(cbuf,0xC4);
2692 emit_d8 (cbuf,0x08);
2693 %}
2694
2695 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2696 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2697 emit_opcode (cbuf, 0x0F );
2698 emit_opcode (cbuf, 0x11 );
2699 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2700
2701 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2702 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2703 %}
2704
2705 // Compute X^Y using Intel's fast hardware instructions, if possible.
2706 // Otherwise return a NaN.
2707 enc_class pow_exp_core_encoding %{
2708 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2710 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2711 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2712 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2713 emit_opcode(cbuf,0x1C);
2714 emit_d8(cbuf,0x24);
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2717 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2718 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2719 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2720 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2721 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2722 emit_d32(cbuf,0xFFFFF800);
2723 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2724 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2725 emit_d32(cbuf,1023);
2726 emit_opcode(cbuf,0x8B); // mov rbx,eax
2727 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2728 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2729 emit_rm(cbuf,0x3,0x4,EAX_enc);
2730 emit_d8(cbuf,20);
2731 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2732 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2733 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2734 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2735 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2736 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2737 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2738 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2739 emit_d32(cbuf,0);
2740 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2741 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2742 %}
2743
2744 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2745 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2746
2747 enc_class Push_Result_Mod_D( regD src) %{
2748 if ($src$$reg != FPR1L_enc) {
2749 // fincstp
2750 emit_opcode (cbuf, 0xD9);
2751 emit_opcode (cbuf, 0xF7);
2752 // FXCH FPR1 with src
2753 emit_opcode(cbuf, 0xD9);
2754 emit_d8(cbuf, 0xC8-1+$src$$reg );
2755 // fdecstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF6);
2758 }
2759 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2760 // // FSTP FPR$dst$$reg
2761 // emit_opcode( cbuf, 0xDD );
2762 // emit_d8( cbuf, 0xD8+$dst$$reg );
2763 %}
2764
2765 enc_class fnstsw_sahf_skip_parity() %{
2766 // fnstsw ax
2767 emit_opcode( cbuf, 0xDF );
2768 emit_opcode( cbuf, 0xE0 );
2769 // sahf
2770 emit_opcode( cbuf, 0x9E );
2771 // jnp ::skip
2772 emit_opcode( cbuf, 0x7B );
2773 emit_opcode( cbuf, 0x05 );
2774 %}
2775
2776 enc_class emitModD() %{
2777 // fprem must be iterative
2778 // :: loop
2779 // fprem
2780 emit_opcode( cbuf, 0xD9 );
2781 emit_opcode( cbuf, 0xF8 );
2782 // wait
2783 emit_opcode( cbuf, 0x9b );
2784 // fnstsw ax
2785 emit_opcode( cbuf, 0xDF );
2786 emit_opcode( cbuf, 0xE0 );
2787 // sahf
2788 emit_opcode( cbuf, 0x9E );
2789 // jp ::loop
2790 emit_opcode( cbuf, 0x0F );
2791 emit_opcode( cbuf, 0x8A );
2792 emit_opcode( cbuf, 0xF4 );
2793 emit_opcode( cbuf, 0xFF );
2794 emit_opcode( cbuf, 0xFF );
2795 emit_opcode( cbuf, 0xFF );
2796 %}
2797
2798 enc_class fpu_flags() %{
2799 // fnstsw_ax
2800 emit_opcode( cbuf, 0xDF);
2801 emit_opcode( cbuf, 0xE0);
2802 // test ax,0x0400
2803 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2804 emit_opcode( cbuf, 0xA9 );
2805 emit_d16 ( cbuf, 0x0400 );
2806 // // // This sequence works, but stalls for 12-16 cycles on PPro
2807 // // test rax,0x0400
2808 // emit_opcode( cbuf, 0xA9 );
2809 // emit_d32 ( cbuf, 0x00000400 );
2810 //
2811 // jz exit (no unordered comparison)
2812 emit_opcode( cbuf, 0x74 );
2813 emit_d8 ( cbuf, 0x02 );
2814 // mov ah,1 - treat as LT case (set carry flag)
2815 emit_opcode( cbuf, 0xB4 );
2816 emit_d8 ( cbuf, 0x01 );
2817 // sahf
2818 emit_opcode( cbuf, 0x9E);
2819 %}
2820
2821 enc_class cmpF_P6_fixup() %{
2822 // Fixup the integer flags in case comparison involved a NaN
2823 //
2824 // JNP exit (no unordered comparison, P-flag is set by NaN)
2825 emit_opcode( cbuf, 0x7B );
2826 emit_d8 ( cbuf, 0x03 );
2827 // MOV AH,1 - treat as LT case (set carry flag)
2828 emit_opcode( cbuf, 0xB4 );
2829 emit_d8 ( cbuf, 0x01 );
2830 // SAHF
2831 emit_opcode( cbuf, 0x9E);
2832 // NOP // target for branch to avoid branch to branch
2833 emit_opcode( cbuf, 0x90);
2834 %}
2835
2836 // fnstsw_ax();
2837 // sahf();
2838 // movl(dst, nan_result);
2839 // jcc(Assembler::parity, exit);
2840 // movl(dst, less_result);
2841 // jcc(Assembler::below, exit);
2842 // movl(dst, equal_result);
2843 // jcc(Assembler::equal, exit);
2844 // movl(dst, greater_result);
2845
2846 // less_result = 1;
2847 // greater_result = -1;
2848 // equal_result = 0;
2849 // nan_result = -1;
2850
2851 enc_class CmpF_Result(eRegI dst) %{
2852 // fnstsw_ax();
2853 emit_opcode( cbuf, 0xDF);
2854 emit_opcode( cbuf, 0xE0);
2855 // sahf
2856 emit_opcode( cbuf, 0x9E);
2857 // movl(dst, nan_result);
2858 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2859 emit_d32( cbuf, -1 );
2860 // jcc(Assembler::parity, exit);
2861 emit_opcode( cbuf, 0x7A );
2862 emit_d8 ( cbuf, 0x13 );
2863 // movl(dst, less_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::below, exit);
2867 emit_opcode( cbuf, 0x72 );
2868 emit_d8 ( cbuf, 0x0C );
2869 // movl(dst, equal_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, 0 );
2872 // jcc(Assembler::equal, exit);
2873 emit_opcode( cbuf, 0x74 );
2874 emit_d8 ( cbuf, 0x05 );
2875 // movl(dst, greater_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 1 );
2878 %}
2879
2880
2881 // XMM version of CmpF_Result. Because the XMM compare
2882 // instructions set the EFLAGS directly. It becomes simpler than
2883 // the float version above.
2884 enc_class CmpX_Result(eRegI dst) %{
2885 MacroAssembler _masm(&cbuf);
2886 Label nan, inc, done;
2887
2888 __ jccb(Assembler::parity, nan);
2889 __ jccb(Assembler::equal, done);
2890 __ jccb(Assembler::above, inc);
2891 __ bind(nan);
2892 __ decrement(as_Register($dst$$reg)); // NO L qqq
2893 __ jmpb(done);
2894 __ bind(inc);
2895 __ increment(as_Register($dst$$reg)); // NO L qqq
2896 __ bind(done);
2897 %}
2898
2899 // Compare the longs and set flags
2900 // BROKEN! Do Not use as-is
2901 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2902 // CMP $src1.hi,$src2.hi
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2905 // JNE,s done
2906 emit_opcode(cbuf,0x75);
2907 emit_d8(cbuf, 2 );
2908 // CMP $src1.lo,$src2.lo
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2911 // done:
2912 %}
2913
2914 enc_class convert_int_long( regL dst, eRegI src ) %{
2915 // mov $dst.lo,$src
2916 int dst_encoding = $dst$$reg;
2917 int src_encoding = $src$$reg;
2918 encode_Copy( cbuf, dst_encoding , src_encoding );
2919 // mov $dst.hi,$src
2920 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2921 // sar $dst.hi,31
2922 emit_opcode( cbuf, 0xC1 );
2923 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2924 emit_d8(cbuf, 0x1F );
2925 %}
2926
2927 enc_class convert_long_double( eRegL src ) %{
2928 // push $src.hi
2929 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2930 // push $src.lo
2931 emit_opcode(cbuf, 0x50+$src$$reg );
2932 // fild 64-bits at [SP]
2933 emit_opcode(cbuf,0xdf);
2934 emit_d8(cbuf, 0x6C);
2935 emit_d8(cbuf, 0x24);
2936 emit_d8(cbuf, 0x00);
2937 // pop stack
2938 emit_opcode(cbuf, 0x83); // add SP, #8
2939 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2940 emit_d8(cbuf, 0x8);
2941 %}
2942
2943 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2944 // IMUL EDX:EAX,$src1
2945 emit_opcode( cbuf, 0xF7 );
2946 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2947 // SAR EDX,$cnt-32
2948 int shift_count = ((int)$cnt$$constant) - 32;
2949 if (shift_count > 0) {
2950 emit_opcode(cbuf, 0xC1);
2951 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2952 emit_d8(cbuf, shift_count);
2953 }
2954 %}
2955
2956 // this version doesn't have add sp, 8
2957 enc_class convert_long_double2( eRegL src ) %{
2958 // push $src.hi
2959 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2960 // push $src.lo
2961 emit_opcode(cbuf, 0x50+$src$$reg );
2962 // fild 64-bits at [SP]
2963 emit_opcode(cbuf,0xdf);
2964 emit_d8(cbuf, 0x6C);
2965 emit_d8(cbuf, 0x24);
2966 emit_d8(cbuf, 0x00);
2967 %}
2968
2969 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2970 // Basic idea: long = (long)int * (long)int
2971 // IMUL EDX:EAX, src
2972 emit_opcode( cbuf, 0xF7 );
2973 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2974 %}
2975
2976 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2977 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2978 // MUL EDX:EAX, src
2979 emit_opcode( cbuf, 0xF7 );
2980 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2981 %}
2982
2983 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2984 // Basic idea: lo(result) = lo(x_lo * y_lo)
2985 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2986 // MOV $tmp,$src.lo
2987 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2988 // IMUL $tmp,EDX
2989 emit_opcode( cbuf, 0x0F );
2990 emit_opcode( cbuf, 0xAF );
2991 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2992 // MOV EDX,$src.hi
2993 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2994 // IMUL EDX,EAX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2998 // ADD $tmp,EDX
2999 emit_opcode( cbuf, 0x03 );
3000 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3001 // MUL EDX:EAX,$src.lo
3002 emit_opcode( cbuf, 0xF7 );
3003 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3004 // ADD EDX,ESI
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3007 %}
3008
3009 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3010 // Basic idea: lo(result) = lo(src * y_lo)
3011 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3012 // IMUL $tmp,EDX,$src
3013 emit_opcode( cbuf, 0x6B );
3014 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3015 emit_d8( cbuf, (int)$src$$constant );
3016 // MOV EDX,$src
3017 emit_opcode(cbuf, 0xB8 + EDX_enc);
3018 emit_d32( cbuf, (int)$src$$constant );
3019 // MUL EDX:EAX,EDX
3020 emit_opcode( cbuf, 0xF7 );
3021 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3022 // ADD EDX,ESI
3023 emit_opcode( cbuf, 0x03 );
3024 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3025 %}
3026
3027 enc_class long_div( eRegL src1, eRegL src2 ) %{
3028 // PUSH src1.hi
3029 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3030 // PUSH src1.lo
3031 emit_opcode(cbuf, 0x50+$src1$$reg );
3032 // PUSH src2.hi
3033 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3034 // PUSH src2.lo
3035 emit_opcode(cbuf, 0x50+$src2$$reg );
3036 // CALL directly to the runtime
3037 cbuf.set_inst_mark();
3038 emit_opcode(cbuf,0xE8); // Call into runtime
3039 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3040 // Restore stack
3041 emit_opcode(cbuf, 0x83); // add SP, #framesize
3042 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3043 emit_d8(cbuf, 4*4);
3044 %}
3045
3046 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3047 // PUSH src1.hi
3048 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3049 // PUSH src1.lo
3050 emit_opcode(cbuf, 0x50+$src1$$reg );
3051 // PUSH src2.hi
3052 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3053 // PUSH src2.lo
3054 emit_opcode(cbuf, 0x50+$src2$$reg );
3055 // CALL directly to the runtime
3056 cbuf.set_inst_mark();
3057 emit_opcode(cbuf,0xE8); // Call into runtime
3058 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3059 // Restore stack
3060 emit_opcode(cbuf, 0x83); // add SP, #framesize
3061 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3062 emit_d8(cbuf, 4*4);
3063 %}
3064
3065 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3066 // MOV $tmp,$src.lo
3067 emit_opcode(cbuf, 0x8B);
3068 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3069 // OR $tmp,$src.hi
3070 emit_opcode(cbuf, 0x0B);
3071 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3072 %}
3073
3074 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3075 // CMP $src1.lo,$src2.lo
3076 emit_opcode( cbuf, 0x3B );
3077 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3078 // JNE,s skip
3079 emit_cc(cbuf, 0x70, 0x5);
3080 emit_d8(cbuf,2);
3081 // CMP $src1.hi,$src2.hi
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3084 %}
3085
3086 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3087 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3090 // MOV $tmp,$src1.hi
3091 emit_opcode( cbuf, 0x8B );
3092 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3093 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3094 emit_opcode( cbuf, 0x1B );
3095 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3096 %}
3097
3098 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3099 // XOR $tmp,$tmp
3100 emit_opcode(cbuf,0x33); // XOR
3101 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3102 // CMP $tmp,$src.lo
3103 emit_opcode( cbuf, 0x3B );
3104 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3105 // SBB $tmp,$src.hi
3106 emit_opcode( cbuf, 0x1B );
3107 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3108 %}
3109
3110 // Sniff, sniff... smells like Gnu Superoptimizer
3111 enc_class neg_long( eRegL dst ) %{
3112 emit_opcode(cbuf,0xF7); // NEG hi
3113 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3114 emit_opcode(cbuf,0xF7); // NEG lo
3115 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3116 emit_opcode(cbuf,0x83); // SBB hi,0
3117 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3118 emit_d8 (cbuf,0 );
3119 %}
3120
3121 enc_class movq_ld(regXD dst, memory mem) %{
3122 MacroAssembler _masm(&cbuf);
3123 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3124 __ movq(as_XMMRegister($dst$$reg), madr);
3125 %}
3126
3127 enc_class movq_st(memory mem, regXD src) %{
3128 MacroAssembler _masm(&cbuf);
3129 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3130 __ movq(madr, as_XMMRegister($src$$reg));
3131 %}
3132
3133 enc_class pshufd_8x8(regX dst, regX src) %{
3134 MacroAssembler _masm(&cbuf);
3135
3136 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3137 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3138 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3139 %}
3140
3141 enc_class pshufd_4x16(regX dst, regX src) %{
3142 MacroAssembler _masm(&cbuf);
3143
3144 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3145 %}
3146
3147 enc_class pshufd(regXD dst, regXD src, int mode) %{
3148 MacroAssembler _masm(&cbuf);
3149
3150 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3151 %}
3152
3153 enc_class pxor(regXD dst, regXD src) %{
3154 MacroAssembler _masm(&cbuf);
3155
3156 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3157 %}
3158
3159 enc_class mov_i2x(regXD dst, eRegI src) %{
3160 MacroAssembler _masm(&cbuf);
3161
3162 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3163 %}
3164
3165
3166 // Because the transitions from emitted code to the runtime
3167 // monitorenter/exit helper stubs are so slow it's critical that
3168 // we inline both the stack-locking fast-path and the inflated fast path.
3169 //
3170 // See also: cmpFastLock and cmpFastUnlock.
3171 //
3172 // What follows is a specialized inline transliteration of the code
3173 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3174 // another option would be to emit TrySlowEnter and TrySlowExit methods
3175 // at startup-time. These methods would accept arguments as
3176 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3177 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3178 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3179 // In practice, however, the # of lock sites is bounded and is usually small.
3180 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3181 // if the processor uses simple bimodal branch predictors keyed by EIP
3182 // Since the helper routines would be called from multiple synchronization
3183 // sites.
3184 //
3185 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3186 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3187 // to those specialized methods. That'd give us a mostly platform-independent
3188 // implementation that the JITs could optimize and inline at their pleasure.
3189 // Done correctly, the only time we'd need to cross to native could would be
3190 // to park() or unpark() threads. We'd also need a few more unsafe operators
3191 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3192 // (b) explicit barriers or fence operations.
3193 //
3194 // TODO:
3195 //
3196 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3197 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3198 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3199 // the lock operators would typically be faster than reifying Self.
3200 //
3201 // * Ideally I'd define the primitives as:
3202 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3203 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3204 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3205 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3206 // Furthermore the register assignments are overconstrained, possibly resulting in
3207 // sub-optimal code near the synchronization site.
3208 //
3209 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3210 // Alternately, use a better sp-proximity test.
3211 //
3212 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3213 // Either one is sufficient to uniquely identify a thread.
3214 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3215 //
3216 // * Intrinsify notify() and notifyAll() for the common cases where the
3217 // object is locked by the calling thread but the waitlist is empty.
3218 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3219 //
3220 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3221 // But beware of excessive branch density on AMD Opterons.
3222 //
3223 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3224 // or failure of the fast-path. If the fast-path fails then we pass
3225 // control to the slow-path, typically in C. In Fast_Lock and
3226 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3227 // will emit a conditional branch immediately after the node.
3228 // So we have branches to branches and lots of ICC.ZF games.
3229 // Instead, it might be better to have C2 pass a "FailureLabel"
3230 // into Fast_Lock and Fast_Unlock. In the case of success, control
3231 // will drop through the node. ICC.ZF is undefined at exit.
3232 // In the case of failure, the node will branch directly to the
3233 // FailureLabel
3234
3235
3236 // obj: object to lock
3237 // box: on-stack box address (displaced header location) - KILLED
3238 // rax,: tmp -- KILLED
3239 // scr: tmp -- KILLED
3240 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3241
3242 Register objReg = as_Register($obj$$reg);
3243 Register boxReg = as_Register($box$$reg);
3244 Register tmpReg = as_Register($tmp$$reg);
3245 Register scrReg = as_Register($scr$$reg);
3246
3247 // Ensure the register assignents are disjoint
3248 guarantee (objReg != boxReg, "") ;
3249 guarantee (objReg != tmpReg, "") ;
3250 guarantee (objReg != scrReg, "") ;
3251 guarantee (boxReg != tmpReg, "") ;
3252 guarantee (boxReg != scrReg, "") ;
3253 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3254
3255 MacroAssembler masm(&cbuf);
3256
3257 if (_counters != NULL) {
3258 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3259 }
3260 if (EmitSync & 1) {
3261 // set box->dhw = unused_mark (3)
3262 // Force all sync thru slow-path: slow_enter() and slow_exit()
3263 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3264 masm.cmpptr (rsp, (int32_t)0) ;
3265 } else
3266 if (EmitSync & 2) {
3267 Label DONE_LABEL ;
3268 if (UseBiasedLocking) {
3269 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3270 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3271 }
3272
3273 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3274 masm.orptr (tmpReg, 0x1);
3275 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3276 if (os::is_MP()) { masm.lock(); }
3277 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3278 masm.jcc(Assembler::equal, DONE_LABEL);
3279 // Recursive locking
3280 masm.subptr(tmpReg, rsp);
3281 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3282 masm.movptr(Address(boxReg, 0), tmpReg);
3283 masm.bind(DONE_LABEL) ;
3284 } else {
3285 // Possible cases that we'll encounter in fast_lock
3286 // ------------------------------------------------
3287 // * Inflated
3288 // -- unlocked
3289 // -- Locked
3290 // = by self
3291 // = by other
3292 // * biased
3293 // -- by Self
3294 // -- by other
3295 // * neutral
3296 // * stack-locked
3297 // -- by self
3298 // = sp-proximity test hits
3299 // = sp-proximity test generates false-negative
3300 // -- by other
3301 //
3302
3303 Label IsInflated, DONE_LABEL, PopDone ;
3304
3305 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3306 // order to reduce the number of conditional branches in the most common cases.
3307 // Beware -- there's a subtle invariant that fetch of the markword
3308 // at [FETCH], below, will never observe a biased encoding (*101b).
3309 // If this invariant is not held we risk exclusion (safety) failure.
3310 if (UseBiasedLocking) {
3311 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3312 }
3313
3314 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3315 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3316 masm.jccb (Assembler::notZero, IsInflated) ;
3317
3318 // Attempt stack-locking ...
3319 masm.orptr (tmpReg, 0x1);
3320 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3321 if (os::is_MP()) { masm.lock(); }
3322 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3323 if (_counters != NULL) {
3324 masm.cond_inc32(Assembler::equal,
3325 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3326 }
3327 masm.jccb (Assembler::equal, DONE_LABEL);
3328
3329 // Recursive locking
3330 masm.subptr(tmpReg, rsp);
3331 masm.andptr(tmpReg, 0xFFFFF003 );
3332 masm.movptr(Address(boxReg, 0), tmpReg);
3333 if (_counters != NULL) {
3334 masm.cond_inc32(Assembler::equal,
3335 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3336 }
3337 masm.jmp (DONE_LABEL) ;
3338
3339 masm.bind (IsInflated) ;
3340
3341 // The object is inflated.
3342 //
3343 // TODO-FIXME: eliminate the ugly use of manifest constants:
3344 // Use markOopDesc::monitor_value instead of "2".
3345 // use markOop::unused_mark() instead of "3".
3346 // The tmpReg value is an objectMonitor reference ORed with
3347 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3348 // objectmonitor pointer by masking off the "2" bit or we can just
3349 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3350 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3351 //
3352 // I use the latter as it avoids AGI stalls.
3353 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3354 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3355 //
3356 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3357
3358 // boxReg refers to the on-stack BasicLock in the current frame.
3359 // We'd like to write:
3360 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3361 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3362 // additional latency as we have another ST in the store buffer that must drain.
3363
3364 if (EmitSync & 8192) {
3365 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3366 masm.get_thread (scrReg) ;
3367 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3368 masm.movptr(tmpReg, 0); // consider: xor vs mov
3369 if (os::is_MP()) { masm.lock(); }
3370 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3371 } else
3372 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3373 masm.movptr(scrReg, boxReg) ;
3374 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3375
3376 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3377 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3378 // prefetchw [eax + Offset(_owner)-2]
3379 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3380 }
3381
3382 if ((EmitSync & 64) == 0) {
3383 // Optimistic form: consider XORL tmpReg,tmpReg
3384 masm.movptr(tmpReg, 0 ) ;
3385 } else {
3386 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3387 // Test-And-CAS instead of CAS
3388 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3389 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3390 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3391 }
3392
3393 // Appears unlocked - try to swing _owner from null to non-null.
3394 // Ideally, I'd manifest "Self" with get_thread and then attempt
3395 // to CAS the register containing Self into m->Owner.
3396 // But we don't have enough registers, so instead we can either try to CAS
3397 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3398 // we later store "Self" into m->Owner. Transiently storing a stack address
3399 // (rsp or the address of the box) into m->owner is harmless.
3400 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3401 if (os::is_MP()) { masm.lock(); }
3402 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3403 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3404 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3405 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3406 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3407 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3408
3409 // If the CAS fails we can either retry or pass control to the slow-path.
3410 // We use the latter tactic.
3411 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3412 // If the CAS was successful ...
3413 // Self has acquired the lock
3414 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3415 // Intentional fall-through into DONE_LABEL ...
3416 } else {
3417 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3418 masm.movptr(boxReg, tmpReg) ;
3419
3420 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3421 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3422 // prefetchw [eax + Offset(_owner)-2]
3423 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3424 }
3425
3426 if ((EmitSync & 64) == 0) {
3427 // Optimistic form
3428 masm.xorptr (tmpReg, tmpReg) ;
3429 } else {
3430 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3431 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3432 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3433 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3434 }
3435
3436 // Appears unlocked - try to swing _owner from null to non-null.
3437 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3438 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3439 masm.get_thread (scrReg) ;
3440 if (os::is_MP()) { masm.lock(); }
3441 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3442
3443 // If the CAS fails we can either retry or pass control to the slow-path.
3444 // We use the latter tactic.
3445 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3446 // If the CAS was successful ...
3447 // Self has acquired the lock
3448 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3449 // Intentional fall-through into DONE_LABEL ...
3450 }
3451
3452 // DONE_LABEL is a hot target - we'd really like to place it at the
3453 // start of cache line by padding with NOPs.
3454 // See the AMD and Intel software optimization manuals for the
3455 // most efficient "long" NOP encodings.
3456 // Unfortunately none of our alignment mechanisms suffice.
3457 masm.bind(DONE_LABEL);
3458
3459 // Avoid branch-to-branch on AMD processors
3460 // This appears to be superstition.
3461 if (EmitSync & 32) masm.nop() ;
3462
3463
3464 // At DONE_LABEL the icc ZFlag is set as follows ...
3465 // Fast_Unlock uses the same protocol.
3466 // ZFlag == 1 -> Success
3467 // ZFlag == 0 -> Failure - force control through the slow-path
3468 }
3469 %}
3470
3471 // obj: object to unlock
3472 // box: box address (displaced header location), killed. Must be EAX.
3473 // rbx,: killed tmp; cannot be obj nor box.
3474 //
3475 // Some commentary on balanced locking:
3476 //
3477 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3478 // Methods that don't have provably balanced locking are forced to run in the
3479 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3480 // The interpreter provides two properties:
3481 // I1: At return-time the interpreter automatically and quietly unlocks any
3482 // objects acquired the current activation (frame). Recall that the
3483 // interpreter maintains an on-stack list of locks currently held by
3484 // a frame.
3485 // I2: If a method attempts to unlock an object that is not held by the
3486 // the frame the interpreter throws IMSX.
3487 //
3488 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3489 // B() doesn't have provably balanced locking so it runs in the interpreter.
3490 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3491 // is still locked by A().
3492 //
3493 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3494 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3495 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3496 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3497
3498 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3499
3500 Register objReg = as_Register($obj$$reg);
3501 Register boxReg = as_Register($box$$reg);
3502 Register tmpReg = as_Register($tmp$$reg);
3503
3504 guarantee (objReg != boxReg, "") ;
3505 guarantee (objReg != tmpReg, "") ;
3506 guarantee (boxReg != tmpReg, "") ;
3507 guarantee (boxReg == as_Register(EAX_enc), "") ;
3508 MacroAssembler masm(&cbuf);
3509
3510 if (EmitSync & 4) {
3511 // Disable - inhibit all inlining. Force control through the slow-path
3512 masm.cmpptr (rsp, 0) ;
3513 } else
3514 if (EmitSync & 8) {
3515 Label DONE_LABEL ;
3516 if (UseBiasedLocking) {
3517 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3518 }
3519 // classic stack-locking code ...
3520 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3521 masm.testptr(tmpReg, tmpReg) ;
3522 masm.jcc (Assembler::zero, DONE_LABEL) ;
3523 if (os::is_MP()) { masm.lock(); }
3524 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3525 masm.bind(DONE_LABEL);
3526 } else {
3527 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3528
3529 // Critically, the biased locking test must have precedence over
3530 // and appear before the (box->dhw == 0) recursive stack-lock test.
3531 if (UseBiasedLocking) {
3532 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3533 }
3534
3535 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3536 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3537 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3538
3539 masm.testptr(tmpReg, 0x02) ; // Inflated?
3540 masm.jccb (Assembler::zero, Stacked) ;
3541
3542 masm.bind (Inflated) ;
3543 // It's inflated.
3544 // Despite our balanced locking property we still check that m->_owner == Self
3545 // as java routines or native JNI code called by this thread might
3546 // have released the lock.
3547 // Refer to the comments in synchronizer.cpp for how we might encode extra
3548 // state in _succ so we can avoid fetching EntryList|cxq.
3549 //
3550 // I'd like to add more cases in fast_lock() and fast_unlock() --
3551 // such as recursive enter and exit -- but we have to be wary of
3552 // I$ bloat, T$ effects and BP$ effects.
3553 //
3554 // If there's no contention try a 1-0 exit. That is, exit without
3555 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3556 // we detect and recover from the race that the 1-0 exit admits.
3557 //
3558 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3559 // before it STs null into _owner, releasing the lock. Updates
3560 // to data protected by the critical section must be visible before
3561 // we drop the lock (and thus before any other thread could acquire
3562 // the lock and observe the fields protected by the lock).
3563 // IA32's memory-model is SPO, so STs are ordered with respect to
3564 // each other and there's no need for an explicit barrier (fence).
3565 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3566
3567 masm.get_thread (boxReg) ;
3568 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3569 // prefetchw [ebx + Offset(_owner)-2]
3570 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3571 }
3572
3573 // Note that we could employ various encoding schemes to reduce
3574 // the number of loads below (currently 4) to just 2 or 3.
3575 // Refer to the comments in synchronizer.cpp.
3576 // In practice the chain of fetches doesn't seem to impact performance, however.
3577 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3578 // Attempt to reduce branch density - AMD's branch predictor.
3579 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3580 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3581 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3582 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3583 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3584 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3585 masm.jmpb (DONE_LABEL) ;
3586 } else {
3587 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3589 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3590 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3591 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3592 masm.jccb (Assembler::notZero, CheckSucc) ;
3593 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3594 masm.jmpb (DONE_LABEL) ;
3595 }
3596
3597 // The Following code fragment (EmitSync & 65536) improves the performance of
3598 // contended applications and contended synchronization microbenchmarks.
3599 // Unfortunately the emission of the code - even though not executed - causes regressions
3600 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3601 // with an equal number of never-executed NOPs results in the same regression.
3602 // We leave it off by default.
3603
3604 if ((EmitSync & 65536) != 0) {
3605 Label LSuccess, LGoSlowPath ;
3606
3607 masm.bind (CheckSucc) ;
3608
3609 // Optional pre-test ... it's safe to elide this
3610 if ((EmitSync & 16) == 0) {
3611 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3612 masm.jccb (Assembler::zero, LGoSlowPath) ;
3613 }
3614
3615 // We have a classic Dekker-style idiom:
3616 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3617 // There are a number of ways to implement the barrier:
3618 // (1) lock:andl &m->_owner, 0
3619 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3620 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3621 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3622 // (2) If supported, an explicit MFENCE is appealing.
3623 // In older IA32 processors MFENCE is slower than lock:add or xchg
3624 // particularly if the write-buffer is full as might be the case if
3625 // if stores closely precede the fence or fence-equivalent instruction.
3626 // In more modern implementations MFENCE appears faster, however.
3627 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3628 // The $lines underlying the top-of-stack should be in M-state.
3629 // The locked add instruction is serializing, of course.
3630 // (4) Use xchg, which is serializing
3631 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3632 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3633 // The integer condition codes will tell us if succ was 0.
3634 // Since _succ and _owner should reside in the same $line and
3635 // we just stored into _owner, it's likely that the $line
3636 // remains in M-state for the lock:orl.
3637 //
3638 // We currently use (3), although it's likely that switching to (2)
3639 // is correct for the future.
3640
3641 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3642 if (os::is_MP()) {
3643 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3644 masm.mfence();
3645 } else {
3646 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3647 }
3648 }
3649 // Ratify _succ remains non-null
3650 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3651 masm.jccb (Assembler::notZero, LSuccess) ;
3652
3653 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3654 if (os::is_MP()) { masm.lock(); }
3655 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3656 masm.jccb (Assembler::notEqual, LSuccess) ;
3657 // Since we're low on registers we installed rsp as a placeholding in _owner.
3658 // Now install Self over rsp. This is safe as we're transitioning from
3659 // non-null to non=null
3660 masm.get_thread (boxReg) ;
3661 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3662 // Intentional fall-through into LGoSlowPath ...
3663
3664 masm.bind (LGoSlowPath) ;
3665 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3666 masm.jmpb (DONE_LABEL) ;
3667
3668 masm.bind (LSuccess) ;
3669 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3670 masm.jmpb (DONE_LABEL) ;
3671 }
3672
3673 masm.bind (Stacked) ;
3674 // It's not inflated and it's not recursively stack-locked and it's not biased.
3675 // It must be stack-locked.
3676 // Try to reset the header to displaced header.
3677 // The "box" value on the stack is stable, so we can reload
3678 // and be assured we observe the same value as above.
3679 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3680 if (os::is_MP()) { masm.lock(); }
3681 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3682 // Intention fall-thru into DONE_LABEL
3683
3684
3685 // DONE_LABEL is a hot target - we'd really like to place it at the
3686 // start of cache line by padding with NOPs.
3687 // See the AMD and Intel software optimization manuals for the
3688 // most efficient "long" NOP encodings.
3689 // Unfortunately none of our alignment mechanisms suffice.
3690 if ((EmitSync & 65536) == 0) {
3691 masm.bind (CheckSucc) ;
3692 }
3693 masm.bind(DONE_LABEL);
3694
3695 // Avoid branch to branch on AMD processors
3696 if (EmitSync & 32768) { masm.nop() ; }
3697 }
3698 %}
3699
3700 enc_class enc_String_Compare() %{
3701 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3702 POP_LABEL, DONE_LABEL, CONT_LABEL,
3703 WHILE_HEAD_LABEL;
3704 MacroAssembler masm(&cbuf);
3705
3706 // Get the first character position in both strings
3707 // [8] char array, [12] offset, [16] count
3708 int value_offset = java_lang_String::value_offset_in_bytes();
3709 int offset_offset = java_lang_String::offset_offset_in_bytes();
3710 int count_offset = java_lang_String::count_offset_in_bytes();
3711 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3712
3713 masm.movptr(rax, Address(rsi, value_offset));
3714 masm.movl(rcx, Address(rsi, offset_offset));
3715 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3716 masm.movptr(rbx, Address(rdi, value_offset));
3717 masm.movl(rcx, Address(rdi, offset_offset));
3718 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3719
3720 // Compute the minimum of the string lengths(rsi) and the
3721 // difference of the string lengths (stack)
3722
3723
3724 if (VM_Version::supports_cmov()) {
3725 masm.movl(rdi, Address(rdi, count_offset));
3726 masm.movl(rsi, Address(rsi, count_offset));
3727 masm.movl(rcx, rdi);
3728 masm.subl(rdi, rsi);
3729 masm.push(rdi);
3730 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3731 } else {
3732 masm.movl(rdi, Address(rdi, count_offset));
3733 masm.movl(rcx, Address(rsi, count_offset));
3734 masm.movl(rsi, rdi);
3735 masm.subl(rdi, rcx);
3736 masm.push(rdi);
3737 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL);
3738 masm.movl(rsi, rcx);
3739 // rsi holds min, rcx is unused
3740 }
3741
3742 // Is the minimum length zero?
3743 masm.bind(ECX_GOOD_LABEL);
3744 masm.testl(rsi, rsi);
3745 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3746
3747 // Load first characters
3748 masm.load_unsigned_word(rcx, Address(rbx, 0));
3749 masm.load_unsigned_word(rdi, Address(rax, 0));
3750
3751 // Compare first characters
3752 masm.subl(rcx, rdi);
3753 masm.jcc(Assembler::notZero, POP_LABEL);
3754 masm.decrementl(rsi);
3755 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3756
3757 {
3758 // Check after comparing first character to see if strings are equivalent
3759 Label LSkip2;
3760 // Check if the strings start at same location
3761 masm.cmpptr(rbx,rax);
3762 masm.jcc(Assembler::notEqual, LSkip2);
3763
3764 // Check if the length difference is zero (from stack)
3765 masm.cmpl(Address(rsp, 0), 0x0);
3766 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3767
3768 // Strings might not be equivalent
3769 masm.bind(LSkip2);
3770 }
3771
3772 // Shift rax, and rbx, to the end of the arrays, negate min
3773 masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
3774 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
3775 masm.negl(rsi);
3776
3777 // Compare the rest of the characters
3778 masm.bind(WHILE_HEAD_LABEL);
3779 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3780 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3781 masm.subl(rcx, rdi);
3782 masm.jcc(Assembler::notZero, POP_LABEL);
3783 masm.incrementl(rsi);
3784 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3785
3786 // Strings are equal up to min length. Return the length difference.
3787 masm.bind(LENGTH_DIFF_LABEL);
3788 masm.pop(rcx);
3789 masm.jmp(DONE_LABEL);
3790
3791 // Discard the stored length difference
3792 masm.bind(POP_LABEL);
3793 masm.addptr(rsp, 4);
3794
3795 // That's it
3796 masm.bind(DONE_LABEL);
3797 %}
3798
3799 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{
3800 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
3801 MacroAssembler masm(&cbuf);
3802
3803 Register ary1Reg = as_Register($ary1$$reg);
3804 Register ary2Reg = as_Register($ary2$$reg);
3805 Register tmp1Reg = as_Register($tmp1$$reg);
3806 Register tmp2Reg = as_Register($tmp2$$reg);
3807 Register resultReg = as_Register($result$$reg);
3808
3809 int length_offset = arrayOopDesc::length_offset_in_bytes();
3810 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3811
3812 // Check the input args
3813 masm.cmpl(ary1Reg, ary2Reg);
3814 masm.jcc(Assembler::equal, TRUE_LABEL);
3815 masm.testl(ary1Reg, ary1Reg);
3816 masm.jcc(Assembler::zero, FALSE_LABEL);
3817 masm.testl(ary2Reg, ary2Reg);
3818 masm.jcc(Assembler::zero, FALSE_LABEL);
3819
3820 // Check the lengths
3821 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
3822 masm.movl(resultReg, Address(ary2Reg, length_offset));
3823 masm.cmpl(tmp2Reg, resultReg);
3824 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3825 masm.testl(resultReg, resultReg);
3826 masm.jcc(Assembler::zero, TRUE_LABEL);
3827
3828 // Get the number of 4 byte vectors to compare
3829 masm.shrl(resultReg, 1);
3830
3831 // Check for odd-length arrays
3832 masm.andl(tmp2Reg, 1);
3833 masm.testl(tmp2Reg, tmp2Reg);
3834 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
3835
3836 // Compare 2-byte "tail" at end of arrays
3837 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3838 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3839 masm.cmpl(tmp1Reg, tmp2Reg);
3840 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3841 masm.testl(resultReg, resultReg);
3842 masm.jcc(Assembler::zero, TRUE_LABEL);
3843
3844 // Setup compare loop
3845 masm.bind(COMPARE_LOOP_HDR);
3846 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
3847 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3848 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3849 masm.negl(resultReg);
3850
3851 // 4-byte-wide compare loop
3852 masm.bind(COMPARE_LOOP);
3853 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
3854 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
3855 masm.cmpl(ary1Reg, ary2Reg);
3856 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3857 masm.increment(resultReg);
3858 masm.jcc(Assembler::notZero, COMPARE_LOOP);
3859
3860 masm.bind(TRUE_LABEL);
3861 masm.movl(resultReg, 1); // return true
3862 masm.jmp(DONE_LABEL);
3863
3864 masm.bind(FALSE_LABEL);
3865 masm.xorl(resultReg, resultReg); // return false
3866
3867 // That's it
3868 masm.bind(DONE_LABEL);
3869 %}
3870
3871 enc_class enc_pop_rdx() %{
3872 emit_opcode(cbuf,0x5A);
3873 %}
3874
3875 enc_class enc_rethrow() %{
3876 cbuf.set_inst_mark();
3877 emit_opcode(cbuf, 0xE9); // jmp entry
3878 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3879 runtime_call_Relocation::spec(), RELOC_IMM32 );
3880 %}
3881
3882
3883 // Convert a double to an int. Java semantics require we do complex
3884 // manglelations in the corner cases. So we set the rounding mode to
3885 // 'zero', store the darned double down as an int, and reset the
3886 // rounding mode to 'nearest'. The hardware throws an exception which
3887 // patches up the correct value directly to the stack.
3888 enc_class D2I_encoding( regD src ) %{
3889 // Flip to round-to-zero mode. We attempted to allow invalid-op
3890 // exceptions here, so that a NAN or other corner-case value will
3891 // thrown an exception (but normal values get converted at full speed).
3892 // However, I2C adapters and other float-stack manglers leave pending
3893 // invalid-op exceptions hanging. We would have to clear them before
3894 // enabling them and that is more expensive than just testing for the
3895 // invalid value Intel stores down in the corner cases.
3896 emit_opcode(cbuf,0xD9); // FLDCW trunc
3897 emit_opcode(cbuf,0x2D);
3898 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3899 // Allocate a word
3900 emit_opcode(cbuf,0x83); // SUB ESP,4
3901 emit_opcode(cbuf,0xEC);
3902 emit_d8(cbuf,0x04);
3903 // Encoding assumes a double has been pushed into FPR0.
3904 // Store down the double as an int, popping the FPU stack
3905 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3906 emit_opcode(cbuf,0x1C);
3907 emit_d8(cbuf,0x24);
3908 // Restore the rounding mode; mask the exception
3909 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3910 emit_opcode(cbuf,0x2D);
3911 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3912 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3913 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3914
3915 // Load the converted int; adjust CPU stack
3916 emit_opcode(cbuf,0x58); // POP EAX
3917 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3918 emit_d32 (cbuf,0x80000000); // 0x80000000
3919 emit_opcode(cbuf,0x75); // JNE around_slow_call
3920 emit_d8 (cbuf,0x07); // Size of slow_call
3921 // Push src onto stack slow-path
3922 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3923 emit_d8 (cbuf,0xC0-1+$src$$reg );
3924 // CALL directly to the runtime
3925 cbuf.set_inst_mark();
3926 emit_opcode(cbuf,0xE8); // Call into runtime
3927 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3928 // Carry on here...
3929 %}
3930
3931 enc_class D2L_encoding( regD src ) %{
3932 emit_opcode(cbuf,0xD9); // FLDCW trunc
3933 emit_opcode(cbuf,0x2D);
3934 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3935 // Allocate a word
3936 emit_opcode(cbuf,0x83); // SUB ESP,8
3937 emit_opcode(cbuf,0xEC);
3938 emit_d8(cbuf,0x08);
3939 // Encoding assumes a double has been pushed into FPR0.
3940 // Store down the double as a long, popping the FPU stack
3941 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3942 emit_opcode(cbuf,0x3C);
3943 emit_d8(cbuf,0x24);
3944 // Restore the rounding mode; mask the exception
3945 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3946 emit_opcode(cbuf,0x2D);
3947 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3948 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3949 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3950
3951 // Load the converted int; adjust CPU stack
3952 emit_opcode(cbuf,0x58); // POP EAX
3953 emit_opcode(cbuf,0x5A); // POP EDX
3954 emit_opcode(cbuf,0x81); // CMP EDX,imm
3955 emit_d8 (cbuf,0xFA); // rdx
3956 emit_d32 (cbuf,0x80000000); // 0x80000000
3957 emit_opcode(cbuf,0x75); // JNE around_slow_call
3958 emit_d8 (cbuf,0x07+4); // Size of slow_call
3959 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3960 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3961 emit_opcode(cbuf,0x75); // JNE around_slow_call
3962 emit_d8 (cbuf,0x07); // Size of slow_call
3963 // Push src onto stack slow-path
3964 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3965 emit_d8 (cbuf,0xC0-1+$src$$reg );
3966 // CALL directly to the runtime
3967 cbuf.set_inst_mark();
3968 emit_opcode(cbuf,0xE8); // Call into runtime
3969 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3970 // Carry on here...
3971 %}
3972
3973 enc_class X2L_encoding( regX src ) %{
3974 // Allocate a word
3975 emit_opcode(cbuf,0x83); // SUB ESP,8
3976 emit_opcode(cbuf,0xEC);
3977 emit_d8(cbuf,0x08);
3978
3979 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3980 emit_opcode (cbuf, 0x0F );
3981 emit_opcode (cbuf, 0x11 );
3982 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3983
3984 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3985 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3986
3987 emit_opcode(cbuf,0xD9); // FLDCW trunc
3988 emit_opcode(cbuf,0x2D);
3989 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3990
3991 // Encoding assumes a double has been pushed into FPR0.
3992 // Store down the double as a long, popping the FPU stack
3993 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3994 emit_opcode(cbuf,0x3C);
3995 emit_d8(cbuf,0x24);
3996
3997 // Restore the rounding mode; mask the exception
3998 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3999 emit_opcode(cbuf,0x2D);
4000 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4001 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4002 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4003
4004 // Load the converted int; adjust CPU stack
4005 emit_opcode(cbuf,0x58); // POP EAX
4006
4007 emit_opcode(cbuf,0x5A); // POP EDX
4008
4009 emit_opcode(cbuf,0x81); // CMP EDX,imm
4010 emit_d8 (cbuf,0xFA); // rdx
4011 emit_d32 (cbuf,0x80000000);// 0x80000000
4012
4013 emit_opcode(cbuf,0x75); // JNE around_slow_call
4014 emit_d8 (cbuf,0x13+4); // Size of slow_call
4015
4016 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4017 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4018
4019 emit_opcode(cbuf,0x75); // JNE around_slow_call
4020 emit_d8 (cbuf,0x13); // Size of slow_call
4021
4022 // Allocate a word
4023 emit_opcode(cbuf,0x83); // SUB ESP,4
4024 emit_opcode(cbuf,0xEC);
4025 emit_d8(cbuf,0x04);
4026
4027 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4028 emit_opcode (cbuf, 0x0F );
4029 emit_opcode (cbuf, 0x11 );
4030 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4031
4032 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4033 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4034
4035 emit_opcode(cbuf,0x83); // ADD ESP,4
4036 emit_opcode(cbuf,0xC4);
4037 emit_d8(cbuf,0x04);
4038
4039 // CALL directly to the runtime
4040 cbuf.set_inst_mark();
4041 emit_opcode(cbuf,0xE8); // Call into runtime
4042 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4043 // Carry on here...
4044 %}
4045
4046 enc_class XD2L_encoding( regXD src ) %{
4047 // Allocate a word
4048 emit_opcode(cbuf,0x83); // SUB ESP,8
4049 emit_opcode(cbuf,0xEC);
4050 emit_d8(cbuf,0x08);
4051
4052 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4053 emit_opcode (cbuf, 0x0F );
4054 emit_opcode (cbuf, 0x11 );
4055 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4056
4057 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4058 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4059
4060 emit_opcode(cbuf,0xD9); // FLDCW trunc
4061 emit_opcode(cbuf,0x2D);
4062 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4063
4064 // Encoding assumes a double has been pushed into FPR0.
4065 // Store down the double as a long, popping the FPU stack
4066 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4067 emit_opcode(cbuf,0x3C);
4068 emit_d8(cbuf,0x24);
4069
4070 // Restore the rounding mode; mask the exception
4071 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4072 emit_opcode(cbuf,0x2D);
4073 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4074 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4075 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4076
4077 // Load the converted int; adjust CPU stack
4078 emit_opcode(cbuf,0x58); // POP EAX
4079
4080 emit_opcode(cbuf,0x5A); // POP EDX
4081
4082 emit_opcode(cbuf,0x81); // CMP EDX,imm
4083 emit_d8 (cbuf,0xFA); // rdx
4084 emit_d32 (cbuf,0x80000000); // 0x80000000
4085
4086 emit_opcode(cbuf,0x75); // JNE around_slow_call
4087 emit_d8 (cbuf,0x13+4); // Size of slow_call
4088
4089 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4090 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4091
4092 emit_opcode(cbuf,0x75); // JNE around_slow_call
4093 emit_d8 (cbuf,0x13); // Size of slow_call
4094
4095 // Push src onto stack slow-path
4096 // Allocate a word
4097 emit_opcode(cbuf,0x83); // SUB ESP,8
4098 emit_opcode(cbuf,0xEC);
4099 emit_d8(cbuf,0x08);
4100
4101 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4102 emit_opcode (cbuf, 0x0F );
4103 emit_opcode (cbuf, 0x11 );
4104 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4105
4106 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4107 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4108
4109 emit_opcode(cbuf,0x83); // ADD ESP,8
4110 emit_opcode(cbuf,0xC4);
4111 emit_d8(cbuf,0x08);
4112
4113 // CALL directly to the runtime
4114 cbuf.set_inst_mark();
4115 emit_opcode(cbuf,0xE8); // Call into runtime
4116 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4117 // Carry on here...
4118 %}
4119
4120 enc_class D2X_encoding( regX dst, regD src ) %{
4121 // Allocate a word
4122 emit_opcode(cbuf,0x83); // SUB ESP,4
4123 emit_opcode(cbuf,0xEC);
4124 emit_d8(cbuf,0x04);
4125 int pop = 0x02;
4126 if ($src$$reg != FPR1L_enc) {
4127 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4128 emit_d8( cbuf, 0xC0-1+$src$$reg );
4129 pop = 0x03;
4130 }
4131 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4132
4133 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4134 emit_opcode (cbuf, 0x0F );
4135 emit_opcode (cbuf, 0x10 );
4136 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4137
4138 emit_opcode(cbuf,0x83); // ADD ESP,4
4139 emit_opcode(cbuf,0xC4);
4140 emit_d8(cbuf,0x04);
4141 // Carry on here...
4142 %}
4143
4144 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4145 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4146
4147 // Compare the result to see if we need to go to the slow path
4148 emit_opcode(cbuf,0x81); // CMP dst,imm
4149 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4150 emit_d32 (cbuf,0x80000000); // 0x80000000
4151
4152 emit_opcode(cbuf,0x75); // JNE around_slow_call
4153 emit_d8 (cbuf,0x13); // Size of slow_call
4154 // Store xmm to a temp memory
4155 // location and push it onto stack.
4156
4157 emit_opcode(cbuf,0x83); // SUB ESP,4
4158 emit_opcode(cbuf,0xEC);
4159 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4160
4161 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4162 emit_opcode (cbuf, 0x0F );
4163 emit_opcode (cbuf, 0x11 );
4164 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4165
4166 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4167 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4168
4169 emit_opcode(cbuf,0x83); // ADD ESP,4
4170 emit_opcode(cbuf,0xC4);
4171 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4172
4173 // CALL directly to the runtime
4174 cbuf.set_inst_mark();
4175 emit_opcode(cbuf,0xE8); // Call into runtime
4176 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4177
4178 // Carry on here...
4179 %}
4180
4181 enc_class X2D_encoding( regD dst, regX src ) %{
4182 // Allocate a word
4183 emit_opcode(cbuf,0x83); // SUB ESP,4
4184 emit_opcode(cbuf,0xEC);
4185 emit_d8(cbuf,0x04);
4186
4187 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4188 emit_opcode (cbuf, 0x0F );
4189 emit_opcode (cbuf, 0x11 );
4190 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4191
4192 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4193 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4194
4195 emit_opcode(cbuf,0x83); // ADD ESP,4
4196 emit_opcode(cbuf,0xC4);
4197 emit_d8(cbuf,0x04);
4198
4199 // Carry on here...
4200 %}
4201
4202 enc_class AbsXF_encoding(regX dst) %{
4203 address signmask_address=(address)float_signmask_pool;
4204 // andpd:\tANDPS $dst,[signconst]
4205 emit_opcode(cbuf, 0x0F);
4206 emit_opcode(cbuf, 0x54);
4207 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4208 emit_d32(cbuf, (int)signmask_address);
4209 %}
4210
4211 enc_class AbsXD_encoding(regXD dst) %{
4212 address signmask_address=(address)double_signmask_pool;
4213 // andpd:\tANDPD $dst,[signconst]
4214 emit_opcode(cbuf, 0x66);
4215 emit_opcode(cbuf, 0x0F);
4216 emit_opcode(cbuf, 0x54);
4217 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4218 emit_d32(cbuf, (int)signmask_address);
4219 %}
4220
4221 enc_class NegXF_encoding(regX dst) %{
4222 address signmask_address=(address)float_signflip_pool;
4223 // andpd:\tXORPS $dst,[signconst]
4224 emit_opcode(cbuf, 0x0F);
4225 emit_opcode(cbuf, 0x57);
4226 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4227 emit_d32(cbuf, (int)signmask_address);
4228 %}
4229
4230 enc_class NegXD_encoding(regXD dst) %{
4231 address signmask_address=(address)double_signflip_pool;
4232 // andpd:\tXORPD $dst,[signconst]
4233 emit_opcode(cbuf, 0x66);
4234 emit_opcode(cbuf, 0x0F);
4235 emit_opcode(cbuf, 0x57);
4236 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4237 emit_d32(cbuf, (int)signmask_address);
4238 %}
4239
4240 enc_class FMul_ST_reg( eRegF src1 ) %{
4241 // Operand was loaded from memory into fp ST (stack top)
4242 // FMUL ST,$src /* D8 C8+i */
4243 emit_opcode(cbuf, 0xD8);
4244 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4245 %}
4246
4247 enc_class FAdd_ST_reg( eRegF src2 ) %{
4248 // FADDP ST,src2 /* D8 C0+i */
4249 emit_opcode(cbuf, 0xD8);
4250 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4251 //could use FADDP src2,fpST /* DE C0+i */
4252 %}
4253
4254 enc_class FAddP_reg_ST( eRegF src2 ) %{
4255 // FADDP src2,ST /* DE C0+i */
4256 emit_opcode(cbuf, 0xDE);
4257 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4258 %}
4259
4260 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4261 // Operand has been loaded into fp ST (stack top)
4262 // FSUB ST,$src1
4263 emit_opcode(cbuf, 0xD8);
4264 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4265
4266 // FDIV
4267 emit_opcode(cbuf, 0xD8);
4268 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4269 %}
4270
4271 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4272 // Operand was loaded from memory into fp ST (stack top)
4273 // FADD ST,$src /* D8 C0+i */
4274 emit_opcode(cbuf, 0xD8);
4275 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4276
4277 // FMUL ST,src2 /* D8 C*+i */
4278 emit_opcode(cbuf, 0xD8);
4279 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4280 %}
4281
4282
4283 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4284 // Operand was loaded from memory into fp ST (stack top)
4285 // FADD ST,$src /* D8 C0+i */
4286 emit_opcode(cbuf, 0xD8);
4287 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4288
4289 // FMULP src2,ST /* DE C8+i */
4290 emit_opcode(cbuf, 0xDE);
4291 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4292 %}
4293
4294 enc_class enc_membar_acquire %{
4295 // Doug Lea believes this is not needed with current Sparcs and TSO.
4296 // MacroAssembler masm(&cbuf);
4297 // masm.membar();
4298 %}
4299
4300 enc_class enc_membar_release %{
4301 // Doug Lea believes this is not needed with current Sparcs and TSO.
4302 // MacroAssembler masm(&cbuf);
4303 // masm.membar();
4304 %}
4305
4306 enc_class enc_membar_volatile %{
4307 MacroAssembler masm(&cbuf);
4308 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4309 Assembler::StoreStore));
4310 %}
4311
4312 // Atomically load the volatile long
4313 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4314 emit_opcode(cbuf,0xDF);
4315 int rm_byte_opcode = 0x05;
4316 int base = $mem$$base;
4317 int index = $mem$$index;
4318 int scale = $mem$$scale;
4319 int displace = $mem$$disp;
4320 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4321 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4322 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4323 %}
4324
4325 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4326 { // Atomic long load
4327 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4328 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4329 emit_opcode(cbuf,0x0F);
4330 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4331 int base = $mem$$base;
4332 int index = $mem$$index;
4333 int scale = $mem$$scale;
4334 int displace = $mem$$disp;
4335 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4336 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4337 }
4338 { // MOVSD $dst,$tmp ! atomic long store
4339 emit_opcode(cbuf,0xF2);
4340 emit_opcode(cbuf,0x0F);
4341 emit_opcode(cbuf,0x11);
4342 int base = $dst$$base;
4343 int index = $dst$$index;
4344 int scale = $dst$$scale;
4345 int displace = $dst$$disp;
4346 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4347 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4348 }
4349 %}
4350
4351 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4352 { // Atomic long load
4353 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4354 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4355 emit_opcode(cbuf,0x0F);
4356 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4357 int base = $mem$$base;
4358 int index = $mem$$index;
4359 int scale = $mem$$scale;
4360 int displace = $mem$$disp;
4361 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4362 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4363 }
4364 { // MOVD $dst.lo,$tmp
4365 emit_opcode(cbuf,0x66);
4366 emit_opcode(cbuf,0x0F);
4367 emit_opcode(cbuf,0x7E);
4368 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4369 }
4370 { // PSRLQ $tmp,32
4371 emit_opcode(cbuf,0x66);
4372 emit_opcode(cbuf,0x0F);
4373 emit_opcode(cbuf,0x73);
4374 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4375 emit_d8(cbuf, 0x20);
4376 }
4377 { // MOVD $dst.hi,$tmp
4378 emit_opcode(cbuf,0x66);
4379 emit_opcode(cbuf,0x0F);
4380 emit_opcode(cbuf,0x7E);
4381 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4382 }
4383 %}
4384
4385 // Volatile Store Long. Must be atomic, so move it into
4386 // the FP TOS and then do a 64-bit FIST. Has to probe the
4387 // target address before the store (for null-ptr checks)
4388 // so the memory operand is used twice in the encoding.
4389 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4390 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4391 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4392 emit_opcode(cbuf,0xDF);
4393 int rm_byte_opcode = 0x07;
4394 int base = $mem$$base;
4395 int index = $mem$$index;
4396 int scale = $mem$$scale;
4397 int displace = $mem$$disp;
4398 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4399 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4400 %}
4401
4402 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4403 { // Atomic long load
4404 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4405 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4406 emit_opcode(cbuf,0x0F);
4407 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4408 int base = $src$$base;
4409 int index = $src$$index;
4410 int scale = $src$$scale;
4411 int displace = $src$$disp;
4412 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4413 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4414 }
4415 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4416 { // MOVSD $mem,$tmp ! atomic long store
4417 emit_opcode(cbuf,0xF2);
4418 emit_opcode(cbuf,0x0F);
4419 emit_opcode(cbuf,0x11);
4420 int base = $mem$$base;
4421 int index = $mem$$index;
4422 int scale = $mem$$scale;
4423 int displace = $mem$$disp;
4424 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4425 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4426 }
4427 %}
4428
4429 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4430 { // MOVD $tmp,$src.lo
4431 emit_opcode(cbuf,0x66);
4432 emit_opcode(cbuf,0x0F);
4433 emit_opcode(cbuf,0x6E);
4434 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4435 }
4436 { // MOVD $tmp2,$src.hi
4437 emit_opcode(cbuf,0x66);
4438 emit_opcode(cbuf,0x0F);
4439 emit_opcode(cbuf,0x6E);
4440 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4441 }
4442 { // PUNPCKLDQ $tmp,$tmp2
4443 emit_opcode(cbuf,0x66);
4444 emit_opcode(cbuf,0x0F);
4445 emit_opcode(cbuf,0x62);
4446 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4447 }
4448 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4449 { // MOVSD $mem,$tmp ! atomic long store
4450 emit_opcode(cbuf,0xF2);
4451 emit_opcode(cbuf,0x0F);
4452 emit_opcode(cbuf,0x11);
4453 int base = $mem$$base;
4454 int index = $mem$$index;
4455 int scale = $mem$$scale;
4456 int displace = $mem$$disp;
4457 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4458 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4459 }
4460 %}
4461
4462 // Safepoint Poll. This polls the safepoint page, and causes an
4463 // exception if it is not readable. Unfortunately, it kills the condition code
4464 // in the process
4465 // We current use TESTL [spp],EDI
4466 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4467
4468 enc_class Safepoint_Poll() %{
4469 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4470 emit_opcode(cbuf,0x85);
4471 emit_rm (cbuf, 0x0, 0x7, 0x5);
4472 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4473 %}
4474 %}
4475
4476
4477 //----------FRAME--------------------------------------------------------------
4478 // Definition of frame structure and management information.
4479 //
4480 // S T A C K L A Y O U T Allocators stack-slot number
4481 // | (to get allocators register number
4482 // G Owned by | | v add OptoReg::stack0())
4483 // r CALLER | |
4484 // o | +--------+ pad to even-align allocators stack-slot
4485 // w V | pad0 | numbers; owned by CALLER
4486 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4487 // h ^ | in | 5
4488 // | | args | 4 Holes in incoming args owned by SELF
4489 // | | | | 3
4490 // | | +--------+
4491 // V | | old out| Empty on Intel, window on Sparc
4492 // | old |preserve| Must be even aligned.
4493 // | SP-+--------+----> Matcher::_old_SP, even aligned
4494 // | | in | 3 area for Intel ret address
4495 // Owned by |preserve| Empty on Sparc.
4496 // SELF +--------+
4497 // | | pad2 | 2 pad to align old SP
4498 // | +--------+ 1
4499 // | | locks | 0
4500 // | +--------+----> OptoReg::stack0(), even aligned
4501 // | | pad1 | 11 pad to align new SP
4502 // | +--------+
4503 // | | | 10
4504 // | | spills | 9 spills
4505 // V | | 8 (pad0 slot for callee)
4506 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4507 // ^ | out | 7
4508 // | | args | 6 Holes in outgoing args owned by CALLEE
4509 // Owned by +--------+
4510 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4511 // | new |preserve| Must be even-aligned.
4512 // | SP-+--------+----> Matcher::_new_SP, even aligned
4513 // | | |
4514 //
4515 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4516 // known from SELF's arguments and the Java calling convention.
4517 // Region 6-7 is determined per call site.
4518 // Note 2: If the calling convention leaves holes in the incoming argument
4519 // area, those holes are owned by SELF. Holes in the outgoing area
4520 // are owned by the CALLEE. Holes should not be nessecary in the
4521 // incoming area, as the Java calling convention is completely under
4522 // the control of the AD file. Doubles can be sorted and packed to
4523 // avoid holes. Holes in the outgoing arguments may be nessecary for
4524 // varargs C calling conventions.
4525 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4526 // even aligned with pad0 as needed.
4527 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4528 // region 6-11 is even aligned; it may be padded out more so that
4529 // the region from SP to FP meets the minimum stack alignment.
4530
4531 frame %{
4532 // What direction does stack grow in (assumed to be same for C & Java)
4533 stack_direction(TOWARDS_LOW);
4534
4535 // These three registers define part of the calling convention
4536 // between compiled code and the interpreter.
4537 inline_cache_reg(EAX); // Inline Cache Register
4538 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4539
4540 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4541 cisc_spilling_operand_name(indOffset32);
4542
4543 // Number of stack slots consumed by locking an object
4544 sync_stack_slots(1);
4545
4546 // Compiled code's Frame Pointer
4547 frame_pointer(ESP);
4548 // Interpreter stores its frame pointer in a register which is
4549 // stored to the stack by I2CAdaptors.
4550 // I2CAdaptors convert from interpreted java to compiled java.
4551 interpreter_frame_pointer(EBP);
4552
4553 // Stack alignment requirement
4554 // Alignment size in bytes (128-bit -> 16 bytes)
4555 stack_alignment(StackAlignmentInBytes);
4556
4557 // Number of stack slots between incoming argument block and the start of
4558 // a new frame. The PROLOG must add this many slots to the stack. The
4559 // EPILOG must remove this many slots. Intel needs one slot for
4560 // return address and one for rbp, (must save rbp)
4561 in_preserve_stack_slots(2+VerifyStackAtCalls);
4562
4563 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4564 // for calls to C. Supports the var-args backing area for register parms.
4565 varargs_C_out_slots_killed(0);
4566
4567 // The after-PROLOG location of the return address. Location of
4568 // return address specifies a type (REG or STACK) and a number
4569 // representing the register number (i.e. - use a register name) or
4570 // stack slot.
4571 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4572 // Otherwise, it is above the locks and verification slot and alignment word
4573 return_addr(STACK - 1 +
4574 round_to(1+VerifyStackAtCalls+
4575 Compile::current()->fixed_slots(),
4576 (StackAlignmentInBytes/wordSize)));
4577
4578 // Body of function which returns an integer array locating
4579 // arguments either in registers or in stack slots. Passed an array
4580 // of ideal registers called "sig" and a "length" count. Stack-slot
4581 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4582 // arguments for a CALLEE. Incoming stack arguments are
4583 // automatically biased by the preserve_stack_slots field above.
4584 calling_convention %{
4585 // No difference between ingoing/outgoing just pass false
4586 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4587 %}
4588
4589
4590 // Body of function which returns an integer array locating
4591 // arguments either in registers or in stack slots. Passed an array
4592 // of ideal registers called "sig" and a "length" count. Stack-slot
4593 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4594 // arguments for a CALLEE. Incoming stack arguments are
4595 // automatically biased by the preserve_stack_slots field above.
4596 c_calling_convention %{
4597 // This is obviously always outgoing
4598 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4599 %}
4600
4601 // Location of C & interpreter return values
4602 c_return_value %{
4603 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4604 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4605 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4606
4607 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4608 // that C functions return float and double results in XMM0.
4609 if( ideal_reg == Op_RegD && UseSSE>=2 )
4610 return OptoRegPair(XMM0b_num,XMM0a_num);
4611 if( ideal_reg == Op_RegF && UseSSE>=2 )
4612 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4613
4614 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4615 %}
4616
4617 // Location of return values
4618 return_value %{
4619 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4620 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4621 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4622 if( ideal_reg == Op_RegD && UseSSE>=2 )
4623 return OptoRegPair(XMM0b_num,XMM0a_num);
4624 if( ideal_reg == Op_RegF && UseSSE>=1 )
4625 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4626 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4627 %}
4628
4629 %}
4630
4631 //----------ATTRIBUTES---------------------------------------------------------
4632 //----------Operand Attributes-------------------------------------------------
4633 op_attrib op_cost(0); // Required cost attribute
4634
4635 //----------Instruction Attributes---------------------------------------------
4636 ins_attrib ins_cost(100); // Required cost attribute
4637 ins_attrib ins_size(8); // Required size attribute (in bits)
4638 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4639 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4640 // non-matching short branch variant of some
4641 // long branch?
4642 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4643 // specifies the alignment that some part of the instruction (not
4644 // necessarily the start) requires. If > 1, a compute_padding()
4645 // function must be provided for the instruction
4646
4647 //----------OPERANDS-----------------------------------------------------------
4648 // Operand definitions must precede instruction definitions for correct parsing
4649 // in the ADLC because operands constitute user defined types which are used in
4650 // instruction definitions.
4651
4652 //----------Simple Operands----------------------------------------------------
4653 // Immediate Operands
4654 // Integer Immediate
4655 operand immI() %{
4656 match(ConI);
4657
4658 op_cost(10);
4659 format %{ %}
4660 interface(CONST_INTER);
4661 %}
4662
4663 // Constant for test vs zero
4664 operand immI0() %{
4665 predicate(n->get_int() == 0);
4666 match(ConI);
4667
4668 op_cost(0);
4669 format %{ %}
4670 interface(CONST_INTER);
4671 %}
4672
4673 // Constant for increment
4674 operand immI1() %{
4675 predicate(n->get_int() == 1);
4676 match(ConI);
4677
4678 op_cost(0);
4679 format %{ %}
4680 interface(CONST_INTER);
4681 %}
4682
4683 // Constant for decrement
4684 operand immI_M1() %{
4685 predicate(n->get_int() == -1);
4686 match(ConI);
4687
4688 op_cost(0);
4689 format %{ %}
4690 interface(CONST_INTER);
4691 %}
4692
4693 // Valid scale values for addressing modes
4694 operand immI2() %{
4695 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4696 match(ConI);
4697
4698 format %{ %}
4699 interface(CONST_INTER);
4700 %}
4701
4702 operand immI8() %{
4703 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4704 match(ConI);
4705
4706 op_cost(5);
4707 format %{ %}
4708 interface(CONST_INTER);
4709 %}
4710
4711 operand immI16() %{
4712 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4713 match(ConI);
4714
4715 op_cost(10);
4716 format %{ %}
4717 interface(CONST_INTER);
4718 %}
4719
4720 // Constant for long shifts
4721 operand immI_32() %{
4722 predicate( n->get_int() == 32 );
4723 match(ConI);
4724
4725 op_cost(0);
4726 format %{ %}
4727 interface(CONST_INTER);
4728 %}
4729
4730 operand immI_1_31() %{
4731 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4732 match(ConI);
4733
4734 op_cost(0);
4735 format %{ %}
4736 interface(CONST_INTER);
4737 %}
4738
4739 operand immI_32_63() %{
4740 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4741 match(ConI);
4742 op_cost(0);
4743
4744 format %{ %}
4745 interface(CONST_INTER);
4746 %}
4747
4748 operand immI_1() %{
4749 predicate( n->get_int() == 1 );
4750 match(ConI);
4751
4752 op_cost(0);
4753 format %{ %}
4754 interface(CONST_INTER);
4755 %}
4756
4757 operand immI_2() %{
4758 predicate( n->get_int() == 2 );
4759 match(ConI);
4760
4761 op_cost(0);
4762 format %{ %}
4763 interface(CONST_INTER);
4764 %}
4765
4766 operand immI_3() %{
4767 predicate( n->get_int() == 3 );
4768 match(ConI);
4769
4770 op_cost(0);
4771 format %{ %}
4772 interface(CONST_INTER);
4773 %}
4774
4775 // Pointer Immediate
4776 operand immP() %{
4777 match(ConP);
4778
4779 op_cost(10);
4780 format %{ %}
4781 interface(CONST_INTER);
4782 %}
4783
4784 // NULL Pointer Immediate
4785 operand immP0() %{
4786 predicate( n->get_ptr() == 0 );
4787 match(ConP);
4788 op_cost(0);
4789
4790 format %{ %}
4791 interface(CONST_INTER);
4792 %}
4793
4794 // Long Immediate
4795 operand immL() %{
4796 match(ConL);
4797
4798 op_cost(20);
4799 format %{ %}
4800 interface(CONST_INTER);
4801 %}
4802
4803 // Long Immediate zero
4804 operand immL0() %{
4805 predicate( n->get_long() == 0L );
4806 match(ConL);
4807 op_cost(0);
4808
4809 format %{ %}
4810 interface(CONST_INTER);
4811 %}
4812
4813 // Long Immediate zero
4814 operand immL_M1() %{
4815 predicate( n->get_long() == -1L );
4816 match(ConL);
4817 op_cost(0);
4818
4819 format %{ %}
4820 interface(CONST_INTER);
4821 %}
4822
4823 // Long immediate from 0 to 127.
4824 // Used for a shorter form of long mul by 10.
4825 operand immL_127() %{
4826 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4827 match(ConL);
4828 op_cost(0);
4829
4830 format %{ %}
4831 interface(CONST_INTER);
4832 %}
4833
4834 // Long Immediate: low 32-bit mask
4835 operand immL_32bits() %{
4836 predicate(n->get_long() == 0xFFFFFFFFL);
4837 match(ConL);
4838 op_cost(0);
4839
4840 format %{ %}
4841 interface(CONST_INTER);
4842 %}
4843
4844 // Long Immediate: low 32-bit mask
4845 operand immL32() %{
4846 predicate(n->get_long() == (int)(n->get_long()));
4847 match(ConL);
4848 op_cost(20);
4849
4850 format %{ %}
4851 interface(CONST_INTER);
4852 %}
4853
4854 //Double Immediate zero
4855 operand immD0() %{
4856 // Do additional (and counter-intuitive) test against NaN to work around VC++
4857 // bug that generates code such that NaNs compare equal to 0.0
4858 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4859 match(ConD);
4860
4861 op_cost(5);
4862 format %{ %}
4863 interface(CONST_INTER);
4864 %}
4865
4866 // Double Immediate
4867 operand immD1() %{
4868 predicate( UseSSE<=1 && n->getd() == 1.0 );
4869 match(ConD);
4870
4871 op_cost(5);
4872 format %{ %}
4873 interface(CONST_INTER);
4874 %}
4875
4876 // Double Immediate
4877 operand immD() %{
4878 predicate(UseSSE<=1);
4879 match(ConD);
4880
4881 op_cost(5);
4882 format %{ %}
4883 interface(CONST_INTER);
4884 %}
4885
4886 operand immXD() %{
4887 predicate(UseSSE>=2);
4888 match(ConD);
4889
4890 op_cost(5);
4891 format %{ %}
4892 interface(CONST_INTER);
4893 %}
4894
4895 // Double Immediate zero
4896 operand immXD0() %{
4897 // Do additional (and counter-intuitive) test against NaN to work around VC++
4898 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4899 // compare equal to -0.0.
4900 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4901 match(ConD);
4902
4903 format %{ %}
4904 interface(CONST_INTER);
4905 %}
4906
4907 // Float Immediate zero
4908 operand immF0() %{
4909 predicate( UseSSE == 0 && n->getf() == 0.0 );
4910 match(ConF);
4911
4912 op_cost(5);
4913 format %{ %}
4914 interface(CONST_INTER);
4915 %}
4916
4917 // Float Immediate
4918 operand immF() %{
4919 predicate( UseSSE == 0 );
4920 match(ConF);
4921
4922 op_cost(5);
4923 format %{ %}
4924 interface(CONST_INTER);
4925 %}
4926
4927 // Float Immediate
4928 operand immXF() %{
4929 predicate(UseSSE >= 1);
4930 match(ConF);
4931
4932 op_cost(5);
4933 format %{ %}
4934 interface(CONST_INTER);
4935 %}
4936
4937 // Float Immediate zero. Zero and not -0.0
4938 operand immXF0() %{
4939 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4940 match(ConF);
4941
4942 op_cost(5);
4943 format %{ %}
4944 interface(CONST_INTER);
4945 %}
4946
4947 // Immediates for special shifts (sign extend)
4948
4949 // Constants for increment
4950 operand immI_16() %{
4951 predicate( n->get_int() == 16 );
4952 match(ConI);
4953
4954 format %{ %}
4955 interface(CONST_INTER);
4956 %}
4957
4958 operand immI_24() %{
4959 predicate( n->get_int() == 24 );
4960 match(ConI);
4961
4962 format %{ %}
4963 interface(CONST_INTER);
4964 %}
4965
4966 // Constant for byte-wide masking
4967 operand immI_255() %{
4968 predicate( n->get_int() == 255 );
4969 match(ConI);
4970
4971 format %{ %}
4972 interface(CONST_INTER);
4973 %}
4974
4975 // Register Operands
4976 // Integer Register
4977 operand eRegI() %{
4978 constraint(ALLOC_IN_RC(e_reg));
4979 match(RegI);
4980 match(xRegI);
4981 match(eAXRegI);
4982 match(eBXRegI);
4983 match(eCXRegI);
4984 match(eDXRegI);
4985 match(eDIRegI);
4986 match(eSIRegI);
4987
4988 format %{ %}
4989 interface(REG_INTER);
4990 %}
4991
4992 // Subset of Integer Register
4993 operand xRegI(eRegI reg) %{
4994 constraint(ALLOC_IN_RC(x_reg));
4995 match(reg);
4996 match(eAXRegI);
4997 match(eBXRegI);
4998 match(eCXRegI);
4999 match(eDXRegI);
5000
5001 format %{ %}
5002 interface(REG_INTER);
5003 %}
5004
5005 // Special Registers
5006 operand eAXRegI(xRegI reg) %{
5007 constraint(ALLOC_IN_RC(eax_reg));
5008 match(reg);
5009 match(eRegI);
5010
5011 format %{ "EAX" %}
5012 interface(REG_INTER);
5013 %}
5014
5015 // Special Registers
5016 operand eBXRegI(xRegI reg) %{
5017 constraint(ALLOC_IN_RC(ebx_reg));
5018 match(reg);
5019 match(eRegI);
5020
5021 format %{ "EBX" %}
5022 interface(REG_INTER);
5023 %}
5024
5025 operand eCXRegI(xRegI reg) %{
5026 constraint(ALLOC_IN_RC(ecx_reg));
5027 match(reg);
5028 match(eRegI);
5029
5030 format %{ "ECX" %}
5031 interface(REG_INTER);
5032 %}
5033
5034 operand eDXRegI(xRegI reg) %{
5035 constraint(ALLOC_IN_RC(edx_reg));
5036 match(reg);
5037 match(eRegI);
5038
5039 format %{ "EDX" %}
5040 interface(REG_INTER);
5041 %}
5042
5043 operand eDIRegI(xRegI reg) %{
5044 constraint(ALLOC_IN_RC(edi_reg));
5045 match(reg);
5046 match(eRegI);
5047
5048 format %{ "EDI" %}
5049 interface(REG_INTER);
5050 %}
5051
5052 operand naxRegI() %{
5053 constraint(ALLOC_IN_RC(nax_reg));
5054 match(RegI);
5055 match(eCXRegI);
5056 match(eDXRegI);
5057 match(eSIRegI);
5058 match(eDIRegI);
5059
5060 format %{ %}
5061 interface(REG_INTER);
5062 %}
5063
5064 operand nadxRegI() %{
5065 constraint(ALLOC_IN_RC(nadx_reg));
5066 match(RegI);
5067 match(eBXRegI);
5068 match(eCXRegI);
5069 match(eSIRegI);
5070 match(eDIRegI);
5071
5072 format %{ %}
5073 interface(REG_INTER);
5074 %}
5075
5076 operand ncxRegI() %{
5077 constraint(ALLOC_IN_RC(ncx_reg));
5078 match(RegI);
5079 match(eAXRegI);
5080 match(eDXRegI);
5081 match(eSIRegI);
5082 match(eDIRegI);
5083
5084 format %{ %}
5085 interface(REG_INTER);
5086 %}
5087
5088 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5089 // //
5090 operand eSIRegI(xRegI reg) %{
5091 constraint(ALLOC_IN_RC(esi_reg));
5092 match(reg);
5093 match(eRegI);
5094
5095 format %{ "ESI" %}
5096 interface(REG_INTER);
5097 %}
5098
5099 // Pointer Register
5100 operand anyRegP() %{
5101 constraint(ALLOC_IN_RC(any_reg));
5102 match(RegP);
5103 match(eAXRegP);
5104 match(eBXRegP);
5105 match(eCXRegP);
5106 match(eDIRegP);
5107 match(eRegP);
5108
5109 format %{ %}
5110 interface(REG_INTER);
5111 %}
5112
5113 operand eRegP() %{
5114 constraint(ALLOC_IN_RC(e_reg));
5115 match(RegP);
5116 match(eAXRegP);
5117 match(eBXRegP);
5118 match(eCXRegP);
5119 match(eDIRegP);
5120
5121 format %{ %}
5122 interface(REG_INTER);
5123 %}
5124
5125 // On windows95, EBP is not safe to use for implicit null tests.
5126 operand eRegP_no_EBP() %{
5127 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5128 match(RegP);
5129 match(eAXRegP);
5130 match(eBXRegP);
5131 match(eCXRegP);
5132 match(eDIRegP);
5133
5134 op_cost(100);
5135 format %{ %}
5136 interface(REG_INTER);
5137 %}
5138
5139 operand naxRegP() %{
5140 constraint(ALLOC_IN_RC(nax_reg));
5141 match(RegP);
5142 match(eBXRegP);
5143 match(eDXRegP);
5144 match(eCXRegP);
5145 match(eSIRegP);
5146 match(eDIRegP);
5147
5148 format %{ %}
5149 interface(REG_INTER);
5150 %}
5151
5152 operand nabxRegP() %{
5153 constraint(ALLOC_IN_RC(nabx_reg));
5154 match(RegP);
5155 match(eCXRegP);
5156 match(eDXRegP);
5157 match(eSIRegP);
5158 match(eDIRegP);
5159
5160 format %{ %}
5161 interface(REG_INTER);
5162 %}
5163
5164 operand pRegP() %{
5165 constraint(ALLOC_IN_RC(p_reg));
5166 match(RegP);
5167 match(eBXRegP);
5168 match(eDXRegP);
5169 match(eSIRegP);
5170 match(eDIRegP);
5171
5172 format %{ %}
5173 interface(REG_INTER);
5174 %}
5175
5176 // Special Registers
5177 // Return a pointer value
5178 operand eAXRegP(eRegP reg) %{
5179 constraint(ALLOC_IN_RC(eax_reg));
5180 match(reg);
5181 format %{ "EAX" %}
5182 interface(REG_INTER);
5183 %}
5184
5185 // Used in AtomicAdd
5186 operand eBXRegP(eRegP reg) %{
5187 constraint(ALLOC_IN_RC(ebx_reg));
5188 match(reg);
5189 format %{ "EBX" %}
5190 interface(REG_INTER);
5191 %}
5192
5193 // Tail-call (interprocedural jump) to interpreter
5194 operand eCXRegP(eRegP reg) %{
5195 constraint(ALLOC_IN_RC(ecx_reg));
5196 match(reg);
5197 format %{ "ECX" %}
5198 interface(REG_INTER);
5199 %}
5200
5201 operand eSIRegP(eRegP reg) %{
5202 constraint(ALLOC_IN_RC(esi_reg));
5203 match(reg);
5204 format %{ "ESI" %}
5205 interface(REG_INTER);
5206 %}
5207
5208 // Used in rep stosw
5209 operand eDIRegP(eRegP reg) %{
5210 constraint(ALLOC_IN_RC(edi_reg));
5211 match(reg);
5212 format %{ "EDI" %}
5213 interface(REG_INTER);
5214 %}
5215
5216 operand eBPRegP() %{
5217 constraint(ALLOC_IN_RC(ebp_reg));
5218 match(RegP);
5219 format %{ "EBP" %}
5220 interface(REG_INTER);
5221 %}
5222
5223 operand eRegL() %{
5224 constraint(ALLOC_IN_RC(long_reg));
5225 match(RegL);
5226 match(eADXRegL);
5227
5228 format %{ %}
5229 interface(REG_INTER);
5230 %}
5231
5232 operand eADXRegL( eRegL reg ) %{
5233 constraint(ALLOC_IN_RC(eadx_reg));
5234 match(reg);
5235
5236 format %{ "EDX:EAX" %}
5237 interface(REG_INTER);
5238 %}
5239
5240 operand eBCXRegL( eRegL reg ) %{
5241 constraint(ALLOC_IN_RC(ebcx_reg));
5242 match(reg);
5243
5244 format %{ "EBX:ECX" %}
5245 interface(REG_INTER);
5246 %}
5247
5248 // Special case for integer high multiply
5249 operand eADXRegL_low_only() %{
5250 constraint(ALLOC_IN_RC(eadx_reg));
5251 match(RegL);
5252
5253 format %{ "EAX" %}
5254 interface(REG_INTER);
5255 %}
5256
5257 // Flags register, used as output of compare instructions
5258 operand eFlagsReg() %{
5259 constraint(ALLOC_IN_RC(int_flags));
5260 match(RegFlags);
5261
5262 format %{ "EFLAGS" %}
5263 interface(REG_INTER);
5264 %}
5265
5266 // Flags register, used as output of FLOATING POINT compare instructions
5267 operand eFlagsRegU() %{
5268 constraint(ALLOC_IN_RC(int_flags));
5269 match(RegFlags);
5270
5271 format %{ "EFLAGS_U" %}
5272 interface(REG_INTER);
5273 %}
5274
5275 // Condition Code Register used by long compare
5276 operand flagsReg_long_LTGE() %{
5277 constraint(ALLOC_IN_RC(int_flags));
5278 match(RegFlags);
5279 format %{ "FLAGS_LTGE" %}
5280 interface(REG_INTER);
5281 %}
5282 operand flagsReg_long_EQNE() %{
5283 constraint(ALLOC_IN_RC(int_flags));
5284 match(RegFlags);
5285 format %{ "FLAGS_EQNE" %}
5286 interface(REG_INTER);
5287 %}
5288 operand flagsReg_long_LEGT() %{
5289 constraint(ALLOC_IN_RC(int_flags));
5290 match(RegFlags);
5291 format %{ "FLAGS_LEGT" %}
5292 interface(REG_INTER);
5293 %}
5294
5295 // Float register operands
5296 operand regD() %{
5297 predicate( UseSSE < 2 );
5298 constraint(ALLOC_IN_RC(dbl_reg));
5299 match(RegD);
5300 match(regDPR1);
5301 match(regDPR2);
5302 format %{ %}
5303 interface(REG_INTER);
5304 %}
5305
5306 operand regDPR1(regD reg) %{
5307 predicate( UseSSE < 2 );
5308 constraint(ALLOC_IN_RC(dbl_reg0));
5309 match(reg);
5310 format %{ "FPR1" %}
5311 interface(REG_INTER);
5312 %}
5313
5314 operand regDPR2(regD reg) %{
5315 predicate( UseSSE < 2 );
5316 constraint(ALLOC_IN_RC(dbl_reg1));
5317 match(reg);
5318 format %{ "FPR2" %}
5319 interface(REG_INTER);
5320 %}
5321
5322 operand regnotDPR1(regD reg) %{
5323 predicate( UseSSE < 2 );
5324 constraint(ALLOC_IN_RC(dbl_notreg0));
5325 match(reg);
5326 format %{ %}
5327 interface(REG_INTER);
5328 %}
5329
5330 // XMM Double register operands
5331 operand regXD() %{
5332 predicate( UseSSE>=2 );
5333 constraint(ALLOC_IN_RC(xdb_reg));
5334 match(RegD);
5335 match(regXD6);
5336 match(regXD7);
5337 format %{ %}
5338 interface(REG_INTER);
5339 %}
5340
5341 // XMM6 double register operands
5342 operand regXD6(regXD reg) %{
5343 predicate( UseSSE>=2 );
5344 constraint(ALLOC_IN_RC(xdb_reg6));
5345 match(reg);
5346 format %{ "XMM6" %}
5347 interface(REG_INTER);
5348 %}
5349
5350 // XMM7 double register operands
5351 operand regXD7(regXD reg) %{
5352 predicate( UseSSE>=2 );
5353 constraint(ALLOC_IN_RC(xdb_reg7));
5354 match(reg);
5355 format %{ "XMM7" %}
5356 interface(REG_INTER);
5357 %}
5358
5359 // Float register operands
5360 operand regF() %{
5361 predicate( UseSSE < 2 );
5362 constraint(ALLOC_IN_RC(flt_reg));
5363 match(RegF);
5364 match(regFPR1);
5365 format %{ %}
5366 interface(REG_INTER);
5367 %}
5368
5369 // Float register operands
5370 operand regFPR1(regF reg) %{
5371 predicate( UseSSE < 2 );
5372 constraint(ALLOC_IN_RC(flt_reg0));
5373 match(reg);
5374 format %{ "FPR1" %}
5375 interface(REG_INTER);
5376 %}
5377
5378 // XMM register operands
5379 operand regX() %{
5380 predicate( UseSSE>=1 );
5381 constraint(ALLOC_IN_RC(xmm_reg));
5382 match(RegF);
5383 format %{ %}
5384 interface(REG_INTER);
5385 %}
5386
5387
5388 //----------Memory Operands----------------------------------------------------
5389 // Direct Memory Operand
5390 operand direct(immP addr) %{
5391 match(addr);
5392
5393 format %{ "[$addr]" %}
5394 interface(MEMORY_INTER) %{
5395 base(0xFFFFFFFF);
5396 index(0x4);
5397 scale(0x0);
5398 disp($addr);
5399 %}
5400 %}
5401
5402 // Indirect Memory Operand
5403 operand indirect(eRegP reg) %{
5404 constraint(ALLOC_IN_RC(e_reg));
5405 match(reg);
5406
5407 format %{ "[$reg]" %}
5408 interface(MEMORY_INTER) %{
5409 base($reg);
5410 index(0x4);
5411 scale(0x0);
5412 disp(0x0);
5413 %}
5414 %}
5415
5416 // Indirect Memory Plus Short Offset Operand
5417 operand indOffset8(eRegP reg, immI8 off) %{
5418 match(AddP reg off);
5419
5420 format %{ "[$reg + $off]" %}
5421 interface(MEMORY_INTER) %{
5422 base($reg);
5423 index(0x4);
5424 scale(0x0);
5425 disp($off);
5426 %}
5427 %}
5428
5429 // Indirect Memory Plus Long Offset Operand
5430 operand indOffset32(eRegP reg, immI off) %{
5431 match(AddP reg off);
5432
5433 format %{ "[$reg + $off]" %}
5434 interface(MEMORY_INTER) %{
5435 base($reg);
5436 index(0x4);
5437 scale(0x0);
5438 disp($off);
5439 %}
5440 %}
5441
5442 // Indirect Memory Plus Long Offset Operand
5443 operand indOffset32X(eRegI reg, immP off) %{
5444 match(AddP off reg);
5445
5446 format %{ "[$reg + $off]" %}
5447 interface(MEMORY_INTER) %{
5448 base($reg);
5449 index(0x4);
5450 scale(0x0);
5451 disp($off);
5452 %}
5453 %}
5454
5455 // Indirect Memory Plus Index Register Plus Offset Operand
5456 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5457 match(AddP (AddP reg ireg) off);
5458
5459 op_cost(10);
5460 format %{"[$reg + $off + $ireg]" %}
5461 interface(MEMORY_INTER) %{
5462 base($reg);
5463 index($ireg);
5464 scale(0x0);
5465 disp($off);
5466 %}
5467 %}
5468
5469 // Indirect Memory Plus Index Register Plus Offset Operand
5470 operand indIndex(eRegP reg, eRegI ireg) %{
5471 match(AddP reg ireg);
5472
5473 op_cost(10);
5474 format %{"[$reg + $ireg]" %}
5475 interface(MEMORY_INTER) %{
5476 base($reg);
5477 index($ireg);
5478 scale(0x0);
5479 disp(0x0);
5480 %}
5481 %}
5482
5483 // // -------------------------------------------------------------------------
5484 // // 486 architecture doesn't support "scale * index + offset" with out a base
5485 // // -------------------------------------------------------------------------
5486 // // Scaled Memory Operands
5487 // // Indirect Memory Times Scale Plus Offset Operand
5488 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5489 // match(AddP off (LShiftI ireg scale));
5490 //
5491 // op_cost(10);
5492 // format %{"[$off + $ireg << $scale]" %}
5493 // interface(MEMORY_INTER) %{
5494 // base(0x4);
5495 // index($ireg);
5496 // scale($scale);
5497 // disp($off);
5498 // %}
5499 // %}
5500
5501 // Indirect Memory Times Scale Plus Index Register
5502 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5503 match(AddP reg (LShiftI ireg scale));
5504
5505 op_cost(10);
5506 format %{"[$reg + $ireg << $scale]" %}
5507 interface(MEMORY_INTER) %{
5508 base($reg);
5509 index($ireg);
5510 scale($scale);
5511 disp(0x0);
5512 %}
5513 %}
5514
5515 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5516 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5517 match(AddP (AddP reg (LShiftI ireg scale)) off);
5518
5519 op_cost(10);
5520 format %{"[$reg + $off + $ireg << $scale]" %}
5521 interface(MEMORY_INTER) %{
5522 base($reg);
5523 index($ireg);
5524 scale($scale);
5525 disp($off);
5526 %}
5527 %}
5528
5529 //----------Load Long Memory Operands------------------------------------------
5530 // The load-long idiom will use it's address expression again after loading
5531 // the first word of the long. If the load-long destination overlaps with
5532 // registers used in the addressing expression, the 2nd half will be loaded
5533 // from a clobbered address. Fix this by requiring that load-long use
5534 // address registers that do not overlap with the load-long target.
5535
5536 // load-long support
5537 operand load_long_RegP() %{
5538 constraint(ALLOC_IN_RC(esi_reg));
5539 match(RegP);
5540 match(eSIRegP);
5541 op_cost(100);
5542 format %{ %}
5543 interface(REG_INTER);
5544 %}
5545
5546 // Indirect Memory Operand Long
5547 operand load_long_indirect(load_long_RegP reg) %{
5548 constraint(ALLOC_IN_RC(esi_reg));
5549 match(reg);
5550
5551 format %{ "[$reg]" %}
5552 interface(MEMORY_INTER) %{
5553 base($reg);
5554 index(0x4);
5555 scale(0x0);
5556 disp(0x0);
5557 %}
5558 %}
5559
5560 // Indirect Memory Plus Long Offset Operand
5561 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5562 match(AddP reg off);
5563
5564 format %{ "[$reg + $off]" %}
5565 interface(MEMORY_INTER) %{
5566 base($reg);
5567 index(0x4);
5568 scale(0x0);
5569 disp($off);
5570 %}
5571 %}
5572
5573 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5574
5575
5576 //----------Special Memory Operands--------------------------------------------
5577 // Stack Slot Operand - This operand is used for loading and storing temporary
5578 // values on the stack where a match requires a value to
5579 // flow through memory.
5580 operand stackSlotP(sRegP reg) %{
5581 constraint(ALLOC_IN_RC(stack_slots));
5582 // No match rule because this operand is only generated in matching
5583 format %{ "[$reg]" %}
5584 interface(MEMORY_INTER) %{
5585 base(0x4); // ESP
5586 index(0x4); // No Index
5587 scale(0x0); // No Scale
5588 disp($reg); // Stack Offset
5589 %}
5590 %}
5591
5592 operand stackSlotI(sRegI reg) %{
5593 constraint(ALLOC_IN_RC(stack_slots));
5594 // No match rule because this operand is only generated in matching
5595 format %{ "[$reg]" %}
5596 interface(MEMORY_INTER) %{
5597 base(0x4); // ESP
5598 index(0x4); // No Index
5599 scale(0x0); // No Scale
5600 disp($reg); // Stack Offset
5601 %}
5602 %}
5603
5604 operand stackSlotF(sRegF reg) %{
5605 constraint(ALLOC_IN_RC(stack_slots));
5606 // No match rule because this operand is only generated in matching
5607 format %{ "[$reg]" %}
5608 interface(MEMORY_INTER) %{
5609 base(0x4); // ESP
5610 index(0x4); // No Index
5611 scale(0x0); // No Scale
5612 disp($reg); // Stack Offset
5613 %}
5614 %}
5615
5616 operand stackSlotD(sRegD reg) %{
5617 constraint(ALLOC_IN_RC(stack_slots));
5618 // No match rule because this operand is only generated in matching
5619 format %{ "[$reg]" %}
5620 interface(MEMORY_INTER) %{
5621 base(0x4); // ESP
5622 index(0x4); // No Index
5623 scale(0x0); // No Scale
5624 disp($reg); // Stack Offset
5625 %}
5626 %}
5627
5628 operand stackSlotL(sRegL reg) %{
5629 constraint(ALLOC_IN_RC(stack_slots));
5630 // No match rule because this operand is only generated in matching
5631 format %{ "[$reg]" %}
5632 interface(MEMORY_INTER) %{
5633 base(0x4); // ESP
5634 index(0x4); // No Index
5635 scale(0x0); // No Scale
5636 disp($reg); // Stack Offset
5637 %}
5638 %}
5639
5640 //----------Memory Operands - Win95 Implicit Null Variants----------------
5641 // Indirect Memory Operand
5642 operand indirect_win95_safe(eRegP_no_EBP reg)
5643 %{
5644 constraint(ALLOC_IN_RC(e_reg));
5645 match(reg);
5646
5647 op_cost(100);
5648 format %{ "[$reg]" %}
5649 interface(MEMORY_INTER) %{
5650 base($reg);
5651 index(0x4);
5652 scale(0x0);
5653 disp(0x0);
5654 %}
5655 %}
5656
5657 // Indirect Memory Plus Short Offset Operand
5658 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5659 %{
5660 match(AddP reg off);
5661
5662 op_cost(100);
5663 format %{ "[$reg + $off]" %}
5664 interface(MEMORY_INTER) %{
5665 base($reg);
5666 index(0x4);
5667 scale(0x0);
5668 disp($off);
5669 %}
5670 %}
5671
5672 // Indirect Memory Plus Long Offset Operand
5673 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5674 %{
5675 match(AddP reg off);
5676
5677 op_cost(100);
5678 format %{ "[$reg + $off]" %}
5679 interface(MEMORY_INTER) %{
5680 base($reg);
5681 index(0x4);
5682 scale(0x0);
5683 disp($off);
5684 %}
5685 %}
5686
5687 // Indirect Memory Plus Index Register Plus Offset Operand
5688 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5689 %{
5690 match(AddP (AddP reg ireg) off);
5691
5692 op_cost(100);
5693 format %{"[$reg + $off + $ireg]" %}
5694 interface(MEMORY_INTER) %{
5695 base($reg);
5696 index($ireg);
5697 scale(0x0);
5698 disp($off);
5699 %}
5700 %}
5701
5702 // Indirect Memory Times Scale Plus Index Register
5703 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5704 %{
5705 match(AddP reg (LShiftI ireg scale));
5706
5707 op_cost(100);
5708 format %{"[$reg + $ireg << $scale]" %}
5709 interface(MEMORY_INTER) %{
5710 base($reg);
5711 index($ireg);
5712 scale($scale);
5713 disp(0x0);
5714 %}
5715 %}
5716
5717 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5718 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5719 %{
5720 match(AddP (AddP reg (LShiftI ireg scale)) off);
5721
5722 op_cost(100);
5723 format %{"[$reg + $off + $ireg << $scale]" %}
5724 interface(MEMORY_INTER) %{
5725 base($reg);
5726 index($ireg);
5727 scale($scale);
5728 disp($off);
5729 %}
5730 %}
5731
5732 //----------Conditional Branch Operands----------------------------------------
5733 // Comparison Op - This is the operation of the comparison, and is limited to
5734 // the following set of codes:
5735 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5736 //
5737 // Other attributes of the comparison, such as unsignedness, are specified
5738 // by the comparison instruction that sets a condition code flags register.
5739 // That result is represented by a flags operand whose subtype is appropriate
5740 // to the unsignedness (etc.) of the comparison.
5741 //
5742 // Later, the instruction which matches both the Comparison Op (a Bool) and
5743 // the flags (produced by the Cmp) specifies the coding of the comparison op
5744 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5745
5746 // Comparision Code
5747 operand cmpOp() %{
5748 match(Bool);
5749
5750 format %{ "" %}
5751 interface(COND_INTER) %{
5752 equal(0x4);
5753 not_equal(0x5);
5754 less(0xC);
5755 greater_equal(0xD);
5756 less_equal(0xE);
5757 greater(0xF);
5758 %}
5759 %}
5760
5761 // Comparison Code, unsigned compare. Used by FP also, with
5762 // C2 (unordered) turned into GT or LT already. The other bits
5763 // C0 and C3 are turned into Carry & Zero flags.
5764 operand cmpOpU() %{
5765 match(Bool);
5766
5767 format %{ "" %}
5768 interface(COND_INTER) %{
5769 equal(0x4);
5770 not_equal(0x5);
5771 less(0x2);
5772 greater_equal(0x3);
5773 less_equal(0x6);
5774 greater(0x7);
5775 %}
5776 %}
5777
5778 // Comparison Code for FP conditional move
5779 operand cmpOp_fcmov() %{
5780 match(Bool);
5781
5782 format %{ "" %}
5783 interface(COND_INTER) %{
5784 equal (0x0C8);
5785 not_equal (0x1C8);
5786 less (0x0C0);
5787 greater_equal(0x1C0);
5788 less_equal (0x0D0);
5789 greater (0x1D0);
5790 %}
5791 %}
5792
5793 // Comparision Code used in long compares
5794 operand cmpOp_commute() %{
5795 match(Bool);
5796
5797 format %{ "" %}
5798 interface(COND_INTER) %{
5799 equal(0x4);
5800 not_equal(0x5);
5801 less(0xF);
5802 greater_equal(0xE);
5803 less_equal(0xD);
5804 greater(0xC);
5805 %}
5806 %}
5807
5808 //----------OPERAND CLASSES----------------------------------------------------
5809 // Operand Classes are groups of operands that are used as to simplify
5810 // instruction definitions by not requiring the AD writer to specify seperate
5811 // instructions for every form of operand when the instruction accepts
5812 // multiple operand types with the same basic encoding and format. The classic
5813 // case of this is memory operands.
5814
5815 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5816 indIndex, indIndexScale, indIndexScaleOffset);
5817
5818 // Long memory operations are encoded in 2 instructions and a +4 offset.
5819 // This means some kind of offset is always required and you cannot use
5820 // an oop as the offset (done when working on static globals).
5821 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5822 indIndex, indIndexScale, indIndexScaleOffset);
5823
5824
5825 //----------PIPELINE-----------------------------------------------------------
5826 // Rules which define the behavior of the target architectures pipeline.
5827 pipeline %{
5828
5829 //----------ATTRIBUTES---------------------------------------------------------
5830 attributes %{
5831 variable_size_instructions; // Fixed size instructions
5832 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5833 instruction_unit_size = 1; // An instruction is 1 bytes long
5834 instruction_fetch_unit_size = 16; // The processor fetches one line
5835 instruction_fetch_units = 1; // of 16 bytes
5836
5837 // List of nop instructions
5838 nops( MachNop );
5839 %}
5840
5841 //----------RESOURCES----------------------------------------------------------
5842 // Resources are the functional units available to the machine
5843
5844 // Generic P2/P3 pipeline
5845 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5846 // 3 instructions decoded per cycle.
5847 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5848 // 2 ALU op, only ALU0 handles mul/div instructions.
5849 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5850 MS0, MS1, MEM = MS0 | MS1,
5851 BR, FPU,
5852 ALU0, ALU1, ALU = ALU0 | ALU1 );
5853
5854 //----------PIPELINE DESCRIPTION-----------------------------------------------
5855 // Pipeline Description specifies the stages in the machine's pipeline
5856
5857 // Generic P2/P3 pipeline
5858 pipe_desc(S0, S1, S2, S3, S4, S5);
5859
5860 //----------PIPELINE CLASSES---------------------------------------------------
5861 // Pipeline Classes describe the stages in which input and output are
5862 // referenced by the hardware pipeline.
5863
5864 // Naming convention: ialu or fpu
5865 // Then: _reg
5866 // Then: _reg if there is a 2nd register
5867 // Then: _long if it's a pair of instructions implementing a long
5868 // Then: _fat if it requires the big decoder
5869 // Or: _mem if it requires the big decoder and a memory unit.
5870
5871 // Integer ALU reg operation
5872 pipe_class ialu_reg(eRegI dst) %{
5873 single_instruction;
5874 dst : S4(write);
5875 dst : S3(read);
5876 DECODE : S0; // any decoder
5877 ALU : S3; // any alu
5878 %}
5879
5880 // Long ALU reg operation
5881 pipe_class ialu_reg_long(eRegL dst) %{
5882 instruction_count(2);
5883 dst : S4(write);
5884 dst : S3(read);
5885 DECODE : S0(2); // any 2 decoders
5886 ALU : S3(2); // both alus
5887 %}
5888
5889 // Integer ALU reg operation using big decoder
5890 pipe_class ialu_reg_fat(eRegI dst) %{
5891 single_instruction;
5892 dst : S4(write);
5893 dst : S3(read);
5894 D0 : S0; // big decoder only
5895 ALU : S3; // any alu
5896 %}
5897
5898 // Long ALU reg operation using big decoder
5899 pipe_class ialu_reg_long_fat(eRegL dst) %{
5900 instruction_count(2);
5901 dst : S4(write);
5902 dst : S3(read);
5903 D0 : S0(2); // big decoder only; twice
5904 ALU : S3(2); // any 2 alus
5905 %}
5906
5907 // Integer ALU reg-reg operation
5908 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5909 single_instruction;
5910 dst : S4(write);
5911 src : S3(read);
5912 DECODE : S0; // any decoder
5913 ALU : S3; // any alu
5914 %}
5915
5916 // Long ALU reg-reg operation
5917 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5918 instruction_count(2);
5919 dst : S4(write);
5920 src : S3(read);
5921 DECODE : S0(2); // any 2 decoders
5922 ALU : S3(2); // both alus
5923 %}
5924
5925 // Integer ALU reg-reg operation
5926 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5927 single_instruction;
5928 dst : S4(write);
5929 src : S3(read);
5930 D0 : S0; // big decoder only
5931 ALU : S3; // any alu
5932 %}
5933
5934 // Long ALU reg-reg operation
5935 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5936 instruction_count(2);
5937 dst : S4(write);
5938 src : S3(read);
5939 D0 : S0(2); // big decoder only; twice
5940 ALU : S3(2); // both alus
5941 %}
5942
5943 // Integer ALU reg-mem operation
5944 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5945 single_instruction;
5946 dst : S5(write);
5947 mem : S3(read);
5948 D0 : S0; // big decoder only
5949 ALU : S4; // any alu
5950 MEM : S3; // any mem
5951 %}
5952
5953 // Long ALU reg-mem operation
5954 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5955 instruction_count(2);
5956 dst : S5(write);
5957 mem : S3(read);
5958 D0 : S0(2); // big decoder only; twice
5959 ALU : S4(2); // any 2 alus
5960 MEM : S3(2); // both mems
5961 %}
5962
5963 // Integer mem operation (prefetch)
5964 pipe_class ialu_mem(memory mem)
5965 %{
5966 single_instruction;
5967 mem : S3(read);
5968 D0 : S0; // big decoder only
5969 MEM : S3; // any mem
5970 %}
5971
5972 // Integer Store to Memory
5973 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5974 single_instruction;
5975 mem : S3(read);
5976 src : S5(read);
5977 D0 : S0; // big decoder only
5978 ALU : S4; // any alu
5979 MEM : S3;
5980 %}
5981
5982 // Long Store to Memory
5983 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5984 instruction_count(2);
5985 mem : S3(read);
5986 src : S5(read);
5987 D0 : S0(2); // big decoder only; twice
5988 ALU : S4(2); // any 2 alus
5989 MEM : S3(2); // Both mems
5990 %}
5991
5992 // Integer Store to Memory
5993 pipe_class ialu_mem_imm(memory mem) %{
5994 single_instruction;
5995 mem : S3(read);
5996 D0 : S0; // big decoder only
5997 ALU : S4; // any alu
5998 MEM : S3;
5999 %}
6000
6001 // Integer ALU0 reg-reg operation
6002 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6003 single_instruction;
6004 dst : S4(write);
6005 src : S3(read);
6006 D0 : S0; // Big decoder only
6007 ALU0 : S3; // only alu0
6008 %}
6009
6010 // Integer ALU0 reg-mem operation
6011 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6012 single_instruction;
6013 dst : S5(write);
6014 mem : S3(read);
6015 D0 : S0; // big decoder only
6016 ALU0 : S4; // ALU0 only
6017 MEM : S3; // any mem
6018 %}
6019
6020 // Integer ALU reg-reg operation
6021 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6022 single_instruction;
6023 cr : S4(write);
6024 src1 : S3(read);
6025 src2 : S3(read);
6026 DECODE : S0; // any decoder
6027 ALU : S3; // any alu
6028 %}
6029
6030 // Integer ALU reg-imm operation
6031 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6032 single_instruction;
6033 cr : S4(write);
6034 src1 : S3(read);
6035 DECODE : S0; // any decoder
6036 ALU : S3; // any alu
6037 %}
6038
6039 // Integer ALU reg-mem operation
6040 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6041 single_instruction;
6042 cr : S4(write);
6043 src1 : S3(read);
6044 src2 : S3(read);
6045 D0 : S0; // big decoder only
6046 ALU : S4; // any alu
6047 MEM : S3;
6048 %}
6049
6050 // Conditional move reg-reg
6051 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6052 instruction_count(4);
6053 y : S4(read);
6054 q : S3(read);
6055 p : S3(read);
6056 DECODE : S0(4); // any decoder
6057 %}
6058
6059 // Conditional move reg-reg
6060 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6061 single_instruction;
6062 dst : S4(write);
6063 src : S3(read);
6064 cr : S3(read);
6065 DECODE : S0; // any decoder
6066 %}
6067
6068 // Conditional move reg-mem
6069 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6070 single_instruction;
6071 dst : S4(write);
6072 src : S3(read);
6073 cr : S3(read);
6074 DECODE : S0; // any decoder
6075 MEM : S3;
6076 %}
6077
6078 // Conditional move reg-reg long
6079 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6080 single_instruction;
6081 dst : S4(write);
6082 src : S3(read);
6083 cr : S3(read);
6084 DECODE : S0(2); // any 2 decoders
6085 %}
6086
6087 // Conditional move double reg-reg
6088 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6089 single_instruction;
6090 dst : S4(write);
6091 src : S3(read);
6092 cr : S3(read);
6093 DECODE : S0; // any decoder
6094 %}
6095
6096 // Float reg-reg operation
6097 pipe_class fpu_reg(regD dst) %{
6098 instruction_count(2);
6099 dst : S3(read);
6100 DECODE : S0(2); // any 2 decoders
6101 FPU : S3;
6102 %}
6103
6104 // Float reg-reg operation
6105 pipe_class fpu_reg_reg(regD dst, regD src) %{
6106 instruction_count(2);
6107 dst : S4(write);
6108 src : S3(read);
6109 DECODE : S0(2); // any 2 decoders
6110 FPU : S3;
6111 %}
6112
6113 // Float reg-reg operation
6114 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6115 instruction_count(3);
6116 dst : S4(write);
6117 src1 : S3(read);
6118 src2 : S3(read);
6119 DECODE : S0(3); // any 3 decoders
6120 FPU : S3(2);
6121 %}
6122
6123 // Float reg-reg operation
6124 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6125 instruction_count(4);
6126 dst : S4(write);
6127 src1 : S3(read);
6128 src2 : S3(read);
6129 src3 : S3(read);
6130 DECODE : S0(4); // any 3 decoders
6131 FPU : S3(2);
6132 %}
6133
6134 // Float reg-reg operation
6135 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6136 instruction_count(4);
6137 dst : S4(write);
6138 src1 : S3(read);
6139 src2 : S3(read);
6140 src3 : S3(read);
6141 DECODE : S1(3); // any 3 decoders
6142 D0 : S0; // Big decoder only
6143 FPU : S3(2);
6144 MEM : S3;
6145 %}
6146
6147 // Float reg-mem operation
6148 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6149 instruction_count(2);
6150 dst : S5(write);
6151 mem : S3(read);
6152 D0 : S0; // big decoder only
6153 DECODE : S1; // any decoder for FPU POP
6154 FPU : S4;
6155 MEM : S3; // any mem
6156 %}
6157
6158 // Float reg-mem operation
6159 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6160 instruction_count(3);
6161 dst : S5(write);
6162 src1 : S3(read);
6163 mem : S3(read);
6164 D0 : S0; // big decoder only
6165 DECODE : S1(2); // any decoder for FPU POP
6166 FPU : S4;
6167 MEM : S3; // any mem
6168 %}
6169
6170 // Float mem-reg operation
6171 pipe_class fpu_mem_reg(memory mem, regD src) %{
6172 instruction_count(2);
6173 src : S5(read);
6174 mem : S3(read);
6175 DECODE : S0; // any decoder for FPU PUSH
6176 D0 : S1; // big decoder only
6177 FPU : S4;
6178 MEM : S3; // any mem
6179 %}
6180
6181 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6182 instruction_count(3);
6183 src1 : S3(read);
6184 src2 : S3(read);
6185 mem : S3(read);
6186 DECODE : S0(2); // any decoder for FPU PUSH
6187 D0 : S1; // big decoder only
6188 FPU : S4;
6189 MEM : S3; // any mem
6190 %}
6191
6192 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6193 instruction_count(3);
6194 src1 : S3(read);
6195 src2 : S3(read);
6196 mem : S4(read);
6197 DECODE : S0; // any decoder for FPU PUSH
6198 D0 : S0(2); // big decoder only
6199 FPU : S4;
6200 MEM : S3(2); // any mem
6201 %}
6202
6203 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6204 instruction_count(2);
6205 src1 : S3(read);
6206 dst : S4(read);
6207 D0 : S0(2); // big decoder only
6208 MEM : S3(2); // any mem
6209 %}
6210
6211 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6212 instruction_count(3);
6213 src1 : S3(read);
6214 src2 : S3(read);
6215 dst : S4(read);
6216 D0 : S0(3); // big decoder only
6217 FPU : S4;
6218 MEM : S3(3); // any mem
6219 %}
6220
6221 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6222 instruction_count(3);
6223 src1 : S4(read);
6224 mem : S4(read);
6225 DECODE : S0; // any decoder for FPU PUSH
6226 D0 : S0(2); // big decoder only
6227 FPU : S4;
6228 MEM : S3(2); // any mem
6229 %}
6230
6231 // Float load constant
6232 pipe_class fpu_reg_con(regD dst) %{
6233 instruction_count(2);
6234 dst : S5(write);
6235 D0 : S0; // big decoder only for the load
6236 DECODE : S1; // any decoder for FPU POP
6237 FPU : S4;
6238 MEM : S3; // any mem
6239 %}
6240
6241 // Float load constant
6242 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6243 instruction_count(3);
6244 dst : S5(write);
6245 src : S3(read);
6246 D0 : S0; // big decoder only for the load
6247 DECODE : S1(2); // any decoder for FPU POP
6248 FPU : S4;
6249 MEM : S3; // any mem
6250 %}
6251
6252 // UnConditional branch
6253 pipe_class pipe_jmp( label labl ) %{
6254 single_instruction;
6255 BR : S3;
6256 %}
6257
6258 // Conditional branch
6259 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6260 single_instruction;
6261 cr : S1(read);
6262 BR : S3;
6263 %}
6264
6265 // Allocation idiom
6266 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6267 instruction_count(1); force_serialization;
6268 fixed_latency(6);
6269 heap_ptr : S3(read);
6270 DECODE : S0(3);
6271 D0 : S2;
6272 MEM : S3;
6273 ALU : S3(2);
6274 dst : S5(write);
6275 BR : S5;
6276 %}
6277
6278 // Generic big/slow expanded idiom
6279 pipe_class pipe_slow( ) %{
6280 instruction_count(10); multiple_bundles; force_serialization;
6281 fixed_latency(100);
6282 D0 : S0(2);
6283 MEM : S3(2);
6284 %}
6285
6286 // The real do-nothing guy
6287 pipe_class empty( ) %{
6288 instruction_count(0);
6289 %}
6290
6291 // Define the class for the Nop node
6292 define %{
6293 MachNop = empty;
6294 %}
6295
6296 %}
6297
6298 //----------INSTRUCTIONS-------------------------------------------------------
6299 //
6300 // match -- States which machine-independent subtree may be replaced
6301 // by this instruction.
6302 // ins_cost -- The estimated cost of this instruction is used by instruction
6303 // selection to identify a minimum cost tree of machine
6304 // instructions that matches a tree of machine-independent
6305 // instructions.
6306 // format -- A string providing the disassembly for this instruction.
6307 // The value of an instruction's operand may be inserted
6308 // by referring to it with a '$' prefix.
6309 // opcode -- Three instruction opcodes may be provided. These are referred
6310 // to within an encode class as $primary, $secondary, and $tertiary
6311 // respectively. The primary opcode is commonly used to
6312 // indicate the type of machine instruction, while secondary
6313 // and tertiary are often used for prefix options or addressing
6314 // modes.
6315 // ins_encode -- A list of encode classes with parameters. The encode class
6316 // name must have been defined in an 'enc_class' specification
6317 // in the encode section of the architecture description.
6318
6319 //----------BSWAP-Instruction--------------------------------------------------
6320 instruct bytes_reverse_int(eRegI dst) %{
6321 match(Set dst (ReverseBytesI dst));
6322
6323 format %{ "BSWAP $dst" %}
6324 opcode(0x0F, 0xC8);
6325 ins_encode( OpcP, OpcSReg(dst) );
6326 ins_pipe( ialu_reg );
6327 %}
6328
6329 instruct bytes_reverse_long(eRegL dst) %{
6330 match(Set dst (ReverseBytesL dst));
6331
6332 format %{ "BSWAP $dst.lo\n\t"
6333 "BSWAP $dst.hi\n\t"
6334 "XCHG $dst.lo $dst.hi" %}
6335
6336 ins_cost(125);
6337 ins_encode( bswap_long_bytes(dst) );
6338 ins_pipe( ialu_reg_reg);
6339 %}
6340
6341
6342 //----------Load/Store/Move Instructions---------------------------------------
6343 //----------Load Instructions--------------------------------------------------
6344 // Load Byte (8bit signed)
6345 instruct loadB(xRegI dst, memory mem) %{
6346 match(Set dst (LoadB mem));
6347
6348 ins_cost(125);
6349 format %{ "MOVSX8 $dst,$mem" %}
6350 opcode(0xBE, 0x0F);
6351 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6352 ins_pipe( ialu_reg_mem );
6353 %}
6354
6355 // Load Byte (8bit UNsigned)
6356 instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{
6357 match(Set dst (AndI (LoadB mem) bytemask));
6358
6359 ins_cost(125);
6360 format %{ "MOVZX8 $dst,$mem" %}
6361 opcode(0xB6, 0x0F);
6362 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6363 ins_pipe( ialu_reg_mem );
6364 %}
6365
6366 // Load Char (16bit unsigned)
6367 instruct loadC(eRegI dst, memory mem) %{
6368 match(Set dst (LoadC mem));
6369
6370 ins_cost(125);
6371 format %{ "MOVZX $dst,$mem" %}
6372 opcode(0xB7, 0x0F);
6373 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6374 ins_pipe( ialu_reg_mem );
6375 %}
6376
6377 // Load Integer
6378 instruct loadI(eRegI dst, memory mem) %{
6379 match(Set dst (LoadI mem));
6380
6381 ins_cost(125);
6382 format %{ "MOV $dst,$mem" %}
6383 opcode(0x8B);
6384 ins_encode( OpcP, RegMem(dst,mem));
6385 ins_pipe( ialu_reg_mem );
6386 %}
6387
6388 // Load Long. Cannot clobber address while loading, so restrict address
6389 // register to ESI
6390 instruct loadL(eRegL dst, load_long_memory mem) %{
6391 predicate(!((LoadLNode*)n)->require_atomic_access());
6392 match(Set dst (LoadL mem));
6393
6394 ins_cost(250);
6395 format %{ "MOV $dst.lo,$mem\n\t"
6396 "MOV $dst.hi,$mem+4" %}
6397 opcode(0x8B, 0x8B);
6398 ins_encode( OpcP, RegMem(dst,mem), OpcS, RegMem_Hi(dst,mem));
6399 ins_pipe( ialu_reg_long_mem );
6400 %}
6401
6402 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6403 // then store it down to the stack and reload on the int
6404 // side.
6405 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6406 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6407 match(Set dst (LoadL mem));
6408
6409 ins_cost(200);
6410 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6411 "FISTp $dst" %}
6412 ins_encode(enc_loadL_volatile(mem,dst));
6413 ins_pipe( fpu_reg_mem );
6414 %}
6415
6416 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6417 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6418 match(Set dst (LoadL mem));
6419 effect(TEMP tmp);
6420 ins_cost(180);
6421 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6422 "MOVSD $dst,$tmp" %}
6423 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6424 ins_pipe( pipe_slow );
6425 %}
6426
6427 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6428 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6429 match(Set dst (LoadL mem));
6430 effect(TEMP tmp);
6431 ins_cost(160);
6432 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6433 "MOVD $dst.lo,$tmp\n\t"
6434 "PSRLQ $tmp,32\n\t"
6435 "MOVD $dst.hi,$tmp" %}
6436 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6437 ins_pipe( pipe_slow );
6438 %}
6439
6440 // Load Range
6441 instruct loadRange(eRegI dst, memory mem) %{
6442 match(Set dst (LoadRange mem));
6443
6444 ins_cost(125);
6445 format %{ "MOV $dst,$mem" %}
6446 opcode(0x8B);
6447 ins_encode( OpcP, RegMem(dst,mem));
6448 ins_pipe( ialu_reg_mem );
6449 %}
6450
6451
6452 // Load Pointer
6453 instruct loadP(eRegP dst, memory mem) %{
6454 match(Set dst (LoadP mem));
6455
6456 ins_cost(125);
6457 format %{ "MOV $dst,$mem" %}
6458 opcode(0x8B);
6459 ins_encode( OpcP, RegMem(dst,mem));
6460 ins_pipe( ialu_reg_mem );
6461 %}
6462
6463 // Load Klass Pointer
6464 instruct loadKlass(eRegP dst, memory mem) %{
6465 match(Set dst (LoadKlass mem));
6466
6467 ins_cost(125);
6468 format %{ "MOV $dst,$mem" %}
6469 opcode(0x8B);
6470 ins_encode( OpcP, RegMem(dst,mem));
6471 ins_pipe( ialu_reg_mem );
6472 %}
6473
6474 // Load Short (16bit signed)
6475 instruct loadS(eRegI dst, memory mem) %{
6476 match(Set dst (LoadS mem));
6477
6478 ins_cost(125);
6479 format %{ "MOVSX $dst,$mem" %}
6480 opcode(0xBF, 0x0F);
6481 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6482 ins_pipe( ialu_reg_mem );
6483 %}
6484
6485 // Load Double
6486 instruct loadD(regD dst, memory mem) %{
6487 predicate(UseSSE<=1);
6488 match(Set dst (LoadD mem));
6489
6490 ins_cost(150);
6491 format %{ "FLD_D ST,$mem\n\t"
6492 "FSTP $dst" %}
6493 opcode(0xDD); /* DD /0 */
6494 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6495 Pop_Reg_D(dst) );
6496 ins_pipe( fpu_reg_mem );
6497 %}
6498
6499 // Load Double to XMM
6500 instruct loadXD(regXD dst, memory mem) %{
6501 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6502 match(Set dst (LoadD mem));
6503 ins_cost(145);
6504 format %{ "MOVSD $dst,$mem" %}
6505 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6506 ins_pipe( pipe_slow );
6507 %}
6508
6509 instruct loadXD_partial(regXD dst, memory mem) %{
6510 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6511 match(Set dst (LoadD mem));
6512 ins_cost(145);
6513 format %{ "MOVLPD $dst,$mem" %}
6514 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6515 ins_pipe( pipe_slow );
6516 %}
6517
6518 // Load to XMM register (single-precision floating point)
6519 // MOVSS instruction
6520 instruct loadX(regX dst, memory mem) %{
6521 predicate(UseSSE>=1);
6522 match(Set dst (LoadF mem));
6523 ins_cost(145);
6524 format %{ "MOVSS $dst,$mem" %}
6525 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6526 ins_pipe( pipe_slow );
6527 %}
6528
6529 // Load Float
6530 instruct loadF(regF dst, memory mem) %{
6531 predicate(UseSSE==0);
6532 match(Set dst (LoadF mem));
6533
6534 ins_cost(150);
6535 format %{ "FLD_S ST,$mem\n\t"
6536 "FSTP $dst" %}
6537 opcode(0xD9); /* D9 /0 */
6538 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6539 Pop_Reg_F(dst) );
6540 ins_pipe( fpu_reg_mem );
6541 %}
6542
6543 // Load Aligned Packed Byte to XMM register
6544 instruct loadA8B(regXD dst, memory mem) %{
6545 predicate(UseSSE>=1);
6546 match(Set dst (Load8B mem));
6547 ins_cost(125);
6548 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6549 ins_encode( movq_ld(dst, mem));
6550 ins_pipe( pipe_slow );
6551 %}
6552
6553 // Load Aligned Packed Short to XMM register
6554 instruct loadA4S(regXD dst, memory mem) %{
6555 predicate(UseSSE>=1);
6556 match(Set dst (Load4S mem));
6557 ins_cost(125);
6558 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6559 ins_encode( movq_ld(dst, mem));
6560 ins_pipe( pipe_slow );
6561 %}
6562
6563 // Load Aligned Packed Char to XMM register
6564 instruct loadA4C(regXD dst, memory mem) %{
6565 predicate(UseSSE>=1);
6566 match(Set dst (Load4C mem));
6567 ins_cost(125);
6568 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6569 ins_encode( movq_ld(dst, mem));
6570 ins_pipe( pipe_slow );
6571 %}
6572
6573 // Load Aligned Packed Integer to XMM register
6574 instruct load2IU(regXD dst, memory mem) %{
6575 predicate(UseSSE>=1);
6576 match(Set dst (Load2I mem));
6577 ins_cost(125);
6578 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6579 ins_encode( movq_ld(dst, mem));
6580 ins_pipe( pipe_slow );
6581 %}
6582
6583 // Load Aligned Packed Single to XMM
6584 instruct loadA2F(regXD dst, memory mem) %{
6585 predicate(UseSSE>=1);
6586 match(Set dst (Load2F mem));
6587 ins_cost(145);
6588 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6589 ins_encode( movq_ld(dst, mem));
6590 ins_pipe( pipe_slow );
6591 %}
6592
6593 // Load Effective Address
6594 instruct leaP8(eRegP dst, indOffset8 mem) %{
6595 match(Set dst mem);
6596
6597 ins_cost(110);
6598 format %{ "LEA $dst,$mem" %}
6599 opcode(0x8D);
6600 ins_encode( OpcP, RegMem(dst,mem));
6601 ins_pipe( ialu_reg_reg_fat );
6602 %}
6603
6604 instruct leaP32(eRegP dst, indOffset32 mem) %{
6605 match(Set dst mem);
6606
6607 ins_cost(110);
6608 format %{ "LEA $dst,$mem" %}
6609 opcode(0x8D);
6610 ins_encode( OpcP, RegMem(dst,mem));
6611 ins_pipe( ialu_reg_reg_fat );
6612 %}
6613
6614 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6615 match(Set dst mem);
6616
6617 ins_cost(110);
6618 format %{ "LEA $dst,$mem" %}
6619 opcode(0x8D);
6620 ins_encode( OpcP, RegMem(dst,mem));
6621 ins_pipe( ialu_reg_reg_fat );
6622 %}
6623
6624 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6625 match(Set dst mem);
6626
6627 ins_cost(110);
6628 format %{ "LEA $dst,$mem" %}
6629 opcode(0x8D);
6630 ins_encode( OpcP, RegMem(dst,mem));
6631 ins_pipe( ialu_reg_reg_fat );
6632 %}
6633
6634 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6635 match(Set dst mem);
6636
6637 ins_cost(110);
6638 format %{ "LEA $dst,$mem" %}
6639 opcode(0x8D);
6640 ins_encode( OpcP, RegMem(dst,mem));
6641 ins_pipe( ialu_reg_reg_fat );
6642 %}
6643
6644 // Load Constant
6645 instruct loadConI(eRegI dst, immI src) %{
6646 match(Set dst src);
6647
6648 format %{ "MOV $dst,$src" %}
6649 ins_encode( LdImmI(dst, src) );
6650 ins_pipe( ialu_reg_fat );
6651 %}
6652
6653 // Load Constant zero
6654 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6655 match(Set dst src);
6656 effect(KILL cr);
6657
6658 ins_cost(50);
6659 format %{ "XOR $dst,$dst" %}
6660 opcode(0x33); /* + rd */
6661 ins_encode( OpcP, RegReg( dst, dst ) );
6662 ins_pipe( ialu_reg );
6663 %}
6664
6665 instruct loadConP(eRegP dst, immP src) %{
6666 match(Set dst src);
6667
6668 format %{ "MOV $dst,$src" %}
6669 opcode(0xB8); /* + rd */
6670 ins_encode( LdImmP(dst, src) );
6671 ins_pipe( ialu_reg_fat );
6672 %}
6673
6674 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6675 match(Set dst src);
6676 effect(KILL cr);
6677 ins_cost(200);
6678 format %{ "MOV $dst.lo,$src.lo\n\t"
6679 "MOV $dst.hi,$src.hi" %}
6680 opcode(0xB8);
6681 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6682 ins_pipe( ialu_reg_long_fat );
6683 %}
6684
6685 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6686 match(Set dst src);
6687 effect(KILL cr);
6688 ins_cost(150);
6689 format %{ "XOR $dst.lo,$dst.lo\n\t"
6690 "XOR $dst.hi,$dst.hi" %}
6691 opcode(0x33,0x33);
6692 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6693 ins_pipe( ialu_reg_long );
6694 %}
6695
6696 // The instruction usage is guarded by predicate in operand immF().
6697 instruct loadConF(regF dst, immF src) %{
6698 match(Set dst src);
6699 ins_cost(125);
6700
6701 format %{ "FLD_S ST,$src\n\t"
6702 "FSTP $dst" %}
6703 opcode(0xD9, 0x00); /* D9 /0 */
6704 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
6705 ins_pipe( fpu_reg_con );
6706 %}
6707
6708 // The instruction usage is guarded by predicate in operand immXF().
6709 instruct loadConX(regX dst, immXF con) %{
6710 match(Set dst con);
6711 ins_cost(125);
6712 format %{ "MOVSS $dst,[$con]" %}
6713 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
6714 ins_pipe( pipe_slow );
6715 %}
6716
6717 // The instruction usage is guarded by predicate in operand immXF0().
6718 instruct loadConX0(regX dst, immXF0 src) %{
6719 match(Set dst src);
6720 ins_cost(100);
6721 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6722 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6723 ins_pipe( pipe_slow );
6724 %}
6725
6726 // The instruction usage is guarded by predicate in operand immD().
6727 instruct loadConD(regD dst, immD src) %{
6728 match(Set dst src);
6729 ins_cost(125);
6730
6731 format %{ "FLD_D ST,$src\n\t"
6732 "FSTP $dst" %}
6733 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
6734 ins_pipe( fpu_reg_con );
6735 %}
6736
6737 // The instruction usage is guarded by predicate in operand immXD().
6738 instruct loadConXD(regXD dst, immXD con) %{
6739 match(Set dst con);
6740 ins_cost(125);
6741 format %{ "MOVSD $dst,[$con]" %}
6742 ins_encode(load_conXD(dst, con));
6743 ins_pipe( pipe_slow );
6744 %}
6745
6746 // The instruction usage is guarded by predicate in operand immXD0().
6747 instruct loadConXD0(regXD dst, immXD0 src) %{
6748 match(Set dst src);
6749 ins_cost(100);
6750 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6751 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6752 ins_pipe( pipe_slow );
6753 %}
6754
6755 // Load Stack Slot
6756 instruct loadSSI(eRegI dst, stackSlotI src) %{
6757 match(Set dst src);
6758 ins_cost(125);
6759
6760 format %{ "MOV $dst,$src" %}
6761 opcode(0x8B);
6762 ins_encode( OpcP, RegMem(dst,src));
6763 ins_pipe( ialu_reg_mem );
6764 %}
6765
6766 instruct loadSSL(eRegL dst, stackSlotL src) %{
6767 match(Set dst src);
6768
6769 ins_cost(200);
6770 format %{ "MOV $dst,$src.lo\n\t"
6771 "MOV $dst+4,$src.hi" %}
6772 opcode(0x8B, 0x8B);
6773 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6774 ins_pipe( ialu_mem_long_reg );
6775 %}
6776
6777 // Load Stack Slot
6778 instruct loadSSP(eRegP dst, stackSlotP src) %{
6779 match(Set dst src);
6780 ins_cost(125);
6781
6782 format %{ "MOV $dst,$src" %}
6783 opcode(0x8B);
6784 ins_encode( OpcP, RegMem(dst,src));
6785 ins_pipe( ialu_reg_mem );
6786 %}
6787
6788 // Load Stack Slot
6789 instruct loadSSF(regF dst, stackSlotF src) %{
6790 match(Set dst src);
6791 ins_cost(125);
6792
6793 format %{ "FLD_S $src\n\t"
6794 "FSTP $dst" %}
6795 opcode(0xD9); /* D9 /0, FLD m32real */
6796 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6797 Pop_Reg_F(dst) );
6798 ins_pipe( fpu_reg_mem );
6799 %}
6800
6801 // Load Stack Slot
6802 instruct loadSSD(regD dst, stackSlotD src) %{
6803 match(Set dst src);
6804 ins_cost(125);
6805
6806 format %{ "FLD_D $src\n\t"
6807 "FSTP $dst" %}
6808 opcode(0xDD); /* DD /0, FLD m64real */
6809 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6810 Pop_Reg_D(dst) );
6811 ins_pipe( fpu_reg_mem );
6812 %}
6813
6814 // Prefetch instructions.
6815 // Must be safe to execute with invalid address (cannot fault).
6816
6817 instruct prefetchr0( memory mem ) %{
6818 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
6819 match(PrefetchRead mem);
6820 ins_cost(0);
6821 size(0);
6822 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6823 ins_encode();
6824 ins_pipe(empty);
6825 %}
6826
6827 instruct prefetchr( memory mem ) %{
6828 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
6829 match(PrefetchRead mem);
6830 ins_cost(100);
6831
6832 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6833 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
6834 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6835 ins_pipe(ialu_mem);
6836 %}
6837
6838 instruct prefetchrNTA( memory mem ) %{
6839 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6840 match(PrefetchRead mem);
6841 ins_cost(100);
6842
6843 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6844 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6845 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6846 ins_pipe(ialu_mem);
6847 %}
6848
6849 instruct prefetchrT0( memory mem ) %{
6850 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6851 match(PrefetchRead mem);
6852 ins_cost(100);
6853
6854 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6855 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6856 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6857 ins_pipe(ialu_mem);
6858 %}
6859
6860 instruct prefetchrT2( memory mem ) %{
6861 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6862 match(PrefetchRead mem);
6863 ins_cost(100);
6864
6865 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6866 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6867 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
6868 ins_pipe(ialu_mem);
6869 %}
6870
6871 instruct prefetchw0( memory mem ) %{
6872 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
6873 match(PrefetchWrite mem);
6874 ins_cost(0);
6875 size(0);
6876 format %{ "Prefetch (non-SSE is empty encoding)" %}
6877 ins_encode();
6878 ins_pipe(empty);
6879 %}
6880
6881 instruct prefetchw( memory mem ) %{
6882 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
6883 match( PrefetchWrite mem );
6884 ins_cost(100);
6885
6886 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6887 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6888 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6889 ins_pipe(ialu_mem);
6890 %}
6891
6892 instruct prefetchwNTA( memory mem ) %{
6893 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6894 match(PrefetchWrite mem);
6895 ins_cost(100);
6896
6897 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6898 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6899 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6900 ins_pipe(ialu_mem);
6901 %}
6902
6903 instruct prefetchwT0( memory mem ) %{
6904 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6905 match(PrefetchWrite mem);
6906 ins_cost(100);
6907
6908 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
6909 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6910 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6911 ins_pipe(ialu_mem);
6912 %}
6913
6914 instruct prefetchwT2( memory mem ) %{
6915 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6916 match(PrefetchWrite mem);
6917 ins_cost(100);
6918
6919 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
6920 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6921 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
6922 ins_pipe(ialu_mem);
6923 %}
6924
6925 //----------Store Instructions-------------------------------------------------
6926
6927 // Store Byte
6928 instruct storeB(memory mem, xRegI src) %{
6929 match(Set mem (StoreB mem src));
6930
6931 ins_cost(125);
6932 format %{ "MOV8 $mem,$src" %}
6933 opcode(0x88);
6934 ins_encode( OpcP, RegMem( src, mem ) );
6935 ins_pipe( ialu_mem_reg );
6936 %}
6937
6938 // Store Char/Short
6939 instruct storeC(memory mem, eRegI src) %{
6940 match(Set mem (StoreC mem src));
6941
6942 ins_cost(125);
6943 format %{ "MOV16 $mem,$src" %}
6944 opcode(0x89, 0x66);
6945 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6946 ins_pipe( ialu_mem_reg );
6947 %}
6948
6949 // Store Integer
6950 instruct storeI(memory mem, eRegI src) %{
6951 match(Set mem (StoreI mem src));
6952
6953 ins_cost(125);
6954 format %{ "MOV $mem,$src" %}
6955 opcode(0x89);
6956 ins_encode( OpcP, RegMem( src, mem ) );
6957 ins_pipe( ialu_mem_reg );
6958 %}
6959
6960 // Store Long
6961 instruct storeL(long_memory mem, eRegL src) %{
6962 predicate(!((StoreLNode*)n)->require_atomic_access());
6963 match(Set mem (StoreL mem src));
6964
6965 ins_cost(200);
6966 format %{ "MOV $mem,$src.lo\n\t"
6967 "MOV $mem+4,$src.hi" %}
6968 opcode(0x89, 0x89);
6969 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6970 ins_pipe( ialu_mem_long_reg );
6971 %}
6972
6973 // Volatile Store Long. Must be atomic, so move it into
6974 // the FP TOS and then do a 64-bit FIST. Has to probe the
6975 // target address before the store (for null-ptr checks)
6976 // so the memory operand is used twice in the encoding.
6977 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6978 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6979 match(Set mem (StoreL mem src));
6980 effect( KILL cr );
6981 ins_cost(400);
6982 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6983 "FILD $src\n\t"
6984 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6985 opcode(0x3B);
6986 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6987 ins_pipe( fpu_reg_mem );
6988 %}
6989
6990 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
6991 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6992 match(Set mem (StoreL mem src));
6993 effect( TEMP tmp, KILL cr );
6994 ins_cost(380);
6995 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6996 "MOVSD $tmp,$src\n\t"
6997 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6998 opcode(0x3B);
6999 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7000 ins_pipe( pipe_slow );
7001 %}
7002
7003 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7004 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7005 match(Set mem (StoreL mem src));
7006 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7007 ins_cost(360);
7008 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7009 "MOVD $tmp,$src.lo\n\t"
7010 "MOVD $tmp2,$src.hi\n\t"
7011 "PUNPCKLDQ $tmp,$tmp2\n\t"
7012 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7013 opcode(0x3B);
7014 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7015 ins_pipe( pipe_slow );
7016 %}
7017
7018 // Store Pointer; for storing unknown oops and raw pointers
7019 instruct storeP(memory mem, anyRegP src) %{
7020 match(Set mem (StoreP mem src));
7021
7022 ins_cost(125);
7023 format %{ "MOV $mem,$src" %}
7024 opcode(0x89);
7025 ins_encode( OpcP, RegMem( src, mem ) );
7026 ins_pipe( ialu_mem_reg );
7027 %}
7028
7029 // Store Integer Immediate
7030 instruct storeImmI(memory mem, immI src) %{
7031 match(Set mem (StoreI mem src));
7032
7033 ins_cost(150);
7034 format %{ "MOV $mem,$src" %}
7035 opcode(0xC7); /* C7 /0 */
7036 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7037 ins_pipe( ialu_mem_imm );
7038 %}
7039
7040 // Store Short/Char Immediate
7041 instruct storeImmI16(memory mem, immI16 src) %{
7042 predicate(UseStoreImmI16);
7043 match(Set mem (StoreC mem src));
7044
7045 ins_cost(150);
7046 format %{ "MOV16 $mem,$src" %}
7047 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7048 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7049 ins_pipe( ialu_mem_imm );
7050 %}
7051
7052 // Store Pointer Immediate; null pointers or constant oops that do not
7053 // need card-mark barriers.
7054 instruct storeImmP(memory mem, immP src) %{
7055 match(Set mem (StoreP mem src));
7056
7057 ins_cost(150);
7058 format %{ "MOV $mem,$src" %}
7059 opcode(0xC7); /* C7 /0 */
7060 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7061 ins_pipe( ialu_mem_imm );
7062 %}
7063
7064 // Store Byte Immediate
7065 instruct storeImmB(memory mem, immI8 src) %{
7066 match(Set mem (StoreB mem src));
7067
7068 ins_cost(150);
7069 format %{ "MOV8 $mem,$src" %}
7070 opcode(0xC6); /* C6 /0 */
7071 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7072 ins_pipe( ialu_mem_imm );
7073 %}
7074
7075 // Store Aligned Packed Byte XMM register to memory
7076 instruct storeA8B(memory mem, regXD src) %{
7077 predicate(UseSSE>=1);
7078 match(Set mem (Store8B mem src));
7079 ins_cost(145);
7080 format %{ "MOVQ $mem,$src\t! packed8B" %}
7081 ins_encode( movq_st(mem, src));
7082 ins_pipe( pipe_slow );
7083 %}
7084
7085 // Store Aligned Packed Char/Short XMM register to memory
7086 instruct storeA4C(memory mem, regXD src) %{
7087 predicate(UseSSE>=1);
7088 match(Set mem (Store4C mem src));
7089 ins_cost(145);
7090 format %{ "MOVQ $mem,$src\t! packed4C" %}
7091 ins_encode( movq_st(mem, src));
7092 ins_pipe( pipe_slow );
7093 %}
7094
7095 // Store Aligned Packed Integer XMM register to memory
7096 instruct storeA2I(memory mem, regXD src) %{
7097 predicate(UseSSE>=1);
7098 match(Set mem (Store2I mem src));
7099 ins_cost(145);
7100 format %{ "MOVQ $mem,$src\t! packed2I" %}
7101 ins_encode( movq_st(mem, src));
7102 ins_pipe( pipe_slow );
7103 %}
7104
7105 // Store CMS card-mark Immediate
7106 instruct storeImmCM(memory mem, immI8 src) %{
7107 match(Set mem (StoreCM mem src));
7108
7109 ins_cost(150);
7110 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7111 opcode(0xC6); /* C6 /0 */
7112 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7113 ins_pipe( ialu_mem_imm );
7114 %}
7115
7116 // Store Double
7117 instruct storeD( memory mem, regDPR1 src) %{
7118 predicate(UseSSE<=1);
7119 match(Set mem (StoreD mem src));
7120
7121 ins_cost(100);
7122 format %{ "FST_D $mem,$src" %}
7123 opcode(0xDD); /* DD /2 */
7124 ins_encode( enc_FP_store(mem,src) );
7125 ins_pipe( fpu_mem_reg );
7126 %}
7127
7128 // Store double does rounding on x86
7129 instruct storeD_rounded( memory mem, regDPR1 src) %{
7130 predicate(UseSSE<=1);
7131 match(Set mem (StoreD mem (RoundDouble src)));
7132
7133 ins_cost(100);
7134 format %{ "FST_D $mem,$src\t# round" %}
7135 opcode(0xDD); /* DD /2 */
7136 ins_encode( enc_FP_store(mem,src) );
7137 ins_pipe( fpu_mem_reg );
7138 %}
7139
7140 // Store XMM register to memory (double-precision floating points)
7141 // MOVSD instruction
7142 instruct storeXD(memory mem, regXD src) %{
7143 predicate(UseSSE>=2);
7144 match(Set mem (StoreD mem src));
7145 ins_cost(95);
7146 format %{ "MOVSD $mem,$src" %}
7147 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7148 ins_pipe( pipe_slow );
7149 %}
7150
7151 // Store XMM register to memory (single-precision floating point)
7152 // MOVSS instruction
7153 instruct storeX(memory mem, regX src) %{
7154 predicate(UseSSE>=1);
7155 match(Set mem (StoreF mem src));
7156 ins_cost(95);
7157 format %{ "MOVSS $mem,$src" %}
7158 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7159 ins_pipe( pipe_slow );
7160 %}
7161
7162 // Store Aligned Packed Single Float XMM register to memory
7163 instruct storeA2F(memory mem, regXD src) %{
7164 predicate(UseSSE>=1);
7165 match(Set mem (Store2F mem src));
7166 ins_cost(145);
7167 format %{ "MOVQ $mem,$src\t! packed2F" %}
7168 ins_encode( movq_st(mem, src));
7169 ins_pipe( pipe_slow );
7170 %}
7171
7172 // Store Float
7173 instruct storeF( memory mem, regFPR1 src) %{
7174 predicate(UseSSE==0);
7175 match(Set mem (StoreF mem src));
7176
7177 ins_cost(100);
7178 format %{ "FST_S $mem,$src" %}
7179 opcode(0xD9); /* D9 /2 */
7180 ins_encode( enc_FP_store(mem,src) );
7181 ins_pipe( fpu_mem_reg );
7182 %}
7183
7184 // Store Float does rounding on x86
7185 instruct storeF_rounded( memory mem, regFPR1 src) %{
7186 predicate(UseSSE==0);
7187 match(Set mem (StoreF mem (RoundFloat src)));
7188
7189 ins_cost(100);
7190 format %{ "FST_S $mem,$src\t# round" %}
7191 opcode(0xD9); /* D9 /2 */
7192 ins_encode( enc_FP_store(mem,src) );
7193 ins_pipe( fpu_mem_reg );
7194 %}
7195
7196 // Store Float does rounding on x86
7197 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7198 predicate(UseSSE<=1);
7199 match(Set mem (StoreF mem (ConvD2F src)));
7200
7201 ins_cost(100);
7202 format %{ "FST_S $mem,$src\t# D-round" %}
7203 opcode(0xD9); /* D9 /2 */
7204 ins_encode( enc_FP_store(mem,src) );
7205 ins_pipe( fpu_mem_reg );
7206 %}
7207
7208 // Store immediate Float value (it is faster than store from FPU register)
7209 // The instruction usage is guarded by predicate in operand immF().
7210 instruct storeF_imm( memory mem, immF src) %{
7211 match(Set mem (StoreF mem src));
7212
7213 ins_cost(50);
7214 format %{ "MOV $mem,$src\t# store float" %}
7215 opcode(0xC7); /* C7 /0 */
7216 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7217 ins_pipe( ialu_mem_imm );
7218 %}
7219
7220 // Store immediate Float value (it is faster than store from XMM register)
7221 // The instruction usage is guarded by predicate in operand immXF().
7222 instruct storeX_imm( memory mem, immXF src) %{
7223 match(Set mem (StoreF mem src));
7224
7225 ins_cost(50);
7226 format %{ "MOV $mem,$src\t# store float" %}
7227 opcode(0xC7); /* C7 /0 */
7228 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7229 ins_pipe( ialu_mem_imm );
7230 %}
7231
7232 // Store Integer to stack slot
7233 instruct storeSSI(stackSlotI dst, eRegI src) %{
7234 match(Set dst src);
7235
7236 ins_cost(100);
7237 format %{ "MOV $dst,$src" %}
7238 opcode(0x89);
7239 ins_encode( OpcPRegSS( dst, src ) );
7240 ins_pipe( ialu_mem_reg );
7241 %}
7242
7243 // Store Integer to stack slot
7244 instruct storeSSP(stackSlotP dst, eRegP src) %{
7245 match(Set dst src);
7246
7247 ins_cost(100);
7248 format %{ "MOV $dst,$src" %}
7249 opcode(0x89);
7250 ins_encode( OpcPRegSS( dst, src ) );
7251 ins_pipe( ialu_mem_reg );
7252 %}
7253
7254 // Store Long to stack slot
7255 instruct storeSSL(stackSlotL dst, eRegL src) %{
7256 match(Set dst src);
7257
7258 ins_cost(200);
7259 format %{ "MOV $dst,$src.lo\n\t"
7260 "MOV $dst+4,$src.hi" %}
7261 opcode(0x89, 0x89);
7262 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7263 ins_pipe( ialu_mem_long_reg );
7264 %}
7265
7266 //----------MemBar Instructions-----------------------------------------------
7267 // Memory barrier flavors
7268
7269 instruct membar_acquire() %{
7270 match(MemBarAcquire);
7271 ins_cost(400);
7272
7273 size(0);
7274 format %{ "MEMBAR-acquire" %}
7275 ins_encode( enc_membar_acquire );
7276 ins_pipe(pipe_slow);
7277 %}
7278
7279 instruct membar_acquire_lock() %{
7280 match(MemBarAcquire);
7281 predicate(Matcher::prior_fast_lock(n));
7282 ins_cost(0);
7283
7284 size(0);
7285 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7286 ins_encode( );
7287 ins_pipe(empty);
7288 %}
7289
7290 instruct membar_release() %{
7291 match(MemBarRelease);
7292 ins_cost(400);
7293
7294 size(0);
7295 format %{ "MEMBAR-release" %}
7296 ins_encode( enc_membar_release );
7297 ins_pipe(pipe_slow);
7298 %}
7299
7300 instruct membar_release_lock() %{
7301 match(MemBarRelease);
7302 predicate(Matcher::post_fast_unlock(n));
7303 ins_cost(0);
7304
7305 size(0);
7306 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7307 ins_encode( );
7308 ins_pipe(empty);
7309 %}
7310
7311 instruct membar_volatile() %{
7312 match(MemBarVolatile);
7313 ins_cost(400);
7314
7315 format %{ "MEMBAR-volatile" %}
7316 ins_encode( enc_membar_volatile );
7317 ins_pipe(pipe_slow);
7318 %}
7319
7320 instruct unnecessary_membar_volatile() %{
7321 match(MemBarVolatile);
7322 predicate(Matcher::post_store_load_barrier(n));
7323 ins_cost(0);
7324
7325 size(0);
7326 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7327 ins_encode( );
7328 ins_pipe(empty);
7329 %}
7330
7331 //----------Move Instructions--------------------------------------------------
7332 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7333 match(Set dst (CastX2P src));
7334 format %{ "# X2P $dst, $src" %}
7335 ins_encode( /*empty encoding*/ );
7336 ins_cost(0);
7337 ins_pipe(empty);
7338 %}
7339
7340 instruct castP2X(eRegI dst, eRegP src ) %{
7341 match(Set dst (CastP2X src));
7342 ins_cost(50);
7343 format %{ "MOV $dst, $src\t# CastP2X" %}
7344 ins_encode( enc_Copy( dst, src) );
7345 ins_pipe( ialu_reg_reg );
7346 %}
7347
7348 //----------Conditional Move---------------------------------------------------
7349 // Conditional move
7350 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7351 predicate(VM_Version::supports_cmov() );
7352 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7353 ins_cost(200);
7354 format %{ "CMOV$cop $dst,$src" %}
7355 opcode(0x0F,0x40);
7356 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7357 ins_pipe( pipe_cmov_reg );
7358 %}
7359
7360 instruct cmovI_regU( eRegI dst, eRegI src, eFlagsRegU cr, cmpOpU cop ) %{
7361 predicate(VM_Version::supports_cmov() );
7362 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7363 ins_cost(200);
7364 format %{ "CMOV$cop $dst,$src" %}
7365 opcode(0x0F,0x40);
7366 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7367 ins_pipe( pipe_cmov_reg );
7368 %}
7369
7370 // Conditional move
7371 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7372 predicate(VM_Version::supports_cmov() );
7373 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7374 ins_cost(250);
7375 format %{ "CMOV$cop $dst,$src" %}
7376 opcode(0x0F,0x40);
7377 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7378 ins_pipe( pipe_cmov_mem );
7379 %}
7380
7381 // Conditional move
7382 instruct cmovI_memu(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7383 predicate(VM_Version::supports_cmov() );
7384 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7385 ins_cost(250);
7386 format %{ "CMOV$cop $dst,$src" %}
7387 opcode(0x0F,0x40);
7388 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7389 ins_pipe( pipe_cmov_mem );
7390 %}
7391
7392 // Conditional move
7393 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7394 predicate(VM_Version::supports_cmov() );
7395 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7396 ins_cost(200);
7397 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7398 opcode(0x0F,0x40);
7399 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7400 ins_pipe( pipe_cmov_reg );
7401 %}
7402
7403 // Conditional move (non-P6 version)
7404 // Note: a CMoveP is generated for stubs and native wrappers
7405 // regardless of whether we are on a P6, so we
7406 // emulate a cmov here
7407 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7408 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7409 ins_cost(300);
7410 format %{ "Jn$cop skip\n\t"
7411 "MOV $dst,$src\t# pointer\n"
7412 "skip:" %}
7413 opcode(0x8b);
7414 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7415 ins_pipe( pipe_cmov_reg );
7416 %}
7417
7418 // Conditional move
7419 instruct cmovP_regU(eRegP dst, eRegP src, eFlagsRegU cr, cmpOpU cop ) %{
7420 predicate(VM_Version::supports_cmov() );
7421 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7422 ins_cost(200);
7423 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7424 opcode(0x0F,0x40);
7425 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7426 ins_pipe( pipe_cmov_reg );
7427 %}
7428
7429 // DISABLED: Requires the ADLC to emit a bottom_type call that
7430 // correctly meets the two pointer arguments; one is an incoming
7431 // register but the other is a memory operand. ALSO appears to
7432 // be buggy with implicit null checks.
7433 //
7434 //// Conditional move
7435 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7436 // predicate(VM_Version::supports_cmov() );
7437 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7438 // ins_cost(250);
7439 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7440 // opcode(0x0F,0x40);
7441 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7442 // ins_pipe( pipe_cmov_mem );
7443 //%}
7444 //
7445 //// Conditional move
7446 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7447 // predicate(VM_Version::supports_cmov() );
7448 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7449 // ins_cost(250);
7450 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7451 // opcode(0x0F,0x40);
7452 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7453 // ins_pipe( pipe_cmov_mem );
7454 //%}
7455
7456 // Conditional move
7457 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7458 predicate(UseSSE<=1);
7459 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7460 ins_cost(200);
7461 format %{ "FCMOV$cop $dst,$src\t# double" %}
7462 opcode(0xDA);
7463 ins_encode( enc_cmov_d(cop,src) );
7464 ins_pipe( pipe_cmovD_reg );
7465 %}
7466
7467 // Conditional move
7468 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7469 predicate(UseSSE==0);
7470 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7471 ins_cost(200);
7472 format %{ "FCMOV$cop $dst,$src\t# float" %}
7473 opcode(0xDA);
7474 ins_encode( enc_cmov_d(cop,src) );
7475 ins_pipe( pipe_cmovD_reg );
7476 %}
7477
7478 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7479 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7480 predicate(UseSSE<=1);
7481 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7482 ins_cost(200);
7483 format %{ "Jn$cop skip\n\t"
7484 "MOV $dst,$src\t# double\n"
7485 "skip:" %}
7486 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7487 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7488 ins_pipe( pipe_cmovD_reg );
7489 %}
7490
7491 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7492 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7493 predicate(UseSSE==0);
7494 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7495 ins_cost(200);
7496 format %{ "Jn$cop skip\n\t"
7497 "MOV $dst,$src\t# float\n"
7498 "skip:" %}
7499 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7500 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7501 ins_pipe( pipe_cmovD_reg );
7502 %}
7503
7504 // No CMOVE with SSE/SSE2
7505 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7506 predicate (UseSSE>=1);
7507 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7508 ins_cost(200);
7509 format %{ "Jn$cop skip\n\t"
7510 "MOVSS $dst,$src\t# float\n"
7511 "skip:" %}
7512 ins_encode %{
7513 Label skip;
7514 // Invert sense of branch from sense of CMOV
7515 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7516 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7517 __ bind(skip);
7518 %}
7519 ins_pipe( pipe_slow );
7520 %}
7521
7522 // No CMOVE with SSE/SSE2
7523 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7524 predicate (UseSSE>=2);
7525 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7526 ins_cost(200);
7527 format %{ "Jn$cop skip\n\t"
7528 "MOVSD $dst,$src\t# float\n"
7529 "skip:" %}
7530 ins_encode %{
7531 Label skip;
7532 // Invert sense of branch from sense of CMOV
7533 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7534 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7535 __ bind(skip);
7536 %}
7537 ins_pipe( pipe_slow );
7538 %}
7539
7540 // unsigned version
7541 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7542 predicate (UseSSE>=1);
7543 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7544 ins_cost(200);
7545 format %{ "Jn$cop skip\n\t"
7546 "MOVSS $dst,$src\t# float\n"
7547 "skip:" %}
7548 ins_encode %{
7549 Label skip;
7550 // Invert sense of branch from sense of CMOV
7551 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7552 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7553 __ bind(skip);
7554 %}
7555 ins_pipe( pipe_slow );
7556 %}
7557
7558 // unsigned version
7559 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7560 predicate (UseSSE>=2);
7561 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7562 ins_cost(200);
7563 format %{ "Jn$cop skip\n\t"
7564 "MOVSD $dst,$src\t# float\n"
7565 "skip:" %}
7566 ins_encode %{
7567 Label skip;
7568 // Invert sense of branch from sense of CMOV
7569 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7570 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7571 __ bind(skip);
7572 %}
7573 ins_pipe( pipe_slow );
7574 %}
7575
7576 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7577 predicate(VM_Version::supports_cmov() );
7578 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7579 ins_cost(200);
7580 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7581 "CMOV$cop $dst.hi,$src.hi" %}
7582 opcode(0x0F,0x40);
7583 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7584 ins_pipe( pipe_cmov_reg_long );
7585 %}
7586
7587 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7588 predicate(VM_Version::supports_cmov() );
7589 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7590 ins_cost(200);
7591 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7592 "CMOV$cop $dst.hi,$src.hi" %}
7593 opcode(0x0F,0x40);
7594 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7595 ins_pipe( pipe_cmov_reg_long );
7596 %}
7597
7598 //----------Arithmetic Instructions--------------------------------------------
7599 //----------Addition Instructions----------------------------------------------
7600 // Integer Addition Instructions
7601 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7602 match(Set dst (AddI dst src));
7603 effect(KILL cr);
7604
7605 size(2);
7606 format %{ "ADD $dst,$src" %}
7607 opcode(0x03);
7608 ins_encode( OpcP, RegReg( dst, src) );
7609 ins_pipe( ialu_reg_reg );
7610 %}
7611
7612 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7613 match(Set dst (AddI dst src));
7614 effect(KILL cr);
7615
7616 format %{ "ADD $dst,$src" %}
7617 opcode(0x81, 0x00); /* /0 id */
7618 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7619 ins_pipe( ialu_reg );
7620 %}
7621
7622 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7623 predicate(UseIncDec);
7624 match(Set dst (AddI dst src));
7625 effect(KILL cr);
7626
7627 size(1);
7628 format %{ "INC $dst" %}
7629 opcode(0x40); /* */
7630 ins_encode( Opc_plus( primary, dst ) );
7631 ins_pipe( ialu_reg );
7632 %}
7633
7634 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7635 match(Set dst (AddI src0 src1));
7636 ins_cost(110);
7637
7638 format %{ "LEA $dst,[$src0 + $src1]" %}
7639 opcode(0x8D); /* 0x8D /r */
7640 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7641 ins_pipe( ialu_reg_reg );
7642 %}
7643
7644 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7645 match(Set dst (AddP src0 src1));
7646 ins_cost(110);
7647
7648 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7649 opcode(0x8D); /* 0x8D /r */
7650 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7651 ins_pipe( ialu_reg_reg );
7652 %}
7653
7654 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7655 predicate(UseIncDec);
7656 match(Set dst (AddI dst src));
7657 effect(KILL cr);
7658
7659 size(1);
7660 format %{ "DEC $dst" %}
7661 opcode(0x48); /* */
7662 ins_encode( Opc_plus( primary, dst ) );
7663 ins_pipe( ialu_reg );
7664 %}
7665
7666 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7667 match(Set dst (AddP dst src));
7668 effect(KILL cr);
7669
7670 size(2);
7671 format %{ "ADD $dst,$src" %}
7672 opcode(0x03);
7673 ins_encode( OpcP, RegReg( dst, src) );
7674 ins_pipe( ialu_reg_reg );
7675 %}
7676
7677 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7678 match(Set dst (AddP dst src));
7679 effect(KILL cr);
7680
7681 format %{ "ADD $dst,$src" %}
7682 opcode(0x81,0x00); /* Opcode 81 /0 id */
7683 // ins_encode( RegImm( dst, src) );
7684 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7685 ins_pipe( ialu_reg );
7686 %}
7687
7688 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7689 match(Set dst (AddI dst (LoadI src)));
7690 effect(KILL cr);
7691
7692 ins_cost(125);
7693 format %{ "ADD $dst,$src" %}
7694 opcode(0x03);
7695 ins_encode( OpcP, RegMem( dst, src) );
7696 ins_pipe( ialu_reg_mem );
7697 %}
7698
7699 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7700 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7701 effect(KILL cr);
7702
7703 ins_cost(150);
7704 format %{ "ADD $dst,$src" %}
7705 opcode(0x01); /* Opcode 01 /r */
7706 ins_encode( OpcP, RegMem( src, dst ) );
7707 ins_pipe( ialu_mem_reg );
7708 %}
7709
7710 // Add Memory with Immediate
7711 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7712 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7713 effect(KILL cr);
7714
7715 ins_cost(125);
7716 format %{ "ADD $dst,$src" %}
7717 opcode(0x81); /* Opcode 81 /0 id */
7718 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7719 ins_pipe( ialu_mem_imm );
7720 %}
7721
7722 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7723 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7724 effect(KILL cr);
7725
7726 ins_cost(125);
7727 format %{ "INC $dst" %}
7728 opcode(0xFF); /* Opcode FF /0 */
7729 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7730 ins_pipe( ialu_mem_imm );
7731 %}
7732
7733 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7734 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7735 effect(KILL cr);
7736
7737 ins_cost(125);
7738 format %{ "DEC $dst" %}
7739 opcode(0xFF); /* Opcode FF /1 */
7740 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7741 ins_pipe( ialu_mem_imm );
7742 %}
7743
7744
7745 instruct checkCastPP( eRegP dst ) %{
7746 match(Set dst (CheckCastPP dst));
7747
7748 size(0);
7749 format %{ "#checkcastPP of $dst" %}
7750 ins_encode( /*empty encoding*/ );
7751 ins_pipe( empty );
7752 %}
7753
7754 instruct castPP( eRegP dst ) %{
7755 match(Set dst (CastPP dst));
7756 format %{ "#castPP of $dst" %}
7757 ins_encode( /*empty encoding*/ );
7758 ins_pipe( empty );
7759 %}
7760
7761 instruct castII( eRegI dst ) %{
7762 match(Set dst (CastII dst));
7763 format %{ "#castII of $dst" %}
7764 ins_encode( /*empty encoding*/ );
7765 ins_cost(0);
7766 ins_pipe( empty );
7767 %}
7768
7769
7770 // Load-locked - same as a regular pointer load when used with compare-swap
7771 instruct loadPLocked(eRegP dst, memory mem) %{
7772 match(Set dst (LoadPLocked mem));
7773
7774 ins_cost(125);
7775 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7776 opcode(0x8B);
7777 ins_encode( OpcP, RegMem(dst,mem));
7778 ins_pipe( ialu_reg_mem );
7779 %}
7780
7781 // LoadLong-locked - same as a volatile long load when used with compare-swap
7782 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
7783 predicate(UseSSE<=1);
7784 match(Set dst (LoadLLocked mem));
7785
7786 ins_cost(200);
7787 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7788 "FISTp $dst" %}
7789 ins_encode(enc_loadL_volatile(mem,dst));
7790 ins_pipe( fpu_reg_mem );
7791 %}
7792
7793 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
7794 predicate(UseSSE>=2);
7795 match(Set dst (LoadLLocked mem));
7796 effect(TEMP tmp);
7797 ins_cost(180);
7798 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7799 "MOVSD $dst,$tmp" %}
7800 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
7801 ins_pipe( pipe_slow );
7802 %}
7803
7804 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
7805 predicate(UseSSE>=2);
7806 match(Set dst (LoadLLocked mem));
7807 effect(TEMP tmp);
7808 ins_cost(160);
7809 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7810 "MOVD $dst.lo,$tmp\n\t"
7811 "PSRLQ $tmp,32\n\t"
7812 "MOVD $dst.hi,$tmp" %}
7813 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
7814 ins_pipe( pipe_slow );
7815 %}
7816
7817 // Conditional-store of the updated heap-top.
7818 // Used during allocation of the shared heap.
7819 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7820 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7821 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7822 // EAX is killed if there is contention, but then it's also unused.
7823 // In the common case of no contention, EAX holds the new oop address.
7824 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7825 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7826 ins_pipe( pipe_cmpxchg );
7827 %}
7828
7829 // Conditional-store of a long value
7830 // Returns a boolean value (0/1) on success. Implemented with a CMPXCHG8 on Intel.
7831 // mem_ptr can actually be in either ESI or EDI
7832 instruct storeLConditional( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7833 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
7834 effect(KILL cr);
7835 // EDX:EAX is killed if there is contention, but then it's also unused.
7836 // In the common case of no contention, EDX:EAX holds the new oop address.
7837 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7838 "MOV $res,0\n\t"
7839 "JNE,s fail\n\t"
7840 "MOV $res,1\n"
7841 "fail:" %}
7842 ins_encode( enc_cmpxchg8(mem_ptr),
7843 enc_flags_ne_to_boolean(res) );
7844 ins_pipe( pipe_cmpxchg );
7845 %}
7846
7847 // Conditional-store of a long value
7848 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7849 // mem_ptr can actually be in either ESI or EDI
7850 instruct storeLConditional_flags( eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr, immI0 zero ) %{
7851 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
7852 // EDX:EAX is killed if there is contention, but then it's also unused.
7853 // In the common case of no contention, EDX:EAX holds the new oop address.
7854 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" %}
7855 ins_encode( enc_cmpxchg8(mem_ptr) );
7856 ins_pipe( pipe_cmpxchg );
7857 %}
7858
7859 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7860
7861 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7862 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7863 effect(KILL cr, KILL oldval);
7864 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7865 "MOV $res,0\n\t"
7866 "JNE,s fail\n\t"
7867 "MOV $res,1\n"
7868 "fail:" %}
7869 ins_encode( enc_cmpxchg8(mem_ptr),
7870 enc_flags_ne_to_boolean(res) );
7871 ins_pipe( pipe_cmpxchg );
7872 %}
7873
7874 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7875 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7876 effect(KILL cr, KILL oldval);
7877 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7878 "MOV $res,0\n\t"
7879 "JNE,s fail\n\t"
7880 "MOV $res,1\n"
7881 "fail:" %}
7882 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7883 ins_pipe( pipe_cmpxchg );
7884 %}
7885
7886 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7887 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7888 effect(KILL cr, KILL oldval);
7889 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7890 "MOV $res,0\n\t"
7891 "JNE,s fail\n\t"
7892 "MOV $res,1\n"
7893 "fail:" %}
7894 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7895 ins_pipe( pipe_cmpxchg );
7896 %}
7897
7898 //----------Subtraction Instructions-------------------------------------------
7899 // Integer Subtraction Instructions
7900 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7901 match(Set dst (SubI dst src));
7902 effect(KILL cr);
7903
7904 size(2);
7905 format %{ "SUB $dst,$src" %}
7906 opcode(0x2B);
7907 ins_encode( OpcP, RegReg( dst, src) );
7908 ins_pipe( ialu_reg_reg );
7909 %}
7910
7911 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7912 match(Set dst (SubI dst src));
7913 effect(KILL cr);
7914
7915 format %{ "SUB $dst,$src" %}
7916 opcode(0x81,0x05); /* Opcode 81 /5 */
7917 // ins_encode( RegImm( dst, src) );
7918 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7919 ins_pipe( ialu_reg );
7920 %}
7921
7922 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7923 match(Set dst (SubI dst (LoadI src)));
7924 effect(KILL cr);
7925
7926 ins_cost(125);
7927 format %{ "SUB $dst,$src" %}
7928 opcode(0x2B);
7929 ins_encode( OpcP, RegMem( dst, src) );
7930 ins_pipe( ialu_reg_mem );
7931 %}
7932
7933 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7934 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7935 effect(KILL cr);
7936
7937 ins_cost(150);
7938 format %{ "SUB $dst,$src" %}
7939 opcode(0x29); /* Opcode 29 /r */
7940 ins_encode( OpcP, RegMem( src, dst ) );
7941 ins_pipe( ialu_mem_reg );
7942 %}
7943
7944 // Subtract from a pointer
7945 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
7946 match(Set dst (AddP dst (SubI zero src)));
7947 effect(KILL cr);
7948
7949 size(2);
7950 format %{ "SUB $dst,$src" %}
7951 opcode(0x2B);
7952 ins_encode( OpcP, RegReg( dst, src) );
7953 ins_pipe( ialu_reg_reg );
7954 %}
7955
7956 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
7957 match(Set dst (SubI zero dst));
7958 effect(KILL cr);
7959
7960 size(2);
7961 format %{ "NEG $dst" %}
7962 opcode(0xF7,0x03); // Opcode F7 /3
7963 ins_encode( OpcP, RegOpc( dst ) );
7964 ins_pipe( ialu_reg );
7965 %}
7966
7967
7968 //----------Multiplication/Division Instructions-------------------------------
7969 // Integer Multiplication Instructions
7970 // Multiply Register
7971 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7972 match(Set dst (MulI dst src));
7973 effect(KILL cr);
7974
7975 size(3);
7976 ins_cost(300);
7977 format %{ "IMUL $dst,$src" %}
7978 opcode(0xAF, 0x0F);
7979 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7980 ins_pipe( ialu_reg_reg_alu0 );
7981 %}
7982
7983 // Multiply 32-bit Immediate
7984 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
7985 match(Set dst (MulI src imm));
7986 effect(KILL cr);
7987
7988 ins_cost(300);
7989 format %{ "IMUL $dst,$src,$imm" %}
7990 opcode(0x69); /* 69 /r id */
7991 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7992 ins_pipe( ialu_reg_reg_alu0 );
7993 %}
7994
7995 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7996 match(Set dst src);
7997 effect(KILL cr);
7998
7999 // Note that this is artificially increased to make it more expensive than loadConL
8000 ins_cost(250);
8001 format %{ "MOV EAX,$src\t// low word only" %}
8002 opcode(0xB8);
8003 ins_encode( LdImmL_Lo(dst, src) );
8004 ins_pipe( ialu_reg_fat );
8005 %}
8006
8007 // Multiply by 32-bit Immediate, taking the shifted high order results
8008 // (special case for shift by 32)
8009 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8010 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8011 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8012 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8013 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8014 effect(USE src1, KILL cr);
8015
8016 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8017 ins_cost(0*100 + 1*400 - 150);
8018 format %{ "IMUL EDX:EAX,$src1" %}
8019 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8020 ins_pipe( pipe_slow );
8021 %}
8022
8023 // Multiply by 32-bit Immediate, taking the shifted high order results
8024 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8025 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8026 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8027 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8028 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8029 effect(USE src1, KILL cr);
8030
8031 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8032 ins_cost(1*100 + 1*400 - 150);
8033 format %{ "IMUL EDX:EAX,$src1\n\t"
8034 "SAR EDX,$cnt-32" %}
8035 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8036 ins_pipe( pipe_slow );
8037 %}
8038
8039 // Multiply Memory 32-bit Immediate
8040 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8041 match(Set dst (MulI (LoadI src) imm));
8042 effect(KILL cr);
8043
8044 ins_cost(300);
8045 format %{ "IMUL $dst,$src,$imm" %}
8046 opcode(0x69); /* 69 /r id */
8047 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8048 ins_pipe( ialu_reg_mem_alu0 );
8049 %}
8050
8051 // Multiply Memory
8052 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8053 match(Set dst (MulI dst (LoadI src)));
8054 effect(KILL cr);
8055
8056 ins_cost(350);
8057 format %{ "IMUL $dst,$src" %}
8058 opcode(0xAF, 0x0F);
8059 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8060 ins_pipe( ialu_reg_mem_alu0 );
8061 %}
8062
8063 // Multiply Register Int to Long
8064 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8065 // Basic Idea: long = (long)int * (long)int
8066 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8067 effect(DEF dst, USE src, USE src1, KILL flags);
8068
8069 ins_cost(300);
8070 format %{ "IMUL $dst,$src1" %}
8071
8072 ins_encode( long_int_multiply( dst, src1 ) );
8073 ins_pipe( ialu_reg_reg_alu0 );
8074 %}
8075
8076 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8077 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8078 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8079 effect(KILL flags);
8080
8081 ins_cost(300);
8082 format %{ "MUL $dst,$src1" %}
8083
8084 ins_encode( long_uint_multiply(dst, src1) );
8085 ins_pipe( ialu_reg_reg_alu0 );
8086 %}
8087
8088 // Multiply Register Long
8089 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8090 match(Set dst (MulL dst src));
8091 effect(KILL cr, TEMP tmp);
8092 ins_cost(4*100+3*400);
8093 // Basic idea: lo(result) = lo(x_lo * y_lo)
8094 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8095 format %{ "MOV $tmp,$src.lo\n\t"
8096 "IMUL $tmp,EDX\n\t"
8097 "MOV EDX,$src.hi\n\t"
8098 "IMUL EDX,EAX\n\t"
8099 "ADD $tmp,EDX\n\t"
8100 "MUL EDX:EAX,$src.lo\n\t"
8101 "ADD EDX,$tmp" %}
8102 ins_encode( long_multiply( dst, src, tmp ) );
8103 ins_pipe( pipe_slow );
8104 %}
8105
8106 // Multiply Register Long by small constant
8107 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8108 match(Set dst (MulL dst src));
8109 effect(KILL cr, TEMP tmp);
8110 ins_cost(2*100+2*400);
8111 size(12);
8112 // Basic idea: lo(result) = lo(src * EAX)
8113 // hi(result) = hi(src * EAX) + lo(src * EDX)
8114 format %{ "IMUL $tmp,EDX,$src\n\t"
8115 "MOV EDX,$src\n\t"
8116 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8117 "ADD EDX,$tmp" %}
8118 ins_encode( long_multiply_con( dst, src, tmp ) );
8119 ins_pipe( pipe_slow );
8120 %}
8121
8122 // Integer DIV with Register
8123 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8124 match(Set rax (DivI rax div));
8125 effect(KILL rdx, KILL cr);
8126 size(26);
8127 ins_cost(30*100+10*100);
8128 format %{ "CMP EAX,0x80000000\n\t"
8129 "JNE,s normal\n\t"
8130 "XOR EDX,EDX\n\t"
8131 "CMP ECX,-1\n\t"
8132 "JE,s done\n"
8133 "normal: CDQ\n\t"
8134 "IDIV $div\n\t"
8135 "done:" %}
8136 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8137 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8138 ins_pipe( ialu_reg_reg_alu0 );
8139 %}
8140
8141 // Divide Register Long
8142 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8143 match(Set dst (DivL src1 src2));
8144 effect( KILL cr, KILL cx, KILL bx );
8145 ins_cost(10000);
8146 format %{ "PUSH $src1.hi\n\t"
8147 "PUSH $src1.lo\n\t"
8148 "PUSH $src2.hi\n\t"
8149 "PUSH $src2.lo\n\t"
8150 "CALL SharedRuntime::ldiv\n\t"
8151 "ADD ESP,16" %}
8152 ins_encode( long_div(src1,src2) );
8153 ins_pipe( pipe_slow );
8154 %}
8155
8156 // Integer DIVMOD with Register, both quotient and mod results
8157 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8158 match(DivModI rax div);
8159 effect(KILL cr);
8160 size(26);
8161 ins_cost(30*100+10*100);
8162 format %{ "CMP EAX,0x80000000\n\t"
8163 "JNE,s normal\n\t"
8164 "XOR EDX,EDX\n\t"
8165 "CMP ECX,-1\n\t"
8166 "JE,s done\n"
8167 "normal: CDQ\n\t"
8168 "IDIV $div\n\t"
8169 "done:" %}
8170 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8171 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8172 ins_pipe( pipe_slow );
8173 %}
8174
8175 // Integer MOD with Register
8176 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8177 match(Set rdx (ModI rax div));
8178 effect(KILL rax, KILL cr);
8179
8180 size(26);
8181 ins_cost(300);
8182 format %{ "CDQ\n\t"
8183 "IDIV $div" %}
8184 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8185 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8186 ins_pipe( ialu_reg_reg_alu0 );
8187 %}
8188
8189 // Remainder Register Long
8190 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8191 match(Set dst (ModL src1 src2));
8192 effect( KILL cr, KILL cx, KILL bx );
8193 ins_cost(10000);
8194 format %{ "PUSH $src1.hi\n\t"
8195 "PUSH $src1.lo\n\t"
8196 "PUSH $src2.hi\n\t"
8197 "PUSH $src2.lo\n\t"
8198 "CALL SharedRuntime::lrem\n\t"
8199 "ADD ESP,16" %}
8200 ins_encode( long_mod(src1,src2) );
8201 ins_pipe( pipe_slow );
8202 %}
8203
8204 // Integer Shift Instructions
8205 // Shift Left by one
8206 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8207 match(Set dst (LShiftI dst shift));
8208 effect(KILL cr);
8209
8210 size(2);
8211 format %{ "SHL $dst,$shift" %}
8212 opcode(0xD1, 0x4); /* D1 /4 */
8213 ins_encode( OpcP, RegOpc( dst ) );
8214 ins_pipe( ialu_reg );
8215 %}
8216
8217 // Shift Left by 8-bit immediate
8218 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8219 match(Set dst (LShiftI dst shift));
8220 effect(KILL cr);
8221
8222 size(3);
8223 format %{ "SHL $dst,$shift" %}
8224 opcode(0xC1, 0x4); /* C1 /4 ib */
8225 ins_encode( RegOpcImm( dst, shift) );
8226 ins_pipe( ialu_reg );
8227 %}
8228
8229 // Shift Left by variable
8230 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8231 match(Set dst (LShiftI dst shift));
8232 effect(KILL cr);
8233
8234 size(2);
8235 format %{ "SHL $dst,$shift" %}
8236 opcode(0xD3, 0x4); /* D3 /4 */
8237 ins_encode( OpcP, RegOpc( dst ) );
8238 ins_pipe( ialu_reg_reg );
8239 %}
8240
8241 // Arithmetic shift right by one
8242 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8243 match(Set dst (RShiftI dst shift));
8244 effect(KILL cr);
8245
8246 size(2);
8247 format %{ "SAR $dst,$shift" %}
8248 opcode(0xD1, 0x7); /* D1 /7 */
8249 ins_encode( OpcP, RegOpc( dst ) );
8250 ins_pipe( ialu_reg );
8251 %}
8252
8253 // Arithmetic shift right by one
8254 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8255 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8256 effect(KILL cr);
8257 format %{ "SAR $dst,$shift" %}
8258 opcode(0xD1, 0x7); /* D1 /7 */
8259 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8260 ins_pipe( ialu_mem_imm );
8261 %}
8262
8263 // Arithmetic Shift Right by 8-bit immediate
8264 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8265 match(Set dst (RShiftI dst shift));
8266 effect(KILL cr);
8267
8268 size(3);
8269 format %{ "SAR $dst,$shift" %}
8270 opcode(0xC1, 0x7); /* C1 /7 ib */
8271 ins_encode( RegOpcImm( dst, shift ) );
8272 ins_pipe( ialu_mem_imm );
8273 %}
8274
8275 // Arithmetic Shift Right by 8-bit immediate
8276 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8277 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8278 effect(KILL cr);
8279
8280 format %{ "SAR $dst,$shift" %}
8281 opcode(0xC1, 0x7); /* C1 /7 ib */
8282 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8283 ins_pipe( ialu_mem_imm );
8284 %}
8285
8286 // Arithmetic Shift Right by variable
8287 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8288 match(Set dst (RShiftI dst shift));
8289 effect(KILL cr);
8290
8291 size(2);
8292 format %{ "SAR $dst,$shift" %}
8293 opcode(0xD3, 0x7); /* D3 /7 */
8294 ins_encode( OpcP, RegOpc( dst ) );
8295 ins_pipe( ialu_reg_reg );
8296 %}
8297
8298 // Logical shift right by one
8299 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8300 match(Set dst (URShiftI dst shift));
8301 effect(KILL cr);
8302
8303 size(2);
8304 format %{ "SHR $dst,$shift" %}
8305 opcode(0xD1, 0x5); /* D1 /5 */
8306 ins_encode( OpcP, RegOpc( dst ) );
8307 ins_pipe( ialu_reg );
8308 %}
8309
8310 // Logical Shift Right by 8-bit immediate
8311 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8312 match(Set dst (URShiftI dst shift));
8313 effect(KILL cr);
8314
8315 size(3);
8316 format %{ "SHR $dst,$shift" %}
8317 opcode(0xC1, 0x5); /* C1 /5 ib */
8318 ins_encode( RegOpcImm( dst, shift) );
8319 ins_pipe( ialu_reg );
8320 %}
8321
8322 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8323 // This idiom is used by the compiler for the i2b bytecode.
8324 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8325 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8326 effect(KILL cr);
8327
8328 size(3);
8329 format %{ "MOVSX $dst,$src :8" %}
8330 opcode(0xBE, 0x0F);
8331 ins_encode( OpcS, OpcP, RegReg( dst, src));
8332 ins_pipe( ialu_reg_reg );
8333 %}
8334
8335 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8336 // This idiom is used by the compiler the i2s bytecode.
8337 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8338 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8339 effect(KILL cr);
8340
8341 size(3);
8342 format %{ "MOVSX $dst,$src :16" %}
8343 opcode(0xBF, 0x0F);
8344 ins_encode( OpcS, OpcP, RegReg( dst, src));
8345 ins_pipe( ialu_reg_reg );
8346 %}
8347
8348
8349 // Logical Shift Right by variable
8350 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8351 match(Set dst (URShiftI dst shift));
8352 effect(KILL cr);
8353
8354 size(2);
8355 format %{ "SHR $dst,$shift" %}
8356 opcode(0xD3, 0x5); /* D3 /5 */
8357 ins_encode( OpcP, RegOpc( dst ) );
8358 ins_pipe( ialu_reg_reg );
8359 %}
8360
8361
8362 //----------Logical Instructions-----------------------------------------------
8363 //----------Integer Logical Instructions---------------------------------------
8364 // And Instructions
8365 // And Register with Register
8366 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8367 match(Set dst (AndI dst src));
8368 effect(KILL cr);
8369
8370 size(2);
8371 format %{ "AND $dst,$src" %}
8372 opcode(0x23);
8373 ins_encode( OpcP, RegReg( dst, src) );
8374 ins_pipe( ialu_reg_reg );
8375 %}
8376
8377 // And Register with Immediate
8378 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8379 match(Set dst (AndI dst src));
8380 effect(KILL cr);
8381
8382 format %{ "AND $dst,$src" %}
8383 opcode(0x81,0x04); /* Opcode 81 /4 */
8384 // ins_encode( RegImm( dst, src) );
8385 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8386 ins_pipe( ialu_reg );
8387 %}
8388
8389 // And Register with Memory
8390 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8391 match(Set dst (AndI dst (LoadI src)));
8392 effect(KILL cr);
8393
8394 ins_cost(125);
8395 format %{ "AND $dst,$src" %}
8396 opcode(0x23);
8397 ins_encode( OpcP, RegMem( dst, src) );
8398 ins_pipe( ialu_reg_mem );
8399 %}
8400
8401 // And Memory with Register
8402 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8403 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8404 effect(KILL cr);
8405
8406 ins_cost(150);
8407 format %{ "AND $dst,$src" %}
8408 opcode(0x21); /* Opcode 21 /r */
8409 ins_encode( OpcP, RegMem( src, dst ) );
8410 ins_pipe( ialu_mem_reg );
8411 %}
8412
8413 // And Memory with Immediate
8414 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8415 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8416 effect(KILL cr);
8417
8418 ins_cost(125);
8419 format %{ "AND $dst,$src" %}
8420 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8421 // ins_encode( MemImm( dst, src) );
8422 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8423 ins_pipe( ialu_mem_imm );
8424 %}
8425
8426 // Or Instructions
8427 // Or Register with Register
8428 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8429 match(Set dst (OrI dst src));
8430 effect(KILL cr);
8431
8432 size(2);
8433 format %{ "OR $dst,$src" %}
8434 opcode(0x0B);
8435 ins_encode( OpcP, RegReg( dst, src) );
8436 ins_pipe( ialu_reg_reg );
8437 %}
8438
8439 // Or Register with Immediate
8440 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8441 match(Set dst (OrI dst src));
8442 effect(KILL cr);
8443
8444 format %{ "OR $dst,$src" %}
8445 opcode(0x81,0x01); /* Opcode 81 /1 id */
8446 // ins_encode( RegImm( dst, src) );
8447 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8448 ins_pipe( ialu_reg );
8449 %}
8450
8451 // Or Register with Memory
8452 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8453 match(Set dst (OrI dst (LoadI src)));
8454 effect(KILL cr);
8455
8456 ins_cost(125);
8457 format %{ "OR $dst,$src" %}
8458 opcode(0x0B);
8459 ins_encode( OpcP, RegMem( dst, src) );
8460 ins_pipe( ialu_reg_mem );
8461 %}
8462
8463 // Or Memory with Register
8464 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8465 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8466 effect(KILL cr);
8467
8468 ins_cost(150);
8469 format %{ "OR $dst,$src" %}
8470 opcode(0x09); /* Opcode 09 /r */
8471 ins_encode( OpcP, RegMem( src, dst ) );
8472 ins_pipe( ialu_mem_reg );
8473 %}
8474
8475 // Or Memory with Immediate
8476 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8477 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8478 effect(KILL cr);
8479
8480 ins_cost(125);
8481 format %{ "OR $dst,$src" %}
8482 opcode(0x81,0x1); /* Opcode 81 /1 id */
8483 // ins_encode( MemImm( dst, src) );
8484 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8485 ins_pipe( ialu_mem_imm );
8486 %}
8487
8488 // ROL/ROR
8489 // ROL expand
8490 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8491 effect(USE_DEF dst, USE shift, KILL cr);
8492
8493 format %{ "ROL $dst, $shift" %}
8494 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8495 ins_encode( OpcP, RegOpc( dst ));
8496 ins_pipe( ialu_reg );
8497 %}
8498
8499 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8500 effect(USE_DEF dst, USE shift, KILL cr);
8501
8502 format %{ "ROL $dst, $shift" %}
8503 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8504 ins_encode( RegOpcImm(dst, shift) );
8505 ins_pipe(ialu_reg);
8506 %}
8507
8508 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8509 effect(USE_DEF dst, USE shift, KILL cr);
8510
8511 format %{ "ROL $dst, $shift" %}
8512 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8513 ins_encode(OpcP, RegOpc(dst));
8514 ins_pipe( ialu_reg_reg );
8515 %}
8516 // end of ROL expand
8517
8518 // ROL 32bit by one once
8519 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8520 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8521
8522 expand %{
8523 rolI_eReg_imm1(dst, lshift, cr);
8524 %}
8525 %}
8526
8527 // ROL 32bit var by imm8 once
8528 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8529 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8530 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8531
8532 expand %{
8533 rolI_eReg_imm8(dst, lshift, cr);
8534 %}
8535 %}
8536
8537 // ROL 32bit var by var once
8538 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8539 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8540
8541 expand %{
8542 rolI_eReg_CL(dst, shift, cr);
8543 %}
8544 %}
8545
8546 // ROL 32bit var by var once
8547 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8548 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8549
8550 expand %{
8551 rolI_eReg_CL(dst, shift, cr);
8552 %}
8553 %}
8554
8555 // ROR expand
8556 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8557 effect(USE_DEF dst, USE shift, KILL cr);
8558
8559 format %{ "ROR $dst, $shift" %}
8560 opcode(0xD1,0x1); /* Opcode D1 /1 */
8561 ins_encode( OpcP, RegOpc( dst ) );
8562 ins_pipe( ialu_reg );
8563 %}
8564
8565 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8566 effect (USE_DEF dst, USE shift, KILL cr);
8567
8568 format %{ "ROR $dst, $shift" %}
8569 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8570 ins_encode( RegOpcImm(dst, shift) );
8571 ins_pipe( ialu_reg );
8572 %}
8573
8574 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8575 effect(USE_DEF dst, USE shift, KILL cr);
8576
8577 format %{ "ROR $dst, $shift" %}
8578 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8579 ins_encode(OpcP, RegOpc(dst));
8580 ins_pipe( ialu_reg_reg );
8581 %}
8582 // end of ROR expand
8583
8584 // ROR right once
8585 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8586 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8587
8588 expand %{
8589 rorI_eReg_imm1(dst, rshift, cr);
8590 %}
8591 %}
8592
8593 // ROR 32bit by immI8 once
8594 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8595 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8596 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8597
8598 expand %{
8599 rorI_eReg_imm8(dst, rshift, cr);
8600 %}
8601 %}
8602
8603 // ROR 32bit var by var once
8604 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8605 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8606
8607 expand %{
8608 rorI_eReg_CL(dst, shift, cr);
8609 %}
8610 %}
8611
8612 // ROR 32bit var by var once
8613 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8614 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8615
8616 expand %{
8617 rorI_eReg_CL(dst, shift, cr);
8618 %}
8619 %}
8620
8621 // Xor Instructions
8622 // Xor Register with Register
8623 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8624 match(Set dst (XorI dst src));
8625 effect(KILL cr);
8626
8627 size(2);
8628 format %{ "XOR $dst,$src" %}
8629 opcode(0x33);
8630 ins_encode( OpcP, RegReg( dst, src) );
8631 ins_pipe( ialu_reg_reg );
8632 %}
8633
8634 // Xor Register with Immediate -1
8635 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
8636 match(Set dst (XorI dst imm));
8637
8638 size(2);
8639 format %{ "NOT $dst" %}
8640 ins_encode %{
8641 __ notl($dst$$Register);
8642 %}
8643 ins_pipe( ialu_reg );
8644 %}
8645
8646 // Xor Register with Immediate
8647 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8648 match(Set dst (XorI dst src));
8649 effect(KILL cr);
8650
8651 format %{ "XOR $dst,$src" %}
8652 opcode(0x81,0x06); /* Opcode 81 /6 id */
8653 // ins_encode( RegImm( dst, src) );
8654 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8655 ins_pipe( ialu_reg );
8656 %}
8657
8658 // Xor Register with Memory
8659 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8660 match(Set dst (XorI dst (LoadI src)));
8661 effect(KILL cr);
8662
8663 ins_cost(125);
8664 format %{ "XOR $dst,$src" %}
8665 opcode(0x33);
8666 ins_encode( OpcP, RegMem(dst, src) );
8667 ins_pipe( ialu_reg_mem );
8668 %}
8669
8670 // Xor Memory with Register
8671 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8672 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8673 effect(KILL cr);
8674
8675 ins_cost(150);
8676 format %{ "XOR $dst,$src" %}
8677 opcode(0x31); /* Opcode 31 /r */
8678 ins_encode( OpcP, RegMem( src, dst ) );
8679 ins_pipe( ialu_mem_reg );
8680 %}
8681
8682 // Xor Memory with Immediate
8683 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8684 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8685 effect(KILL cr);
8686
8687 ins_cost(125);
8688 format %{ "XOR $dst,$src" %}
8689 opcode(0x81,0x6); /* Opcode 81 /6 id */
8690 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8691 ins_pipe( ialu_mem_imm );
8692 %}
8693
8694 //----------Convert Int to Boolean---------------------------------------------
8695
8696 instruct movI_nocopy(eRegI dst, eRegI src) %{
8697 effect( DEF dst, USE src );
8698 format %{ "MOV $dst,$src" %}
8699 ins_encode( enc_Copy( dst, src) );
8700 ins_pipe( ialu_reg_reg );
8701 %}
8702
8703 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8704 effect( USE_DEF dst, USE src, KILL cr );
8705
8706 size(4);
8707 format %{ "NEG $dst\n\t"
8708 "ADC $dst,$src" %}
8709 ins_encode( neg_reg(dst),
8710 OpcRegReg(0x13,dst,src) );
8711 ins_pipe( ialu_reg_reg_long );
8712 %}
8713
8714 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
8715 match(Set dst (Conv2B src));
8716
8717 expand %{
8718 movI_nocopy(dst,src);
8719 ci2b(dst,src,cr);
8720 %}
8721 %}
8722
8723 instruct movP_nocopy(eRegI dst, eRegP src) %{
8724 effect( DEF dst, USE src );
8725 format %{ "MOV $dst,$src" %}
8726 ins_encode( enc_Copy( dst, src) );
8727 ins_pipe( ialu_reg_reg );
8728 %}
8729
8730 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
8731 effect( USE_DEF dst, USE src, KILL cr );
8732 format %{ "NEG $dst\n\t"
8733 "ADC $dst,$src" %}
8734 ins_encode( neg_reg(dst),
8735 OpcRegReg(0x13,dst,src) );
8736 ins_pipe( ialu_reg_reg_long );
8737 %}
8738
8739 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
8740 match(Set dst (Conv2B src));
8741
8742 expand %{
8743 movP_nocopy(dst,src);
8744 cp2b(dst,src,cr);
8745 %}
8746 %}
8747
8748 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8749 match(Set dst (CmpLTMask p q));
8750 effect( KILL cr );
8751 ins_cost(400);
8752
8753 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8754 format %{ "XOR $dst,$dst\n\t"
8755 "CMP $p,$q\n\t"
8756 "SETlt $dst\n\t"
8757 "NEG $dst" %}
8758 ins_encode( OpcRegReg(0x33,dst,dst),
8759 OpcRegReg(0x3B,p,q),
8760 setLT_reg(dst), neg_reg(dst) );
8761 ins_pipe( pipe_slow );
8762 %}
8763
8764 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
8765 match(Set dst (CmpLTMask dst zero));
8766 effect( DEF dst, KILL cr );
8767 ins_cost(100);
8768
8769 format %{ "SAR $dst,31" %}
8770 opcode(0xC1, 0x7); /* C1 /7 ib */
8771 ins_encode( RegOpcImm( dst, 0x1F ) );
8772 ins_pipe( ialu_reg );
8773 %}
8774
8775
8776 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8777 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8778 effect( KILL tmp, KILL cr );
8779 ins_cost(400);
8780 // annoyingly, $tmp has no edges so you cant ask for it in
8781 // any format or encoding
8782 format %{ "SUB $p,$q\n\t"
8783 "SBB ECX,ECX\n\t"
8784 "AND ECX,$y\n\t"
8785 "ADD $p,ECX" %}
8786 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8787 ins_pipe( pipe_cmplt );
8788 %}
8789
8790 /* If I enable this, I encourage spilling in the inner loop of compress.
8791 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8792 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8793 effect( USE_KILL tmp, KILL cr );
8794 ins_cost(400);
8795
8796 format %{ "SUB $p,$q\n\t"
8797 "SBB ECX,ECX\n\t"
8798 "AND ECX,$y\n\t"
8799 "ADD $p,ECX" %}
8800 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8801 %}
8802 */
8803
8804 //----------Long Instructions------------------------------------------------
8805 // Add Long Register with Register
8806 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8807 match(Set dst (AddL dst src));
8808 effect(KILL cr);
8809 ins_cost(200);
8810 format %{ "ADD $dst.lo,$src.lo\n\t"
8811 "ADC $dst.hi,$src.hi" %}
8812 opcode(0x03, 0x13);
8813 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8814 ins_pipe( ialu_reg_reg_long );
8815 %}
8816
8817 // Add Long Register with Immediate
8818 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8819 match(Set dst (AddL dst src));
8820 effect(KILL cr);
8821 format %{ "ADD $dst.lo,$src.lo\n\t"
8822 "ADC $dst.hi,$src.hi" %}
8823 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8824 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8825 ins_pipe( ialu_reg_long );
8826 %}
8827
8828 // Add Long Register with Memory
8829 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8830 match(Set dst (AddL dst (LoadL mem)));
8831 effect(KILL cr);
8832 ins_cost(125);
8833 format %{ "ADD $dst.lo,$mem\n\t"
8834 "ADC $dst.hi,$mem+4" %}
8835 opcode(0x03, 0x13);
8836 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8837 ins_pipe( ialu_reg_long_mem );
8838 %}
8839
8840 // Subtract Long Register with Register.
8841 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8842 match(Set dst (SubL dst src));
8843 effect(KILL cr);
8844 ins_cost(200);
8845 format %{ "SUB $dst.lo,$src.lo\n\t"
8846 "SBB $dst.hi,$src.hi" %}
8847 opcode(0x2B, 0x1B);
8848 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8849 ins_pipe( ialu_reg_reg_long );
8850 %}
8851
8852 // Subtract Long Register with Immediate
8853 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8854 match(Set dst (SubL dst src));
8855 effect(KILL cr);
8856 format %{ "SUB $dst.lo,$src.lo\n\t"
8857 "SBB $dst.hi,$src.hi" %}
8858 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8859 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8860 ins_pipe( ialu_reg_long );
8861 %}
8862
8863 // Subtract Long Register with Memory
8864 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8865 match(Set dst (SubL dst (LoadL mem)));
8866 effect(KILL cr);
8867 ins_cost(125);
8868 format %{ "SUB $dst.lo,$mem\n\t"
8869 "SBB $dst.hi,$mem+4" %}
8870 opcode(0x2B, 0x1B);
8871 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8872 ins_pipe( ialu_reg_long_mem );
8873 %}
8874
8875 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8876 match(Set dst (SubL zero dst));
8877 effect(KILL cr);
8878 ins_cost(300);
8879 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8880 ins_encode( neg_long(dst) );
8881 ins_pipe( ialu_reg_reg_long );
8882 %}
8883
8884 // And Long Register with Register
8885 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8886 match(Set dst (AndL dst src));
8887 effect(KILL cr);
8888 format %{ "AND $dst.lo,$src.lo\n\t"
8889 "AND $dst.hi,$src.hi" %}
8890 opcode(0x23,0x23);
8891 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8892 ins_pipe( ialu_reg_reg_long );
8893 %}
8894
8895 // And Long Register with Immediate
8896 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8897 match(Set dst (AndL dst src));
8898 effect(KILL cr);
8899 format %{ "AND $dst.lo,$src.lo\n\t"
8900 "AND $dst.hi,$src.hi" %}
8901 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8902 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8903 ins_pipe( ialu_reg_long );
8904 %}
8905
8906 // And Long Register with Memory
8907 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8908 match(Set dst (AndL dst (LoadL mem)));
8909 effect(KILL cr);
8910 ins_cost(125);
8911 format %{ "AND $dst.lo,$mem\n\t"
8912 "AND $dst.hi,$mem+4" %}
8913 opcode(0x23, 0x23);
8914 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8915 ins_pipe( ialu_reg_long_mem );
8916 %}
8917
8918 // Or Long Register with Register
8919 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8920 match(Set dst (OrL dst src));
8921 effect(KILL cr);
8922 format %{ "OR $dst.lo,$src.lo\n\t"
8923 "OR $dst.hi,$src.hi" %}
8924 opcode(0x0B,0x0B);
8925 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8926 ins_pipe( ialu_reg_reg_long );
8927 %}
8928
8929 // Or Long Register with Immediate
8930 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8931 match(Set dst (OrL dst src));
8932 effect(KILL cr);
8933 format %{ "OR $dst.lo,$src.lo\n\t"
8934 "OR $dst.hi,$src.hi" %}
8935 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8936 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8937 ins_pipe( ialu_reg_long );
8938 %}
8939
8940 // Or Long Register with Memory
8941 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8942 match(Set dst (OrL dst (LoadL mem)));
8943 effect(KILL cr);
8944 ins_cost(125);
8945 format %{ "OR $dst.lo,$mem\n\t"
8946 "OR $dst.hi,$mem+4" %}
8947 opcode(0x0B,0x0B);
8948 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8949 ins_pipe( ialu_reg_long_mem );
8950 %}
8951
8952 // Xor Long Register with Register
8953 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8954 match(Set dst (XorL dst src));
8955 effect(KILL cr);
8956 format %{ "XOR $dst.lo,$src.lo\n\t"
8957 "XOR $dst.hi,$src.hi" %}
8958 opcode(0x33,0x33);
8959 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8960 ins_pipe( ialu_reg_reg_long );
8961 %}
8962
8963 // Xor Long Register with Immediate -1
8964 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
8965 match(Set dst (XorL dst imm));
8966 format %{ "NOT $dst.lo\n\t"
8967 "NOT $dst.hi" %}
8968 ins_encode %{
8969 __ notl($dst$$Register);
8970 __ notl(HIGH_FROM_LOW($dst$$Register));
8971 %}
8972 ins_pipe( ialu_reg_long );
8973 %}
8974
8975 // Xor Long Register with Immediate
8976 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8977 match(Set dst (XorL dst src));
8978 effect(KILL cr);
8979 format %{ "XOR $dst.lo,$src.lo\n\t"
8980 "XOR $dst.hi,$src.hi" %}
8981 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
8982 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8983 ins_pipe( ialu_reg_long );
8984 %}
8985
8986 // Xor Long Register with Memory
8987 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8988 match(Set dst (XorL dst (LoadL mem)));
8989 effect(KILL cr);
8990 ins_cost(125);
8991 format %{ "XOR $dst.lo,$mem\n\t"
8992 "XOR $dst.hi,$mem+4" %}
8993 opcode(0x33,0x33);
8994 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8995 ins_pipe( ialu_reg_long_mem );
8996 %}
8997
8998 // Shift Left Long by 1
8999 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9000 predicate(UseNewLongLShift);
9001 match(Set dst (LShiftL dst cnt));
9002 effect(KILL cr);
9003 ins_cost(100);
9004 format %{ "ADD $dst.lo,$dst.lo\n\t"
9005 "ADC $dst.hi,$dst.hi" %}
9006 ins_encode %{
9007 __ addl($dst$$Register,$dst$$Register);
9008 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9009 %}
9010 ins_pipe( ialu_reg_long );
9011 %}
9012
9013 // Shift Left Long by 2
9014 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9015 predicate(UseNewLongLShift);
9016 match(Set dst (LShiftL dst cnt));
9017 effect(KILL cr);
9018 ins_cost(100);
9019 format %{ "ADD $dst.lo,$dst.lo\n\t"
9020 "ADC $dst.hi,$dst.hi\n\t"
9021 "ADD $dst.lo,$dst.lo\n\t"
9022 "ADC $dst.hi,$dst.hi" %}
9023 ins_encode %{
9024 __ addl($dst$$Register,$dst$$Register);
9025 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9026 __ addl($dst$$Register,$dst$$Register);
9027 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9028 %}
9029 ins_pipe( ialu_reg_long );
9030 %}
9031
9032 // Shift Left Long by 3
9033 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9034 predicate(UseNewLongLShift);
9035 match(Set dst (LShiftL dst cnt));
9036 effect(KILL cr);
9037 ins_cost(100);
9038 format %{ "ADD $dst.lo,$dst.lo\n\t"
9039 "ADC $dst.hi,$dst.hi\n\t"
9040 "ADD $dst.lo,$dst.lo\n\t"
9041 "ADC $dst.hi,$dst.hi\n\t"
9042 "ADD $dst.lo,$dst.lo\n\t"
9043 "ADC $dst.hi,$dst.hi" %}
9044 ins_encode %{
9045 __ addl($dst$$Register,$dst$$Register);
9046 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9047 __ addl($dst$$Register,$dst$$Register);
9048 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9049 __ addl($dst$$Register,$dst$$Register);
9050 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9051 %}
9052 ins_pipe( ialu_reg_long );
9053 %}
9054
9055 // Shift Left Long by 1-31
9056 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9057 match(Set dst (LShiftL dst cnt));
9058 effect(KILL cr);
9059 ins_cost(200);
9060 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9061 "SHL $dst.lo,$cnt" %}
9062 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9063 ins_encode( move_long_small_shift(dst,cnt) );
9064 ins_pipe( ialu_reg_long );
9065 %}
9066
9067 // Shift Left Long by 32-63
9068 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9069 match(Set dst (LShiftL dst cnt));
9070 effect(KILL cr);
9071 ins_cost(300);
9072 format %{ "MOV $dst.hi,$dst.lo\n"
9073 "\tSHL $dst.hi,$cnt-32\n"
9074 "\tXOR $dst.lo,$dst.lo" %}
9075 opcode(0xC1, 0x4); /* C1 /4 ib */
9076 ins_encode( move_long_big_shift_clr(dst,cnt) );
9077 ins_pipe( ialu_reg_long );
9078 %}
9079
9080 // Shift Left Long by variable
9081 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9082 match(Set dst (LShiftL dst shift));
9083 effect(KILL cr);
9084 ins_cost(500+200);
9085 size(17);
9086 format %{ "TEST $shift,32\n\t"
9087 "JEQ,s small\n\t"
9088 "MOV $dst.hi,$dst.lo\n\t"
9089 "XOR $dst.lo,$dst.lo\n"
9090 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9091 "SHL $dst.lo,$shift" %}
9092 ins_encode( shift_left_long( dst, shift ) );
9093 ins_pipe( pipe_slow );
9094 %}
9095
9096 // Shift Right Long by 1-31
9097 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9098 match(Set dst (URShiftL dst cnt));
9099 effect(KILL cr);
9100 ins_cost(200);
9101 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9102 "SHR $dst.hi,$cnt" %}
9103 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9104 ins_encode( move_long_small_shift(dst,cnt) );
9105 ins_pipe( ialu_reg_long );
9106 %}
9107
9108 // Shift Right Long by 32-63
9109 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9110 match(Set dst (URShiftL dst cnt));
9111 effect(KILL cr);
9112 ins_cost(300);
9113 format %{ "MOV $dst.lo,$dst.hi\n"
9114 "\tSHR $dst.lo,$cnt-32\n"
9115 "\tXOR $dst.hi,$dst.hi" %}
9116 opcode(0xC1, 0x5); /* C1 /5 ib */
9117 ins_encode( move_long_big_shift_clr(dst,cnt) );
9118 ins_pipe( ialu_reg_long );
9119 %}
9120
9121 // Shift Right Long by variable
9122 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9123 match(Set dst (URShiftL dst shift));
9124 effect(KILL cr);
9125 ins_cost(600);
9126 size(17);
9127 format %{ "TEST $shift,32\n\t"
9128 "JEQ,s small\n\t"
9129 "MOV $dst.lo,$dst.hi\n\t"
9130 "XOR $dst.hi,$dst.hi\n"
9131 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9132 "SHR $dst.hi,$shift" %}
9133 ins_encode( shift_right_long( dst, shift ) );
9134 ins_pipe( pipe_slow );
9135 %}
9136
9137 // Shift Right Long by 1-31
9138 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9139 match(Set dst (RShiftL dst cnt));
9140 effect(KILL cr);
9141 ins_cost(200);
9142 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9143 "SAR $dst.hi,$cnt" %}
9144 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9145 ins_encode( move_long_small_shift(dst,cnt) );
9146 ins_pipe( ialu_reg_long );
9147 %}
9148
9149 // Shift Right Long by 32-63
9150 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9151 match(Set dst (RShiftL dst cnt));
9152 effect(KILL cr);
9153 ins_cost(300);
9154 format %{ "MOV $dst.lo,$dst.hi\n"
9155 "\tSAR $dst.lo,$cnt-32\n"
9156 "\tSAR $dst.hi,31" %}
9157 opcode(0xC1, 0x7); /* C1 /7 ib */
9158 ins_encode( move_long_big_shift_sign(dst,cnt) );
9159 ins_pipe( ialu_reg_long );
9160 %}
9161
9162 // Shift Right arithmetic Long by variable
9163 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9164 match(Set dst (RShiftL dst shift));
9165 effect(KILL cr);
9166 ins_cost(600);
9167 size(18);
9168 format %{ "TEST $shift,32\n\t"
9169 "JEQ,s small\n\t"
9170 "MOV $dst.lo,$dst.hi\n\t"
9171 "SAR $dst.hi,31\n"
9172 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9173 "SAR $dst.hi,$shift" %}
9174 ins_encode( shift_right_arith_long( dst, shift ) );
9175 ins_pipe( pipe_slow );
9176 %}
9177
9178
9179 //----------Double Instructions------------------------------------------------
9180 // Double Math
9181
9182 // Compare & branch
9183
9184 // P6 version of float compare, sets condition codes in EFLAGS
9185 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9186 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9187 match(Set cr (CmpD src1 src2));
9188 effect(KILL rax);
9189 ins_cost(150);
9190 format %{ "FLD $src1\n\t"
9191 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9192 "JNP exit\n\t"
9193 "MOV ah,1 // saw a NaN, set CF\n\t"
9194 "SAHF\n"
9195 "exit:\tNOP // avoid branch to branch" %}
9196 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9197 ins_encode( Push_Reg_D(src1),
9198 OpcP, RegOpc(src2),
9199 cmpF_P6_fixup );
9200 ins_pipe( pipe_slow );
9201 %}
9202
9203 // Compare & branch
9204 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9205 predicate(UseSSE<=1);
9206 match(Set cr (CmpD src1 src2));
9207 effect(KILL rax);
9208 ins_cost(200);
9209 format %{ "FLD $src1\n\t"
9210 "FCOMp $src2\n\t"
9211 "FNSTSW AX\n\t"
9212 "TEST AX,0x400\n\t"
9213 "JZ,s flags\n\t"
9214 "MOV AH,1\t# unordered treat as LT\n"
9215 "flags:\tSAHF" %}
9216 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9217 ins_encode( Push_Reg_D(src1),
9218 OpcP, RegOpc(src2),
9219 fpu_flags);
9220 ins_pipe( pipe_slow );
9221 %}
9222
9223 // Compare vs zero into -1,0,1
9224 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9225 predicate(UseSSE<=1);
9226 match(Set dst (CmpD3 src1 zero));
9227 effect(KILL cr, KILL rax);
9228 ins_cost(280);
9229 format %{ "FTSTD $dst,$src1" %}
9230 opcode(0xE4, 0xD9);
9231 ins_encode( Push_Reg_D(src1),
9232 OpcS, OpcP, PopFPU,
9233 CmpF_Result(dst));
9234 ins_pipe( pipe_slow );
9235 %}
9236
9237 // Compare into -1,0,1
9238 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9239 predicate(UseSSE<=1);
9240 match(Set dst (CmpD3 src1 src2));
9241 effect(KILL cr, KILL rax);
9242 ins_cost(300);
9243 format %{ "FCMPD $dst,$src1,$src2" %}
9244 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9245 ins_encode( Push_Reg_D(src1),
9246 OpcP, RegOpc(src2),
9247 CmpF_Result(dst));
9248 ins_pipe( pipe_slow );
9249 %}
9250
9251 // float compare and set condition codes in EFLAGS by XMM regs
9252 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9253 predicate(UseSSE>=2);
9254 match(Set cr (CmpD dst src));
9255 effect(KILL rax);
9256 ins_cost(125);
9257 format %{ "COMISD $dst,$src\n"
9258 "\tJNP exit\n"
9259 "\tMOV ah,1 // saw a NaN, set CF\n"
9260 "\tSAHF\n"
9261 "exit:\tNOP // avoid branch to branch" %}
9262 opcode(0x66, 0x0F, 0x2F);
9263 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9264 ins_pipe( pipe_slow );
9265 %}
9266
9267 // float compare and set condition codes in EFLAGS by XMM regs
9268 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9269 predicate(UseSSE>=2);
9270 match(Set cr (CmpD dst (LoadD src)));
9271 effect(KILL rax);
9272 ins_cost(145);
9273 format %{ "COMISD $dst,$src\n"
9274 "\tJNP exit\n"
9275 "\tMOV ah,1 // saw a NaN, set CF\n"
9276 "\tSAHF\n"
9277 "exit:\tNOP // avoid branch to branch" %}
9278 opcode(0x66, 0x0F, 0x2F);
9279 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9280 ins_pipe( pipe_slow );
9281 %}
9282
9283 // Compare into -1,0,1 in XMM
9284 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9285 predicate(UseSSE>=2);
9286 match(Set dst (CmpD3 src1 src2));
9287 effect(KILL cr);
9288 ins_cost(255);
9289 format %{ "XOR $dst,$dst\n"
9290 "\tCOMISD $src1,$src2\n"
9291 "\tJP,s nan\n"
9292 "\tJEQ,s exit\n"
9293 "\tJA,s inc\n"
9294 "nan:\tDEC $dst\n"
9295 "\tJMP,s exit\n"
9296 "inc:\tINC $dst\n"
9297 "exit:"
9298 %}
9299 opcode(0x66, 0x0F, 0x2F);
9300 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9301 CmpX_Result(dst));
9302 ins_pipe( pipe_slow );
9303 %}
9304
9305 // Compare into -1,0,1 in XMM and memory
9306 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9307 predicate(UseSSE>=2);
9308 match(Set dst (CmpD3 src1 (LoadD mem)));
9309 effect(KILL cr);
9310 ins_cost(275);
9311 format %{ "COMISD $src1,$mem\n"
9312 "\tMOV $dst,0\t\t# do not blow flags\n"
9313 "\tJP,s nan\n"
9314 "\tJEQ,s exit\n"
9315 "\tJA,s inc\n"
9316 "nan:\tDEC $dst\n"
9317 "\tJMP,s exit\n"
9318 "inc:\tINC $dst\n"
9319 "exit:"
9320 %}
9321 opcode(0x66, 0x0F, 0x2F);
9322 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9323 LdImmI(dst,0x0), CmpX_Result(dst));
9324 ins_pipe( pipe_slow );
9325 %}
9326
9327
9328 instruct subD_reg(regD dst, regD src) %{
9329 predicate (UseSSE <=1);
9330 match(Set dst (SubD dst src));
9331
9332 format %{ "FLD $src\n\t"
9333 "DSUBp $dst,ST" %}
9334 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9335 ins_cost(150);
9336 ins_encode( Push_Reg_D(src),
9337 OpcP, RegOpc(dst) );
9338 ins_pipe( fpu_reg_reg );
9339 %}
9340
9341 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9342 predicate (UseSSE <=1);
9343 match(Set dst (RoundDouble (SubD src1 src2)));
9344 ins_cost(250);
9345
9346 format %{ "FLD $src2\n\t"
9347 "DSUB ST,$src1\n\t"
9348 "FSTP_D $dst\t# D-round" %}
9349 opcode(0xD8, 0x5);
9350 ins_encode( Push_Reg_D(src2),
9351 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9352 ins_pipe( fpu_mem_reg_reg );
9353 %}
9354
9355
9356 instruct subD_reg_mem(regD dst, memory src) %{
9357 predicate (UseSSE <=1);
9358 match(Set dst (SubD dst (LoadD src)));
9359 ins_cost(150);
9360
9361 format %{ "FLD $src\n\t"
9362 "DSUBp $dst,ST" %}
9363 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9364 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9365 OpcP, RegOpc(dst) );
9366 ins_pipe( fpu_reg_mem );
9367 %}
9368
9369 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9370 predicate (UseSSE<=1);
9371 match(Set dst (AbsD src));
9372 ins_cost(100);
9373 format %{ "FABS" %}
9374 opcode(0xE1, 0xD9);
9375 ins_encode( OpcS, OpcP );
9376 ins_pipe( fpu_reg_reg );
9377 %}
9378
9379 instruct absXD_reg( regXD dst ) %{
9380 predicate(UseSSE>=2);
9381 match(Set dst (AbsD dst));
9382 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9383 ins_encode( AbsXD_encoding(dst));
9384 ins_pipe( pipe_slow );
9385 %}
9386
9387 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9388 predicate(UseSSE<=1);
9389 match(Set dst (NegD src));
9390 ins_cost(100);
9391 format %{ "FCHS" %}
9392 opcode(0xE0, 0xD9);
9393 ins_encode( OpcS, OpcP );
9394 ins_pipe( fpu_reg_reg );
9395 %}
9396
9397 instruct negXD_reg( regXD dst ) %{
9398 predicate(UseSSE>=2);
9399 match(Set dst (NegD dst));
9400 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9401 ins_encode %{
9402 __ xorpd($dst$$XMMRegister,
9403 ExternalAddress((address)double_signflip_pool));
9404 %}
9405 ins_pipe( pipe_slow );
9406 %}
9407
9408 instruct addD_reg(regD dst, regD src) %{
9409 predicate(UseSSE<=1);
9410 match(Set dst (AddD dst src));
9411 format %{ "FLD $src\n\t"
9412 "DADD $dst,ST" %}
9413 size(4);
9414 ins_cost(150);
9415 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9416 ins_encode( Push_Reg_D(src),
9417 OpcP, RegOpc(dst) );
9418 ins_pipe( fpu_reg_reg );
9419 %}
9420
9421
9422 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9423 predicate(UseSSE<=1);
9424 match(Set dst (RoundDouble (AddD src1 src2)));
9425 ins_cost(250);
9426
9427 format %{ "FLD $src2\n\t"
9428 "DADD ST,$src1\n\t"
9429 "FSTP_D $dst\t# D-round" %}
9430 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9431 ins_encode( Push_Reg_D(src2),
9432 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9433 ins_pipe( fpu_mem_reg_reg );
9434 %}
9435
9436
9437 instruct addD_reg_mem(regD dst, memory src) %{
9438 predicate(UseSSE<=1);
9439 match(Set dst (AddD dst (LoadD src)));
9440 ins_cost(150);
9441
9442 format %{ "FLD $src\n\t"
9443 "DADDp $dst,ST" %}
9444 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9445 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9446 OpcP, RegOpc(dst) );
9447 ins_pipe( fpu_reg_mem );
9448 %}
9449
9450 // add-to-memory
9451 instruct addD_mem_reg(memory dst, regD src) %{
9452 predicate(UseSSE<=1);
9453 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9454 ins_cost(150);
9455
9456 format %{ "FLD_D $dst\n\t"
9457 "DADD ST,$src\n\t"
9458 "FST_D $dst" %}
9459 opcode(0xDD, 0x0);
9460 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9461 Opcode(0xD8), RegOpc(src),
9462 set_instruction_start,
9463 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9464 ins_pipe( fpu_reg_mem );
9465 %}
9466
9467 instruct addD_reg_imm1(regD dst, immD1 src) %{
9468 predicate(UseSSE<=1);
9469 match(Set dst (AddD dst src));
9470 ins_cost(125);
9471 format %{ "FLD1\n\t"
9472 "DADDp $dst,ST" %}
9473 opcode(0xDE, 0x00);
9474 ins_encode( LdImmD(src),
9475 OpcP, RegOpc(dst) );
9476 ins_pipe( fpu_reg );
9477 %}
9478
9479 instruct addD_reg_imm(regD dst, immD src) %{
9480 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9481 match(Set dst (AddD dst src));
9482 ins_cost(200);
9483 format %{ "FLD_D [$src]\n\t"
9484 "DADDp $dst,ST" %}
9485 opcode(0xDE, 0x00); /* DE /0 */
9486 ins_encode( LdImmD(src),
9487 OpcP, RegOpc(dst));
9488 ins_pipe( fpu_reg_mem );
9489 %}
9490
9491 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9492 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9493 match(Set dst (RoundDouble (AddD src con)));
9494 ins_cost(200);
9495 format %{ "FLD_D [$con]\n\t"
9496 "DADD ST,$src\n\t"
9497 "FSTP_D $dst\t# D-round" %}
9498 opcode(0xD8, 0x00); /* D8 /0 */
9499 ins_encode( LdImmD(con),
9500 OpcP, RegOpc(src), Pop_Mem_D(dst));
9501 ins_pipe( fpu_mem_reg_con );
9502 %}
9503
9504 // Add two double precision floating point values in xmm
9505 instruct addXD_reg(regXD dst, regXD src) %{
9506 predicate(UseSSE>=2);
9507 match(Set dst (AddD dst src));
9508 format %{ "ADDSD $dst,$src" %}
9509 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
9510 ins_pipe( pipe_slow );
9511 %}
9512
9513 instruct addXD_imm(regXD dst, immXD con) %{
9514 predicate(UseSSE>=2);
9515 match(Set dst (AddD dst con));
9516 format %{ "ADDSD $dst,[$con]" %}
9517 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
9518 ins_pipe( pipe_slow );
9519 %}
9520
9521 instruct addXD_mem(regXD dst, memory mem) %{
9522 predicate(UseSSE>=2);
9523 match(Set dst (AddD dst (LoadD mem)));
9524 format %{ "ADDSD $dst,$mem" %}
9525 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
9526 ins_pipe( pipe_slow );
9527 %}
9528
9529 // Sub two double precision floating point values in xmm
9530 instruct subXD_reg(regXD dst, regXD src) %{
9531 predicate(UseSSE>=2);
9532 match(Set dst (SubD dst src));
9533 format %{ "SUBSD $dst,$src" %}
9534 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
9535 ins_pipe( pipe_slow );
9536 %}
9537
9538 instruct subXD_imm(regXD dst, immXD con) %{
9539 predicate(UseSSE>=2);
9540 match(Set dst (SubD dst con));
9541 format %{ "SUBSD $dst,[$con]" %}
9542 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
9543 ins_pipe( pipe_slow );
9544 %}
9545
9546 instruct subXD_mem(regXD dst, memory mem) %{
9547 predicate(UseSSE>=2);
9548 match(Set dst (SubD dst (LoadD mem)));
9549 format %{ "SUBSD $dst,$mem" %}
9550 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
9551 ins_pipe( pipe_slow );
9552 %}
9553
9554 // Mul two double precision floating point values in xmm
9555 instruct mulXD_reg(regXD dst, regXD src) %{
9556 predicate(UseSSE>=2);
9557 match(Set dst (MulD dst src));
9558 format %{ "MULSD $dst,$src" %}
9559 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
9560 ins_pipe( pipe_slow );
9561 %}
9562
9563 instruct mulXD_imm(regXD dst, immXD con) %{
9564 predicate(UseSSE>=2);
9565 match(Set dst (MulD dst con));
9566 format %{ "MULSD $dst,[$con]" %}
9567 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
9568 ins_pipe( pipe_slow );
9569 %}
9570
9571 instruct mulXD_mem(regXD dst, memory mem) %{
9572 predicate(UseSSE>=2);
9573 match(Set dst (MulD dst (LoadD mem)));
9574 format %{ "MULSD $dst,$mem" %}
9575 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
9576 ins_pipe( pipe_slow );
9577 %}
9578
9579 // Div two double precision floating point values in xmm
9580 instruct divXD_reg(regXD dst, regXD src) %{
9581 predicate(UseSSE>=2);
9582 match(Set dst (DivD dst src));
9583 format %{ "DIVSD $dst,$src" %}
9584 opcode(0xF2, 0x0F, 0x5E);
9585 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
9586 ins_pipe( pipe_slow );
9587 %}
9588
9589 instruct divXD_imm(regXD dst, immXD con) %{
9590 predicate(UseSSE>=2);
9591 match(Set dst (DivD dst con));
9592 format %{ "DIVSD $dst,[$con]" %}
9593 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
9594 ins_pipe( pipe_slow );
9595 %}
9596
9597 instruct divXD_mem(regXD dst, memory mem) %{
9598 predicate(UseSSE>=2);
9599 match(Set dst (DivD dst (LoadD mem)));
9600 format %{ "DIVSD $dst,$mem" %}
9601 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
9602 ins_pipe( pipe_slow );
9603 %}
9604
9605
9606 instruct mulD_reg(regD dst, regD src) %{
9607 predicate(UseSSE<=1);
9608 match(Set dst (MulD dst src));
9609 format %{ "FLD $src\n\t"
9610 "DMULp $dst,ST" %}
9611 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9612 ins_cost(150);
9613 ins_encode( Push_Reg_D(src),
9614 OpcP, RegOpc(dst) );
9615 ins_pipe( fpu_reg_reg );
9616 %}
9617
9618 // Strict FP instruction biases argument before multiply then
9619 // biases result to avoid double rounding of subnormals.
9620 //
9621 // scale arg1 by multiplying arg1 by 2^(-15360)
9622 // load arg2
9623 // multiply scaled arg1 by arg2
9624 // rescale product by 2^(15360)
9625 //
9626 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
9627 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9628 match(Set dst (MulD dst src));
9629 ins_cost(1); // Select this instruction for all strict FP double multiplies
9630
9631 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9632 "DMULp $dst,ST\n\t"
9633 "FLD $src\n\t"
9634 "DMULp $dst,ST\n\t"
9635 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9636 "DMULp $dst,ST\n\t" %}
9637 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9638 ins_encode( strictfp_bias1(dst),
9639 Push_Reg_D(src),
9640 OpcP, RegOpc(dst),
9641 strictfp_bias2(dst) );
9642 ins_pipe( fpu_reg_reg );
9643 %}
9644
9645 instruct mulD_reg_imm(regD dst, immD src) %{
9646 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9647 match(Set dst (MulD dst src));
9648 ins_cost(200);
9649 format %{ "FLD_D [$src]\n\t"
9650 "DMULp $dst,ST" %}
9651 opcode(0xDE, 0x1); /* DE /1 */
9652 ins_encode( LdImmD(src),
9653 OpcP, RegOpc(dst) );
9654 ins_pipe( fpu_reg_mem );
9655 %}
9656
9657
9658 instruct mulD_reg_mem(regD dst, memory src) %{
9659 predicate( UseSSE<=1 );
9660 match(Set dst (MulD dst (LoadD src)));
9661 ins_cost(200);
9662 format %{ "FLD_D $src\n\t"
9663 "DMULp $dst,ST" %}
9664 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9665 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9666 OpcP, RegOpc(dst) );
9667 ins_pipe( fpu_reg_mem );
9668 %}
9669
9670 //
9671 // Cisc-alternate to reg-reg multiply
9672 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
9673 predicate( UseSSE<=1 );
9674 match(Set dst (MulD src (LoadD mem)));
9675 ins_cost(250);
9676 format %{ "FLD_D $mem\n\t"
9677 "DMUL ST,$src\n\t"
9678 "FSTP_D $dst" %}
9679 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9680 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9681 OpcReg_F(src),
9682 Pop_Reg_D(dst) );
9683 ins_pipe( fpu_reg_reg_mem );
9684 %}
9685
9686
9687 // MACRO3 -- addD a mulD
9688 // This instruction is a '2-address' instruction in that the result goes
9689 // back to src2. This eliminates a move from the macro; possibly the
9690 // register allocator will have to add it back (and maybe not).
9691 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
9692 predicate( UseSSE<=1 );
9693 match(Set src2 (AddD (MulD src0 src1) src2));
9694 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9695 "DMUL ST,$src1\n\t"
9696 "DADDp $src2,ST" %}
9697 ins_cost(250);
9698 opcode(0xDD); /* LoadD DD /0 */
9699 ins_encode( Push_Reg_F(src0),
9700 FMul_ST_reg(src1),
9701 FAddP_reg_ST(src2) );
9702 ins_pipe( fpu_reg_reg_reg );
9703 %}
9704
9705
9706 // MACRO3 -- subD a mulD
9707 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
9708 predicate( UseSSE<=1 );
9709 match(Set src2 (SubD (MulD src0 src1) src2));
9710 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9711 "DMUL ST,$src1\n\t"
9712 "DSUBRp $src2,ST" %}
9713 ins_cost(250);
9714 ins_encode( Push_Reg_F(src0),
9715 FMul_ST_reg(src1),
9716 Opcode(0xDE), Opc_plus(0xE0,src2));
9717 ins_pipe( fpu_reg_reg_reg );
9718 %}
9719
9720
9721 instruct divD_reg(regD dst, regD src) %{
9722 predicate( UseSSE<=1 );
9723 match(Set dst (DivD dst src));
9724
9725 format %{ "FLD $src\n\t"
9726 "FDIVp $dst,ST" %}
9727 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9728 ins_cost(150);
9729 ins_encode( Push_Reg_D(src),
9730 OpcP, RegOpc(dst) );
9731 ins_pipe( fpu_reg_reg );
9732 %}
9733
9734 // Strict FP instruction biases argument before division then
9735 // biases result, to avoid double rounding of subnormals.
9736 //
9737 // scale dividend by multiplying dividend by 2^(-15360)
9738 // load divisor
9739 // divide scaled dividend by divisor
9740 // rescale quotient by 2^(15360)
9741 //
9742 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
9743 predicate (UseSSE<=1);
9744 match(Set dst (DivD dst src));
9745 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9746 ins_cost(01);
9747
9748 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9749 "DMULp $dst,ST\n\t"
9750 "FLD $src\n\t"
9751 "FDIVp $dst,ST\n\t"
9752 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9753 "DMULp $dst,ST\n\t" %}
9754 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9755 ins_encode( strictfp_bias1(dst),
9756 Push_Reg_D(src),
9757 OpcP, RegOpc(dst),
9758 strictfp_bias2(dst) );
9759 ins_pipe( fpu_reg_reg );
9760 %}
9761
9762 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9763 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9764 match(Set dst (RoundDouble (DivD src1 src2)));
9765
9766 format %{ "FLD $src1\n\t"
9767 "FDIV ST,$src2\n\t"
9768 "FSTP_D $dst\t# D-round" %}
9769 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9770 ins_encode( Push_Reg_D(src1),
9771 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
9772 ins_pipe( fpu_mem_reg_reg );
9773 %}
9774
9775
9776 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
9777 predicate(UseSSE<=1);
9778 match(Set dst (ModD dst src));
9779 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
9780
9781 format %{ "DMOD $dst,$src" %}
9782 ins_cost(250);
9783 ins_encode(Push_Reg_Mod_D(dst, src),
9784 emitModD(),
9785 Push_Result_Mod_D(src),
9786 Pop_Reg_D(dst));
9787 ins_pipe( pipe_slow );
9788 %}
9789
9790 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
9791 predicate(UseSSE>=2);
9792 match(Set dst (ModD src0 src1));
9793 effect(KILL rax, KILL cr);
9794
9795 format %{ "SUB ESP,8\t # DMOD\n"
9796 "\tMOVSD [ESP+0],$src1\n"
9797 "\tFLD_D [ESP+0]\n"
9798 "\tMOVSD [ESP+0],$src0\n"
9799 "\tFLD_D [ESP+0]\n"
9800 "loop:\tFPREM\n"
9801 "\tFWAIT\n"
9802 "\tFNSTSW AX\n"
9803 "\tSAHF\n"
9804 "\tJP loop\n"
9805 "\tFSTP_D [ESP+0]\n"
9806 "\tMOVSD $dst,[ESP+0]\n"
9807 "\tADD ESP,8\n"
9808 "\tFSTP ST0\t # Restore FPU Stack"
9809 %}
9810 ins_cost(250);
9811 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
9812 ins_pipe( pipe_slow );
9813 %}
9814
9815 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
9816 predicate (UseSSE<=1);
9817 match(Set dst (SinD src));
9818 ins_cost(1800);
9819 format %{ "DSIN $dst" %}
9820 opcode(0xD9, 0xFE);
9821 ins_encode( OpcP, OpcS );
9822 ins_pipe( pipe_slow );
9823 %}
9824
9825 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
9826 predicate (UseSSE>=2);
9827 match(Set dst (SinD dst));
9828 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9829 ins_cost(1800);
9830 format %{ "DSIN $dst" %}
9831 opcode(0xD9, 0xFE);
9832 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9833 ins_pipe( pipe_slow );
9834 %}
9835
9836 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
9837 predicate (UseSSE<=1);
9838 match(Set dst (CosD src));
9839 ins_cost(1800);
9840 format %{ "DCOS $dst" %}
9841 opcode(0xD9, 0xFF);
9842 ins_encode( OpcP, OpcS );
9843 ins_pipe( pipe_slow );
9844 %}
9845
9846 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
9847 predicate (UseSSE>=2);
9848 match(Set dst (CosD dst));
9849 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9850 ins_cost(1800);
9851 format %{ "DCOS $dst" %}
9852 opcode(0xD9, 0xFF);
9853 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9854 ins_pipe( pipe_slow );
9855 %}
9856
9857 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
9858 predicate (UseSSE<=1);
9859 match(Set dst(TanD src));
9860 format %{ "DTAN $dst" %}
9861 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9862 Opcode(0xDD), Opcode(0xD8)); // fstp st
9863 ins_pipe( pipe_slow );
9864 %}
9865
9866 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
9867 predicate (UseSSE>=2);
9868 match(Set dst(TanD dst));
9869 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9870 format %{ "DTAN $dst" %}
9871 ins_encode( Push_SrcXD(dst),
9872 Opcode(0xD9), Opcode(0xF2), // fptan
9873 Opcode(0xDD), Opcode(0xD8), // fstp st
9874 Push_ResultXD(dst) );
9875 ins_pipe( pipe_slow );
9876 %}
9877
9878 instruct atanD_reg(regD dst, regD src) %{
9879 predicate (UseSSE<=1);
9880 match(Set dst(AtanD dst src));
9881 format %{ "DATA $dst,$src" %}
9882 opcode(0xD9, 0xF3);
9883 ins_encode( Push_Reg_D(src),
9884 OpcP, OpcS, RegOpc(dst) );
9885 ins_pipe( pipe_slow );
9886 %}
9887
9888 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
9889 predicate (UseSSE>=2);
9890 match(Set dst(AtanD dst src));
9891 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9892 format %{ "DATA $dst,$src" %}
9893 opcode(0xD9, 0xF3);
9894 ins_encode( Push_SrcXD(src),
9895 OpcP, OpcS, Push_ResultXD(dst) );
9896 ins_pipe( pipe_slow );
9897 %}
9898
9899 instruct sqrtD_reg(regD dst, regD src) %{
9900 predicate (UseSSE<=1);
9901 match(Set dst (SqrtD src));
9902 format %{ "DSQRT $dst,$src" %}
9903 opcode(0xFA, 0xD9);
9904 ins_encode( Push_Reg_D(src),
9905 OpcS, OpcP, Pop_Reg_D(dst) );
9906 ins_pipe( pipe_slow );
9907 %}
9908
9909 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9910 predicate (UseSSE<=1);
9911 match(Set Y (PowD X Y)); // Raise X to the Yth power
9912 effect(KILL rax, KILL rbx, KILL rcx);
9913 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
9914 "FLD_D $X\n\t"
9915 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
9916
9917 "FDUP \t\t\t# Q Q\n\t"
9918 "FRNDINT\t\t\t# int(Q) Q\n\t"
9919 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9920 "FISTP dword [ESP]\n\t"
9921 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9922 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9923 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9924 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9925 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9926 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9927 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9928 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9929 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9930 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9931 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9932 "MOV [ESP+0],0\n\t"
9933 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9934
9935 "ADD ESP,8"
9936 %}
9937 ins_encode( push_stack_temp_qword,
9938 Push_Reg_D(X),
9939 Opcode(0xD9), Opcode(0xF1), // fyl2x
9940 pow_exp_core_encoding,
9941 pop_stack_temp_qword);
9942 ins_pipe( pipe_slow );
9943 %}
9944
9945 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
9946 predicate (UseSSE>=2);
9947 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9948 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
9949 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
9950 "MOVSD [ESP],$src1\n\t"
9951 "FLD FPR1,$src1\n\t"
9952 "MOVSD [ESP],$src0\n\t"
9953 "FLD FPR1,$src0\n\t"
9954 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
9955
9956 "FDUP \t\t\t# Q Q\n\t"
9957 "FRNDINT\t\t\t# int(Q) Q\n\t"
9958 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9959 "FISTP dword [ESP]\n\t"
9960 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9961 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9962 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9963 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9964 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9965 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9966 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9967 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9968 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9969 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9970 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9971 "MOV [ESP+0],0\n\t"
9972 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9973
9974 "FST_D [ESP]\n\t"
9975 "MOVSD $dst,[ESP]\n\t"
9976 "ADD ESP,8"
9977 %}
9978 ins_encode( push_stack_temp_qword,
9979 push_xmm_to_fpr1(src1),
9980 push_xmm_to_fpr1(src0),
9981 Opcode(0xD9), Opcode(0xF1), // fyl2x
9982 pow_exp_core_encoding,
9983 Push_ResultXD(dst) );
9984 ins_pipe( pipe_slow );
9985 %}
9986
9987
9988 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9989 predicate (UseSSE<=1);
9990 match(Set dpr1 (ExpD dpr1));
9991 effect(KILL rax, KILL rbx, KILL rcx);
9992 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
9993 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
9994 "FMULP \t\t\t# Q=X*log2(e)\n\t"
9995
9996 "FDUP \t\t\t# Q Q\n\t"
9997 "FRNDINT\t\t\t# int(Q) Q\n\t"
9998 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9999 "FISTP dword [ESP]\n\t"
10000 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10001 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10002 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10003 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10004 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10005 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10006 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10007 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10008 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10009 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10010 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10011 "MOV [ESP+0],0\n\t"
10012 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10013
10014 "ADD ESP,8"
10015 %}
10016 ins_encode( push_stack_temp_qword,
10017 Opcode(0xD9), Opcode(0xEA), // fldl2e
10018 Opcode(0xDE), Opcode(0xC9), // fmulp
10019 pow_exp_core_encoding,
10020 pop_stack_temp_qword);
10021 ins_pipe( pipe_slow );
10022 %}
10023
10024 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10025 predicate (UseSSE>=2);
10026 match(Set dst (ExpD src));
10027 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10028 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10029 "MOVSD [ESP],$src\n\t"
10030 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10031 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10032
10033 "FDUP \t\t\t# Q Q\n\t"
10034 "FRNDINT\t\t\t# int(Q) Q\n\t"
10035 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10036 "FISTP dword [ESP]\n\t"
10037 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10038 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10039 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10040 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10041 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10042 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10043 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10044 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10045 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10046 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10047 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10048 "MOV [ESP+0],0\n\t"
10049 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10050
10051 "FST_D [ESP]\n\t"
10052 "MOVSD $dst,[ESP]\n\t"
10053 "ADD ESP,8"
10054 %}
10055 ins_encode( Push_SrcXD(src),
10056 Opcode(0xD9), Opcode(0xEA), // fldl2e
10057 Opcode(0xDE), Opcode(0xC9), // fmulp
10058 pow_exp_core_encoding,
10059 Push_ResultXD(dst) );
10060 ins_pipe( pipe_slow );
10061 %}
10062
10063
10064
10065 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10066 predicate (UseSSE<=1);
10067 // The source Double operand on FPU stack
10068 match(Set dst (Log10D src));
10069 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10070 // fxch ; swap ST(0) with ST(1)
10071 // fyl2x ; compute log_10(2) * log_2(x)
10072 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10073 "FXCH \n\t"
10074 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10075 %}
10076 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10077 Opcode(0xD9), Opcode(0xC9), // fxch
10078 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10079
10080 ins_pipe( pipe_slow );
10081 %}
10082
10083 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10084 predicate (UseSSE>=2);
10085 effect(KILL cr);
10086 match(Set dst (Log10D src));
10087 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10088 // fyl2x ; compute log_10(2) * log_2(x)
10089 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10090 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10091 %}
10092 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10093 Push_SrcXD(src),
10094 Opcode(0xD9), Opcode(0xF1), // fyl2x
10095 Push_ResultXD(dst));
10096
10097 ins_pipe( pipe_slow );
10098 %}
10099
10100 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10101 predicate (UseSSE<=1);
10102 // The source Double operand on FPU stack
10103 match(Set dst (LogD src));
10104 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10105 // fxch ; swap ST(0) with ST(1)
10106 // fyl2x ; compute log_e(2) * log_2(x)
10107 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10108 "FXCH \n\t"
10109 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10110 %}
10111 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10112 Opcode(0xD9), Opcode(0xC9), // fxch
10113 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10114
10115 ins_pipe( pipe_slow );
10116 %}
10117
10118 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10119 predicate (UseSSE>=2);
10120 effect(KILL cr);
10121 // The source and result Double operands in XMM registers
10122 match(Set dst (LogD src));
10123 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10124 // fyl2x ; compute log_e(2) * log_2(x)
10125 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10126 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10127 %}
10128 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10129 Push_SrcXD(src),
10130 Opcode(0xD9), Opcode(0xF1), // fyl2x
10131 Push_ResultXD(dst));
10132 ins_pipe( pipe_slow );
10133 %}
10134
10135 //-------------Float Instructions-------------------------------
10136 // Float Math
10137
10138 // Code for float compare:
10139 // fcompp();
10140 // fwait(); fnstsw_ax();
10141 // sahf();
10142 // movl(dst, unordered_result);
10143 // jcc(Assembler::parity, exit);
10144 // movl(dst, less_result);
10145 // jcc(Assembler::below, exit);
10146 // movl(dst, equal_result);
10147 // jcc(Assembler::equal, exit);
10148 // movl(dst, greater_result);
10149 // exit:
10150
10151 // P6 version of float compare, sets condition codes in EFLAGS
10152 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10153 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10154 match(Set cr (CmpF src1 src2));
10155 effect(KILL rax);
10156 ins_cost(150);
10157 format %{ "FLD $src1\n\t"
10158 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10159 "JNP exit\n\t"
10160 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10161 "SAHF\n"
10162 "exit:\tNOP // avoid branch to branch" %}
10163 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10164 ins_encode( Push_Reg_D(src1),
10165 OpcP, RegOpc(src2),
10166 cmpF_P6_fixup );
10167 ins_pipe( pipe_slow );
10168 %}
10169
10170
10171 // Compare & branch
10172 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10173 predicate(UseSSE == 0);
10174 match(Set cr (CmpF src1 src2));
10175 effect(KILL rax);
10176 ins_cost(200);
10177 format %{ "FLD $src1\n\t"
10178 "FCOMp $src2\n\t"
10179 "FNSTSW AX\n\t"
10180 "TEST AX,0x400\n\t"
10181 "JZ,s flags\n\t"
10182 "MOV AH,1\t# unordered treat as LT\n"
10183 "flags:\tSAHF" %}
10184 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10185 ins_encode( Push_Reg_D(src1),
10186 OpcP, RegOpc(src2),
10187 fpu_flags);
10188 ins_pipe( pipe_slow );
10189 %}
10190
10191 // Compare vs zero into -1,0,1
10192 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10193 predicate(UseSSE == 0);
10194 match(Set dst (CmpF3 src1 zero));
10195 effect(KILL cr, KILL rax);
10196 ins_cost(280);
10197 format %{ "FTSTF $dst,$src1" %}
10198 opcode(0xE4, 0xD9);
10199 ins_encode( Push_Reg_D(src1),
10200 OpcS, OpcP, PopFPU,
10201 CmpF_Result(dst));
10202 ins_pipe( pipe_slow );
10203 %}
10204
10205 // Compare into -1,0,1
10206 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10207 predicate(UseSSE == 0);
10208 match(Set dst (CmpF3 src1 src2));
10209 effect(KILL cr, KILL rax);
10210 ins_cost(300);
10211 format %{ "FCMPF $dst,$src1,$src2" %}
10212 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10213 ins_encode( Push_Reg_D(src1),
10214 OpcP, RegOpc(src2),
10215 CmpF_Result(dst));
10216 ins_pipe( pipe_slow );
10217 %}
10218
10219 // float compare and set condition codes in EFLAGS by XMM regs
10220 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10221 predicate(UseSSE>=1);
10222 match(Set cr (CmpF dst src));
10223 effect(KILL rax);
10224 ins_cost(145);
10225 format %{ "COMISS $dst,$src\n"
10226 "\tJNP exit\n"
10227 "\tMOV ah,1 // saw a NaN, set CF\n"
10228 "\tSAHF\n"
10229 "exit:\tNOP // avoid branch to branch" %}
10230 opcode(0x0F, 0x2F);
10231 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10232 ins_pipe( pipe_slow );
10233 %}
10234
10235 // float compare and set condition codes in EFLAGS by XMM regs
10236 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10237 predicate(UseSSE>=1);
10238 match(Set cr (CmpF dst (LoadF src)));
10239 effect(KILL rax);
10240 ins_cost(165);
10241 format %{ "COMISS $dst,$src\n"
10242 "\tJNP exit\n"
10243 "\tMOV ah,1 // saw a NaN, set CF\n"
10244 "\tSAHF\n"
10245 "exit:\tNOP // avoid branch to branch" %}
10246 opcode(0x0F, 0x2F);
10247 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10248 ins_pipe( pipe_slow );
10249 %}
10250
10251 // Compare into -1,0,1 in XMM
10252 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10253 predicate(UseSSE>=1);
10254 match(Set dst (CmpF3 src1 src2));
10255 effect(KILL cr);
10256 ins_cost(255);
10257 format %{ "XOR $dst,$dst\n"
10258 "\tCOMISS $src1,$src2\n"
10259 "\tJP,s nan\n"
10260 "\tJEQ,s exit\n"
10261 "\tJA,s inc\n"
10262 "nan:\tDEC $dst\n"
10263 "\tJMP,s exit\n"
10264 "inc:\tINC $dst\n"
10265 "exit:"
10266 %}
10267 opcode(0x0F, 0x2F);
10268 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10269 ins_pipe( pipe_slow );
10270 %}
10271
10272 // Compare into -1,0,1 in XMM and memory
10273 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10274 predicate(UseSSE>=1);
10275 match(Set dst (CmpF3 src1 (LoadF mem)));
10276 effect(KILL cr);
10277 ins_cost(275);
10278 format %{ "COMISS $src1,$mem\n"
10279 "\tMOV $dst,0\t\t# do not blow flags\n"
10280 "\tJP,s nan\n"
10281 "\tJEQ,s exit\n"
10282 "\tJA,s inc\n"
10283 "nan:\tDEC $dst\n"
10284 "\tJMP,s exit\n"
10285 "inc:\tINC $dst\n"
10286 "exit:"
10287 %}
10288 opcode(0x0F, 0x2F);
10289 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10290 ins_pipe( pipe_slow );
10291 %}
10292
10293 // Spill to obtain 24-bit precision
10294 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10295 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10296 match(Set dst (SubF src1 src2));
10297
10298 format %{ "FSUB $dst,$src1 - $src2" %}
10299 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10300 ins_encode( Push_Reg_F(src1),
10301 OpcReg_F(src2),
10302 Pop_Mem_F(dst) );
10303 ins_pipe( fpu_mem_reg_reg );
10304 %}
10305 //
10306 // This instruction does not round to 24-bits
10307 instruct subF_reg(regF dst, regF src) %{
10308 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10309 match(Set dst (SubF dst src));
10310
10311 format %{ "FSUB $dst,$src" %}
10312 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10313 ins_encode( Push_Reg_F(src),
10314 OpcP, RegOpc(dst) );
10315 ins_pipe( fpu_reg_reg );
10316 %}
10317
10318 // Spill to obtain 24-bit precision
10319 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10320 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10321 match(Set dst (AddF src1 src2));
10322
10323 format %{ "FADD $dst,$src1,$src2" %}
10324 opcode(0xD8, 0x0); /* D8 C0+i */
10325 ins_encode( Push_Reg_F(src2),
10326 OpcReg_F(src1),
10327 Pop_Mem_F(dst) );
10328 ins_pipe( fpu_mem_reg_reg );
10329 %}
10330 //
10331 // This instruction does not round to 24-bits
10332 instruct addF_reg(regF dst, regF src) %{
10333 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10334 match(Set dst (AddF dst src));
10335
10336 format %{ "FLD $src\n\t"
10337 "FADDp $dst,ST" %}
10338 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10339 ins_encode( Push_Reg_F(src),
10340 OpcP, RegOpc(dst) );
10341 ins_pipe( fpu_reg_reg );
10342 %}
10343
10344 // Add two single precision floating point values in xmm
10345 instruct addX_reg(regX dst, regX src) %{
10346 predicate(UseSSE>=1);
10347 match(Set dst (AddF dst src));
10348 format %{ "ADDSS $dst,$src" %}
10349 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10350 ins_pipe( pipe_slow );
10351 %}
10352
10353 instruct addX_imm(regX dst, immXF con) %{
10354 predicate(UseSSE>=1);
10355 match(Set dst (AddF dst con));
10356 format %{ "ADDSS $dst,[$con]" %}
10357 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10358 ins_pipe( pipe_slow );
10359 %}
10360
10361 instruct addX_mem(regX dst, memory mem) %{
10362 predicate(UseSSE>=1);
10363 match(Set dst (AddF dst (LoadF mem)));
10364 format %{ "ADDSS $dst,$mem" %}
10365 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10366 ins_pipe( pipe_slow );
10367 %}
10368
10369 // Subtract two single precision floating point values in xmm
10370 instruct subX_reg(regX dst, regX src) %{
10371 predicate(UseSSE>=1);
10372 match(Set dst (SubF dst src));
10373 format %{ "SUBSS $dst,$src" %}
10374 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10375 ins_pipe( pipe_slow );
10376 %}
10377
10378 instruct subX_imm(regX dst, immXF con) %{
10379 predicate(UseSSE>=1);
10380 match(Set dst (SubF dst con));
10381 format %{ "SUBSS $dst,[$con]" %}
10382 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10383 ins_pipe( pipe_slow );
10384 %}
10385
10386 instruct subX_mem(regX dst, memory mem) %{
10387 predicate(UseSSE>=1);
10388 match(Set dst (SubF dst (LoadF mem)));
10389 format %{ "SUBSS $dst,$mem" %}
10390 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10391 ins_pipe( pipe_slow );
10392 %}
10393
10394 // Multiply two single precision floating point values in xmm
10395 instruct mulX_reg(regX dst, regX src) %{
10396 predicate(UseSSE>=1);
10397 match(Set dst (MulF dst src));
10398 format %{ "MULSS $dst,$src" %}
10399 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10400 ins_pipe( pipe_slow );
10401 %}
10402
10403 instruct mulX_imm(regX dst, immXF con) %{
10404 predicate(UseSSE>=1);
10405 match(Set dst (MulF dst con));
10406 format %{ "MULSS $dst,[$con]" %}
10407 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10408 ins_pipe( pipe_slow );
10409 %}
10410
10411 instruct mulX_mem(regX dst, memory mem) %{
10412 predicate(UseSSE>=1);
10413 match(Set dst (MulF dst (LoadF mem)));
10414 format %{ "MULSS $dst,$mem" %}
10415 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10416 ins_pipe( pipe_slow );
10417 %}
10418
10419 // Divide two single precision floating point values in xmm
10420 instruct divX_reg(regX dst, regX src) %{
10421 predicate(UseSSE>=1);
10422 match(Set dst (DivF dst src));
10423 format %{ "DIVSS $dst,$src" %}
10424 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10425 ins_pipe( pipe_slow );
10426 %}
10427
10428 instruct divX_imm(regX dst, immXF con) %{
10429 predicate(UseSSE>=1);
10430 match(Set dst (DivF dst con));
10431 format %{ "DIVSS $dst,[$con]" %}
10432 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10433 ins_pipe( pipe_slow );
10434 %}
10435
10436 instruct divX_mem(regX dst, memory mem) %{
10437 predicate(UseSSE>=1);
10438 match(Set dst (DivF dst (LoadF mem)));
10439 format %{ "DIVSS $dst,$mem" %}
10440 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10441 ins_pipe( pipe_slow );
10442 %}
10443
10444 // Get the square root of a single precision floating point values in xmm
10445 instruct sqrtX_reg(regX dst, regX src) %{
10446 predicate(UseSSE>=1);
10447 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10448 format %{ "SQRTSS $dst,$src" %}
10449 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10450 ins_pipe( pipe_slow );
10451 %}
10452
10453 instruct sqrtX_mem(regX dst, memory mem) %{
10454 predicate(UseSSE>=1);
10455 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10456 format %{ "SQRTSS $dst,$mem" %}
10457 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10458 ins_pipe( pipe_slow );
10459 %}
10460
10461 // Get the square root of a double precision floating point values in xmm
10462 instruct sqrtXD_reg(regXD dst, regXD src) %{
10463 predicate(UseSSE>=2);
10464 match(Set dst (SqrtD src));
10465 format %{ "SQRTSD $dst,$src" %}
10466 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10467 ins_pipe( pipe_slow );
10468 %}
10469
10470 instruct sqrtXD_mem(regXD dst, memory mem) %{
10471 predicate(UseSSE>=2);
10472 match(Set dst (SqrtD (LoadD mem)));
10473 format %{ "SQRTSD $dst,$mem" %}
10474 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10475 ins_pipe( pipe_slow );
10476 %}
10477
10478 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10479 predicate(UseSSE==0);
10480 match(Set dst (AbsF src));
10481 ins_cost(100);
10482 format %{ "FABS" %}
10483 opcode(0xE1, 0xD9);
10484 ins_encode( OpcS, OpcP );
10485 ins_pipe( fpu_reg_reg );
10486 %}
10487
10488 instruct absX_reg(regX dst ) %{
10489 predicate(UseSSE>=1);
10490 match(Set dst (AbsF dst));
10491 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
10492 ins_encode( AbsXF_encoding(dst));
10493 ins_pipe( pipe_slow );
10494 %}
10495
10496 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
10497 predicate(UseSSE==0);
10498 match(Set dst (NegF src));
10499 ins_cost(100);
10500 format %{ "FCHS" %}
10501 opcode(0xE0, 0xD9);
10502 ins_encode( OpcS, OpcP );
10503 ins_pipe( fpu_reg_reg );
10504 %}
10505
10506 instruct negX_reg( regX dst ) %{
10507 predicate(UseSSE>=1);
10508 match(Set dst (NegF dst));
10509 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
10510 ins_encode( NegXF_encoding(dst));
10511 ins_pipe( pipe_slow );
10512 %}
10513
10514 // Cisc-alternate to addF_reg
10515 // Spill to obtain 24-bit precision
10516 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10517 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10518 match(Set dst (AddF src1 (LoadF src2)));
10519
10520 format %{ "FLD $src2\n\t"
10521 "FADD ST,$src1\n\t"
10522 "FSTP_S $dst" %}
10523 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10524 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10525 OpcReg_F(src1),
10526 Pop_Mem_F(dst) );
10527 ins_pipe( fpu_mem_reg_mem );
10528 %}
10529 //
10530 // Cisc-alternate to addF_reg
10531 // This instruction does not round to 24-bits
10532 instruct addF_reg_mem(regF dst, memory src) %{
10533 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10534 match(Set dst (AddF dst (LoadF src)));
10535
10536 format %{ "FADD $dst,$src" %}
10537 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10538 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10539 OpcP, RegOpc(dst) );
10540 ins_pipe( fpu_reg_mem );
10541 %}
10542
10543 // // Following two instructions for _222_mpegaudio
10544 // Spill to obtain 24-bit precision
10545 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
10546 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10547 match(Set dst (AddF src1 src2));
10548
10549 format %{ "FADD $dst,$src1,$src2" %}
10550 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10551 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10552 OpcReg_F(src2),
10553 Pop_Mem_F(dst) );
10554 ins_pipe( fpu_mem_reg_mem );
10555 %}
10556
10557 // Cisc-spill variant
10558 // Spill to obtain 24-bit precision
10559 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10560 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10561 match(Set dst (AddF src1 (LoadF src2)));
10562
10563 format %{ "FADD $dst,$src1,$src2 cisc" %}
10564 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10565 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10566 set_instruction_start,
10567 OpcP, RMopc_Mem(secondary,src1),
10568 Pop_Mem_F(dst) );
10569 ins_pipe( fpu_mem_mem_mem );
10570 %}
10571
10572 // Spill to obtain 24-bit precision
10573 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10574 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10575 match(Set dst (AddF src1 src2));
10576
10577 format %{ "FADD $dst,$src1,$src2" %}
10578 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10579 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10580 set_instruction_start,
10581 OpcP, RMopc_Mem(secondary,src1),
10582 Pop_Mem_F(dst) );
10583 ins_pipe( fpu_mem_mem_mem );
10584 %}
10585
10586
10587 // Spill to obtain 24-bit precision
10588 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10589 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10590 match(Set dst (AddF src1 src2));
10591 format %{ "FLD $src1\n\t"
10592 "FADD $src2\n\t"
10593 "FSTP_S $dst" %}
10594 opcode(0xD8, 0x00); /* D8 /0 */
10595 ins_encode( Push_Reg_F(src1),
10596 Opc_MemImm_F(src2),
10597 Pop_Mem_F(dst));
10598 ins_pipe( fpu_mem_reg_con );
10599 %}
10600 //
10601 // This instruction does not round to 24-bits
10602 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
10603 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10604 match(Set dst (AddF src1 src2));
10605 format %{ "FLD $src1\n\t"
10606 "FADD $src2\n\t"
10607 "FSTP_S $dst" %}
10608 opcode(0xD8, 0x00); /* D8 /0 */
10609 ins_encode( Push_Reg_F(src1),
10610 Opc_MemImm_F(src2),
10611 Pop_Reg_F(dst));
10612 ins_pipe( fpu_reg_reg_con );
10613 %}
10614
10615 // Spill to obtain 24-bit precision
10616 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
10617 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10618 match(Set dst (MulF src1 src2));
10619
10620 format %{ "FLD $src1\n\t"
10621 "FMUL $src2\n\t"
10622 "FSTP_S $dst" %}
10623 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10624 ins_encode( Push_Reg_F(src1),
10625 OpcReg_F(src2),
10626 Pop_Mem_F(dst) );
10627 ins_pipe( fpu_mem_reg_reg );
10628 %}
10629 //
10630 // This instruction does not round to 24-bits
10631 instruct mulF_reg(regF dst, regF src1, regF src2) %{
10632 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10633 match(Set dst (MulF src1 src2));
10634
10635 format %{ "FLD $src1\n\t"
10636 "FMUL $src2\n\t"
10637 "FSTP_S $dst" %}
10638 opcode(0xD8, 0x1); /* D8 C8+i */
10639 ins_encode( Push_Reg_F(src2),
10640 OpcReg_F(src1),
10641 Pop_Reg_F(dst) );
10642 ins_pipe( fpu_reg_reg_reg );
10643 %}
10644
10645
10646 // Spill to obtain 24-bit precision
10647 // Cisc-alternate to reg-reg multiply
10648 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10649 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10650 match(Set dst (MulF src1 (LoadF src2)));
10651
10652 format %{ "FLD_S $src2\n\t"
10653 "FMUL $src1\n\t"
10654 "FSTP_S $dst" %}
10655 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10656 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10657 OpcReg_F(src1),
10658 Pop_Mem_F(dst) );
10659 ins_pipe( fpu_mem_reg_mem );
10660 %}
10661 //
10662 // This instruction does not round to 24-bits
10663 // Cisc-alternate to reg-reg multiply
10664 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
10665 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10666 match(Set dst (MulF src1 (LoadF src2)));
10667
10668 format %{ "FMUL $dst,$src1,$src2" %}
10669 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10670 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10671 OpcReg_F(src1),
10672 Pop_Reg_F(dst) );
10673 ins_pipe( fpu_reg_reg_mem );
10674 %}
10675
10676 // Spill to obtain 24-bit precision
10677 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10678 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10679 match(Set dst (MulF src1 src2));
10680
10681 format %{ "FMUL $dst,$src1,$src2" %}
10682 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10683 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10684 set_instruction_start,
10685 OpcP, RMopc_Mem(secondary,src1),
10686 Pop_Mem_F(dst) );
10687 ins_pipe( fpu_mem_mem_mem );
10688 %}
10689
10690 // Spill to obtain 24-bit precision
10691 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10692 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10693 match(Set dst (MulF src1 src2));
10694
10695 format %{ "FMULc $dst,$src1,$src2" %}
10696 opcode(0xD8, 0x1); /* D8 /1*/
10697 ins_encode( Push_Reg_F(src1),
10698 Opc_MemImm_F(src2),
10699 Pop_Mem_F(dst));
10700 ins_pipe( fpu_mem_reg_con );
10701 %}
10702 //
10703 // This instruction does not round to 24-bits
10704 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
10705 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10706 match(Set dst (MulF src1 src2));
10707
10708 format %{ "FMULc $dst. $src1, $src2" %}
10709 opcode(0xD8, 0x1); /* D8 /1*/
10710 ins_encode( Push_Reg_F(src1),
10711 Opc_MemImm_F(src2),
10712 Pop_Reg_F(dst));
10713 ins_pipe( fpu_reg_reg_con );
10714 %}
10715
10716
10717 //
10718 // MACRO1 -- subsume unshared load into mulF
10719 // This instruction does not round to 24-bits
10720 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
10721 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10722 match(Set dst (MulF (LoadF mem1) src));
10723
10724 format %{ "FLD $mem1 ===MACRO1===\n\t"
10725 "FMUL ST,$src\n\t"
10726 "FSTP $dst" %}
10727 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10728 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10729 OpcReg_F(src),
10730 Pop_Reg_F(dst) );
10731 ins_pipe( fpu_reg_reg_mem );
10732 %}
10733 //
10734 // MACRO2 -- addF a mulF which subsumed an unshared load
10735 // This instruction does not round to 24-bits
10736 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
10737 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10738 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10739 ins_cost(95);
10740
10741 format %{ "FLD $mem1 ===MACRO2===\n\t"
10742 "FMUL ST,$src1 subsume mulF left load\n\t"
10743 "FADD ST,$src2\n\t"
10744 "FSTP $dst" %}
10745 opcode(0xD9); /* LoadF D9 /0 */
10746 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10747 FMul_ST_reg(src1),
10748 FAdd_ST_reg(src2),
10749 Pop_Reg_F(dst) );
10750 ins_pipe( fpu_reg_mem_reg_reg );
10751 %}
10752
10753 // MACRO3 -- addF a mulF
10754 // This instruction does not round to 24-bits. It is a '2-address'
10755 // instruction in that the result goes back to src2. This eliminates
10756 // a move from the macro; possibly the register allocator will have
10757 // to add it back (and maybe not).
10758 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
10759 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10760 match(Set src2 (AddF (MulF src0 src1) src2));
10761
10762 format %{ "FLD $src0 ===MACRO3===\n\t"
10763 "FMUL ST,$src1\n\t"
10764 "FADDP $src2,ST" %}
10765 opcode(0xD9); /* LoadF D9 /0 */
10766 ins_encode( Push_Reg_F(src0),
10767 FMul_ST_reg(src1),
10768 FAddP_reg_ST(src2) );
10769 ins_pipe( fpu_reg_reg_reg );
10770 %}
10771
10772 // MACRO4 -- divF subF
10773 // This instruction does not round to 24-bits
10774 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
10775 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10776 match(Set dst (DivF (SubF src2 src1) src3));
10777
10778 format %{ "FLD $src2 ===MACRO4===\n\t"
10779 "FSUB ST,$src1\n\t"
10780 "FDIV ST,$src3\n\t"
10781 "FSTP $dst" %}
10782 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10783 ins_encode( Push_Reg_F(src2),
10784 subF_divF_encode(src1,src3),
10785 Pop_Reg_F(dst) );
10786 ins_pipe( fpu_reg_reg_reg_reg );
10787 %}
10788
10789 // Spill to obtain 24-bit precision
10790 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
10791 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10792 match(Set dst (DivF src1 src2));
10793
10794 format %{ "FDIV $dst,$src1,$src2" %}
10795 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10796 ins_encode( Push_Reg_F(src1),
10797 OpcReg_F(src2),
10798 Pop_Mem_F(dst) );
10799 ins_pipe( fpu_mem_reg_reg );
10800 %}
10801 //
10802 // This instruction does not round to 24-bits
10803 instruct divF_reg(regF dst, regF src) %{
10804 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10805 match(Set dst (DivF dst src));
10806
10807 format %{ "FDIV $dst,$src" %}
10808 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10809 ins_encode( Push_Reg_F(src),
10810 OpcP, RegOpc(dst) );
10811 ins_pipe( fpu_reg_reg );
10812 %}
10813
10814
10815 // Spill to obtain 24-bit precision
10816 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10817 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10818 match(Set dst (ModF src1 src2));
10819 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10820
10821 format %{ "FMOD $dst,$src1,$src2" %}
10822 ins_encode( Push_Reg_Mod_D(src1, src2),
10823 emitModD(),
10824 Push_Result_Mod_D(src2),
10825 Pop_Mem_F(dst));
10826 ins_pipe( pipe_slow );
10827 %}
10828 //
10829 // This instruction does not round to 24-bits
10830 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
10831 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10832 match(Set dst (ModF dst src));
10833 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10834
10835 format %{ "FMOD $dst,$src" %}
10836 ins_encode(Push_Reg_Mod_D(dst, src),
10837 emitModD(),
10838 Push_Result_Mod_D(src),
10839 Pop_Reg_F(dst));
10840 ins_pipe( pipe_slow );
10841 %}
10842
10843 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
10844 predicate(UseSSE>=1);
10845 match(Set dst (ModF src0 src1));
10846 effect(KILL rax, KILL cr);
10847 format %{ "SUB ESP,4\t # FMOD\n"
10848 "\tMOVSS [ESP+0],$src1\n"
10849 "\tFLD_S [ESP+0]\n"
10850 "\tMOVSS [ESP+0],$src0\n"
10851 "\tFLD_S [ESP+0]\n"
10852 "loop:\tFPREM\n"
10853 "\tFWAIT\n"
10854 "\tFNSTSW AX\n"
10855 "\tSAHF\n"
10856 "\tJP loop\n"
10857 "\tFSTP_S [ESP+0]\n"
10858 "\tMOVSS $dst,[ESP+0]\n"
10859 "\tADD ESP,4\n"
10860 "\tFSTP ST0\t # Restore FPU Stack"
10861 %}
10862 ins_cost(250);
10863 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
10864 ins_pipe( pipe_slow );
10865 %}
10866
10867
10868 //----------Arithmetic Conversion Instructions---------------------------------
10869 // The conversions operations are all Alpha sorted. Please keep it that way!
10870
10871 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
10872 predicate(UseSSE==0);
10873 match(Set dst (RoundFloat src));
10874 ins_cost(125);
10875 format %{ "FST_S $dst,$src\t# F-round" %}
10876 ins_encode( Pop_Mem_Reg_F(dst, src) );
10877 ins_pipe( fpu_mem_reg );
10878 %}
10879
10880 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
10881 predicate(UseSSE<=1);
10882 match(Set dst (RoundDouble src));
10883 ins_cost(125);
10884 format %{ "FST_D $dst,$src\t# D-round" %}
10885 ins_encode( Pop_Mem_Reg_D(dst, src) );
10886 ins_pipe( fpu_mem_reg );
10887 %}
10888
10889 // Force rounding to 24-bit precision and 6-bit exponent
10890 instruct convD2F_reg(stackSlotF dst, regD src) %{
10891 predicate(UseSSE==0);
10892 match(Set dst (ConvD2F src));
10893 format %{ "FST_S $dst,$src\t# F-round" %}
10894 expand %{
10895 roundFloat_mem_reg(dst,src);
10896 %}
10897 %}
10898
10899 // Force rounding to 24-bit precision and 6-bit exponent
10900 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
10901 predicate(UseSSE==1);
10902 match(Set dst (ConvD2F src));
10903 effect( KILL cr );
10904 format %{ "SUB ESP,4\n\t"
10905 "FST_S [ESP],$src\t# F-round\n\t"
10906 "MOVSS $dst,[ESP]\n\t"
10907 "ADD ESP,4" %}
10908 ins_encode( D2X_encoding(dst, src) );
10909 ins_pipe( pipe_slow );
10910 %}
10911
10912 // Force rounding double precision to single precision
10913 instruct convXD2X_reg(regX dst, regXD src) %{
10914 predicate(UseSSE>=2);
10915 match(Set dst (ConvD2F src));
10916 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10917 opcode(0xF2, 0x0F, 0x5A);
10918 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10919 ins_pipe( pipe_slow );
10920 %}
10921
10922 instruct convF2D_reg_reg(regD dst, regF src) %{
10923 predicate(UseSSE==0);
10924 match(Set dst (ConvF2D src));
10925 format %{ "FST_S $dst,$src\t# D-round" %}
10926 ins_encode( Pop_Reg_Reg_D(dst, src));
10927 ins_pipe( fpu_reg_reg );
10928 %}
10929
10930 instruct convF2D_reg(stackSlotD dst, regF src) %{
10931 predicate(UseSSE==1);
10932 match(Set dst (ConvF2D src));
10933 format %{ "FST_D $dst,$src\t# D-round" %}
10934 expand %{
10935 roundDouble_mem_reg(dst,src);
10936 %}
10937 %}
10938
10939 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
10940 predicate(UseSSE==1);
10941 match(Set dst (ConvF2D src));
10942 effect( KILL cr );
10943 format %{ "SUB ESP,4\n\t"
10944 "MOVSS [ESP] $src\n\t"
10945 "FLD_S [ESP]\n\t"
10946 "ADD ESP,4\n\t"
10947 "FSTP $dst\t# D-round" %}
10948 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
10949 ins_pipe( pipe_slow );
10950 %}
10951
10952 instruct convX2XD_reg(regXD dst, regX src) %{
10953 predicate(UseSSE>=2);
10954 match(Set dst (ConvF2D src));
10955 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10956 opcode(0xF3, 0x0F, 0x5A);
10957 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10958 ins_pipe( pipe_slow );
10959 %}
10960
10961 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10962 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10963 predicate(UseSSE<=1);
10964 match(Set dst (ConvD2I src));
10965 effect( KILL tmp, KILL cr );
10966 format %{ "FLD $src\t# Convert double to int \n\t"
10967 "FLDCW trunc mode\n\t"
10968 "SUB ESP,4\n\t"
10969 "FISTp [ESP + #0]\n\t"
10970 "FLDCW std/24-bit mode\n\t"
10971 "POP EAX\n\t"
10972 "CMP EAX,0x80000000\n\t"
10973 "JNE,s fast\n\t"
10974 "FLD_D $src\n\t"
10975 "CALL d2i_wrapper\n"
10976 "fast:" %}
10977 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
10978 ins_pipe( pipe_slow );
10979 %}
10980
10981 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10982 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
10983 predicate(UseSSE>=2);
10984 match(Set dst (ConvD2I src));
10985 effect( KILL tmp, KILL cr );
10986 format %{ "CVTTSD2SI $dst, $src\n\t"
10987 "CMP $dst,0x80000000\n\t"
10988 "JNE,s fast\n\t"
10989 "SUB ESP, 8\n\t"
10990 "MOVSD [ESP], $src\n\t"
10991 "FLD_D [ESP]\n\t"
10992 "ADD ESP, 8\n\t"
10993 "CALL d2i_wrapper\n"
10994 "fast:" %}
10995 opcode(0x1); // double-precision conversion
10996 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
10997 ins_pipe( pipe_slow );
10998 %}
10999
11000 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11001 predicate(UseSSE<=1);
11002 match(Set dst (ConvD2L src));
11003 effect( KILL cr );
11004 format %{ "FLD $src\t# Convert double to long\n\t"
11005 "FLDCW trunc mode\n\t"
11006 "SUB ESP,8\n\t"
11007 "FISTp [ESP + #0]\n\t"
11008 "FLDCW std/24-bit mode\n\t"
11009 "POP EAX\n\t"
11010 "POP EDX\n\t"
11011 "CMP EDX,0x80000000\n\t"
11012 "JNE,s fast\n\t"
11013 "TEST EAX,EAX\n\t"
11014 "JNE,s fast\n\t"
11015 "FLD $src\n\t"
11016 "CALL d2l_wrapper\n"
11017 "fast:" %}
11018 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11019 ins_pipe( pipe_slow );
11020 %}
11021
11022 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11023 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11024 predicate (UseSSE>=2);
11025 match(Set dst (ConvD2L src));
11026 effect( KILL cr );
11027 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11028 "MOVSD [ESP],$src\n\t"
11029 "FLD_D [ESP]\n\t"
11030 "FLDCW trunc mode\n\t"
11031 "FISTp [ESP + #0]\n\t"
11032 "FLDCW std/24-bit mode\n\t"
11033 "POP EAX\n\t"
11034 "POP EDX\n\t"
11035 "CMP EDX,0x80000000\n\t"
11036 "JNE,s fast\n\t"
11037 "TEST EAX,EAX\n\t"
11038 "JNE,s fast\n\t"
11039 "SUB ESP,8\n\t"
11040 "MOVSD [ESP],$src\n\t"
11041 "FLD_D [ESP]\n\t"
11042 "CALL d2l_wrapper\n"
11043 "fast:" %}
11044 ins_encode( XD2L_encoding(src) );
11045 ins_pipe( pipe_slow );
11046 %}
11047
11048 // Convert a double to an int. Java semantics require we do complex
11049 // manglations in the corner cases. So we set the rounding mode to
11050 // 'zero', store the darned double down as an int, and reset the
11051 // rounding mode to 'nearest'. The hardware stores a flag value down
11052 // if we would overflow or converted a NAN; we check for this and
11053 // and go the slow path if needed.
11054 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11055 predicate(UseSSE==0);
11056 match(Set dst (ConvF2I src));
11057 effect( KILL tmp, KILL cr );
11058 format %{ "FLD $src\t# Convert float to int \n\t"
11059 "FLDCW trunc mode\n\t"
11060 "SUB ESP,4\n\t"
11061 "FISTp [ESP + #0]\n\t"
11062 "FLDCW std/24-bit mode\n\t"
11063 "POP EAX\n\t"
11064 "CMP EAX,0x80000000\n\t"
11065 "JNE,s fast\n\t"
11066 "FLD $src\n\t"
11067 "CALL d2i_wrapper\n"
11068 "fast:" %}
11069 // D2I_encoding works for F2I
11070 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11071 ins_pipe( pipe_slow );
11072 %}
11073
11074 // Convert a float in xmm to an int reg.
11075 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11076 predicate(UseSSE>=1);
11077 match(Set dst (ConvF2I src));
11078 effect( KILL tmp, KILL cr );
11079 format %{ "CVTTSS2SI $dst, $src\n\t"
11080 "CMP $dst,0x80000000\n\t"
11081 "JNE,s fast\n\t"
11082 "SUB ESP, 4\n\t"
11083 "MOVSS [ESP], $src\n\t"
11084 "FLD [ESP]\n\t"
11085 "ADD ESP, 4\n\t"
11086 "CALL d2i_wrapper\n"
11087 "fast:" %}
11088 opcode(0x0); // single-precision conversion
11089 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11090 ins_pipe( pipe_slow );
11091 %}
11092
11093 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11094 predicate(UseSSE==0);
11095 match(Set dst (ConvF2L src));
11096 effect( KILL cr );
11097 format %{ "FLD $src\t# Convert float to long\n\t"
11098 "FLDCW trunc mode\n\t"
11099 "SUB ESP,8\n\t"
11100 "FISTp [ESP + #0]\n\t"
11101 "FLDCW std/24-bit mode\n\t"
11102 "POP EAX\n\t"
11103 "POP EDX\n\t"
11104 "CMP EDX,0x80000000\n\t"
11105 "JNE,s fast\n\t"
11106 "TEST EAX,EAX\n\t"
11107 "JNE,s fast\n\t"
11108 "FLD $src\n\t"
11109 "CALL d2l_wrapper\n"
11110 "fast:" %}
11111 // D2L_encoding works for F2L
11112 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11113 ins_pipe( pipe_slow );
11114 %}
11115
11116 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11117 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11118 predicate (UseSSE>=1);
11119 match(Set dst (ConvF2L src));
11120 effect( KILL cr );
11121 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11122 "MOVSS [ESP],$src\n\t"
11123 "FLD_S [ESP]\n\t"
11124 "FLDCW trunc mode\n\t"
11125 "FISTp [ESP + #0]\n\t"
11126 "FLDCW std/24-bit mode\n\t"
11127 "POP EAX\n\t"
11128 "POP EDX\n\t"
11129 "CMP EDX,0x80000000\n\t"
11130 "JNE,s fast\n\t"
11131 "TEST EAX,EAX\n\t"
11132 "JNE,s fast\n\t"
11133 "SUB ESP,4\t# Convert float to long\n\t"
11134 "MOVSS [ESP],$src\n\t"
11135 "FLD_S [ESP]\n\t"
11136 "ADD ESP,4\n\t"
11137 "CALL d2l_wrapper\n"
11138 "fast:" %}
11139 ins_encode( X2L_encoding(src) );
11140 ins_pipe( pipe_slow );
11141 %}
11142
11143 instruct convI2D_reg(regD dst, stackSlotI src) %{
11144 predicate( UseSSE<=1 );
11145 match(Set dst (ConvI2D src));
11146 format %{ "FILD $src\n\t"
11147 "FSTP $dst" %}
11148 opcode(0xDB, 0x0); /* DB /0 */
11149 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11150 ins_pipe( fpu_reg_mem );
11151 %}
11152
11153 instruct convI2XD_reg(regXD dst, eRegI src) %{
11154 predicate( UseSSE>=2 && !UseXmmI2D );
11155 match(Set dst (ConvI2D src));
11156 format %{ "CVTSI2SD $dst,$src" %}
11157 opcode(0xF2, 0x0F, 0x2A);
11158 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11159 ins_pipe( pipe_slow );
11160 %}
11161
11162 instruct convI2XD_mem(regXD dst, memory mem) %{
11163 predicate( UseSSE>=2 );
11164 match(Set dst (ConvI2D (LoadI mem)));
11165 format %{ "CVTSI2SD $dst,$mem" %}
11166 opcode(0xF2, 0x0F, 0x2A);
11167 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11168 ins_pipe( pipe_slow );
11169 %}
11170
11171 instruct convXI2XD_reg(regXD dst, eRegI src)
11172 %{
11173 predicate( UseSSE>=2 && UseXmmI2D );
11174 match(Set dst (ConvI2D src));
11175
11176 format %{ "MOVD $dst,$src\n\t"
11177 "CVTDQ2PD $dst,$dst\t# i2d" %}
11178 ins_encode %{
11179 __ movdl($dst$$XMMRegister, $src$$Register);
11180 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11181 %}
11182 ins_pipe(pipe_slow); // XXX
11183 %}
11184
11185 instruct convI2D_mem(regD dst, memory mem) %{
11186 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11187 match(Set dst (ConvI2D (LoadI mem)));
11188 format %{ "FILD $mem\n\t"
11189 "FSTP $dst" %}
11190 opcode(0xDB); /* DB /0 */
11191 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11192 Pop_Reg_D(dst));
11193 ins_pipe( fpu_reg_mem );
11194 %}
11195
11196 // Convert a byte to a float; no rounding step needed.
11197 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11198 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11199 match(Set dst (ConvI2F src));
11200 format %{ "FILD $src\n\t"
11201 "FSTP $dst" %}
11202
11203 opcode(0xDB, 0x0); /* DB /0 */
11204 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11205 ins_pipe( fpu_reg_mem );
11206 %}
11207
11208 // In 24-bit mode, force exponent rounding by storing back out
11209 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11210 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11211 match(Set dst (ConvI2F src));
11212 ins_cost(200);
11213 format %{ "FILD $src\n\t"
11214 "FSTP_S $dst" %}
11215 opcode(0xDB, 0x0); /* DB /0 */
11216 ins_encode( Push_Mem_I(src),
11217 Pop_Mem_F(dst));
11218 ins_pipe( fpu_mem_mem );
11219 %}
11220
11221 // In 24-bit mode, force exponent rounding by storing back out
11222 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11223 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11224 match(Set dst (ConvI2F (LoadI mem)));
11225 ins_cost(200);
11226 format %{ "FILD $mem\n\t"
11227 "FSTP_S $dst" %}
11228 opcode(0xDB); /* DB /0 */
11229 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11230 Pop_Mem_F(dst));
11231 ins_pipe( fpu_mem_mem );
11232 %}
11233
11234 // This instruction does not round to 24-bits
11235 instruct convI2F_reg(regF dst, stackSlotI src) %{
11236 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11237 match(Set dst (ConvI2F src));
11238 format %{ "FILD $src\n\t"
11239 "FSTP $dst" %}
11240 opcode(0xDB, 0x0); /* DB /0 */
11241 ins_encode( Push_Mem_I(src),
11242 Pop_Reg_F(dst));
11243 ins_pipe( fpu_reg_mem );
11244 %}
11245
11246 // This instruction does not round to 24-bits
11247 instruct convI2F_mem(regF dst, memory mem) %{
11248 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11249 match(Set dst (ConvI2F (LoadI mem)));
11250 format %{ "FILD $mem\n\t"
11251 "FSTP $dst" %}
11252 opcode(0xDB); /* DB /0 */
11253 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11254 Pop_Reg_F(dst));
11255 ins_pipe( fpu_reg_mem );
11256 %}
11257
11258 // Convert an int to a float in xmm; no rounding step needed.
11259 instruct convI2X_reg(regX dst, eRegI src) %{
11260 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11261 match(Set dst (ConvI2F src));
11262 format %{ "CVTSI2SS $dst, $src" %}
11263
11264 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11265 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11266 ins_pipe( pipe_slow );
11267 %}
11268
11269 instruct convXI2X_reg(regX dst, eRegI src)
11270 %{
11271 predicate( UseSSE>=2 && UseXmmI2F );
11272 match(Set dst (ConvI2F src));
11273
11274 format %{ "MOVD $dst,$src\n\t"
11275 "CVTDQ2PS $dst,$dst\t# i2f" %}
11276 ins_encode %{
11277 __ movdl($dst$$XMMRegister, $src$$Register);
11278 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11279 %}
11280 ins_pipe(pipe_slow); // XXX
11281 %}
11282
11283 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11284 match(Set dst (ConvI2L src));
11285 effect(KILL cr);
11286 format %{ "MOV $dst.lo,$src\n\t"
11287 "MOV $dst.hi,$src\n\t"
11288 "SAR $dst.hi,31" %}
11289 ins_encode(convert_int_long(dst,src));
11290 ins_pipe( ialu_reg_reg_long );
11291 %}
11292
11293 // Zero-extend convert int to long
11294 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11295 match(Set dst (AndL (ConvI2L src) mask) );
11296 effect( KILL flags );
11297 format %{ "MOV $dst.lo,$src\n\t"
11298 "XOR $dst.hi,$dst.hi" %}
11299 opcode(0x33); // XOR
11300 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11301 ins_pipe( ialu_reg_reg_long );
11302 %}
11303
11304 // Zero-extend long
11305 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11306 match(Set dst (AndL src mask) );
11307 effect( KILL flags );
11308 format %{ "MOV $dst.lo,$src.lo\n\t"
11309 "XOR $dst.hi,$dst.hi\n\t" %}
11310 opcode(0x33); // XOR
11311 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11312 ins_pipe( ialu_reg_reg_long );
11313 %}
11314
11315 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11316 predicate (UseSSE<=1);
11317 match(Set dst (ConvL2D src));
11318 effect( KILL cr );
11319 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11320 "PUSH $src.lo\n\t"
11321 "FILD ST,[ESP + #0]\n\t"
11322 "ADD ESP,8\n\t"
11323 "FSTP_D $dst\t# D-round" %}
11324 opcode(0xDF, 0x5); /* DF /5 */
11325 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11326 ins_pipe( pipe_slow );
11327 %}
11328
11329 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11330 predicate (UseSSE>=2);
11331 match(Set dst (ConvL2D src));
11332 effect( KILL cr );
11333 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11334 "PUSH $src.lo\n\t"
11335 "FILD_D [ESP]\n\t"
11336 "FSTP_D [ESP]\n\t"
11337 "MOVSD $dst,[ESP]\n\t"
11338 "ADD ESP,8" %}
11339 opcode(0xDF, 0x5); /* DF /5 */
11340 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11341 ins_pipe( pipe_slow );
11342 %}
11343
11344 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11345 predicate (UseSSE>=1);
11346 match(Set dst (ConvL2F src));
11347 effect( KILL cr );
11348 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11349 "PUSH $src.lo\n\t"
11350 "FILD_D [ESP]\n\t"
11351 "FSTP_S [ESP]\n\t"
11352 "MOVSS $dst,[ESP]\n\t"
11353 "ADD ESP,8" %}
11354 opcode(0xDF, 0x5); /* DF /5 */
11355 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11356 ins_pipe( pipe_slow );
11357 %}
11358
11359 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11360 match(Set dst (ConvL2F src));
11361 effect( KILL cr );
11362 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11363 "PUSH $src.lo\n\t"
11364 "FILD ST,[ESP + #0]\n\t"
11365 "ADD ESP,8\n\t"
11366 "FSTP_S $dst\t# F-round" %}
11367 opcode(0xDF, 0x5); /* DF /5 */
11368 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11369 ins_pipe( pipe_slow );
11370 %}
11371
11372 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11373 match(Set dst (ConvL2I src));
11374 effect( DEF dst, USE src );
11375 format %{ "MOV $dst,$src.lo" %}
11376 ins_encode(enc_CopyL_Lo(dst,src));
11377 ins_pipe( ialu_reg_reg );
11378 %}
11379
11380
11381 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11382 match(Set dst (MoveF2I src));
11383 effect( DEF dst, USE src );
11384 ins_cost(100);
11385 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11386 opcode(0x8B);
11387 ins_encode( OpcP, RegMem(dst,src));
11388 ins_pipe( ialu_reg_mem );
11389 %}
11390
11391 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11392 predicate(UseSSE==0);
11393 match(Set dst (MoveF2I src));
11394 effect( DEF dst, USE src );
11395
11396 ins_cost(125);
11397 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11398 ins_encode( Pop_Mem_Reg_F(dst, src) );
11399 ins_pipe( fpu_mem_reg );
11400 %}
11401
11402 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11403 predicate(UseSSE>=1);
11404 match(Set dst (MoveF2I src));
11405 effect( DEF dst, USE src );
11406
11407 ins_cost(95);
11408 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11409 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11410 ins_pipe( pipe_slow );
11411 %}
11412
11413 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11414 predicate(UseSSE>=2);
11415 match(Set dst (MoveF2I src));
11416 effect( DEF dst, USE src );
11417 ins_cost(85);
11418 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11419 ins_encode( MovX2I_reg(dst, src));
11420 ins_pipe( pipe_slow );
11421 %}
11422
11423 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11424 match(Set dst (MoveI2F src));
11425 effect( DEF dst, USE src );
11426
11427 ins_cost(100);
11428 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11429 opcode(0x89);
11430 ins_encode( OpcPRegSS( dst, src ) );
11431 ins_pipe( ialu_mem_reg );
11432 %}
11433
11434
11435 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11436 predicate(UseSSE==0);
11437 match(Set dst (MoveI2F src));
11438 effect(DEF dst, USE src);
11439
11440 ins_cost(125);
11441 format %{ "FLD_S $src\n\t"
11442 "FSTP $dst\t# MoveI2F_stack_reg" %}
11443 opcode(0xD9); /* D9 /0, FLD m32real */
11444 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11445 Pop_Reg_F(dst) );
11446 ins_pipe( fpu_reg_mem );
11447 %}
11448
11449 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11450 predicate(UseSSE>=1);
11451 match(Set dst (MoveI2F src));
11452 effect( DEF dst, USE src );
11453
11454 ins_cost(95);
11455 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11456 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11457 ins_pipe( pipe_slow );
11458 %}
11459
11460 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11461 predicate(UseSSE>=2);
11462 match(Set dst (MoveI2F src));
11463 effect( DEF dst, USE src );
11464
11465 ins_cost(85);
11466 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11467 ins_encode( MovI2X_reg(dst, src) );
11468 ins_pipe( pipe_slow );
11469 %}
11470
11471 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11472 match(Set dst (MoveD2L src));
11473 effect(DEF dst, USE src);
11474
11475 ins_cost(250);
11476 format %{ "MOV $dst.lo,$src\n\t"
11477 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11478 opcode(0x8B, 0x8B);
11479 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11480 ins_pipe( ialu_mem_long_reg );
11481 %}
11482
11483 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11484 predicate(UseSSE<=1);
11485 match(Set dst (MoveD2L src));
11486 effect(DEF dst, USE src);
11487
11488 ins_cost(125);
11489 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11490 ins_encode( Pop_Mem_Reg_D(dst, src) );
11491 ins_pipe( fpu_mem_reg );
11492 %}
11493
11494 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
11495 predicate(UseSSE>=2);
11496 match(Set dst (MoveD2L src));
11497 effect(DEF dst, USE src);
11498 ins_cost(95);
11499
11500 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11501 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
11502 ins_pipe( pipe_slow );
11503 %}
11504
11505 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
11506 predicate(UseSSE>=2);
11507 match(Set dst (MoveD2L src));
11508 effect(DEF dst, USE src, TEMP tmp);
11509 ins_cost(85);
11510 format %{ "MOVD $dst.lo,$src\n\t"
11511 "PSHUFLW $tmp,$src,0x4E\n\t"
11512 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11513 ins_encode( MovXD2L_reg(dst, src, tmp) );
11514 ins_pipe( pipe_slow );
11515 %}
11516
11517 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11518 match(Set dst (MoveL2D src));
11519 effect(DEF dst, USE src);
11520
11521 ins_cost(200);
11522 format %{ "MOV $dst,$src.lo\n\t"
11523 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11524 opcode(0x89, 0x89);
11525 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11526 ins_pipe( ialu_mem_long_reg );
11527 %}
11528
11529
11530 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11531 predicate(UseSSE<=1);
11532 match(Set dst (MoveL2D src));
11533 effect(DEF dst, USE src);
11534 ins_cost(125);
11535
11536 format %{ "FLD_D $src\n\t"
11537 "FSTP $dst\t# MoveL2D_stack_reg" %}
11538 opcode(0xDD); /* DD /0, FLD m64real */
11539 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11540 Pop_Reg_D(dst) );
11541 ins_pipe( fpu_reg_mem );
11542 %}
11543
11544
11545 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
11546 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11547 match(Set dst (MoveL2D src));
11548 effect(DEF dst, USE src);
11549
11550 ins_cost(95);
11551 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11552 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11553 ins_pipe( pipe_slow );
11554 %}
11555
11556 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
11557 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11558 match(Set dst (MoveL2D src));
11559 effect(DEF dst, USE src);
11560
11561 ins_cost(95);
11562 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11563 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
11564 ins_pipe( pipe_slow );
11565 %}
11566
11567 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
11568 predicate(UseSSE>=2);
11569 match(Set dst (MoveL2D src));
11570 effect(TEMP dst, USE src, TEMP tmp);
11571 ins_cost(85);
11572 format %{ "MOVD $dst,$src.lo\n\t"
11573 "MOVD $tmp,$src.hi\n\t"
11574 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11575 ins_encode( MovL2XD_reg(dst, src, tmp) );
11576 ins_pipe( pipe_slow );
11577 %}
11578
11579 // Replicate scalar to packed byte (1 byte) values in xmm
11580 instruct Repl8B_reg(regXD dst, regXD src) %{
11581 predicate(UseSSE>=2);
11582 match(Set dst (Replicate8B src));
11583 format %{ "MOVDQA $dst,$src\n\t"
11584 "PUNPCKLBW $dst,$dst\n\t"
11585 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11586 ins_encode( pshufd_8x8(dst, src));
11587 ins_pipe( pipe_slow );
11588 %}
11589
11590 // Replicate scalar to packed byte (1 byte) values in xmm
11591 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
11592 predicate(UseSSE>=2);
11593 match(Set dst (Replicate8B src));
11594 format %{ "MOVD $dst,$src\n\t"
11595 "PUNPCKLBW $dst,$dst\n\t"
11596 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11597 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11598 ins_pipe( pipe_slow );
11599 %}
11600
11601 // Replicate scalar zero to packed byte (1 byte) values in xmm
11602 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
11603 predicate(UseSSE>=2);
11604 match(Set dst (Replicate8B zero));
11605 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11606 ins_encode( pxor(dst, dst));
11607 ins_pipe( fpu_reg_reg );
11608 %}
11609
11610 // Replicate scalar to packed shore (2 byte) values in xmm
11611 instruct Repl4S_reg(regXD dst, regXD src) %{
11612 predicate(UseSSE>=2);
11613 match(Set dst (Replicate4S src));
11614 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11615 ins_encode( pshufd_4x16(dst, src));
11616 ins_pipe( fpu_reg_reg );
11617 %}
11618
11619 // Replicate scalar to packed shore (2 byte) values in xmm
11620 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
11621 predicate(UseSSE>=2);
11622 match(Set dst (Replicate4S src));
11623 format %{ "MOVD $dst,$src\n\t"
11624 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11625 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11626 ins_pipe( fpu_reg_reg );
11627 %}
11628
11629 // Replicate scalar zero to packed short (2 byte) values in xmm
11630 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
11631 predicate(UseSSE>=2);
11632 match(Set dst (Replicate4S zero));
11633 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11634 ins_encode( pxor(dst, dst));
11635 ins_pipe( fpu_reg_reg );
11636 %}
11637
11638 // Replicate scalar to packed char (2 byte) values in xmm
11639 instruct Repl4C_reg(regXD dst, regXD src) %{
11640 predicate(UseSSE>=2);
11641 match(Set dst (Replicate4C src));
11642 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11643 ins_encode( pshufd_4x16(dst, src));
11644 ins_pipe( fpu_reg_reg );
11645 %}
11646
11647 // Replicate scalar to packed char (2 byte) values in xmm
11648 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
11649 predicate(UseSSE>=2);
11650 match(Set dst (Replicate4C src));
11651 format %{ "MOVD $dst,$src\n\t"
11652 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11653 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11654 ins_pipe( fpu_reg_reg );
11655 %}
11656
11657 // Replicate scalar zero to packed char (2 byte) values in xmm
11658 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
11659 predicate(UseSSE>=2);
11660 match(Set dst (Replicate4C zero));
11661 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11662 ins_encode( pxor(dst, dst));
11663 ins_pipe( fpu_reg_reg );
11664 %}
11665
11666 // Replicate scalar to packed integer (4 byte) values in xmm
11667 instruct Repl2I_reg(regXD dst, regXD src) %{
11668 predicate(UseSSE>=2);
11669 match(Set dst (Replicate2I src));
11670 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11671 ins_encode( pshufd(dst, src, 0x00));
11672 ins_pipe( fpu_reg_reg );
11673 %}
11674
11675 // Replicate scalar to packed integer (4 byte) values in xmm
11676 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
11677 predicate(UseSSE>=2);
11678 match(Set dst (Replicate2I src));
11679 format %{ "MOVD $dst,$src\n\t"
11680 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11681 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
11682 ins_pipe( fpu_reg_reg );
11683 %}
11684
11685 // Replicate scalar zero to packed integer (2 byte) values in xmm
11686 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
11687 predicate(UseSSE>=2);
11688 match(Set dst (Replicate2I zero));
11689 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11690 ins_encode( pxor(dst, dst));
11691 ins_pipe( fpu_reg_reg );
11692 %}
11693
11694 // Replicate scalar to packed single precision floating point values in xmm
11695 instruct Repl2F_reg(regXD dst, regXD src) %{
11696 predicate(UseSSE>=2);
11697 match(Set dst (Replicate2F src));
11698 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11699 ins_encode( pshufd(dst, src, 0xe0));
11700 ins_pipe( fpu_reg_reg );
11701 %}
11702
11703 // Replicate scalar to packed single precision floating point values in xmm
11704 instruct Repl2F_regX(regXD dst, regX src) %{
11705 predicate(UseSSE>=2);
11706 match(Set dst (Replicate2F src));
11707 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11708 ins_encode( pshufd(dst, src, 0xe0));
11709 ins_pipe( fpu_reg_reg );
11710 %}
11711
11712 // Replicate scalar to packed single precision floating point values in xmm
11713 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
11714 predicate(UseSSE>=2);
11715 match(Set dst (Replicate2F zero));
11716 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11717 ins_encode( pxor(dst, dst));
11718 ins_pipe( fpu_reg_reg );
11719 %}
11720
11721
11722
11723 // =======================================================================
11724 // fast clearing of an array
11725
11726 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11727 match(Set dummy (ClearArray cnt base));
11728 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11729 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11730 "XOR EAX,EAX\n\t"
11731 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11732 opcode(0,0x4);
11733 ins_encode( Opcode(0xD1), RegOpc(ECX),
11734 OpcRegReg(0x33,EAX,EAX),
11735 Opcode(0xF3), Opcode(0xAB) );
11736 ins_pipe( pipe_slow );
11737 %}
11738
11739 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
11740 match(Set result (StrComp str1 str2));
11741 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
11742 //ins_cost(300);
11743
11744 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
11745 ins_encode( enc_String_Compare() );
11746 ins_pipe( pipe_slow );
11747 %}
11748
11749 // fast array equals
11750 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
11751 match(Set result (AryEq ary1 ary2));
11752 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
11753 //ins_cost(300);
11754
11755 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %}
11756 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
11757 ins_pipe( pipe_slow );
11758 %}
11759
11760 //----------Control Flow Instructions------------------------------------------
11761 // Signed compare Instructions
11762 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
11763 match(Set cr (CmpI op1 op2));
11764 effect( DEF cr, USE op1, USE op2 );
11765 format %{ "CMP $op1,$op2" %}
11766 opcode(0x3B); /* Opcode 3B /r */
11767 ins_encode( OpcP, RegReg( op1, op2) );
11768 ins_pipe( ialu_cr_reg_reg );
11769 %}
11770
11771 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
11772 match(Set cr (CmpI op1 op2));
11773 effect( DEF cr, USE op1 );
11774 format %{ "CMP $op1,$op2" %}
11775 opcode(0x81,0x07); /* Opcode 81 /7 */
11776 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11777 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11778 ins_pipe( ialu_cr_reg_imm );
11779 %}
11780
11781 // Cisc-spilled version of cmpI_eReg
11782 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
11783 match(Set cr (CmpI op1 (LoadI op2)));
11784
11785 format %{ "CMP $op1,$op2" %}
11786 ins_cost(500);
11787 opcode(0x3B); /* Opcode 3B /r */
11788 ins_encode( OpcP, RegMem( op1, op2) );
11789 ins_pipe( ialu_cr_reg_mem );
11790 %}
11791
11792 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
11793 match(Set cr (CmpI src zero));
11794 effect( DEF cr, USE src );
11795
11796 format %{ "TEST $src,$src" %}
11797 opcode(0x85);
11798 ins_encode( OpcP, RegReg( src, src ) );
11799 ins_pipe( ialu_cr_reg_imm );
11800 %}
11801
11802 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
11803 match(Set cr (CmpI (AndI src con) zero));
11804
11805 format %{ "TEST $src,$con" %}
11806 opcode(0xF7,0x00);
11807 ins_encode( OpcP, RegOpc(src), Con32(con) );
11808 ins_pipe( ialu_cr_reg_imm );
11809 %}
11810
11811 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
11812 match(Set cr (CmpI (AndI src mem) zero));
11813
11814 format %{ "TEST $src,$mem" %}
11815 opcode(0x85);
11816 ins_encode( OpcP, RegMem( src, mem ) );
11817 ins_pipe( ialu_cr_reg_mem );
11818 %}
11819
11820 // Unsigned compare Instructions; really, same as signed except they
11821 // produce an eFlagsRegU instead of eFlagsReg.
11822 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
11823 match(Set cr (CmpU op1 op2));
11824
11825 format %{ "CMPu $op1,$op2" %}
11826 opcode(0x3B); /* Opcode 3B /r */
11827 ins_encode( OpcP, RegReg( op1, op2) );
11828 ins_pipe( ialu_cr_reg_reg );
11829 %}
11830
11831 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
11832 match(Set cr (CmpU op1 op2));
11833
11834 format %{ "CMPu $op1,$op2" %}
11835 opcode(0x81,0x07); /* Opcode 81 /7 */
11836 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11837 ins_pipe( ialu_cr_reg_imm );
11838 %}
11839
11840 // // Cisc-spilled version of cmpU_eReg
11841 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
11842 match(Set cr (CmpU op1 (LoadI op2)));
11843
11844 format %{ "CMPu $op1,$op2" %}
11845 ins_cost(500);
11846 opcode(0x3B); /* Opcode 3B /r */
11847 ins_encode( OpcP, RegMem( op1, op2) );
11848 ins_pipe( ialu_cr_reg_mem );
11849 %}
11850
11851 // // Cisc-spilled version of cmpU_eReg
11852 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
11853 // match(Set cr (CmpU (LoadI op1) op2));
11854 //
11855 // format %{ "CMPu $op1,$op2" %}
11856 // ins_cost(500);
11857 // opcode(0x39); /* Opcode 39 /r */
11858 // ins_encode( OpcP, RegMem( op1, op2) );
11859 //%}
11860
11861 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
11862 match(Set cr (CmpU src zero));
11863
11864 format %{ "TESTu $src,$src" %}
11865 opcode(0x85);
11866 ins_encode( OpcP, RegReg( src, src ) );
11867 ins_pipe( ialu_cr_reg_imm );
11868 %}
11869
11870 // Unsigned pointer compare Instructions
11871 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11872 match(Set cr (CmpP op1 op2));
11873
11874 format %{ "CMPu $op1,$op2" %}
11875 opcode(0x3B); /* Opcode 3B /r */
11876 ins_encode( OpcP, RegReg( op1, op2) );
11877 ins_pipe( ialu_cr_reg_reg );
11878 %}
11879
11880 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11881 match(Set cr (CmpP op1 op2));
11882
11883 format %{ "CMPu $op1,$op2" %}
11884 opcode(0x81,0x07); /* Opcode 81 /7 */
11885 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11886 ins_pipe( ialu_cr_reg_imm );
11887 %}
11888
11889 // // Cisc-spilled version of cmpP_eReg
11890 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11891 match(Set cr (CmpP op1 (LoadP op2)));
11892
11893 format %{ "CMPu $op1,$op2" %}
11894 ins_cost(500);
11895 opcode(0x3B); /* Opcode 3B /r */
11896 ins_encode( OpcP, RegMem( op1, op2) );
11897 ins_pipe( ialu_cr_reg_mem );
11898 %}
11899
11900 // // Cisc-spilled version of cmpP_eReg
11901 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11902 // match(Set cr (CmpP (LoadP op1) op2));
11903 //
11904 // format %{ "CMPu $op1,$op2" %}
11905 // ins_cost(500);
11906 // opcode(0x39); /* Opcode 39 /r */
11907 // ins_encode( OpcP, RegMem( op1, op2) );
11908 //%}
11909
11910 // Compare raw pointer (used in out-of-heap check).
11911 // Only works because non-oop pointers must be raw pointers
11912 // and raw pointers have no anti-dependencies.
11913 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11914 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11915 match(Set cr (CmpP op1 (LoadP op2)));
11916
11917 format %{ "CMPu $op1,$op2" %}
11918 opcode(0x3B); /* Opcode 3B /r */
11919 ins_encode( OpcP, RegMem( op1, op2) );
11920 ins_pipe( ialu_cr_reg_mem );
11921 %}
11922
11923 //
11924 // This will generate a signed flags result. This should be ok
11925 // since any compare to a zero should be eq/neq.
11926 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11927 match(Set cr (CmpP src zero));
11928
11929 format %{ "TEST $src,$src" %}
11930 opcode(0x85);
11931 ins_encode( OpcP, RegReg( src, src ) );
11932 ins_pipe( ialu_cr_reg_imm );
11933 %}
11934
11935 // Cisc-spilled version of testP_reg
11936 // This will generate a signed flags result. This should be ok
11937 // since any compare to a zero should be eq/neq.
11938 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11939 match(Set cr (CmpP (LoadP op) zero));
11940
11941 format %{ "TEST $op,0xFFFFFFFF" %}
11942 ins_cost(500);
11943 opcode(0xF7); /* Opcode F7 /0 */
11944 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11945 ins_pipe( ialu_cr_reg_imm );
11946 %}
11947
11948 // Yanked all unsigned pointer compare operations.
11949 // Pointer compares are done with CmpP which is already unsigned.
11950
11951 //----------Max and Min--------------------------------------------------------
11952 // Min Instructions
11953 ////
11954 // *** Min and Max using the conditional move are slower than the
11955 // *** branch version on a Pentium III.
11956 // // Conditional move for min
11957 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
11958 // effect( USE_DEF op2, USE op1, USE cr );
11959 // format %{ "CMOVlt $op2,$op1\t! min" %}
11960 // opcode(0x4C,0x0F);
11961 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11962 // ins_pipe( pipe_cmov_reg );
11963 //%}
11964 //
11965 //// Min Register with Register (P6 version)
11966 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
11967 // predicate(VM_Version::supports_cmov() );
11968 // match(Set op2 (MinI op1 op2));
11969 // ins_cost(200);
11970 // expand %{
11971 // eFlagsReg cr;
11972 // compI_eReg(cr,op1,op2);
11973 // cmovI_reg_lt(op2,op1,cr);
11974 // %}
11975 //%}
11976
11977 // Min Register with Register (generic version)
11978 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
11979 match(Set dst (MinI dst src));
11980 effect(KILL flags);
11981 ins_cost(300);
11982
11983 format %{ "MIN $dst,$src" %}
11984 opcode(0xCC);
11985 ins_encode( min_enc(dst,src) );
11986 ins_pipe( pipe_slow );
11987 %}
11988
11989 // Max Register with Register
11990 // *** Min and Max using the conditional move are slower than the
11991 // *** branch version on a Pentium III.
11992 // // Conditional move for max
11993 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
11994 // effect( USE_DEF op2, USE op1, USE cr );
11995 // format %{ "CMOVgt $op2,$op1\t! max" %}
11996 // opcode(0x4F,0x0F);
11997 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11998 // ins_pipe( pipe_cmov_reg );
11999 //%}
12000 //
12001 // // Max Register with Register (P6 version)
12002 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12003 // predicate(VM_Version::supports_cmov() );
12004 // match(Set op2 (MaxI op1 op2));
12005 // ins_cost(200);
12006 // expand %{
12007 // eFlagsReg cr;
12008 // compI_eReg(cr,op1,op2);
12009 // cmovI_reg_gt(op2,op1,cr);
12010 // %}
12011 //%}
12012
12013 // Max Register with Register (generic version)
12014 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12015 match(Set dst (MaxI dst src));
12016 effect(KILL flags);
12017 ins_cost(300);
12018
12019 format %{ "MAX $dst,$src" %}
12020 opcode(0xCC);
12021 ins_encode( max_enc(dst,src) );
12022 ins_pipe( pipe_slow );
12023 %}
12024
12025 // ============================================================================
12026 // Branch Instructions
12027 // Jump Table
12028 instruct jumpXtnd(eRegI switch_val) %{
12029 match(Jump switch_val);
12030 ins_cost(350);
12031
12032 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12033
12034 ins_encode %{
12035 address table_base = __ address_table_constant(_index2label);
12036
12037 // Jump to Address(table_base + switch_reg)
12038 InternalAddress table(table_base);
12039 Address index(noreg, $switch_val$$Register, Address::times_1);
12040 __ jump(ArrayAddress(table, index));
12041 %}
12042 ins_pc_relative(1);
12043 ins_pipe(pipe_jmp);
12044 %}
12045
12046 // Jump Direct - Label defines a relative address from JMP+1
12047 instruct jmpDir(label labl) %{
12048 match(Goto);
12049 effect(USE labl);
12050
12051 ins_cost(300);
12052 format %{ "JMP $labl" %}
12053 size(5);
12054 opcode(0xE9);
12055 ins_encode( OpcP, Lbl( labl ) );
12056 ins_pipe( pipe_jmp );
12057 ins_pc_relative(1);
12058 %}
12059
12060 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12061 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12062 match(If cop cr);
12063 effect(USE labl);
12064
12065 ins_cost(300);
12066 format %{ "J$cop $labl" %}
12067 size(6);
12068 opcode(0x0F, 0x80);
12069 ins_encode( Jcc( cop, labl) );
12070 ins_pipe( pipe_jcc );
12071 ins_pc_relative(1);
12072 %}
12073
12074 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12075 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12076 match(CountedLoopEnd cop cr);
12077 effect(USE labl);
12078
12079 ins_cost(300);
12080 format %{ "J$cop $labl\t# Loop end" %}
12081 size(6);
12082 opcode(0x0F, 0x80);
12083 ins_encode( Jcc( cop, labl) );
12084 ins_pipe( pipe_jcc );
12085 ins_pc_relative(1);
12086 %}
12087
12088 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12089 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12090 match(CountedLoopEnd cop cmp);
12091 effect(USE labl);
12092
12093 ins_cost(300);
12094 format %{ "J$cop,u $labl\t# Loop end" %}
12095 size(6);
12096 opcode(0x0F, 0x80);
12097 ins_encode( Jcc( cop, labl) );
12098 ins_pipe( pipe_jcc );
12099 ins_pc_relative(1);
12100 %}
12101
12102 // Jump Direct Conditional - using unsigned comparison
12103 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12104 match(If cop cmp);
12105 effect(USE labl);
12106
12107 ins_cost(300);
12108 format %{ "J$cop,u $labl" %}
12109 size(6);
12110 opcode(0x0F, 0x80);
12111 ins_encode( Jcc( cop, labl) );
12112 ins_pipe( pipe_jcc );
12113 ins_pc_relative(1);
12114 %}
12115
12116 // ============================================================================
12117 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12118 // array for an instance of the superklass. Set a hidden internal cache on a
12119 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12120 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12121 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12122 match(Set result (PartialSubtypeCheck sub super));
12123 effect( KILL rcx, KILL cr );
12124
12125 ins_cost(1100); // slightly larger than the next version
12126 format %{ "CMPL EAX,ESI\n\t"
12127 "JEQ,s hit\n\t"
12128 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12129 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12130 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12131 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12132 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12133 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12134 "hit:\n\t"
12135 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12136 "miss:\t" %}
12137
12138 opcode(0x1); // Force a XOR of EDI
12139 ins_encode( enc_PartialSubtypeCheck() );
12140 ins_pipe( pipe_slow );
12141 %}
12142
12143 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12144 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12145 effect( KILL rcx, KILL result );
12146
12147 ins_cost(1000);
12148 format %{ "CMPL EAX,ESI\n\t"
12149 "JEQ,s miss\t# Actually a hit; we are done.\n\t"
12150 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12151 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12152 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12153 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12154 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12155 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12156 "miss:\t" %}
12157
12158 opcode(0x0); // No need to XOR EDI
12159 ins_encode( enc_PartialSubtypeCheck() );
12160 ins_pipe( pipe_slow );
12161 %}
12162
12163 // ============================================================================
12164 // Branch Instructions -- short offset versions
12165 //
12166 // These instructions are used to replace jumps of a long offset (the default
12167 // match) with jumps of a shorter offset. These instructions are all tagged
12168 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12169 // match rules in general matching. Instead, the ADLC generates a conversion
12170 // method in the MachNode which can be used to do in-place replacement of the
12171 // long variant with the shorter variant. The compiler will determine if a
12172 // branch can be taken by the is_short_branch_offset() predicate in the machine
12173 // specific code section of the file.
12174
12175 // Jump Direct - Label defines a relative address from JMP+1
12176 instruct jmpDir_short(label labl) %{
12177 match(Goto);
12178 effect(USE labl);
12179
12180 ins_cost(300);
12181 format %{ "JMP,s $labl" %}
12182 size(2);
12183 opcode(0xEB);
12184 ins_encode( OpcP, LblShort( labl ) );
12185 ins_pipe( pipe_jmp );
12186 ins_pc_relative(1);
12187 ins_short_branch(1);
12188 %}
12189
12190 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12191 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12192 match(If cop cr);
12193 effect(USE labl);
12194
12195 ins_cost(300);
12196 format %{ "J$cop,s $labl" %}
12197 size(2);
12198 opcode(0x70);
12199 ins_encode( JccShort( cop, labl) );
12200 ins_pipe( pipe_jcc );
12201 ins_pc_relative(1);
12202 ins_short_branch(1);
12203 %}
12204
12205 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12206 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12207 match(CountedLoopEnd cop cr);
12208 effect(USE labl);
12209
12210 ins_cost(300);
12211 format %{ "J$cop,s $labl" %}
12212 size(2);
12213 opcode(0x70);
12214 ins_encode( JccShort( cop, labl) );
12215 ins_pipe( pipe_jcc );
12216 ins_pc_relative(1);
12217 ins_short_branch(1);
12218 %}
12219
12220 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12221 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12222 match(CountedLoopEnd cop cmp);
12223 effect(USE labl);
12224
12225 ins_cost(300);
12226 format %{ "J$cop,us $labl" %}
12227 size(2);
12228 opcode(0x70);
12229 ins_encode( JccShort( cop, labl) );
12230 ins_pipe( pipe_jcc );
12231 ins_pc_relative(1);
12232 ins_short_branch(1);
12233 %}
12234
12235 // Jump Direct Conditional - using unsigned comparison
12236 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12237 match(If cop cmp);
12238 effect(USE labl);
12239
12240 ins_cost(300);
12241 format %{ "J$cop,us $labl" %}
12242 size(2);
12243 opcode(0x70);
12244 ins_encode( JccShort( cop, labl) );
12245 ins_pipe( pipe_jcc );
12246 ins_pc_relative(1);
12247 ins_short_branch(1);
12248 %}
12249
12250 // ============================================================================
12251 // Long Compare
12252 //
12253 // Currently we hold longs in 2 registers. Comparing such values efficiently
12254 // is tricky. The flavor of compare used depends on whether we are testing
12255 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12256 // The GE test is the negated LT test. The LE test can be had by commuting
12257 // the operands (yielding a GE test) and then negating; negate again for the
12258 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12259 // NE test is negated from that.
12260
12261 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12262 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12263 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12264 // are collapsed internally in the ADLC's dfa-gen code. The match for
12265 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12266 // foo match ends up with the wrong leaf. One fix is to not match both
12267 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12268 // both forms beat the trinary form of long-compare and both are very useful
12269 // on Intel which has so few registers.
12270
12271 // Manifest a CmpL result in an integer register. Very painful.
12272 // This is the test to avoid.
12273 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12274 match(Set dst (CmpL3 src1 src2));
12275 effect( KILL flags );
12276 ins_cost(1000);
12277 format %{ "XOR $dst,$dst\n\t"
12278 "CMP $src1.hi,$src2.hi\n\t"
12279 "JLT,s m_one\n\t"
12280 "JGT,s p_one\n\t"
12281 "CMP $src1.lo,$src2.lo\n\t"
12282 "JB,s m_one\n\t"
12283 "JEQ,s done\n"
12284 "p_one:\tINC $dst\n\t"
12285 "JMP,s done\n"
12286 "m_one:\tDEC $dst\n"
12287 "done:" %}
12288 ins_encode %{
12289 Label p_one, m_one, done;
12290 __ xorptr($dst$$Register, $dst$$Register);
12291 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12292 __ jccb(Assembler::less, m_one);
12293 __ jccb(Assembler::greater, p_one);
12294 __ cmpl($src1$$Register, $src2$$Register);
12295 __ jccb(Assembler::below, m_one);
12296 __ jccb(Assembler::equal, done);
12297 __ bind(p_one);
12298 __ incrementl($dst$$Register);
12299 __ jmpb(done);
12300 __ bind(m_one);
12301 __ decrementl($dst$$Register);
12302 __ bind(done);
12303 %}
12304 ins_pipe( pipe_slow );
12305 %}
12306
12307 //======
12308 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12309 // compares. Can be used for LE or GT compares by reversing arguments.
12310 // NOT GOOD FOR EQ/NE tests.
12311 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12312 match( Set flags (CmpL src zero ));
12313 ins_cost(100);
12314 format %{ "TEST $src.hi,$src.hi" %}
12315 opcode(0x85);
12316 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12317 ins_pipe( ialu_cr_reg_reg );
12318 %}
12319
12320 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12321 // compares. Can be used for LE or GT compares by reversing arguments.
12322 // NOT GOOD FOR EQ/NE tests.
12323 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12324 match( Set flags (CmpL src1 src2 ));
12325 effect( TEMP tmp );
12326 ins_cost(300);
12327 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12328 "MOV $tmp,$src1.hi\n\t"
12329 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12330 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12331 ins_pipe( ialu_cr_reg_reg );
12332 %}
12333
12334 // Long compares reg < zero/req OR reg >= zero/req.
12335 // Just a wrapper for a normal branch, plus the predicate test.
12336 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12337 match(If cmp flags);
12338 effect(USE labl);
12339 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12340 expand %{
12341 jmpCon(cmp,flags,labl); // JLT or JGE...
12342 %}
12343 %}
12344
12345 // Compare 2 longs and CMOVE longs.
12346 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12347 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12348 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12349 ins_cost(400);
12350 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12351 "CMOV$cmp $dst.hi,$src.hi" %}
12352 opcode(0x0F,0x40);
12353 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12354 ins_pipe( pipe_cmov_reg_long );
12355 %}
12356
12357 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12358 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12359 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12360 ins_cost(500);
12361 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12362 "CMOV$cmp $dst.hi,$src.hi" %}
12363 opcode(0x0F,0x40);
12364 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12365 ins_pipe( pipe_cmov_reg_long );
12366 %}
12367
12368 // Compare 2 longs and CMOVE ints.
12369 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12370 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12371 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12372 ins_cost(200);
12373 format %{ "CMOV$cmp $dst,$src" %}
12374 opcode(0x0F,0x40);
12375 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12376 ins_pipe( pipe_cmov_reg );
12377 %}
12378
12379 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12380 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12381 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12382 ins_cost(250);
12383 format %{ "CMOV$cmp $dst,$src" %}
12384 opcode(0x0F,0x40);
12385 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12386 ins_pipe( pipe_cmov_mem );
12387 %}
12388
12389 // Compare 2 longs and CMOVE ints.
12390 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12391 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12392 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12393 ins_cost(200);
12394 format %{ "CMOV$cmp $dst,$src" %}
12395 opcode(0x0F,0x40);
12396 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12397 ins_pipe( pipe_cmov_reg );
12398 %}
12399
12400 // Compare 2 longs and CMOVE doubles
12401 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12402 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12403 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12404 ins_cost(200);
12405 expand %{
12406 fcmovD_regS(cmp,flags,dst,src);
12407 %}
12408 %}
12409
12410 // Compare 2 longs and CMOVE doubles
12411 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
12412 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12413 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12414 ins_cost(200);
12415 expand %{
12416 fcmovXD_regS(cmp,flags,dst,src);
12417 %}
12418 %}
12419
12420 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12421 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12422 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12423 ins_cost(200);
12424 expand %{
12425 fcmovF_regS(cmp,flags,dst,src);
12426 %}
12427 %}
12428
12429 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
12430 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12431 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12432 ins_cost(200);
12433 expand %{
12434 fcmovX_regS(cmp,flags,dst,src);
12435 %}
12436 %}
12437
12438 //======
12439 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12440 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12441 match( Set flags (CmpL src zero ));
12442 effect(TEMP tmp);
12443 ins_cost(200);
12444 format %{ "MOV $tmp,$src.lo\n\t"
12445 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12446 ins_encode( long_cmp_flags0( src, tmp ) );
12447 ins_pipe( ialu_reg_reg_long );
12448 %}
12449
12450 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12451 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12452 match( Set flags (CmpL src1 src2 ));
12453 ins_cost(200+300);
12454 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12455 "JNE,s skip\n\t"
12456 "CMP $src1.hi,$src2.hi\n\t"
12457 "skip:\t" %}
12458 ins_encode( long_cmp_flags1( src1, src2 ) );
12459 ins_pipe( ialu_cr_reg_reg );
12460 %}
12461
12462 // Long compare reg == zero/reg OR reg != zero/reg
12463 // Just a wrapper for a normal branch, plus the predicate test.
12464 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12465 match(If cmp flags);
12466 effect(USE labl);
12467 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12468 expand %{
12469 jmpCon(cmp,flags,labl); // JEQ or JNE...
12470 %}
12471 %}
12472
12473 // Compare 2 longs and CMOVE longs.
12474 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12475 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12476 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12477 ins_cost(400);
12478 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12479 "CMOV$cmp $dst.hi,$src.hi" %}
12480 opcode(0x0F,0x40);
12481 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12482 ins_pipe( pipe_cmov_reg_long );
12483 %}
12484
12485 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12486 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12487 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12488 ins_cost(500);
12489 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12490 "CMOV$cmp $dst.hi,$src.hi" %}
12491 opcode(0x0F,0x40);
12492 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12493 ins_pipe( pipe_cmov_reg_long );
12494 %}
12495
12496 // Compare 2 longs and CMOVE ints.
12497 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12498 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12499 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12500 ins_cost(200);
12501 format %{ "CMOV$cmp $dst,$src" %}
12502 opcode(0x0F,0x40);
12503 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12504 ins_pipe( pipe_cmov_reg );
12505 %}
12506
12507 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12508 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12509 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12510 ins_cost(250);
12511 format %{ "CMOV$cmp $dst,$src" %}
12512 opcode(0x0F,0x40);
12513 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12514 ins_pipe( pipe_cmov_mem );
12515 %}
12516
12517 // Compare 2 longs and CMOVE ints.
12518 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12519 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12520 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12521 ins_cost(200);
12522 format %{ "CMOV$cmp $dst,$src" %}
12523 opcode(0x0F,0x40);
12524 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12525 ins_pipe( pipe_cmov_reg );
12526 %}
12527
12528 // Compare 2 longs and CMOVE doubles
12529 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12530 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12531 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12532 ins_cost(200);
12533 expand %{
12534 fcmovD_regS(cmp,flags,dst,src);
12535 %}
12536 %}
12537
12538 // Compare 2 longs and CMOVE doubles
12539 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
12540 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12541 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12542 ins_cost(200);
12543 expand %{
12544 fcmovXD_regS(cmp,flags,dst,src);
12545 %}
12546 %}
12547
12548 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12549 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12550 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12551 ins_cost(200);
12552 expand %{
12553 fcmovF_regS(cmp,flags,dst,src);
12554 %}
12555 %}
12556
12557 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
12558 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12559 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12560 ins_cost(200);
12561 expand %{
12562 fcmovX_regS(cmp,flags,dst,src);
12563 %}
12564 %}
12565
12566 //======
12567 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12568 // Same as cmpL_reg_flags_LEGT except must negate src
12569 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
12570 match( Set flags (CmpL src zero ));
12571 effect( TEMP tmp );
12572 ins_cost(300);
12573 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12574 "CMP $tmp,$src.lo\n\t"
12575 "SBB $tmp,$src.hi\n\t" %}
12576 ins_encode( long_cmp_flags3(src, tmp) );
12577 ins_pipe( ialu_reg_reg_long );
12578 %}
12579
12580 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12581 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12582 // requires a commuted test to get the same result.
12583 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12584 match( Set flags (CmpL src1 src2 ));
12585 effect( TEMP tmp );
12586 ins_cost(300);
12587 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12588 "MOV $tmp,$src2.hi\n\t"
12589 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12590 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12591 ins_pipe( ialu_cr_reg_reg );
12592 %}
12593
12594 // Long compares reg < zero/req OR reg >= zero/req.
12595 // Just a wrapper for a normal branch, plus the predicate test
12596 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12597 match(If cmp flags);
12598 effect(USE labl);
12599 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12600 ins_cost(300);
12601 expand %{
12602 jmpCon(cmp,flags,labl); // JGT or JLE...
12603 %}
12604 %}
12605
12606 // Compare 2 longs and CMOVE longs.
12607 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12608 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12609 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12610 ins_cost(400);
12611 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12612 "CMOV$cmp $dst.hi,$src.hi" %}
12613 opcode(0x0F,0x40);
12614 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12615 ins_pipe( pipe_cmov_reg_long );
12616 %}
12617
12618 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12619 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12620 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12621 ins_cost(500);
12622 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12623 "CMOV$cmp $dst.hi,$src.hi+4" %}
12624 opcode(0x0F,0x40);
12625 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12626 ins_pipe( pipe_cmov_reg_long );
12627 %}
12628
12629 // Compare 2 longs and CMOVE ints.
12630 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
12631 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12632 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12633 ins_cost(200);
12634 format %{ "CMOV$cmp $dst,$src" %}
12635 opcode(0x0F,0x40);
12636 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12637 ins_pipe( pipe_cmov_reg );
12638 %}
12639
12640 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
12641 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12642 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12643 ins_cost(250);
12644 format %{ "CMOV$cmp $dst,$src" %}
12645 opcode(0x0F,0x40);
12646 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12647 ins_pipe( pipe_cmov_mem );
12648 %}
12649
12650 // Compare 2 longs and CMOVE ptrs.
12651 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12652 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12653 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12654 ins_cost(200);
12655 format %{ "CMOV$cmp $dst,$src" %}
12656 opcode(0x0F,0x40);
12657 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12658 ins_pipe( pipe_cmov_reg );
12659 %}
12660
12661 // Compare 2 longs and CMOVE doubles
12662 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12663 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12664 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12665 ins_cost(200);
12666 expand %{
12667 fcmovD_regS(cmp,flags,dst,src);
12668 %}
12669 %}
12670
12671 // Compare 2 longs and CMOVE doubles
12672 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
12673 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12674 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12675 ins_cost(200);
12676 expand %{
12677 fcmovXD_regS(cmp,flags,dst,src);
12678 %}
12679 %}
12680
12681 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12682 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12683 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12684 ins_cost(200);
12685 expand %{
12686 fcmovF_regS(cmp,flags,dst,src);
12687 %}
12688 %}
12689
12690
12691 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
12692 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12693 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12694 ins_cost(200);
12695 expand %{
12696 fcmovX_regS(cmp,flags,dst,src);
12697 %}
12698 %}
12699
12700
12701 // ============================================================================
12702 // Procedure Call/Return Instructions
12703 // Call Java Static Instruction
12704 // Note: If this code changes, the corresponding ret_addr_offset() and
12705 // compute_padding() functions will have to be adjusted.
12706 instruct CallStaticJavaDirect(method meth) %{
12707 match(CallStaticJava);
12708 effect(USE meth);
12709
12710 ins_cost(300);
12711 format %{ "CALL,static " %}
12712 opcode(0xE8); /* E8 cd */
12713 ins_encode( pre_call_FPU,
12714 Java_Static_Call( meth ),
12715 call_epilog,
12716 post_call_FPU );
12717 ins_pipe( pipe_slow );
12718 ins_pc_relative(1);
12719 ins_alignment(4);
12720 %}
12721
12722 // Call Java Dynamic Instruction
12723 // Note: If this code changes, the corresponding ret_addr_offset() and
12724 // compute_padding() functions will have to be adjusted.
12725 instruct CallDynamicJavaDirect(method meth) %{
12726 match(CallDynamicJava);
12727 effect(USE meth);
12728
12729 ins_cost(300);
12730 format %{ "MOV EAX,(oop)-1\n\t"
12731 "CALL,dynamic" %}
12732 opcode(0xE8); /* E8 cd */
12733 ins_encode( pre_call_FPU,
12734 Java_Dynamic_Call( meth ),
12735 call_epilog,
12736 post_call_FPU );
12737 ins_pipe( pipe_slow );
12738 ins_pc_relative(1);
12739 ins_alignment(4);
12740 %}
12741
12742 // Call Runtime Instruction
12743 instruct CallRuntimeDirect(method meth) %{
12744 match(CallRuntime );
12745 effect(USE meth);
12746
12747 ins_cost(300);
12748 format %{ "CALL,runtime " %}
12749 opcode(0xE8); /* E8 cd */
12750 // Use FFREEs to clear entries in float stack
12751 ins_encode( pre_call_FPU,
12752 FFree_Float_Stack_All,
12753 Java_To_Runtime( meth ),
12754 post_call_FPU );
12755 ins_pipe( pipe_slow );
12756 ins_pc_relative(1);
12757 %}
12758
12759 // Call runtime without safepoint
12760 instruct CallLeafDirect(method meth) %{
12761 match(CallLeaf);
12762 effect(USE meth);
12763
12764 ins_cost(300);
12765 format %{ "CALL_LEAF,runtime " %}
12766 opcode(0xE8); /* E8 cd */
12767 ins_encode( pre_call_FPU,
12768 FFree_Float_Stack_All,
12769 Java_To_Runtime( meth ),
12770 Verify_FPU_For_Leaf, post_call_FPU );
12771 ins_pipe( pipe_slow );
12772 ins_pc_relative(1);
12773 %}
12774
12775 instruct CallLeafNoFPDirect(method meth) %{
12776 match(CallLeafNoFP);
12777 effect(USE meth);
12778
12779 ins_cost(300);
12780 format %{ "CALL_LEAF_NOFP,runtime " %}
12781 opcode(0xE8); /* E8 cd */
12782 ins_encode(Java_To_Runtime(meth));
12783 ins_pipe( pipe_slow );
12784 ins_pc_relative(1);
12785 %}
12786
12787
12788 // Return Instruction
12789 // Remove the return address & jump to it.
12790 instruct Ret() %{
12791 match(Return);
12792 format %{ "RET" %}
12793 opcode(0xC3);
12794 ins_encode(OpcP);
12795 ins_pipe( pipe_jmp );
12796 %}
12797
12798 // Tail Call; Jump from runtime stub to Java code.
12799 // Also known as an 'interprocedural jump'.
12800 // Target of jump will eventually return to caller.
12801 // TailJump below removes the return address.
12802 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12803 match(TailCall jump_target method_oop );
12804 ins_cost(300);
12805 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12806 opcode(0xFF, 0x4); /* Opcode FF /4 */
12807 ins_encode( OpcP, RegOpc(jump_target) );
12808 ins_pipe( pipe_jmp );
12809 %}
12810
12811
12812 // Tail Jump; remove the return address; jump to target.
12813 // TailCall above leaves the return address around.
12814 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12815 match( TailJump jump_target ex_oop );
12816 ins_cost(300);
12817 format %{ "POP EDX\t# pop return address into dummy\n\t"
12818 "JMP $jump_target " %}
12819 opcode(0xFF, 0x4); /* Opcode FF /4 */
12820 ins_encode( enc_pop_rdx,
12821 OpcP, RegOpc(jump_target) );
12822 ins_pipe( pipe_jmp );
12823 %}
12824
12825 // Create exception oop: created by stack-crawling runtime code.
12826 // Created exception is now available to this handler, and is setup
12827 // just prior to jumping to this handler. No code emitted.
12828 instruct CreateException( eAXRegP ex_oop )
12829 %{
12830 match(Set ex_oop (CreateEx));
12831
12832 size(0);
12833 // use the following format syntax
12834 format %{ "# exception oop is in EAX; no code emitted" %}
12835 ins_encode();
12836 ins_pipe( empty );
12837 %}
12838
12839
12840 // Rethrow exception:
12841 // The exception oop will come in the first argument position.
12842 // Then JUMP (not call) to the rethrow stub code.
12843 instruct RethrowException()
12844 %{
12845 match(Rethrow);
12846
12847 // use the following format syntax
12848 format %{ "JMP rethrow_stub" %}
12849 ins_encode(enc_rethrow);
12850 ins_pipe( pipe_jmp );
12851 %}
12852
12853 // inlined locking and unlocking
12854
12855
12856 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
12857 match( Set cr (FastLock object box) );
12858 effect( TEMP tmp, TEMP scr );
12859 ins_cost(300);
12860 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
12861 ins_encode( Fast_Lock(object,box,tmp,scr) );
12862 ins_pipe( pipe_slow );
12863 ins_pc_relative(1);
12864 %}
12865
12866 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12867 match( Set cr (FastUnlock object box) );
12868 effect( TEMP tmp );
12869 ins_cost(300);
12870 format %{ "FASTUNLOCK $object, $box, $tmp" %}
12871 ins_encode( Fast_Unlock(object,box,tmp) );
12872 ins_pipe( pipe_slow );
12873 ins_pc_relative(1);
12874 %}
12875
12876
12877
12878 // ============================================================================
12879 // Safepoint Instruction
12880 instruct safePoint_poll(eFlagsReg cr) %{
12881 match(SafePoint);
12882 effect(KILL cr);
12883
12884 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12885 // On SPARC that might be acceptable as we can generate the address with
12886 // just a sethi, saving an or. By polling at offset 0 we can end up
12887 // putting additional pressure on the index-0 in the D$. Because of
12888 // alignment (just like the situation at hand) the lower indices tend
12889 // to see more traffic. It'd be better to change the polling address
12890 // to offset 0 of the last $line in the polling page.
12891
12892 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12893 ins_cost(125);
12894 size(6) ;
12895 ins_encode( Safepoint_Poll() );
12896 ins_pipe( ialu_reg_mem );
12897 %}
12898
12899 //----------PEEPHOLE RULES-----------------------------------------------------
12900 // These must follow all instruction definitions as they use the names
12901 // defined in the instructions definitions.
12902 //
12903 // peepmatch ( root_instr_name [preceeding_instruction]* );
12904 //
12905 // peepconstraint %{
12906 // (instruction_number.operand_name relational_op instruction_number.operand_name
12907 // [, ...] );
12908 // // instruction numbers are zero-based using left to right order in peepmatch
12909 //
12910 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12911 // // provide an instruction_number.operand_name for each operand that appears
12912 // // in the replacement instruction's match rule
12913 //
12914 // ---------VM FLAGS---------------------------------------------------------
12915 //
12916 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12917 //
12918 // Each peephole rule is given an identifying number starting with zero and
12919 // increasing by one in the order seen by the parser. An individual peephole
12920 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12921 // on the command-line.
12922 //
12923 // ---------CURRENT LIMITATIONS----------------------------------------------
12924 //
12925 // Only match adjacent instructions in same basic block
12926 // Only equality constraints
12927 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12928 // Only one replacement instruction
12929 //
12930 // ---------EXAMPLE----------------------------------------------------------
12931 //
12932 // // pertinent parts of existing instructions in architecture description
12933 // instruct movI(eRegI dst, eRegI src) %{
12934 // match(Set dst (CopyI src));
12935 // %}
12936 //
12937 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12938 // match(Set dst (AddI dst src));
12939 // effect(KILL cr);
12940 // %}
12941 //
12942 // // Change (inc mov) to lea
12943 // peephole %{
12944 // // increment preceeded by register-register move
12945 // peepmatch ( incI_eReg movI );
12946 // // require that the destination register of the increment
12947 // // match the destination register of the move
12948 // peepconstraint ( 0.dst == 1.dst );
12949 // // construct a replacement instruction that sets
12950 // // the destination to ( move's source register + one )
12951 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12952 // %}
12953 //
12954 // Implementation no longer uses movX instructions since
12955 // machine-independent system no longer uses CopyX nodes.
12956 //
12957 // peephole %{
12958 // peepmatch ( incI_eReg movI );
12959 // peepconstraint ( 0.dst == 1.dst );
12960 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12961 // %}
12962 //
12963 // peephole %{
12964 // peepmatch ( decI_eReg movI );
12965 // peepconstraint ( 0.dst == 1.dst );
12966 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12967 // %}
12968 //
12969 // peephole %{
12970 // peepmatch ( addI_eReg_imm movI );
12971 // peepconstraint ( 0.dst == 1.dst );
12972 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12973 // %}
12974 //
12975 // peephole %{
12976 // peepmatch ( addP_eReg_imm movP );
12977 // peepconstraint ( 0.dst == 1.dst );
12978 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12979 // %}
12980
12981 // // Change load of spilled value to only a spill
12982 // instruct storeI(memory mem, eRegI src) %{
12983 // match(Set mem (StoreI mem src));
12984 // %}
12985 //
12986 // instruct loadI(eRegI dst, memory mem) %{
12987 // match(Set dst (LoadI mem));
12988 // %}
12989 //
12990 peephole %{
12991 peepmatch ( loadI storeI );
12992 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12993 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12994 %}
12995
12996 //----------SMARTSPILL RULES---------------------------------------------------
12997 // These must follow all instruction definitions as they use the names
12998 // defined in the instructions definitions.