1 //
2 // Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundry (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 tty->print("FLDCW 24 bit fpu control word");
499 tty->print_cr(""); tty->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 tty->print_cr("# stack bang"); tty->print("\t");
514 }
515 tty->print_cr("PUSHL EBP"); tty->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 tty->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 tty->print_cr(""); tty->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 tty->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 tty->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size ) {
729 if( cbuf ) {
730 emit_opcode (*cbuf, opcode );
731 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
732 #ifndef PRODUCT
733 } else if( !do_size ) {
734 if( size != 0 ) tty->print("\n\t");
735 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
736 if( is_load ) tty->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
737 else tty->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
738 } else { // FLD, FST, PUSH, POP
739 tty->print("%s [ESP + #%d]",op_str,offset);
740 }
741 #endif
742 }
743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
744 return size+3+offset_size;
745 }
746
747 // Helper for XMM registers. Extra opcode bits, limited syntax.
748 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
749 int offset, int reg_lo, int reg_hi, int size ) {
750 if( cbuf ) {
751 if( reg_lo+1 == reg_hi ) { // double move?
752 if( is_load && !UseXmmLoadAndClearUpper )
753 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
754 else
755 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
756 } else {
757 emit_opcode(*cbuf, 0xF3 );
758 }
759 emit_opcode(*cbuf, 0x0F );
760 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
761 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
762 else
763 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
764 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
765 #ifndef PRODUCT
766 } else if( !do_size ) {
767 if( size != 0 ) tty->print("\n\t");
768 if( reg_lo+1 == reg_hi ) { // double move?
769 if( is_load ) tty->print("%s %s,[ESP + #%d]",
770 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
771 Matcher::regName[reg_lo], offset);
772 else tty->print("MOVSD [ESP + #%d],%s",
773 offset, Matcher::regName[reg_lo]);
774 } else {
775 if( is_load ) tty->print("MOVSS %s,[ESP + #%d]",
776 Matcher::regName[reg_lo], offset);
777 else tty->print("MOVSS [ESP + #%d],%s",
778 offset, Matcher::regName[reg_lo]);
779 }
780 #endif
781 }
782 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
783 return size+5+offset_size;
784 }
785
786
787 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
788 int src_hi, int dst_hi, int size ) {
789 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
790 if( cbuf ) {
791 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
792 emit_opcode(*cbuf, 0x66 );
793 }
794 emit_opcode(*cbuf, 0x0F );
795 emit_opcode(*cbuf, 0x28 );
796 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
797 #ifndef PRODUCT
798 } else if( !do_size ) {
799 if( size != 0 ) tty->print("\n\t");
800 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
801 tty->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
802 } else {
803 tty->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
804 }
805 #endif
806 }
807 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
808 } else {
809 if( cbuf ) {
810 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
811 emit_opcode(*cbuf, 0x0F );
812 emit_opcode(*cbuf, 0x10 );
813 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
814 #ifndef PRODUCT
815 } else if( !do_size ) {
816 if( size != 0 ) tty->print("\n\t");
817 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
818 tty->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
819 } else {
820 tty->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
821 }
822 #endif
823 }
824 return size+4;
825 }
826 }
827
828 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size ) {
829 if( cbuf ) {
830 emit_opcode(*cbuf, 0x8B );
831 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
832 #ifndef PRODUCT
833 } else if( !do_size ) {
834 if( size != 0 ) tty->print("\n\t");
835 tty->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
836 #endif
837 }
838 return size+2;
839 }
840
841 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, int offset, int size ) {
842 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
843 if( cbuf ) {
844 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
845 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
846 #ifndef PRODUCT
847 } else if( !do_size ) {
848 if( size != 0 ) tty->print("\n\t");
849 tty->print("FLD %s",Matcher::regName[src_lo]);
850 #endif
851 }
852 size += 2;
853 }
854
855 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
856 const char *op_str;
857 int op;
858 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
859 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
860 op = 0xDD;
861 } else { // 32-bit store
862 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
863 op = 0xD9;
864 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
865 }
866
867 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size);
868 }
869
870 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
871 // Get registers to move
872 OptoReg::Name src_second = ra_->get_reg_second(in(1));
873 OptoReg::Name src_first = ra_->get_reg_first(in(1));
874 OptoReg::Name dst_second = ra_->get_reg_second(this );
875 OptoReg::Name dst_first = ra_->get_reg_first(this );
876
877 enum RC src_second_rc = rc_class(src_second);
878 enum RC src_first_rc = rc_class(src_first);
879 enum RC dst_second_rc = rc_class(dst_second);
880 enum RC dst_first_rc = rc_class(dst_first);
881
882 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
883
884 // Generate spill code!
885 int size = 0;
886
887 if( src_first == dst_first && src_second == dst_second )
888 return size; // Self copy, no move
889
890 // --------------------------------------
891 // Check for mem-mem move. push/pop to move.
892 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
893 if( src_second == dst_first ) { // overlapping stack copy ranges
894 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
895 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size);
896 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size);
897 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
898 }
899 // move low bits
900 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size);
901 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size);
902 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
903 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size);
904 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size);
905 }
906 return size;
907 }
908
909 // --------------------------------------
910 // Check for integer reg-reg copy
911 if( src_first_rc == rc_int && dst_first_rc == rc_int )
912 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size);
913
914 // Check for integer store
915 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
916 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size);
917
918 // Check for integer load
919 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
920 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size);
921
922 // --------------------------------------
923 // Check for float reg-reg copy
924 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
925 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
926 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
927 if( cbuf ) {
928
929 // Note the mucking with the register encode to compensate for the 0/1
930 // indexing issue mentioned in a comment in the reg_def sections
931 // for FPR registers many lines above here.
932
933 if( src_first != FPR1L_num ) {
934 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
935 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
936 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
937 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
938 } else {
939 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
940 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
941 }
942 #ifndef PRODUCT
943 } else if( !do_size ) {
944 if( size != 0 ) st->print("\n\t");
945 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
946 else st->print( "FST %s", Matcher::regName[dst_first]);
947 #endif
948 }
949 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
950 }
951
952 // Check for float store
953 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
954 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size);
955 }
956
957 // Check for float load
958 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
959 int offset = ra_->reg2offset(src_first);
960 const char *op_str;
961 int op;
962 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
963 op_str = "FLD_D";
964 op = 0xDD;
965 } else { // 32-bit load
966 op_str = "FLD_S";
967 op = 0xD9;
968 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
969 }
970 if( cbuf ) {
971 emit_opcode (*cbuf, op );
972 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
973 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
974 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
975 #ifndef PRODUCT
976 } else if( !do_size ) {
977 if( size != 0 ) st->print("\n\t");
978 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
979 #endif
980 }
981 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
982 return size + 3+offset_size+2;
983 }
984
985 // Check for xmm reg-reg copy
986 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
987 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
988 (src_first+1 == src_second && dst_first+1 == dst_second),
989 "no non-adjacent float-moves" );
990 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size);
991 }
992
993 // Check for xmm store
994 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
995 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size);
996 }
997
998 // Check for float xmm load
999 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1000 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size);
1001 }
1002
1003 // Copy from float reg to xmm reg
1004 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1005 // copy to the top of stack from floating point reg
1006 // and use LEA to preserve flags
1007 if( cbuf ) {
1008 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1009 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1010 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1011 emit_d8(*cbuf,0xF8);
1012 #ifndef PRODUCT
1013 } else if( !do_size ) {
1014 if( size != 0 ) st->print("\n\t");
1015 st->print("LEA ESP,[ESP-8]");
1016 #endif
1017 }
1018 size += 4;
1019
1020 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size);
1021
1022 // Copy from the temp memory to the xmm reg.
1023 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size);
1024
1025 if( cbuf ) {
1026 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1027 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1028 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1029 emit_d8(*cbuf,0x08);
1030 #ifndef PRODUCT
1031 } else if( !do_size ) {
1032 if( size != 0 ) st->print("\n\t");
1033 st->print("LEA ESP,[ESP+8]");
1034 #endif
1035 }
1036 size += 4;
1037 return size;
1038 }
1039
1040 assert( size > 0, "missed a case" );
1041
1042 // --------------------------------------------------------------------
1043 // Check for second bits still needing moving.
1044 if( src_second == dst_second )
1045 return size; // Self copy; no move
1046 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1047
1048 // Check for second word int-int move
1049 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1050 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size);
1051
1052 // Check for second word integer store
1053 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1054 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size);
1055
1056 // Check for second word integer load
1057 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1058 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size);
1059
1060
1061 Unimplemented();
1062 }
1063
1064 #ifndef PRODUCT
1065 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1066 implementation( NULL, ra_, false, st );
1067 }
1068 #endif
1069
1070 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1071 implementation( &cbuf, ra_, false, NULL );
1072 }
1073
1074 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1075 return implementation( NULL, ra_, true, NULL );
1076 }
1077
1078 //=============================================================================
1079 #ifndef PRODUCT
1080 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1081 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1082 }
1083 #endif
1084
1085 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1086 MacroAssembler _masm(&cbuf);
1087 __ nop(_count);
1088 }
1089
1090 uint MachNopNode::size(PhaseRegAlloc *) const {
1091 return _count;
1092 }
1093
1094
1095 //=============================================================================
1096 #ifndef PRODUCT
1097 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1098 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1099 int reg = ra_->get_reg_first(this);
1100 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1101 }
1102 #endif
1103
1104 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1105 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1106 int reg = ra_->get_encode(this);
1107 if( offset >= 128 ) {
1108 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1109 emit_rm(cbuf, 0x2, reg, 0x04);
1110 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1111 emit_d32(cbuf, offset);
1112 }
1113 else {
1114 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1115 emit_rm(cbuf, 0x1, reg, 0x04);
1116 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1117 emit_d8(cbuf, offset);
1118 }
1119 }
1120
1121 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1122 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1123 if( offset >= 128 ) {
1124 return 7;
1125 }
1126 else {
1127 return 4;
1128 }
1129 }
1130
1131 //=============================================================================
1132
1133 // emit call stub, compiled java to interpreter
1134 void emit_java_to_interp(CodeBuffer &cbuf ) {
1135 // Stub is fixed up when the corresponding call is converted from calling
1136 // compiled code to calling interpreted code.
1137 // mov rbx,0
1138 // jmp -1
1139
1140 address mark = cbuf.inst_mark(); // get mark within main instrs section
1141
1142 // Note that the code buffer's inst_mark is always relative to insts.
1143 // That's why we must use the macroassembler to generate a stub.
1144 MacroAssembler _masm(&cbuf);
1145
1146 address base =
1147 __ start_a_stub(Compile::MAX_stubs_size);
1148 if (base == NULL) return; // CodeBuffer::expand failed
1149 // static stub relocation stores the instruction address of the call
1150 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1151 // static stub relocation also tags the methodOop in the code-stream.
1152 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1153 // This is recognized as unresolved by relocs/nativeInst/ic code
1154 __ jump(RuntimeAddress(__ pc()));
1155
1156 __ end_a_stub();
1157 // Update current stubs pointer and restore code_end.
1158 }
1159 // size of call stub, compiled java to interpretor
1160 uint size_java_to_interp() {
1161 return 10; // movl; jmp
1162 }
1163 // relocation entries for call stub, compiled java to interpretor
1164 uint reloc_java_to_interp() {
1165 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1166 }
1167
1168 //=============================================================================
1169 #ifndef PRODUCT
1170 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1171 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1172 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1173 st->print_cr("\tNOP");
1174 st->print_cr("\tNOP");
1175 if( !OptoBreakpoint )
1176 st->print_cr("\tNOP");
1177 }
1178 #endif
1179
1180 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1181 MacroAssembler masm(&cbuf);
1182 #ifdef ASSERT
1183 uint code_size = cbuf.code_size();
1184 #endif
1185 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1186 masm.jump_cc(Assembler::notEqual,
1187 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1188 /* WARNING these NOPs are critical so that verified entry point is properly
1189 aligned for patching by NativeJump::patch_verified_entry() */
1190 int nops_cnt = 2;
1191 if( !OptoBreakpoint ) // Leave space for int3
1192 nops_cnt += 1;
1193 masm.nop(nops_cnt);
1194
1195 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1196 }
1197
1198 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1199 return OptoBreakpoint ? 11 : 12;
1200 }
1201
1202
1203 //=============================================================================
1204 uint size_exception_handler() {
1205 // NativeCall instruction size is the same as NativeJump.
1206 // exception handler starts out as jump and can be patched to
1207 // a call be deoptimization. (4932387)
1208 // Note that this value is also credited (in output.cpp) to
1209 // the size of the code section.
1210 return NativeJump::instruction_size;
1211 }
1212
1213 // Emit exception handler code. Stuff framesize into a register
1214 // and call a VM stub routine.
1215 int emit_exception_handler(CodeBuffer& cbuf) {
1216
1217 // Note that the code buffer's inst_mark is always relative to insts.
1218 // That's why we must use the macroassembler to generate a handler.
1219 MacroAssembler _masm(&cbuf);
1220 address base =
1221 __ start_a_stub(size_exception_handler());
1222 if (base == NULL) return 0; // CodeBuffer::expand failed
1223 int offset = __ offset();
1224 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1225 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1226 __ end_a_stub();
1227 return offset;
1228 }
1229
1230 uint size_deopt_handler() {
1231 // NativeCall instruction size is the same as NativeJump.
1232 // exception handler starts out as jump and can be patched to
1233 // a call be deoptimization. (4932387)
1234 // Note that this value is also credited (in output.cpp) to
1235 // the size of the code section.
1236 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1237 }
1238
1239 // Emit deopt handler code.
1240 int emit_deopt_handler(CodeBuffer& cbuf) {
1241
1242 // Note that the code buffer's inst_mark is always relative to insts.
1243 // That's why we must use the macroassembler to generate a handler.
1244 MacroAssembler _masm(&cbuf);
1245 address base =
1246 __ start_a_stub(size_exception_handler());
1247 if (base == NULL) return 0; // CodeBuffer::expand failed
1248 int offset = __ offset();
1249 InternalAddress here(__ pc());
1250 __ pushptr(here.addr());
1251
1252 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1253 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1254 __ end_a_stub();
1255 return offset;
1256 }
1257
1258
1259 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1260 int mark = cbuf.insts()->mark_off();
1261 MacroAssembler _masm(&cbuf);
1262 address double_address = __ double_constant(x);
1263 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1264 emit_d32_reloc(cbuf,
1265 (int)double_address,
1266 internal_word_Relocation::spec(double_address),
1267 RELOC_DISP32);
1268 }
1269
1270 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1271 int mark = cbuf.insts()->mark_off();
1272 MacroAssembler _masm(&cbuf);
1273 address float_address = __ float_constant(x);
1274 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1275 emit_d32_reloc(cbuf,
1276 (int)float_address,
1277 internal_word_Relocation::spec(float_address),
1278 RELOC_DISP32);
1279 }
1280
1281
1282 int Matcher::regnum_to_fpu_offset(int regnum) {
1283 return regnum - 32; // The FP registers are in the second chunk
1284 }
1285
1286 bool is_positive_zero_float(jfloat f) {
1287 return jint_cast(f) == jint_cast(0.0F);
1288 }
1289
1290 bool is_positive_one_float(jfloat f) {
1291 return jint_cast(f) == jint_cast(1.0F);
1292 }
1293
1294 bool is_positive_zero_double(jdouble d) {
1295 return jlong_cast(d) == jlong_cast(0.0);
1296 }
1297
1298 bool is_positive_one_double(jdouble d) {
1299 return jlong_cast(d) == jlong_cast(1.0);
1300 }
1301
1302 // This is UltraSparc specific, true just means we have fast l2f conversion
1303 const bool Matcher::convL2FSupported(void) {
1304 return true;
1305 }
1306
1307 // Vector width in bytes
1308 const uint Matcher::vector_width_in_bytes(void) {
1309 return UseSSE >= 2 ? 8 : 0;
1310 }
1311
1312 // Vector ideal reg
1313 const uint Matcher::vector_ideal_reg(void) {
1314 return Op_RegD;
1315 }
1316
1317 // Is this branch offset short enough that a short branch can be used?
1318 //
1319 // NOTE: If the platform does not provide any short branch variants, then
1320 // this method should return false for offset 0.
1321 bool Matcher::is_short_branch_offset(int offset) {
1322 return (-128 <= offset && offset <= 127);
1323 }
1324
1325 const bool Matcher::isSimpleConstant64(jlong value) {
1326 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1327 return false;
1328 }
1329
1330 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1331 const bool Matcher::init_array_count_is_in_bytes = false;
1332
1333 // Threshold size for cleararray.
1334 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1335
1336 // Should the Matcher clone shifts on addressing modes, expecting them to
1337 // be subsumed into complex addressing expressions or compute them into
1338 // registers? True for Intel but false for most RISCs
1339 const bool Matcher::clone_shift_expressions = true;
1340
1341 // Is it better to copy float constants, or load them directly from memory?
1342 // Intel can load a float constant from a direct address, requiring no
1343 // extra registers. Most RISCs will have to materialize an address into a
1344 // register first, so they would do better to copy the constant from stack.
1345 const bool Matcher::rematerialize_float_constants = true;
1346
1347 // If CPU can load and store mis-aligned doubles directly then no fixup is
1348 // needed. Else we split the double into 2 integer pieces and move it
1349 // piece-by-piece. Only happens when passing doubles into C code as the
1350 // Java calling convention forces doubles to be aligned.
1351 const bool Matcher::misaligned_doubles_ok = true;
1352
1353
1354 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1355 // Get the memory operand from the node
1356 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1357 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1358 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1359 uint opcnt = 1; // First operand
1360 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1361 while( idx >= skipped+num_edges ) {
1362 skipped += num_edges;
1363 opcnt++; // Bump operand count
1364 assert( opcnt < numopnds, "Accessing non-existent operand" );
1365 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1366 }
1367
1368 MachOper *memory = node->_opnds[opcnt];
1369 MachOper *new_memory = NULL;
1370 switch (memory->opcode()) {
1371 case DIRECT:
1372 case INDOFFSET32X:
1373 // No transformation necessary.
1374 return;
1375 case INDIRECT:
1376 new_memory = new (C) indirect_win95_safeOper( );
1377 break;
1378 case INDOFFSET8:
1379 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1380 break;
1381 case INDOFFSET32:
1382 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1383 break;
1384 case INDINDEXOFFSET:
1385 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1386 break;
1387 case INDINDEXSCALE:
1388 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1389 break;
1390 case INDINDEXSCALEOFFSET:
1391 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1392 break;
1393 case LOAD_LONG_INDIRECT:
1394 case LOAD_LONG_INDOFFSET32:
1395 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1396 return;
1397 default:
1398 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1399 return;
1400 }
1401 node->_opnds[opcnt] = new_memory;
1402 }
1403
1404 // Advertise here if the CPU requires explicit rounding operations
1405 // to implement the UseStrictFP mode.
1406 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1407
1408 // Do floats take an entire double register or just half?
1409 const bool Matcher::float_in_double = true;
1410 // Do ints take an entire long register or just half?
1411 const bool Matcher::int_in_long = false;
1412
1413 // Return whether or not this register is ever used as an argument. This
1414 // function is used on startup to build the trampoline stubs in generateOptoStub.
1415 // Registers not mentioned will be killed by the VM call in the trampoline, and
1416 // arguments in those registers not be available to the callee.
1417 bool Matcher::can_be_java_arg( int reg ) {
1418 if( reg == ECX_num || reg == EDX_num ) return true;
1419 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1420 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1421 return false;
1422 }
1423
1424 bool Matcher::is_spillable_arg( int reg ) {
1425 return can_be_java_arg(reg);
1426 }
1427
1428 // Register for DIVI projection of divmodI
1429 RegMask Matcher::divI_proj_mask() {
1430 return EAX_REG_mask;
1431 }
1432
1433 // Register for MODI projection of divmodI
1434 RegMask Matcher::modI_proj_mask() {
1435 return EDX_REG_mask;
1436 }
1437
1438 // Register for DIVL projection of divmodL
1439 RegMask Matcher::divL_proj_mask() {
1440 ShouldNotReachHere();
1441 return RegMask();
1442 }
1443
1444 // Register for MODL projection of divmodL
1445 RegMask Matcher::modL_proj_mask() {
1446 ShouldNotReachHere();
1447 return RegMask();
1448 }
1449
1450 %}
1451
1452 //----------ENCODING BLOCK-----------------------------------------------------
1453 // This block specifies the encoding classes used by the compiler to output
1454 // byte streams. Encoding classes generate functions which are called by
1455 // Machine Instruction Nodes in order to generate the bit encoding of the
1456 // instruction. Operands specify their base encoding interface with the
1457 // interface keyword. There are currently supported four interfaces,
1458 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1459 // operand to generate a function which returns its register number when
1460 // queried. CONST_INTER causes an operand to generate a function which
1461 // returns the value of the constant when queried. MEMORY_INTER causes an
1462 // operand to generate four functions which return the Base Register, the
1463 // Index Register, the Scale Value, and the Offset Value of the operand when
1464 // queried. COND_INTER causes an operand to generate six functions which
1465 // return the encoding code (ie - encoding bits for the instruction)
1466 // associated with each basic boolean condition for a conditional instruction.
1467 // Instructions specify two basic values for encoding. They use the
1468 // ins_encode keyword to specify their encoding class (which must be one of
1469 // the class names specified in the encoding block), and they use the
1470 // opcode keyword to specify, in order, their primary, secondary, and
1471 // tertiary opcode. Only the opcode sections which a particular instruction
1472 // needs for encoding need to be specified.
1473 encode %{
1474 // Build emit functions for each basic byte or larger field in the intel
1475 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1476 // code in the enc_class source block. Emit functions will live in the
1477 // main source block for now. In future, we can generalize this by
1478 // adding a syntax that specifies the sizes of fields in an order,
1479 // so that the adlc can build the emit functions automagically
1480 enc_class OpcP %{ // Emit opcode
1481 emit_opcode(cbuf,$primary);
1482 %}
1483
1484 enc_class OpcS %{ // Emit opcode
1485 emit_opcode(cbuf,$secondary);
1486 %}
1487
1488 enc_class Opcode(immI d8 ) %{ // Emit opcode
1489 emit_opcode(cbuf,$d8$$constant);
1490 %}
1491
1492 enc_class SizePrefix %{
1493 emit_opcode(cbuf,0x66);
1494 %}
1495
1496 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1497 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1498 %}
1499
1500 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1501 emit_opcode(cbuf,$opcode$$constant);
1502 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1503 %}
1504
1505 enc_class mov_r32_imm0( eRegI dst ) %{
1506 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1507 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1508 %}
1509
1510 enc_class cdq_enc %{
1511 // Full implementation of Java idiv and irem; checks for
1512 // special case as described in JVM spec., p.243 & p.271.
1513 //
1514 // normal case special case
1515 //
1516 // input : rax,: dividend min_int
1517 // reg: divisor -1
1518 //
1519 // output: rax,: quotient (= rax, idiv reg) min_int
1520 // rdx: remainder (= rax, irem reg) 0
1521 //
1522 // Code sequnce:
1523 //
1524 // 81 F8 00 00 00 80 cmp rax,80000000h
1525 // 0F 85 0B 00 00 00 jne normal_case
1526 // 33 D2 xor rdx,edx
1527 // 83 F9 FF cmp rcx,0FFh
1528 // 0F 84 03 00 00 00 je done
1529 // normal_case:
1530 // 99 cdq
1531 // F7 F9 idiv rax,ecx
1532 // done:
1533 //
1534 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1535 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1536 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1537 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1538 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1539 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1540 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1541 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1542 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1543 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1544 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1545 // normal_case:
1546 emit_opcode(cbuf,0x99); // cdq
1547 // idiv (note: must be emitted by the user of this rule)
1548 // normal:
1549 %}
1550
1551 // Dense encoding for older common ops
1552 enc_class Opc_plus(immI opcode, eRegI reg) %{
1553 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1554 %}
1555
1556
1557 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1558 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1559 // Check for 8-bit immediate, and set sign extend bit in opcode
1560 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1561 emit_opcode(cbuf, $primary | 0x02);
1562 }
1563 else { // If 32-bit immediate
1564 emit_opcode(cbuf, $primary);
1565 }
1566 %}
1567
1568 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1569 // Emit primary opcode and set sign-extend bit
1570 // Check for 8-bit immediate, and set sign extend bit in opcode
1571 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1572 emit_opcode(cbuf, $primary | 0x02); }
1573 else { // If 32-bit immediate
1574 emit_opcode(cbuf, $primary);
1575 }
1576 // Emit r/m byte with secondary opcode, after primary opcode.
1577 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1578 %}
1579
1580 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1581 // Check for 8-bit immediate, and set sign extend bit in opcode
1582 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1583 $$$emit8$imm$$constant;
1584 }
1585 else { // If 32-bit immediate
1586 // Output immediate
1587 $$$emit32$imm$$constant;
1588 }
1589 %}
1590
1591 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1592 // Emit primary opcode and set sign-extend bit
1593 // Check for 8-bit immediate, and set sign extend bit in opcode
1594 int con = (int)$imm$$constant; // Throw away top bits
1595 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1596 // Emit r/m byte with secondary opcode, after primary opcode.
1597 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1598 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1599 else emit_d32(cbuf,con);
1600 %}
1601
1602 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1603 // Emit primary opcode and set sign-extend bit
1604 // Check for 8-bit immediate, and set sign extend bit in opcode
1605 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1606 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1607 // Emit r/m byte with tertiary opcode, after primary opcode.
1608 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1609 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1610 else emit_d32(cbuf,con);
1611 %}
1612
1613 enc_class Lbl (label labl) %{ // JMP, CALL
1614 Label *l = $labl$$label;
1615 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1616 %}
1617
1618 enc_class LblShort (label labl) %{ // JMP, CALL
1619 Label *l = $labl$$label;
1620 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1621 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1622 emit_d8(cbuf, disp);
1623 %}
1624
1625 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1626 emit_cc(cbuf, $secondary, $dst$$reg );
1627 %}
1628
1629 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1630 int destlo = $dst$$reg;
1631 int desthi = HIGH_FROM_LOW(destlo);
1632 // bswap lo
1633 emit_opcode(cbuf, 0x0F);
1634 emit_cc(cbuf, 0xC8, destlo);
1635 // bswap hi
1636 emit_opcode(cbuf, 0x0F);
1637 emit_cc(cbuf, 0xC8, desthi);
1638 // xchg lo and hi
1639 emit_opcode(cbuf, 0x87);
1640 emit_rm(cbuf, 0x3, destlo, desthi);
1641 %}
1642
1643 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1644 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1645 %}
1646
1647 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1648 Label *l = $labl$$label;
1649 $$$emit8$primary;
1650 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1651 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1652 %}
1653
1654 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1655 Label *l = $labl$$label;
1656 emit_cc(cbuf, $primary, $cop$$cmpcode);
1657 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1658 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1659 emit_d8(cbuf, disp);
1660 %}
1661
1662 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1663 $$$emit8$primary;
1664 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1665 %}
1666
1667 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1668 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1669 emit_d8(cbuf, op >> 8 );
1670 emit_d8(cbuf, op & 255);
1671 %}
1672
1673 // emulate a CMOV with a conditional branch around a MOV
1674 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1675 // Invert sense of branch from sense of CMOV
1676 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1677 emit_d8( cbuf, $brOffs$$constant );
1678 %}
1679
1680 enc_class enc_PartialSubtypeCheck( ) %{
1681 Register Redi = as_Register(EDI_enc); // result register
1682 Register Reax = as_Register(EAX_enc); // super class
1683 Register Recx = as_Register(ECX_enc); // killed
1684 Register Resi = as_Register(ESI_enc); // sub class
1685 Label hit, miss;
1686
1687 MacroAssembler _masm(&cbuf);
1688 // Compare super with sub directly, since super is not in its own SSA.
1689 // The compiler used to emit this test, but we fold it in here,
1690 // to allow platform-specific tweaking on sparc.
1691 __ cmpptr(Reax, Resi);
1692 __ jcc(Assembler::equal, hit);
1693 #ifndef PRODUCT
1694 __ incrementl(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1695 #endif //PRODUCT
1696 __ movptr(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
1697 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes()));
1698 __ addptr(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
1699 __ repne_scan();
1700 __ jcc(Assembler::notEqual, miss);
1701 __ movptr(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax);
1702 __ bind(hit);
1703 if( $primary )
1704 __ xorptr(Redi,Redi);
1705 __ bind(miss);
1706 %}
1707
1708 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1709 MacroAssembler masm(&cbuf);
1710 int start = masm.offset();
1711 if (UseSSE >= 2) {
1712 if (VerifyFPU) {
1713 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1714 }
1715 } else {
1716 // External c_calling_convention expects the FPU stack to be 'clean'.
1717 // Compiled code leaves it dirty. Do cleanup now.
1718 masm.empty_FPU_stack();
1719 }
1720 if (sizeof_FFree_Float_Stack_All == -1) {
1721 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1722 } else {
1723 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1724 }
1725 %}
1726
1727 enc_class Verify_FPU_For_Leaf %{
1728 if( VerifyFPU ) {
1729 MacroAssembler masm(&cbuf);
1730 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1731 }
1732 %}
1733
1734 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1735 // This is the instruction starting address for relocation info.
1736 cbuf.set_inst_mark();
1737 $$$emit8$primary;
1738 // CALL directly to the runtime
1739 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1740 runtime_call_Relocation::spec(), RELOC_IMM32 );
1741
1742 if (UseSSE >= 2) {
1743 MacroAssembler _masm(&cbuf);
1744 BasicType rt = tf()->return_type();
1745
1746 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1747 // A C runtime call where the return value is unused. In SSE2+
1748 // mode the result needs to be removed from the FPU stack. It's
1749 // likely that this function call could be removed by the
1750 // optimizer if the C function is a pure function.
1751 __ ffree(0);
1752 } else if (rt == T_FLOAT) {
1753 __ lea(rsp, Address(rsp, -4));
1754 __ fstp_s(Address(rsp, 0));
1755 __ movflt(xmm0, Address(rsp, 0));
1756 __ lea(rsp, Address(rsp, 4));
1757 } else if (rt == T_DOUBLE) {
1758 __ lea(rsp, Address(rsp, -8));
1759 __ fstp_d(Address(rsp, 0));
1760 __ movdbl(xmm0, Address(rsp, 0));
1761 __ lea(rsp, Address(rsp, 8));
1762 }
1763 }
1764 %}
1765
1766
1767 enc_class pre_call_FPU %{
1768 // If method sets FPU control word restore it here
1769 if( Compile::current()->in_24_bit_fp_mode() ) {
1770 MacroAssembler masm(&cbuf);
1771 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1772 }
1773 %}
1774
1775 enc_class post_call_FPU %{
1776 // If method sets FPU control word do it here also
1777 if( Compile::current()->in_24_bit_fp_mode() ) {
1778 MacroAssembler masm(&cbuf);
1779 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1780 }
1781 %}
1782
1783 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1784 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1785 // who we intended to call.
1786 cbuf.set_inst_mark();
1787 $$$emit8$primary;
1788 if ( !_method ) {
1789 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1790 runtime_call_Relocation::spec(), RELOC_IMM32 );
1791 } else if(_optimized_virtual) {
1792 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1793 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1794 } else {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 static_call_Relocation::spec(), RELOC_IMM32 );
1797 }
1798 if( _method ) { // Emit stub for static call
1799 emit_java_to_interp(cbuf);
1800 }
1801 %}
1802
1803 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1804 // !!!!!
1805 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1806 // emit_call_dynamic_prologue( cbuf );
1807 cbuf.set_inst_mark();
1808 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1809 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1810 address virtual_call_oop_addr = cbuf.inst_mark();
1811 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1812 // who we intended to call.
1813 cbuf.set_inst_mark();
1814 $$$emit8$primary;
1815 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1816 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1817 %}
1818
1819 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1820 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1821 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1822
1823 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1824 cbuf.set_inst_mark();
1825 $$$emit8$primary;
1826 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1827 emit_d8(cbuf, disp); // Displacement
1828
1829 %}
1830
1831 enc_class Xor_Reg (eRegI dst) %{
1832 emit_opcode(cbuf, 0x33);
1833 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1834 %}
1835
1836 // Following encoding is no longer used, but may be restored if calling
1837 // convention changes significantly.
1838 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1839 //
1840 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1841 // // int ic_reg = Matcher::inline_cache_reg();
1842 // // int ic_encode = Matcher::_regEncode[ic_reg];
1843 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1844 // // int imo_encode = Matcher::_regEncode[imo_reg];
1845 //
1846 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1847 // // // so we load it immediately before the call
1848 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1849 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1850 //
1851 // // xor rbp,ebp
1852 // emit_opcode(cbuf, 0x33);
1853 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1854 //
1855 // // CALL to interpreter.
1856 // cbuf.set_inst_mark();
1857 // $$$emit8$primary;
1858 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1859 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1860 // %}
1861
1862 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1863 $$$emit8$primary;
1864 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1865 $$$emit8$shift$$constant;
1866 %}
1867
1868 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1869 // Load immediate does not have a zero or sign extended version
1870 // for 8-bit immediates
1871 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1872 $$$emit32$src$$constant;
1873 %}
1874
1875 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1876 // Load immediate does not have a zero or sign extended version
1877 // for 8-bit immediates
1878 emit_opcode(cbuf, $primary + $dst$$reg);
1879 $$$emit32$src$$constant;
1880 %}
1881
1882 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1883 // Load immediate does not have a zero or sign extended version
1884 // for 8-bit immediates
1885 int dst_enc = $dst$$reg;
1886 int src_con = $src$$constant & 0x0FFFFFFFFL;
1887 if (src_con == 0) {
1888 // xor dst, dst
1889 emit_opcode(cbuf, 0x33);
1890 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1891 } else {
1892 emit_opcode(cbuf, $primary + dst_enc);
1893 emit_d32(cbuf, src_con);
1894 }
1895 %}
1896
1897 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1898 // Load immediate does not have a zero or sign extended version
1899 // for 8-bit immediates
1900 int dst_enc = $dst$$reg + 2;
1901 int src_con = ((julong)($src$$constant)) >> 32;
1902 if (src_con == 0) {
1903 // xor dst, dst
1904 emit_opcode(cbuf, 0x33);
1905 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1906 } else {
1907 emit_opcode(cbuf, $primary + dst_enc);
1908 emit_d32(cbuf, src_con);
1909 }
1910 %}
1911
1912
1913 enc_class LdImmD (immD src) %{ // Load Immediate
1914 if( is_positive_zero_double($src$$constant)) {
1915 // FLDZ
1916 emit_opcode(cbuf,0xD9);
1917 emit_opcode(cbuf,0xEE);
1918 } else if( is_positive_one_double($src$$constant)) {
1919 // FLD1
1920 emit_opcode(cbuf,0xD9);
1921 emit_opcode(cbuf,0xE8);
1922 } else {
1923 emit_opcode(cbuf,0xDD);
1924 emit_rm(cbuf, 0x0, 0x0, 0x5);
1925 emit_double_constant(cbuf, $src$$constant);
1926 }
1927 %}
1928
1929
1930 enc_class LdImmF (immF src) %{ // Load Immediate
1931 if( is_positive_zero_float($src$$constant)) {
1932 emit_opcode(cbuf,0xD9);
1933 emit_opcode(cbuf,0xEE);
1934 } else if( is_positive_one_float($src$$constant)) {
1935 emit_opcode(cbuf,0xD9);
1936 emit_opcode(cbuf,0xE8);
1937 } else {
1938 $$$emit8$primary;
1939 // Load immediate does not have a zero or sign extended version
1940 // for 8-bit immediates
1941 // First load to TOS, then move to dst
1942 emit_rm(cbuf, 0x0, 0x0, 0x5);
1943 emit_float_constant(cbuf, $src$$constant);
1944 }
1945 %}
1946
1947 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1948 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1949 emit_float_constant(cbuf, $con$$constant);
1950 %}
1951
1952 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1953 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1954 emit_double_constant(cbuf, $con$$constant);
1955 %}
1956
1957 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1958 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1959 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1960 emit_opcode(cbuf, 0x0F);
1961 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1962 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1963 emit_double_constant(cbuf, $con$$constant);
1964 %}
1965
1966 enc_class Opc_MemImm_F(immF src) %{
1967 cbuf.set_inst_mark();
1968 $$$emit8$primary;
1969 emit_rm(cbuf, 0x0, $secondary, 0x5);
1970 emit_float_constant(cbuf, $src$$constant);
1971 %}
1972
1973
1974 enc_class MovI2X_reg(regX dst, eRegI src) %{
1975 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1976 emit_opcode(cbuf, 0x0F );
1977 emit_opcode(cbuf, 0x6E );
1978 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1979 %}
1980
1981 enc_class MovX2I_reg(eRegI dst, regX src) %{
1982 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1983 emit_opcode(cbuf, 0x0F );
1984 emit_opcode(cbuf, 0x7E );
1985 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1986 %}
1987
1988 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1989 { // MOVD $dst,$src.lo
1990 emit_opcode(cbuf,0x66);
1991 emit_opcode(cbuf,0x0F);
1992 emit_opcode(cbuf,0x6E);
1993 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1994 }
1995 { // MOVD $tmp,$src.hi
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2000 }
2001 { // PUNPCKLDQ $dst,$tmp
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x62);
2005 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2006 }
2007 %}
2008
2009 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2010 { // MOVD $dst.lo,$src
2011 emit_opcode(cbuf,0x66);
2012 emit_opcode(cbuf,0x0F);
2013 emit_opcode(cbuf,0x7E);
2014 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2015 }
2016 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2017 emit_opcode(cbuf,0xF2);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x70);
2020 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2021 emit_d8(cbuf, 0x4E);
2022 }
2023 { // MOVD $dst.hi,$tmp
2024 emit_opcode(cbuf,0x66);
2025 emit_opcode(cbuf,0x0F);
2026 emit_opcode(cbuf,0x7E);
2027 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2028 }
2029 %}
2030
2031
2032 // Encode a reg-reg copy. If it is useless, then empty encoding.
2033 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2034 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2035 %}
2036
2037 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2038 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2039 %}
2040
2041 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2042 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2043 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2044 %}
2045
2046 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2047 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2048 %}
2049
2050 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2051 $$$emit8$primary;
2052 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2053 %}
2054
2055 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2056 $$$emit8$secondary;
2057 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2058 %}
2059
2060 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2061 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2062 %}
2063
2064 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2065 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2066 %}
2067
2068 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2069 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2070 %}
2071
2072 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2073 // Output immediate
2074 $$$emit32$src$$constant;
2075 %}
2076
2077 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2078 // Output Float immediate bits
2079 jfloat jf = $src$$constant;
2080 int jf_as_bits = jint_cast( jf );
2081 emit_d32(cbuf, jf_as_bits);
2082 %}
2083
2084 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2085 // Output Float immediate bits
2086 jfloat jf = $src$$constant;
2087 int jf_as_bits = jint_cast( jf );
2088 emit_d32(cbuf, jf_as_bits);
2089 %}
2090
2091 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2092 // Output immediate
2093 $$$emit16$src$$constant;
2094 %}
2095
2096 enc_class Con_d32(immI src) %{
2097 emit_d32(cbuf,$src$$constant);
2098 %}
2099
2100 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2101 // Output immediate memory reference
2102 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2103 emit_d32(cbuf, 0x00);
2104 %}
2105
2106 enc_class lock_prefix( ) %{
2107 if( os::is_MP() )
2108 emit_opcode(cbuf,0xF0); // [Lock]
2109 %}
2110
2111 // Cmp-xchg long value.
2112 // Note: we need to swap rbx, and rcx before and after the
2113 // cmpxchg8 instruction because the instruction uses
2114 // rcx as the high order word of the new value to store but
2115 // our register encoding uses rbx,.
2116 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2117
2118 // XCHG rbx,ecx
2119 emit_opcode(cbuf,0x87);
2120 emit_opcode(cbuf,0xD9);
2121 // [Lock]
2122 if( os::is_MP() )
2123 emit_opcode(cbuf,0xF0);
2124 // CMPXCHG8 [Eptr]
2125 emit_opcode(cbuf,0x0F);
2126 emit_opcode(cbuf,0xC7);
2127 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2128 // XCHG rbx,ecx
2129 emit_opcode(cbuf,0x87);
2130 emit_opcode(cbuf,0xD9);
2131 %}
2132
2133 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2134 // [Lock]
2135 if( os::is_MP() )
2136 emit_opcode(cbuf,0xF0);
2137
2138 // CMPXCHG [Eptr]
2139 emit_opcode(cbuf,0x0F);
2140 emit_opcode(cbuf,0xB1);
2141 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2142 %}
2143
2144 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2145 int res_encoding = $res$$reg;
2146
2147 // MOV res,0
2148 emit_opcode( cbuf, 0xB8 + res_encoding);
2149 emit_d32( cbuf, 0 );
2150 // JNE,s fail
2151 emit_opcode(cbuf,0x75);
2152 emit_d8(cbuf, 5 );
2153 // MOV res,1
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 1 );
2156 // fail:
2157 %}
2158
2159 enc_class set_instruction_start( ) %{
2160 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2161 %}
2162
2163 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2164 int reg_encoding = $ereg$$reg;
2165 int base = $mem$$base;
2166 int index = $mem$$index;
2167 int scale = $mem$$scale;
2168 int displace = $mem$$disp;
2169 bool disp_is_oop = $mem->disp_is_oop();
2170 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2171 %}
2172
2173 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2174 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2175 int base = $mem$$base;
2176 int index = $mem$$index;
2177 int scale = $mem$$scale;
2178 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2179 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2180 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2181 %}
2182
2183 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2184 int r1, r2;
2185 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2186 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2187 emit_opcode(cbuf,0x0F);
2188 emit_opcode(cbuf,$tertiary);
2189 emit_rm(cbuf, 0x3, r1, r2);
2190 emit_d8(cbuf,$cnt$$constant);
2191 emit_d8(cbuf,$primary);
2192 emit_rm(cbuf, 0x3, $secondary, r1);
2193 emit_d8(cbuf,$cnt$$constant);
2194 %}
2195
2196 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2197 emit_opcode( cbuf, 0x8B ); // Move
2198 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2199 emit_d8(cbuf,$primary);
2200 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2201 emit_d8(cbuf,$cnt$$constant-32);
2202 emit_d8(cbuf,$primary);
2203 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2204 emit_d8(cbuf,31);
2205 %}
2206
2207 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2208 int r1, r2;
2209 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2210 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2211
2212 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2213 emit_rm(cbuf, 0x3, r1, r2);
2214 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2215 emit_opcode(cbuf,$primary);
2216 emit_rm(cbuf, 0x3, $secondary, r1);
2217 emit_d8(cbuf,$cnt$$constant-32);
2218 }
2219 emit_opcode(cbuf,0x33); // XOR r2,r2
2220 emit_rm(cbuf, 0x3, r2, r2);
2221 %}
2222
2223 // Clone of RegMem but accepts an extra parameter to access each
2224 // half of a double in memory; it never needs relocation info.
2225 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2226 emit_opcode(cbuf,$opcode$$constant);
2227 int reg_encoding = $rm_reg$$reg;
2228 int base = $mem$$base;
2229 int index = $mem$$index;
2230 int scale = $mem$$scale;
2231 int displace = $mem$$disp + $disp_for_half$$constant;
2232 bool disp_is_oop = false;
2233 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2234 %}
2235
2236 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2237 //
2238 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2239 // and it never needs relocation information.
2240 // Frequently used to move data between FPU's Stack Top and memory.
2241 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2242 int rm_byte_opcode = $rm_opcode$$constant;
2243 int base = $mem$$base;
2244 int index = $mem$$index;
2245 int scale = $mem$$scale;
2246 int displace = $mem$$disp;
2247 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2248 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2249 %}
2250
2251 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2252 int rm_byte_opcode = $rm_opcode$$constant;
2253 int base = $mem$$base;
2254 int index = $mem$$index;
2255 int scale = $mem$$scale;
2256 int displace = $mem$$disp;
2257 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2258 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2259 %}
2260
2261 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2262 int reg_encoding = $dst$$reg;
2263 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2264 int index = 0x04; // 0x04 indicates no index
2265 int scale = 0x00; // 0x00 indicates no scale
2266 int displace = $src1$$constant; // 0x00 indicates no displacement
2267 bool disp_is_oop = false;
2268 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2269 %}
2270
2271 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2272 // Compare dst,src
2273 emit_opcode(cbuf,0x3B);
2274 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2275 // jmp dst < src around move
2276 emit_opcode(cbuf,0x7C);
2277 emit_d8(cbuf,2);
2278 // move dst,src
2279 emit_opcode(cbuf,0x8B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 %}
2282
2283 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2284 // Compare dst,src
2285 emit_opcode(cbuf,0x3B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 // jmp dst > src around move
2288 emit_opcode(cbuf,0x7F);
2289 emit_d8(cbuf,2);
2290 // move dst,src
2291 emit_opcode(cbuf,0x8B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 %}
2294
2295 enc_class enc_FP_store(memory mem, regD src) %{
2296 // If src is FPR1, we can just FST to store it.
2297 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2298 int reg_encoding = 0x2; // Just store
2299 int base = $mem$$base;
2300 int index = $mem$$index;
2301 int scale = $mem$$scale;
2302 int displace = $mem$$disp;
2303 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2304 if( $src$$reg != FPR1L_enc ) {
2305 reg_encoding = 0x3; // Store & pop
2306 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2307 emit_d8( cbuf, 0xC0-1+$src$$reg );
2308 }
2309 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2310 emit_opcode(cbuf,$primary);
2311 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2312 %}
2313
2314 enc_class neg_reg(eRegI dst) %{
2315 // NEG $dst
2316 emit_opcode(cbuf,0xF7);
2317 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2318 %}
2319
2320 enc_class setLT_reg(eCXRegI dst) %{
2321 // SETLT $dst
2322 emit_opcode(cbuf,0x0F);
2323 emit_opcode(cbuf,0x9C);
2324 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2325 %}
2326
2327 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2328 int tmpReg = $tmp$$reg;
2329
2330 // SUB $p,$q
2331 emit_opcode(cbuf,0x2B);
2332 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2333 // SBB $tmp,$tmp
2334 emit_opcode(cbuf,0x1B);
2335 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2336 // AND $tmp,$y
2337 emit_opcode(cbuf,0x23);
2338 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2339 // ADD $p,$tmp
2340 emit_opcode(cbuf,0x03);
2341 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2342 %}
2343
2344 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2345 int tmpReg = $tmp$$reg;
2346
2347 // SUB $p,$q
2348 emit_opcode(cbuf,0x2B);
2349 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2350 // SBB $tmp,$tmp
2351 emit_opcode(cbuf,0x1B);
2352 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2353 // AND $tmp,$y
2354 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2355 emit_opcode(cbuf,0x23);
2356 int reg_encoding = tmpReg;
2357 int base = $mem$$base;
2358 int index = $mem$$index;
2359 int scale = $mem$$scale;
2360 int displace = $mem$$disp;
2361 bool disp_is_oop = $mem->disp_is_oop();
2362 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2363 // ADD $p,$tmp
2364 emit_opcode(cbuf,0x03);
2365 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2366 %}
2367
2368 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2369 // TEST shift,32
2370 emit_opcode(cbuf,0xF7);
2371 emit_rm(cbuf, 0x3, 0, ECX_enc);
2372 emit_d32(cbuf,0x20);
2373 // JEQ,s small
2374 emit_opcode(cbuf, 0x74);
2375 emit_d8(cbuf, 0x04);
2376 // MOV $dst.hi,$dst.lo
2377 emit_opcode( cbuf, 0x8B );
2378 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2379 // CLR $dst.lo
2380 emit_opcode(cbuf, 0x33);
2381 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2382 // small:
2383 // SHLD $dst.hi,$dst.lo,$shift
2384 emit_opcode(cbuf,0x0F);
2385 emit_opcode(cbuf,0xA5);
2386 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2387 // SHL $dst.lo,$shift"
2388 emit_opcode(cbuf,0xD3);
2389 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2390 %}
2391
2392 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2393 // TEST shift,32
2394 emit_opcode(cbuf,0xF7);
2395 emit_rm(cbuf, 0x3, 0, ECX_enc);
2396 emit_d32(cbuf,0x20);
2397 // JEQ,s small
2398 emit_opcode(cbuf, 0x74);
2399 emit_d8(cbuf, 0x04);
2400 // MOV $dst.lo,$dst.hi
2401 emit_opcode( cbuf, 0x8B );
2402 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2403 // CLR $dst.hi
2404 emit_opcode(cbuf, 0x33);
2405 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2406 // small:
2407 // SHRD $dst.lo,$dst.hi,$shift
2408 emit_opcode(cbuf,0x0F);
2409 emit_opcode(cbuf,0xAD);
2410 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2411 // SHR $dst.hi,$shift"
2412 emit_opcode(cbuf,0xD3);
2413 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2414 %}
2415
2416 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2417 // TEST shift,32
2418 emit_opcode(cbuf,0xF7);
2419 emit_rm(cbuf, 0x3, 0, ECX_enc);
2420 emit_d32(cbuf,0x20);
2421 // JEQ,s small
2422 emit_opcode(cbuf, 0x74);
2423 emit_d8(cbuf, 0x05);
2424 // MOV $dst.lo,$dst.hi
2425 emit_opcode( cbuf, 0x8B );
2426 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2427 // SAR $dst.hi,31
2428 emit_opcode(cbuf, 0xC1);
2429 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2430 emit_d8(cbuf, 0x1F );
2431 // small:
2432 // SHRD $dst.lo,$dst.hi,$shift
2433 emit_opcode(cbuf,0x0F);
2434 emit_opcode(cbuf,0xAD);
2435 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2436 // SAR $dst.hi,$shift"
2437 emit_opcode(cbuf,0xD3);
2438 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2439 %}
2440
2441
2442 // ----------------- Encodings for floating point unit -----------------
2443 // May leave result in FPU-TOS or FPU reg depending on opcodes
2444 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2445 $$$emit8$primary;
2446 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2447 %}
2448
2449 // Pop argument in FPR0 with FSTP ST(0)
2450 enc_class PopFPU() %{
2451 emit_opcode( cbuf, 0xDD );
2452 emit_d8( cbuf, 0xD8 );
2453 %}
2454
2455 // !!!!! equivalent to Pop_Reg_F
2456 enc_class Pop_Reg_D( regD dst ) %{
2457 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2458 emit_d8( cbuf, 0xD8+$dst$$reg );
2459 %}
2460
2461 enc_class Push_Reg_D( regD dst ) %{
2462 emit_opcode( cbuf, 0xD9 );
2463 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2464 %}
2465
2466 enc_class strictfp_bias1( regD dst ) %{
2467 emit_opcode( cbuf, 0xDB ); // FLD m80real
2468 emit_opcode( cbuf, 0x2D );
2469 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2470 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2471 emit_opcode( cbuf, 0xC8+$dst$$reg );
2472 %}
2473
2474 enc_class strictfp_bias2( regD dst ) %{
2475 emit_opcode( cbuf, 0xDB ); // FLD m80real
2476 emit_opcode( cbuf, 0x2D );
2477 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2478 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2479 emit_opcode( cbuf, 0xC8+$dst$$reg );
2480 %}
2481
2482 // Special case for moving an integer register to a stack slot.
2483 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2484 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2485 %}
2486
2487 // Special case for moving a register to a stack slot.
2488 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2489 // Opcode already emitted
2490 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2491 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2492 emit_d32(cbuf, $dst$$disp); // Displacement
2493 %}
2494
2495 // Push the integer in stackSlot 'src' onto FP-stack
2496 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2497 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2498 %}
2499
2500 // Push the float in stackSlot 'src' onto FP-stack
2501 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2502 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2503 %}
2504
2505 // Push the double in stackSlot 'src' onto FP-stack
2506 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2507 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2508 %}
2509
2510 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2511 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2512 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2513 %}
2514
2515 // Same as Pop_Mem_F except for opcode
2516 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2518 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2519 %}
2520
2521 enc_class Pop_Reg_F( regF dst ) %{
2522 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2523 emit_d8( cbuf, 0xD8+$dst$$reg );
2524 %}
2525
2526 enc_class Push_Reg_F( regF dst ) %{
2527 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2528 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2529 %}
2530
2531 // Push FPU's float to a stack-slot, and pop FPU-stack
2532 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2533 int pop = 0x02;
2534 if ($src$$reg != FPR1L_enc) {
2535 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2536 emit_d8( cbuf, 0xC0-1+$src$$reg );
2537 pop = 0x03;
2538 }
2539 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2540 %}
2541
2542 // Push FPU's double to a stack-slot, and pop FPU-stack
2543 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2544 int pop = 0x02;
2545 if ($src$$reg != FPR1L_enc) {
2546 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2547 emit_d8( cbuf, 0xC0-1+$src$$reg );
2548 pop = 0x03;
2549 }
2550 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2551 %}
2552
2553 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2554 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2555 int pop = 0xD0 - 1; // -1 since we skip FLD
2556 if ($src$$reg != FPR1L_enc) {
2557 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2558 emit_d8( cbuf, 0xC0-1+$src$$reg );
2559 pop = 0xD8;
2560 }
2561 emit_opcode( cbuf, 0xDD );
2562 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2563 %}
2564
2565
2566 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2567 MacroAssembler masm(&cbuf);
2568 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2569 masm.fmul( $src2$$reg+0); // value at TOS
2570 masm.fadd( $src$$reg+0); // value at TOS
2571 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2572 %}
2573
2574
2575 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2576 // load dst in FPR0
2577 emit_opcode( cbuf, 0xD9 );
2578 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2579 if ($src$$reg != FPR1L_enc) {
2580 // fincstp
2581 emit_opcode (cbuf, 0xD9);
2582 emit_opcode (cbuf, 0xF7);
2583 // swap src with FPR1:
2584 // FXCH FPR1 with src
2585 emit_opcode(cbuf, 0xD9);
2586 emit_d8(cbuf, 0xC8-1+$src$$reg );
2587 // fdecstp
2588 emit_opcode (cbuf, 0xD9);
2589 emit_opcode (cbuf, 0xF6);
2590 }
2591 %}
2592
2593 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2594 // Allocate a word
2595 emit_opcode(cbuf,0x83); // SUB ESP,8
2596 emit_opcode(cbuf,0xEC);
2597 emit_d8(cbuf,0x08);
2598
2599 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2600 emit_opcode (cbuf, 0x0F );
2601 emit_opcode (cbuf, 0x11 );
2602 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2603
2604 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2605 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2606
2607 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2608 emit_opcode (cbuf, 0x0F );
2609 emit_opcode (cbuf, 0x11 );
2610 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2611
2612 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2613 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2614
2615 %}
2616
2617 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2618 // Allocate a word
2619 emit_opcode(cbuf,0x83); // SUB ESP,4
2620 emit_opcode(cbuf,0xEC);
2621 emit_d8(cbuf,0x04);
2622
2623 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2624 emit_opcode (cbuf, 0x0F );
2625 emit_opcode (cbuf, 0x11 );
2626 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2627
2628 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2629 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2630
2631 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2632 emit_opcode (cbuf, 0x0F );
2633 emit_opcode (cbuf, 0x11 );
2634 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2635
2636 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2637 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2638
2639 %}
2640
2641 enc_class Push_ResultXD(regXD dst) %{
2642 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2643
2644 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2645 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2646 emit_opcode (cbuf, 0x0F );
2647 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2648 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2649
2650 emit_opcode(cbuf,0x83); // ADD ESP,8
2651 emit_opcode(cbuf,0xC4);
2652 emit_d8(cbuf,0x08);
2653 %}
2654
2655 enc_class Push_ResultX(regX dst, immI d8) %{
2656 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2657
2658 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2659 emit_opcode (cbuf, 0x0F );
2660 emit_opcode (cbuf, 0x10 );
2661 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2662
2663 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2664 emit_opcode(cbuf,0xC4);
2665 emit_d8(cbuf,$d8$$constant);
2666 %}
2667
2668 enc_class Push_SrcXD(regXD src) %{
2669 // Allocate a word
2670 emit_opcode(cbuf,0x83); // SUB ESP,8
2671 emit_opcode(cbuf,0xEC);
2672 emit_d8(cbuf,0x08);
2673
2674 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2675 emit_opcode (cbuf, 0x0F );
2676 emit_opcode (cbuf, 0x11 );
2677 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2678
2679 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2680 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2681 %}
2682
2683 enc_class push_stack_temp_qword() %{
2684 emit_opcode(cbuf,0x83); // SUB ESP,8
2685 emit_opcode(cbuf,0xEC);
2686 emit_d8 (cbuf,0x08);
2687 %}
2688
2689 enc_class pop_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // ADD ESP,8
2691 emit_opcode(cbuf,0xC4);
2692 emit_d8 (cbuf,0x08);
2693 %}
2694
2695 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2696 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2697 emit_opcode (cbuf, 0x0F );
2698 emit_opcode (cbuf, 0x11 );
2699 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2700
2701 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2702 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2703 %}
2704
2705 // Compute X^Y using Intel's fast hardware instructions, if possible.
2706 // Otherwise return a NaN.
2707 enc_class pow_exp_core_encoding %{
2708 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2710 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2711 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2712 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2713 emit_opcode(cbuf,0x1C);
2714 emit_d8(cbuf,0x24);
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2717 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2718 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2719 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2720 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2721 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2722 emit_d32(cbuf,0xFFFFF800);
2723 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2724 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2725 emit_d32(cbuf,1023);
2726 emit_opcode(cbuf,0x8B); // mov rbx,eax
2727 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2728 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2729 emit_rm(cbuf,0x3,0x4,EAX_enc);
2730 emit_d8(cbuf,20);
2731 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2732 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2733 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2734 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2735 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2736 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2737 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2738 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2739 emit_d32(cbuf,0);
2740 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2741 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2742 %}
2743
2744 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2745 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2746
2747 enc_class Push_Result_Mod_D( regD src) %{
2748 if ($src$$reg != FPR1L_enc) {
2749 // fincstp
2750 emit_opcode (cbuf, 0xD9);
2751 emit_opcode (cbuf, 0xF7);
2752 // FXCH FPR1 with src
2753 emit_opcode(cbuf, 0xD9);
2754 emit_d8(cbuf, 0xC8-1+$src$$reg );
2755 // fdecstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF6);
2758 }
2759 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2760 // // FSTP FPR$dst$$reg
2761 // emit_opcode( cbuf, 0xDD );
2762 // emit_d8( cbuf, 0xD8+$dst$$reg );
2763 %}
2764
2765 enc_class fnstsw_sahf_skip_parity() %{
2766 // fnstsw ax
2767 emit_opcode( cbuf, 0xDF );
2768 emit_opcode( cbuf, 0xE0 );
2769 // sahf
2770 emit_opcode( cbuf, 0x9E );
2771 // jnp ::skip
2772 emit_opcode( cbuf, 0x7B );
2773 emit_opcode( cbuf, 0x05 );
2774 %}
2775
2776 enc_class emitModD() %{
2777 // fprem must be iterative
2778 // :: loop
2779 // fprem
2780 emit_opcode( cbuf, 0xD9 );
2781 emit_opcode( cbuf, 0xF8 );
2782 // wait
2783 emit_opcode( cbuf, 0x9b );
2784 // fnstsw ax
2785 emit_opcode( cbuf, 0xDF );
2786 emit_opcode( cbuf, 0xE0 );
2787 // sahf
2788 emit_opcode( cbuf, 0x9E );
2789 // jp ::loop
2790 emit_opcode( cbuf, 0x0F );
2791 emit_opcode( cbuf, 0x8A );
2792 emit_opcode( cbuf, 0xF4 );
2793 emit_opcode( cbuf, 0xFF );
2794 emit_opcode( cbuf, 0xFF );
2795 emit_opcode( cbuf, 0xFF );
2796 %}
2797
2798 enc_class fpu_flags() %{
2799 // fnstsw_ax
2800 emit_opcode( cbuf, 0xDF);
2801 emit_opcode( cbuf, 0xE0);
2802 // test ax,0x0400
2803 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2804 emit_opcode( cbuf, 0xA9 );
2805 emit_d16 ( cbuf, 0x0400 );
2806 // // // This sequence works, but stalls for 12-16 cycles on PPro
2807 // // test rax,0x0400
2808 // emit_opcode( cbuf, 0xA9 );
2809 // emit_d32 ( cbuf, 0x00000400 );
2810 //
2811 // jz exit (no unordered comparison)
2812 emit_opcode( cbuf, 0x74 );
2813 emit_d8 ( cbuf, 0x02 );
2814 // mov ah,1 - treat as LT case (set carry flag)
2815 emit_opcode( cbuf, 0xB4 );
2816 emit_d8 ( cbuf, 0x01 );
2817 // sahf
2818 emit_opcode( cbuf, 0x9E);
2819 %}
2820
2821 enc_class cmpF_P6_fixup() %{
2822 // Fixup the integer flags in case comparison involved a NaN
2823 //
2824 // JNP exit (no unordered comparison, P-flag is set by NaN)
2825 emit_opcode( cbuf, 0x7B );
2826 emit_d8 ( cbuf, 0x03 );
2827 // MOV AH,1 - treat as LT case (set carry flag)
2828 emit_opcode( cbuf, 0xB4 );
2829 emit_d8 ( cbuf, 0x01 );
2830 // SAHF
2831 emit_opcode( cbuf, 0x9E);
2832 // NOP // target for branch to avoid branch to branch
2833 emit_opcode( cbuf, 0x90);
2834 %}
2835
2836 // fnstsw_ax();
2837 // sahf();
2838 // movl(dst, nan_result);
2839 // jcc(Assembler::parity, exit);
2840 // movl(dst, less_result);
2841 // jcc(Assembler::below, exit);
2842 // movl(dst, equal_result);
2843 // jcc(Assembler::equal, exit);
2844 // movl(dst, greater_result);
2845
2846 // less_result = 1;
2847 // greater_result = -1;
2848 // equal_result = 0;
2849 // nan_result = -1;
2850
2851 enc_class CmpF_Result(eRegI dst) %{
2852 // fnstsw_ax();
2853 emit_opcode( cbuf, 0xDF);
2854 emit_opcode( cbuf, 0xE0);
2855 // sahf
2856 emit_opcode( cbuf, 0x9E);
2857 // movl(dst, nan_result);
2858 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2859 emit_d32( cbuf, -1 );
2860 // jcc(Assembler::parity, exit);
2861 emit_opcode( cbuf, 0x7A );
2862 emit_d8 ( cbuf, 0x13 );
2863 // movl(dst, less_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::below, exit);
2867 emit_opcode( cbuf, 0x72 );
2868 emit_d8 ( cbuf, 0x0C );
2869 // movl(dst, equal_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, 0 );
2872 // jcc(Assembler::equal, exit);
2873 emit_opcode( cbuf, 0x74 );
2874 emit_d8 ( cbuf, 0x05 );
2875 // movl(dst, greater_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 1 );
2878 %}
2879
2880
2881 // XMM version of CmpF_Result. Because the XMM compare
2882 // instructions set the EFLAGS directly. It becomes simpler than
2883 // the float version above.
2884 enc_class CmpX_Result(eRegI dst) %{
2885 MacroAssembler _masm(&cbuf);
2886 Label nan, inc, done;
2887
2888 __ jccb(Assembler::parity, nan);
2889 __ jccb(Assembler::equal, done);
2890 __ jccb(Assembler::above, inc);
2891 __ bind(nan);
2892 __ decrement(as_Register($dst$$reg)); // NO L qqq
2893 __ jmpb(done);
2894 __ bind(inc);
2895 __ increment(as_Register($dst$$reg)); // NO L qqq
2896 __ bind(done);
2897 %}
2898
2899 // Compare the longs and set flags
2900 // BROKEN! Do Not use as-is
2901 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2902 // CMP $src1.hi,$src2.hi
2903 emit_opcode( cbuf, 0x3B );
2904 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2905 // JNE,s done
2906 emit_opcode(cbuf,0x75);
2907 emit_d8(cbuf, 2 );
2908 // CMP $src1.lo,$src2.lo
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2911 // done:
2912 %}
2913
2914 enc_class convert_int_long( regL dst, eRegI src ) %{
2915 // mov $dst.lo,$src
2916 int dst_encoding = $dst$$reg;
2917 int src_encoding = $src$$reg;
2918 encode_Copy( cbuf, dst_encoding , src_encoding );
2919 // mov $dst.hi,$src
2920 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2921 // sar $dst.hi,31
2922 emit_opcode( cbuf, 0xC1 );
2923 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2924 emit_d8(cbuf, 0x1F );
2925 %}
2926
2927 enc_class convert_long_double( eRegL src ) %{
2928 // push $src.hi
2929 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2930 // push $src.lo
2931 emit_opcode(cbuf, 0x50+$src$$reg );
2932 // fild 64-bits at [SP]
2933 emit_opcode(cbuf,0xdf);
2934 emit_d8(cbuf, 0x6C);
2935 emit_d8(cbuf, 0x24);
2936 emit_d8(cbuf, 0x00);
2937 // pop stack
2938 emit_opcode(cbuf, 0x83); // add SP, #8
2939 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2940 emit_d8(cbuf, 0x8);
2941 %}
2942
2943 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2944 // IMUL EDX:EAX,$src1
2945 emit_opcode( cbuf, 0xF7 );
2946 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2947 // SAR EDX,$cnt-32
2948 int shift_count = ((int)$cnt$$constant) - 32;
2949 if (shift_count > 0) {
2950 emit_opcode(cbuf, 0xC1);
2951 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2952 emit_d8(cbuf, shift_count);
2953 }
2954 %}
2955
2956 // this version doesn't have add sp, 8
2957 enc_class convert_long_double2( eRegL src ) %{
2958 // push $src.hi
2959 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2960 // push $src.lo
2961 emit_opcode(cbuf, 0x50+$src$$reg );
2962 // fild 64-bits at [SP]
2963 emit_opcode(cbuf,0xdf);
2964 emit_d8(cbuf, 0x6C);
2965 emit_d8(cbuf, 0x24);
2966 emit_d8(cbuf, 0x00);
2967 %}
2968
2969 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2970 // Basic idea: long = (long)int * (long)int
2971 // IMUL EDX:EAX, src
2972 emit_opcode( cbuf, 0xF7 );
2973 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2974 %}
2975
2976 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2977 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2978 // MUL EDX:EAX, src
2979 emit_opcode( cbuf, 0xF7 );
2980 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2981 %}
2982
2983 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2984 // Basic idea: lo(result) = lo(x_lo * y_lo)
2985 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2986 // MOV $tmp,$src.lo
2987 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2988 // IMUL $tmp,EDX
2989 emit_opcode( cbuf, 0x0F );
2990 emit_opcode( cbuf, 0xAF );
2991 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2992 // MOV EDX,$src.hi
2993 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2994 // IMUL EDX,EAX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2998 // ADD $tmp,EDX
2999 emit_opcode( cbuf, 0x03 );
3000 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3001 // MUL EDX:EAX,$src.lo
3002 emit_opcode( cbuf, 0xF7 );
3003 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3004 // ADD EDX,ESI
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3007 %}
3008
3009 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3010 // Basic idea: lo(result) = lo(src * y_lo)
3011 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3012 // IMUL $tmp,EDX,$src
3013 emit_opcode( cbuf, 0x6B );
3014 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3015 emit_d8( cbuf, (int)$src$$constant );
3016 // MOV EDX,$src
3017 emit_opcode(cbuf, 0xB8 + EDX_enc);
3018 emit_d32( cbuf, (int)$src$$constant );
3019 // MUL EDX:EAX,EDX
3020 emit_opcode( cbuf, 0xF7 );
3021 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3022 // ADD EDX,ESI
3023 emit_opcode( cbuf, 0x03 );
3024 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3025 %}
3026
3027 enc_class long_div( eRegL src1, eRegL src2 ) %{
3028 // PUSH src1.hi
3029 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3030 // PUSH src1.lo
3031 emit_opcode(cbuf, 0x50+$src1$$reg );
3032 // PUSH src2.hi
3033 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3034 // PUSH src2.lo
3035 emit_opcode(cbuf, 0x50+$src2$$reg );
3036 // CALL directly to the runtime
3037 cbuf.set_inst_mark();
3038 emit_opcode(cbuf,0xE8); // Call into runtime
3039 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3040 // Restore stack
3041 emit_opcode(cbuf, 0x83); // add SP, #framesize
3042 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3043 emit_d8(cbuf, 4*4);
3044 %}
3045
3046 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3047 // PUSH src1.hi
3048 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3049 // PUSH src1.lo
3050 emit_opcode(cbuf, 0x50+$src1$$reg );
3051 // PUSH src2.hi
3052 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3053 // PUSH src2.lo
3054 emit_opcode(cbuf, 0x50+$src2$$reg );
3055 // CALL directly to the runtime
3056 cbuf.set_inst_mark();
3057 emit_opcode(cbuf,0xE8); // Call into runtime
3058 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3059 // Restore stack
3060 emit_opcode(cbuf, 0x83); // add SP, #framesize
3061 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3062 emit_d8(cbuf, 4*4);
3063 %}
3064
3065 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3066 // MOV $tmp,$src.lo
3067 emit_opcode(cbuf, 0x8B);
3068 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3069 // OR $tmp,$src.hi
3070 emit_opcode(cbuf, 0x0B);
3071 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3072 %}
3073
3074 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3075 // CMP $src1.lo,$src2.lo
3076 emit_opcode( cbuf, 0x3B );
3077 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3078 // JNE,s skip
3079 emit_cc(cbuf, 0x70, 0x5);
3080 emit_d8(cbuf,2);
3081 // CMP $src1.hi,$src2.hi
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3084 %}
3085
3086 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3087 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3090 // MOV $tmp,$src1.hi
3091 emit_opcode( cbuf, 0x8B );
3092 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3093 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3094 emit_opcode( cbuf, 0x1B );
3095 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3096 %}
3097
3098 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3099 // XOR $tmp,$tmp
3100 emit_opcode(cbuf,0x33); // XOR
3101 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3102 // CMP $tmp,$src.lo
3103 emit_opcode( cbuf, 0x3B );
3104 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3105 // SBB $tmp,$src.hi
3106 emit_opcode( cbuf, 0x1B );
3107 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3108 %}
3109
3110 // Sniff, sniff... smells like Gnu Superoptimizer
3111 enc_class neg_long( eRegL dst ) %{
3112 emit_opcode(cbuf,0xF7); // NEG hi
3113 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3114 emit_opcode(cbuf,0xF7); // NEG lo
3115 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3116 emit_opcode(cbuf,0x83); // SBB hi,0
3117 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3118 emit_d8 (cbuf,0 );
3119 %}
3120
3121 enc_class movq_ld(regXD dst, memory mem) %{
3122 MacroAssembler _masm(&cbuf);
3123 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3124 __ movq(as_XMMRegister($dst$$reg), madr);
3125 %}
3126
3127 enc_class movq_st(memory mem, regXD src) %{
3128 MacroAssembler _masm(&cbuf);
3129 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3130 __ movq(madr, as_XMMRegister($src$$reg));
3131 %}
3132
3133 enc_class pshufd_8x8(regX dst, regX src) %{
3134 MacroAssembler _masm(&cbuf);
3135
3136 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3137 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3138 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3139 %}
3140
3141 enc_class pshufd_4x16(regX dst, regX src) %{
3142 MacroAssembler _masm(&cbuf);
3143
3144 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3145 %}
3146
3147 enc_class pshufd(regXD dst, regXD src, int mode) %{
3148 MacroAssembler _masm(&cbuf);
3149
3150 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3151 %}
3152
3153 enc_class pxor(regXD dst, regXD src) %{
3154 MacroAssembler _masm(&cbuf);
3155
3156 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3157 %}
3158
3159 enc_class mov_i2x(regXD dst, eRegI src) %{
3160 MacroAssembler _masm(&cbuf);
3161
3162 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3163 %}
3164
3165
3166 // Because the transitions from emitted code to the runtime
3167 // monitorenter/exit helper stubs are so slow it's critical that
3168 // we inline both the stack-locking fast-path and the inflated fast path.
3169 //
3170 // See also: cmpFastLock and cmpFastUnlock.
3171 //
3172 // What follows is a specialized inline transliteration of the code
3173 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3174 // another option would be to emit TrySlowEnter and TrySlowExit methods
3175 // at startup-time. These methods would accept arguments as
3176 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3177 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3178 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3179 // In practice, however, the # of lock sites is bounded and is usually small.
3180 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3181 // if the processor uses simple bimodal branch predictors keyed by EIP
3182 // Since the helper routines would be called from multiple synchronization
3183 // sites.
3184 //
3185 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3186 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3187 // to those specialized methods. That'd give us a mostly platform-independent
3188 // implementation that the JITs could optimize and inline at their pleasure.
3189 // Done correctly, the only time we'd need to cross to native could would be
3190 // to park() or unpark() threads. We'd also need a few more unsafe operators
3191 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3192 // (b) explicit barriers or fence operations.
3193 //
3194 // TODO:
3195 //
3196 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3197 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3198 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3199 // the lock operators would typically be faster than reifying Self.
3200 //
3201 // * Ideally I'd define the primitives as:
3202 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3203 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3204 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3205 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3206 // Furthermore the register assignments are overconstrained, possibly resulting in
3207 // sub-optimal code near the synchronization site.
3208 //
3209 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3210 // Alternately, use a better sp-proximity test.
3211 //
3212 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3213 // Either one is sufficient to uniquely identify a thread.
3214 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3215 //
3216 // * Intrinsify notify() and notifyAll() for the common cases where the
3217 // object is locked by the calling thread but the waitlist is empty.
3218 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3219 //
3220 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3221 // But beware of excessive branch density on AMD Opterons.
3222 //
3223 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3224 // or failure of the fast-path. If the fast-path fails then we pass
3225 // control to the slow-path, typically in C. In Fast_Lock and
3226 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3227 // will emit a conditional branch immediately after the node.
3228 // So we have branches to branches and lots of ICC.ZF games.
3229 // Instead, it might be better to have C2 pass a "FailureLabel"
3230 // into Fast_Lock and Fast_Unlock. In the case of success, control
3231 // will drop through the node. ICC.ZF is undefined at exit.
3232 // In the case of failure, the node will branch directly to the
3233 // FailureLabel
3234
3235
3236 // obj: object to lock
3237 // box: on-stack box address (displaced header location) - KILLED
3238 // rax,: tmp -- KILLED
3239 // scr: tmp -- KILLED
3240 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3241
3242 Register objReg = as_Register($obj$$reg);
3243 Register boxReg = as_Register($box$$reg);
3244 Register tmpReg = as_Register($tmp$$reg);
3245 Register scrReg = as_Register($scr$$reg);
3246
3247 // Ensure the register assignents are disjoint
3248 guarantee (objReg != boxReg, "") ;
3249 guarantee (objReg != tmpReg, "") ;
3250 guarantee (objReg != scrReg, "") ;
3251 guarantee (boxReg != tmpReg, "") ;
3252 guarantee (boxReg != scrReg, "") ;
3253 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3254
3255 MacroAssembler masm(&cbuf);
3256
3257 if (_counters != NULL) {
3258 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3259 }
3260 if (EmitSync & 1) {
3261 // set box->dhw = unused_mark (3)
3262 // Force all sync thru slow-path: slow_enter() and slow_exit()
3263 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3264 masm.cmpptr (rsp, (int32_t)0) ;
3265 } else
3266 if (EmitSync & 2) {
3267 Label DONE_LABEL ;
3268 if (UseBiasedLocking) {
3269 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3270 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3271 }
3272
3273 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3274 masm.orptr (tmpReg, 0x1);
3275 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3276 if (os::is_MP()) { masm.lock(); }
3277 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3278 masm.jcc(Assembler::equal, DONE_LABEL);
3279 // Recursive locking
3280 masm.subptr(tmpReg, rsp);
3281 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3282 masm.movptr(Address(boxReg, 0), tmpReg);
3283 masm.bind(DONE_LABEL) ;
3284 } else {
3285 // Possible cases that we'll encounter in fast_lock
3286 // ------------------------------------------------
3287 // * Inflated
3288 // -- unlocked
3289 // -- Locked
3290 // = by self
3291 // = by other
3292 // * biased
3293 // -- by Self
3294 // -- by other
3295 // * neutral
3296 // * stack-locked
3297 // -- by self
3298 // = sp-proximity test hits
3299 // = sp-proximity test generates false-negative
3300 // -- by other
3301 //
3302
3303 Label IsInflated, DONE_LABEL, PopDone ;
3304
3305 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3306 // order to reduce the number of conditional branches in the most common cases.
3307 // Beware -- there's a subtle invariant that fetch of the markword
3308 // at [FETCH], below, will never observe a biased encoding (*101b).
3309 // If this invariant is not held we risk exclusion (safety) failure.
3310 if (UseBiasedLocking) {
3311 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3312 }
3313
3314 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3315 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3316 masm.jccb (Assembler::notZero, IsInflated) ;
3317
3318 // Attempt stack-locking ...
3319 masm.orptr (tmpReg, 0x1);
3320 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3321 if (os::is_MP()) { masm.lock(); }
3322 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3323 if (_counters != NULL) {
3324 masm.cond_inc32(Assembler::equal,
3325 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3326 }
3327 masm.jccb (Assembler::equal, DONE_LABEL);
3328
3329 // Recursive locking
3330 masm.subptr(tmpReg, rsp);
3331 masm.andptr(tmpReg, 0xFFFFF003 );
3332 masm.movptr(Address(boxReg, 0), tmpReg);
3333 if (_counters != NULL) {
3334 masm.cond_inc32(Assembler::equal,
3335 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3336 }
3337 masm.jmp (DONE_LABEL) ;
3338
3339 masm.bind (IsInflated) ;
3340
3341 // The object is inflated.
3342 //
3343 // TODO-FIXME: eliminate the ugly use of manifest constants:
3344 // Use markOopDesc::monitor_value instead of "2".
3345 // use markOop::unused_mark() instead of "3".
3346 // The tmpReg value is an objectMonitor reference ORed with
3347 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3348 // objectmonitor pointer by masking off the "2" bit or we can just
3349 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3350 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3351 //
3352 // I use the latter as it avoids AGI stalls.
3353 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3354 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3355 //
3356 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3357
3358 // boxReg refers to the on-stack BasicLock in the current frame.
3359 // We'd like to write:
3360 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3361 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3362 // additional latency as we have another ST in the store buffer that must drain.
3363
3364 if (EmitSync & 8192) {
3365 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3366 masm.get_thread (scrReg) ;
3367 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3368 masm.movptr(tmpReg, 0); // consider: xor vs mov
3369 if (os::is_MP()) { masm.lock(); }
3370 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3371 } else
3372 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3373 masm.movptr(scrReg, boxReg) ;
3374 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3375
3376 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3377 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3378 // prefetchw [eax + Offset(_owner)-2]
3379 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3380 }
3381
3382 if ((EmitSync & 64) == 0) {
3383 // Optimistic form: consider XORL tmpReg,tmpReg
3384 masm.movptr(tmpReg, 0 ) ;
3385 } else {
3386 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3387 // Test-And-CAS instead of CAS
3388 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3389 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3390 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3391 }
3392
3393 // Appears unlocked - try to swing _owner from null to non-null.
3394 // Ideally, I'd manifest "Self" with get_thread and then attempt
3395 // to CAS the register containing Self into m->Owner.
3396 // But we don't have enough registers, so instead we can either try to CAS
3397 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3398 // we later store "Self" into m->Owner. Transiently storing a stack address
3399 // (rsp or the address of the box) into m->owner is harmless.
3400 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3401 if (os::is_MP()) { masm.lock(); }
3402 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3403 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3404 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3405 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3406 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3407 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3408
3409 // If the CAS fails we can either retry or pass control to the slow-path.
3410 // We use the latter tactic.
3411 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3412 // If the CAS was successful ...
3413 // Self has acquired the lock
3414 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3415 // Intentional fall-through into DONE_LABEL ...
3416 } else {
3417 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3418 masm.movptr(boxReg, tmpReg) ;
3419
3420 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3421 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3422 // prefetchw [eax + Offset(_owner)-2]
3423 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3424 }
3425
3426 if ((EmitSync & 64) == 0) {
3427 // Optimistic form
3428 masm.xorptr (tmpReg, tmpReg) ;
3429 } else {
3430 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3431 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3432 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3433 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3434 }
3435
3436 // Appears unlocked - try to swing _owner from null to non-null.
3437 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3438 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3439 masm.get_thread (scrReg) ;
3440 if (os::is_MP()) { masm.lock(); }
3441 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3442
3443 // If the CAS fails we can either retry or pass control to the slow-path.
3444 // We use the latter tactic.
3445 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3446 // If the CAS was successful ...
3447 // Self has acquired the lock
3448 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3449 // Intentional fall-through into DONE_LABEL ...
3450 }
3451
3452 // DONE_LABEL is a hot target - we'd really like to place it at the
3453 // start of cache line by padding with NOPs.
3454 // See the AMD and Intel software optimization manuals for the
3455 // most efficient "long" NOP encodings.
3456 // Unfortunately none of our alignment mechanisms suffice.
3457 masm.bind(DONE_LABEL);
3458
3459 // Avoid branch-to-branch on AMD processors
3460 // This appears to be superstition.
3461 if (EmitSync & 32) masm.nop() ;
3462
3463
3464 // At DONE_LABEL the icc ZFlag is set as follows ...
3465 // Fast_Unlock uses the same protocol.
3466 // ZFlag == 1 -> Success
3467 // ZFlag == 0 -> Failure - force control through the slow-path
3468 }
3469 %}
3470
3471 // obj: object to unlock
3472 // box: box address (displaced header location), killed. Must be EAX.
3473 // rbx,: killed tmp; cannot be obj nor box.
3474 //
3475 // Some commentary on balanced locking:
3476 //
3477 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3478 // Methods that don't have provably balanced locking are forced to run in the
3479 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3480 // The interpreter provides two properties:
3481 // I1: At return-time the interpreter automatically and quietly unlocks any
3482 // objects acquired the current activation (frame). Recall that the
3483 // interpreter maintains an on-stack list of locks currently held by
3484 // a frame.
3485 // I2: If a method attempts to unlock an object that is not held by the
3486 // the frame the interpreter throws IMSX.
3487 //
3488 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3489 // B() doesn't have provably balanced locking so it runs in the interpreter.
3490 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3491 // is still locked by A().
3492 //
3493 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3494 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3495 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3496 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3497
3498 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3499
3500 Register objReg = as_Register($obj$$reg);
3501 Register boxReg = as_Register($box$$reg);
3502 Register tmpReg = as_Register($tmp$$reg);
3503
3504 guarantee (objReg != boxReg, "") ;
3505 guarantee (objReg != tmpReg, "") ;
3506 guarantee (boxReg != tmpReg, "") ;
3507 guarantee (boxReg == as_Register(EAX_enc), "") ;
3508 MacroAssembler masm(&cbuf);
3509
3510 if (EmitSync & 4) {
3511 // Disable - inhibit all inlining. Force control through the slow-path
3512 masm.cmpptr (rsp, 0) ;
3513 } else
3514 if (EmitSync & 8) {
3515 Label DONE_LABEL ;
3516 if (UseBiasedLocking) {
3517 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3518 }
3519 // classic stack-locking code ...
3520 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3521 masm.testptr(tmpReg, tmpReg) ;
3522 masm.jcc (Assembler::zero, DONE_LABEL) ;
3523 if (os::is_MP()) { masm.lock(); }
3524 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3525 masm.bind(DONE_LABEL);
3526 } else {
3527 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3528
3529 // Critically, the biased locking test must have precedence over
3530 // and appear before the (box->dhw == 0) recursive stack-lock test.
3531 if (UseBiasedLocking) {
3532 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3533 }
3534
3535 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3536 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3537 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3538
3539 masm.testptr(tmpReg, 0x02) ; // Inflated?
3540 masm.jccb (Assembler::zero, Stacked) ;
3541
3542 masm.bind (Inflated) ;
3543 // It's inflated.
3544 // Despite our balanced locking property we still check that m->_owner == Self
3545 // as java routines or native JNI code called by this thread might
3546 // have released the lock.
3547 // Refer to the comments in synchronizer.cpp for how we might encode extra
3548 // state in _succ so we can avoid fetching EntryList|cxq.
3549 //
3550 // I'd like to add more cases in fast_lock() and fast_unlock() --
3551 // such as recursive enter and exit -- but we have to be wary of
3552 // I$ bloat, T$ effects and BP$ effects.
3553 //
3554 // If there's no contention try a 1-0 exit. That is, exit without
3555 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3556 // we detect and recover from the race that the 1-0 exit admits.
3557 //
3558 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3559 // before it STs null into _owner, releasing the lock. Updates
3560 // to data protected by the critical section must be visible before
3561 // we drop the lock (and thus before any other thread could acquire
3562 // the lock and observe the fields protected by the lock).
3563 // IA32's memory-model is SPO, so STs are ordered with respect to
3564 // each other and there's no need for an explicit barrier (fence).
3565 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3566
3567 masm.get_thread (boxReg) ;
3568 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3569 // prefetchw [ebx + Offset(_owner)-2]
3570 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3571 }
3572
3573 // Note that we could employ various encoding schemes to reduce
3574 // the number of loads below (currently 4) to just 2 or 3.
3575 // Refer to the comments in synchronizer.cpp.
3576 // In practice the chain of fetches doesn't seem to impact performance, however.
3577 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3578 // Attempt to reduce branch density - AMD's branch predictor.
3579 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3580 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3581 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3582 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3583 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3584 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3585 masm.jmpb (DONE_LABEL) ;
3586 } else {
3587 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3589 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3590 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3591 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3592 masm.jccb (Assembler::notZero, CheckSucc) ;
3593 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3594 masm.jmpb (DONE_LABEL) ;
3595 }
3596
3597 // The Following code fragment (EmitSync & 65536) improves the performance of
3598 // contended applications and contended synchronization microbenchmarks.
3599 // Unfortunately the emission of the code - even though not executed - causes regressions
3600 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3601 // with an equal number of never-executed NOPs results in the same regression.
3602 // We leave it off by default.
3603
3604 if ((EmitSync & 65536) != 0) {
3605 Label LSuccess, LGoSlowPath ;
3606
3607 masm.bind (CheckSucc) ;
3608
3609 // Optional pre-test ... it's safe to elide this
3610 if ((EmitSync & 16) == 0) {
3611 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3612 masm.jccb (Assembler::zero, LGoSlowPath) ;
3613 }
3614
3615 // We have a classic Dekker-style idiom:
3616 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3617 // There are a number of ways to implement the barrier:
3618 // (1) lock:andl &m->_owner, 0
3619 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3620 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3621 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3622 // (2) If supported, an explicit MFENCE is appealing.
3623 // In older IA32 processors MFENCE is slower than lock:add or xchg
3624 // particularly if the write-buffer is full as might be the case if
3625 // if stores closely precede the fence or fence-equivalent instruction.
3626 // In more modern implementations MFENCE appears faster, however.
3627 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3628 // The $lines underlying the top-of-stack should be in M-state.
3629 // The locked add instruction is serializing, of course.
3630 // (4) Use xchg, which is serializing
3631 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3632 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3633 // The integer condition codes will tell us if succ was 0.
3634 // Since _succ and _owner should reside in the same $line and
3635 // we just stored into _owner, it's likely that the $line
3636 // remains in M-state for the lock:orl.
3637 //
3638 // We currently use (3), although it's likely that switching to (2)
3639 // is correct for the future.
3640
3641 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3642 if (os::is_MP()) {
3643 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3644 masm.mfence();
3645 } else {
3646 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3647 }
3648 }
3649 // Ratify _succ remains non-null
3650 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3651 masm.jccb (Assembler::notZero, LSuccess) ;
3652
3653 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3654 if (os::is_MP()) { masm.lock(); }
3655 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3656 masm.jccb (Assembler::notEqual, LSuccess) ;
3657 // Since we're low on registers we installed rsp as a placeholding in _owner.
3658 // Now install Self over rsp. This is safe as we're transitioning from
3659 // non-null to non=null
3660 masm.get_thread (boxReg) ;
3661 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3662 // Intentional fall-through into LGoSlowPath ...
3663
3664 masm.bind (LGoSlowPath) ;
3665 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3666 masm.jmpb (DONE_LABEL) ;
3667
3668 masm.bind (LSuccess) ;
3669 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3670 masm.jmpb (DONE_LABEL) ;
3671 }
3672
3673 masm.bind (Stacked) ;
3674 // It's not inflated and it's not recursively stack-locked and it's not biased.
3675 // It must be stack-locked.
3676 // Try to reset the header to displaced header.
3677 // The "box" value on the stack is stable, so we can reload
3678 // and be assured we observe the same value as above.
3679 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3680 if (os::is_MP()) { masm.lock(); }
3681 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3682 // Intention fall-thru into DONE_LABEL
3683
3684
3685 // DONE_LABEL is a hot target - we'd really like to place it at the
3686 // start of cache line by padding with NOPs.
3687 // See the AMD and Intel software optimization manuals for the
3688 // most efficient "long" NOP encodings.
3689 // Unfortunately none of our alignment mechanisms suffice.
3690 if ((EmitSync & 65536) == 0) {
3691 masm.bind (CheckSucc) ;
3692 }
3693 masm.bind(DONE_LABEL);
3694
3695 // Avoid branch to branch on AMD processors
3696 if (EmitSync & 32768) { masm.nop() ; }
3697 }
3698 %}
3699
3700 enc_class enc_String_Compare() %{
3701 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3702 POP_LABEL, DONE_LABEL, CONT_LABEL,
3703 WHILE_HEAD_LABEL;
3704 MacroAssembler masm(&cbuf);
3705
3706 // Get the first character position in both strings
3707 // [8] char array, [12] offset, [16] count
3708 int value_offset = java_lang_String::value_offset_in_bytes();
3709 int offset_offset = java_lang_String::offset_offset_in_bytes();
3710 int count_offset = java_lang_String::count_offset_in_bytes();
3711 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3712
3713 masm.movptr(rax, Address(rsi, value_offset));
3714 masm.movl(rcx, Address(rsi, offset_offset));
3715 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3716 masm.movptr(rbx, Address(rdi, value_offset));
3717 masm.movl(rcx, Address(rdi, offset_offset));
3718 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3719
3720 // Compute the minimum of the string lengths(rsi) and the
3721 // difference of the string lengths (stack)
3722
3723
3724 if (VM_Version::supports_cmov()) {
3725 masm.movl(rdi, Address(rdi, count_offset));
3726 masm.movl(rsi, Address(rsi, count_offset));
3727 masm.movl(rcx, rdi);
3728 masm.subl(rdi, rsi);
3729 masm.push(rdi);
3730 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3731 } else {
3732 masm.movl(rdi, Address(rdi, count_offset));
3733 masm.movl(rcx, Address(rsi, count_offset));
3734 masm.movl(rsi, rdi);
3735 masm.subl(rdi, rcx);
3736 masm.push(rdi);
3737 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL);
3738 masm.movl(rsi, rcx);
3739 // rsi holds min, rcx is unused
3740 }
3741
3742 // Is the minimum length zero?
3743 masm.bind(ECX_GOOD_LABEL);
3744 masm.testl(rsi, rsi);
3745 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3746
3747 // Load first characters
3748 masm.load_unsigned_word(rcx, Address(rbx, 0));
3749 masm.load_unsigned_word(rdi, Address(rax, 0));
3750
3751 // Compare first characters
3752 masm.subl(rcx, rdi);
3753 masm.jcc(Assembler::notZero, POP_LABEL);
3754 masm.decrementl(rsi);
3755 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3756
3757 {
3758 // Check after comparing first character to see if strings are equivalent
3759 Label LSkip2;
3760 // Check if the strings start at same location
3761 masm.cmpptr(rbx,rax);
3762 masm.jcc(Assembler::notEqual, LSkip2);
3763
3764 // Check if the length difference is zero (from stack)
3765 masm.cmpl(Address(rsp, 0), 0x0);
3766 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3767
3768 // Strings might not be equivalent
3769 masm.bind(LSkip2);
3770 }
3771
3772 // Shift rax, and rbx, to the end of the arrays, negate min
3773 masm.lea(rax, Address(rax, rsi, Address::times_2, 2));
3774 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 2));
3775 masm.negl(rsi);
3776
3777 // Compare the rest of the characters
3778 masm.bind(WHILE_HEAD_LABEL);
3779 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3780 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3781 masm.subl(rcx, rdi);
3782 masm.jcc(Assembler::notZero, POP_LABEL);
3783 masm.incrementl(rsi);
3784 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3785
3786 // Strings are equal up to min length. Return the length difference.
3787 masm.bind(LENGTH_DIFF_LABEL);
3788 masm.pop(rcx);
3789 masm.jmp(DONE_LABEL);
3790
3791 // Discard the stored length difference
3792 masm.bind(POP_LABEL);
3793 masm.addptr(rsp, 4);
3794
3795 // That's it
3796 masm.bind(DONE_LABEL);
3797 %}
3798
3799 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{
3800 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP;
3801 MacroAssembler masm(&cbuf);
3802
3803 Register ary1Reg = as_Register($ary1$$reg);
3804 Register ary2Reg = as_Register($ary2$$reg);
3805 Register tmp1Reg = as_Register($tmp1$$reg);
3806 Register tmp2Reg = as_Register($tmp2$$reg);
3807 Register resultReg = as_Register($result$$reg);
3808
3809 int length_offset = arrayOopDesc::length_offset_in_bytes();
3810 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3811
3812 // Check the input args
3813 masm.cmpl(ary1Reg, ary2Reg);
3814 masm.jcc(Assembler::equal, TRUE_LABEL);
3815 masm.testl(ary1Reg, ary1Reg);
3816 masm.jcc(Assembler::zero, FALSE_LABEL);
3817 masm.testl(ary2Reg, ary2Reg);
3818 masm.jcc(Assembler::zero, FALSE_LABEL);
3819
3820 // Check the lengths
3821 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
3822 masm.movl(resultReg, Address(ary2Reg, length_offset));
3823 masm.cmpl(tmp2Reg, resultReg);
3824 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3825 masm.testl(resultReg, resultReg);
3826 masm.jcc(Assembler::zero, TRUE_LABEL);
3827
3828 // Get the number of 4 byte vectors to compare
3829 masm.shrl(resultReg, 1);
3830
3831 // Check for odd-length arrays
3832 masm.andl(tmp2Reg, 1);
3833 masm.testl(tmp2Reg, tmp2Reg);
3834 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR);
3835
3836 // Compare 2-byte "tail" at end of arrays
3837 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3838 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3839 masm.cmpl(tmp1Reg, tmp2Reg);
3840 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3841 masm.testl(resultReg, resultReg);
3842 masm.jcc(Assembler::zero, TRUE_LABEL);
3843
3844 // Setup compare loop
3845 masm.bind(COMPARE_LOOP_HDR);
3846 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays
3847 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset));
3848 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset));
3849 masm.negl(resultReg);
3850
3851 // 4-byte-wide compare loop
3852 masm.bind(COMPARE_LOOP);
3853 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0));
3854 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0));
3855 masm.cmpl(ary1Reg, ary2Reg);
3856 masm.jcc(Assembler::notEqual, FALSE_LABEL);
3857 masm.increment(resultReg);
3858 masm.jcc(Assembler::notZero, COMPARE_LOOP);
3859
3860 masm.bind(TRUE_LABEL);
3861 masm.movl(resultReg, 1); // return true
3862 masm.jmp(DONE_LABEL);
3863
3864 masm.bind(FALSE_LABEL);
3865 masm.xorl(resultReg, resultReg); // return false
3866
3867 // That's it
3868 masm.bind(DONE_LABEL);
3869 %}
3870
3871 enc_class enc_pop_rdx() %{
3872 emit_opcode(cbuf,0x5A);
3873 %}
3874
3875 enc_class enc_rethrow() %{
3876 cbuf.set_inst_mark();
3877 emit_opcode(cbuf, 0xE9); // jmp entry
3878 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
3879 runtime_call_Relocation::spec(), RELOC_IMM32 );
3880 %}
3881
3882
3883 // Convert a double to an int. Java semantics require we do complex
3884 // manglelations in the corner cases. So we set the rounding mode to
3885 // 'zero', store the darned double down as an int, and reset the
3886 // rounding mode to 'nearest'. The hardware throws an exception which
3887 // patches up the correct value directly to the stack.
3888 enc_class D2I_encoding( regD src ) %{
3889 // Flip to round-to-zero mode. We attempted to allow invalid-op
3890 // exceptions here, so that a NAN or other corner-case value will
3891 // thrown an exception (but normal values get converted at full speed).
3892 // However, I2C adapters and other float-stack manglers leave pending
3893 // invalid-op exceptions hanging. We would have to clear them before
3894 // enabling them and that is more expensive than just testing for the
3895 // invalid value Intel stores down in the corner cases.
3896 emit_opcode(cbuf,0xD9); // FLDCW trunc
3897 emit_opcode(cbuf,0x2D);
3898 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3899 // Allocate a word
3900 emit_opcode(cbuf,0x83); // SUB ESP,4
3901 emit_opcode(cbuf,0xEC);
3902 emit_d8(cbuf,0x04);
3903 // Encoding assumes a double has been pushed into FPR0.
3904 // Store down the double as an int, popping the FPU stack
3905 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3906 emit_opcode(cbuf,0x1C);
3907 emit_d8(cbuf,0x24);
3908 // Restore the rounding mode; mask the exception
3909 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3910 emit_opcode(cbuf,0x2D);
3911 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3912 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3913 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3914
3915 // Load the converted int; adjust CPU stack
3916 emit_opcode(cbuf,0x58); // POP EAX
3917 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3918 emit_d32 (cbuf,0x80000000); // 0x80000000
3919 emit_opcode(cbuf,0x75); // JNE around_slow_call
3920 emit_d8 (cbuf,0x07); // Size of slow_call
3921 // Push src onto stack slow-path
3922 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3923 emit_d8 (cbuf,0xC0-1+$src$$reg );
3924 // CALL directly to the runtime
3925 cbuf.set_inst_mark();
3926 emit_opcode(cbuf,0xE8); // Call into runtime
3927 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3928 // Carry on here...
3929 %}
3930
3931 enc_class D2L_encoding( regD src ) %{
3932 emit_opcode(cbuf,0xD9); // FLDCW trunc
3933 emit_opcode(cbuf,0x2D);
3934 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3935 // Allocate a word
3936 emit_opcode(cbuf,0x83); // SUB ESP,8
3937 emit_opcode(cbuf,0xEC);
3938 emit_d8(cbuf,0x08);
3939 // Encoding assumes a double has been pushed into FPR0.
3940 // Store down the double as a long, popping the FPU stack
3941 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3942 emit_opcode(cbuf,0x3C);
3943 emit_d8(cbuf,0x24);
3944 // Restore the rounding mode; mask the exception
3945 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3946 emit_opcode(cbuf,0x2D);
3947 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3948 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3949 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3950
3951 // Load the converted int; adjust CPU stack
3952 emit_opcode(cbuf,0x58); // POP EAX
3953 emit_opcode(cbuf,0x5A); // POP EDX
3954 emit_opcode(cbuf,0x81); // CMP EDX,imm
3955 emit_d8 (cbuf,0xFA); // rdx
3956 emit_d32 (cbuf,0x80000000); // 0x80000000
3957 emit_opcode(cbuf,0x75); // JNE around_slow_call
3958 emit_d8 (cbuf,0x07+4); // Size of slow_call
3959 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3960 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3961 emit_opcode(cbuf,0x75); // JNE around_slow_call
3962 emit_d8 (cbuf,0x07); // Size of slow_call
3963 // Push src onto stack slow-path
3964 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3965 emit_d8 (cbuf,0xC0-1+$src$$reg );
3966 // CALL directly to the runtime
3967 cbuf.set_inst_mark();
3968 emit_opcode(cbuf,0xE8); // Call into runtime
3969 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3970 // Carry on here...
3971 %}
3972
3973 enc_class X2L_encoding( regX src ) %{
3974 // Allocate a word
3975 emit_opcode(cbuf,0x83); // SUB ESP,8
3976 emit_opcode(cbuf,0xEC);
3977 emit_d8(cbuf,0x08);
3978
3979 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
3980 emit_opcode (cbuf, 0x0F );
3981 emit_opcode (cbuf, 0x11 );
3982 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
3983
3984 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
3985 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
3986
3987 emit_opcode(cbuf,0xD9); // FLDCW trunc
3988 emit_opcode(cbuf,0x2D);
3989 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3990
3991 // Encoding assumes a double has been pushed into FPR0.
3992 // Store down the double as a long, popping the FPU stack
3993 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3994 emit_opcode(cbuf,0x3C);
3995 emit_d8(cbuf,0x24);
3996
3997 // Restore the rounding mode; mask the exception
3998 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3999 emit_opcode(cbuf,0x2D);
4000 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4001 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4002 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4003
4004 // Load the converted int; adjust CPU stack
4005 emit_opcode(cbuf,0x58); // POP EAX
4006
4007 emit_opcode(cbuf,0x5A); // POP EDX
4008
4009 emit_opcode(cbuf,0x81); // CMP EDX,imm
4010 emit_d8 (cbuf,0xFA); // rdx
4011 emit_d32 (cbuf,0x80000000);// 0x80000000
4012
4013 emit_opcode(cbuf,0x75); // JNE around_slow_call
4014 emit_d8 (cbuf,0x13+4); // Size of slow_call
4015
4016 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4017 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4018
4019 emit_opcode(cbuf,0x75); // JNE around_slow_call
4020 emit_d8 (cbuf,0x13); // Size of slow_call
4021
4022 // Allocate a word
4023 emit_opcode(cbuf,0x83); // SUB ESP,4
4024 emit_opcode(cbuf,0xEC);
4025 emit_d8(cbuf,0x04);
4026
4027 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4028 emit_opcode (cbuf, 0x0F );
4029 emit_opcode (cbuf, 0x11 );
4030 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4031
4032 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4033 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4034
4035 emit_opcode(cbuf,0x83); // ADD ESP,4
4036 emit_opcode(cbuf,0xC4);
4037 emit_d8(cbuf,0x04);
4038
4039 // CALL directly to the runtime
4040 cbuf.set_inst_mark();
4041 emit_opcode(cbuf,0xE8); // Call into runtime
4042 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4043 // Carry on here...
4044 %}
4045
4046 enc_class XD2L_encoding( regXD src ) %{
4047 // Allocate a word
4048 emit_opcode(cbuf,0x83); // SUB ESP,8
4049 emit_opcode(cbuf,0xEC);
4050 emit_d8(cbuf,0x08);
4051
4052 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4053 emit_opcode (cbuf, 0x0F );
4054 emit_opcode (cbuf, 0x11 );
4055 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4056
4057 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4058 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4059
4060 emit_opcode(cbuf,0xD9); // FLDCW trunc
4061 emit_opcode(cbuf,0x2D);
4062 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4063
4064 // Encoding assumes a double has been pushed into FPR0.
4065 // Store down the double as a long, popping the FPU stack
4066 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4067 emit_opcode(cbuf,0x3C);
4068 emit_d8(cbuf,0x24);
4069
4070 // Restore the rounding mode; mask the exception
4071 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4072 emit_opcode(cbuf,0x2D);
4073 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4074 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4075 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4076
4077 // Load the converted int; adjust CPU stack
4078 emit_opcode(cbuf,0x58); // POP EAX
4079
4080 emit_opcode(cbuf,0x5A); // POP EDX
4081
4082 emit_opcode(cbuf,0x81); // CMP EDX,imm
4083 emit_d8 (cbuf,0xFA); // rdx
4084 emit_d32 (cbuf,0x80000000); // 0x80000000
4085
4086 emit_opcode(cbuf,0x75); // JNE around_slow_call
4087 emit_d8 (cbuf,0x13+4); // Size of slow_call
4088
4089 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4090 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4091
4092 emit_opcode(cbuf,0x75); // JNE around_slow_call
4093 emit_d8 (cbuf,0x13); // Size of slow_call
4094
4095 // Push src onto stack slow-path
4096 // Allocate a word
4097 emit_opcode(cbuf,0x83); // SUB ESP,8
4098 emit_opcode(cbuf,0xEC);
4099 emit_d8(cbuf,0x08);
4100
4101 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4102 emit_opcode (cbuf, 0x0F );
4103 emit_opcode (cbuf, 0x11 );
4104 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4105
4106 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4107 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4108
4109 emit_opcode(cbuf,0x83); // ADD ESP,8
4110 emit_opcode(cbuf,0xC4);
4111 emit_d8(cbuf,0x08);
4112
4113 // CALL directly to the runtime
4114 cbuf.set_inst_mark();
4115 emit_opcode(cbuf,0xE8); // Call into runtime
4116 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4117 // Carry on here...
4118 %}
4119
4120 enc_class D2X_encoding( regX dst, regD src ) %{
4121 // Allocate a word
4122 emit_opcode(cbuf,0x83); // SUB ESP,4
4123 emit_opcode(cbuf,0xEC);
4124 emit_d8(cbuf,0x04);
4125 int pop = 0x02;
4126 if ($src$$reg != FPR1L_enc) {
4127 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4128 emit_d8( cbuf, 0xC0-1+$src$$reg );
4129 pop = 0x03;
4130 }
4131 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4132
4133 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4134 emit_opcode (cbuf, 0x0F );
4135 emit_opcode (cbuf, 0x10 );
4136 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4137
4138 emit_opcode(cbuf,0x83); // ADD ESP,4
4139 emit_opcode(cbuf,0xC4);
4140 emit_d8(cbuf,0x04);
4141 // Carry on here...
4142 %}
4143
4144 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4145 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4146
4147 // Compare the result to see if we need to go to the slow path
4148 emit_opcode(cbuf,0x81); // CMP dst,imm
4149 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4150 emit_d32 (cbuf,0x80000000); // 0x80000000
4151
4152 emit_opcode(cbuf,0x75); // JNE around_slow_call
4153 emit_d8 (cbuf,0x13); // Size of slow_call
4154 // Store xmm to a temp memory
4155 // location and push it onto stack.
4156
4157 emit_opcode(cbuf,0x83); // SUB ESP,4
4158 emit_opcode(cbuf,0xEC);
4159 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4160
4161 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4162 emit_opcode (cbuf, 0x0F );
4163 emit_opcode (cbuf, 0x11 );
4164 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4165
4166 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4167 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4168
4169 emit_opcode(cbuf,0x83); // ADD ESP,4
4170 emit_opcode(cbuf,0xC4);
4171 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4172
4173 // CALL directly to the runtime
4174 cbuf.set_inst_mark();
4175 emit_opcode(cbuf,0xE8); // Call into runtime
4176 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4177
4178 // Carry on here...
4179 %}
4180
4181 enc_class X2D_encoding( regD dst, regX src ) %{
4182 // Allocate a word
4183 emit_opcode(cbuf,0x83); // SUB ESP,4
4184 emit_opcode(cbuf,0xEC);
4185 emit_d8(cbuf,0x04);
4186
4187 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4188 emit_opcode (cbuf, 0x0F );
4189 emit_opcode (cbuf, 0x11 );
4190 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4191
4192 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4193 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4194
4195 emit_opcode(cbuf,0x83); // ADD ESP,4
4196 emit_opcode(cbuf,0xC4);
4197 emit_d8(cbuf,0x04);
4198
4199 // Carry on here...
4200 %}
4201
4202 enc_class AbsXF_encoding(regX dst) %{
4203 address signmask_address=(address)float_signmask_pool;
4204 // andpd:\tANDPS $dst,[signconst]
4205 emit_opcode(cbuf, 0x0F);
4206 emit_opcode(cbuf, 0x54);
4207 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4208 emit_d32(cbuf, (int)signmask_address);
4209 %}
4210
4211 enc_class AbsXD_encoding(regXD dst) %{
4212 address signmask_address=(address)double_signmask_pool;
4213 // andpd:\tANDPD $dst,[signconst]
4214 emit_opcode(cbuf, 0x66);
4215 emit_opcode(cbuf, 0x0F);
4216 emit_opcode(cbuf, 0x54);
4217 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4218 emit_d32(cbuf, (int)signmask_address);
4219 %}
4220
4221 enc_class NegXF_encoding(regX dst) %{
4222 address signmask_address=(address)float_signflip_pool;
4223 // andpd:\tXORPS $dst,[signconst]
4224 emit_opcode(cbuf, 0x0F);
4225 emit_opcode(cbuf, 0x57);
4226 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4227 emit_d32(cbuf, (int)signmask_address);
4228 %}
4229
4230 enc_class NegXD_encoding(regXD dst) %{
4231 address signmask_address=(address)double_signflip_pool;
4232 // andpd:\tXORPD $dst,[signconst]
4233 emit_opcode(cbuf, 0x66);
4234 emit_opcode(cbuf, 0x0F);
4235 emit_opcode(cbuf, 0x57);
4236 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4237 emit_d32(cbuf, (int)signmask_address);
4238 %}
4239
4240 enc_class FMul_ST_reg( eRegF src1 ) %{
4241 // Operand was loaded from memory into fp ST (stack top)
4242 // FMUL ST,$src /* D8 C8+i */
4243 emit_opcode(cbuf, 0xD8);
4244 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4245 %}
4246
4247 enc_class FAdd_ST_reg( eRegF src2 ) %{
4248 // FADDP ST,src2 /* D8 C0+i */
4249 emit_opcode(cbuf, 0xD8);
4250 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4251 //could use FADDP src2,fpST /* DE C0+i */
4252 %}
4253
4254 enc_class FAddP_reg_ST( eRegF src2 ) %{
4255 // FADDP src2,ST /* DE C0+i */
4256 emit_opcode(cbuf, 0xDE);
4257 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4258 %}
4259
4260 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4261 // Operand has been loaded into fp ST (stack top)
4262 // FSUB ST,$src1
4263 emit_opcode(cbuf, 0xD8);
4264 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4265
4266 // FDIV
4267 emit_opcode(cbuf, 0xD8);
4268 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4269 %}
4270
4271 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4272 // Operand was loaded from memory into fp ST (stack top)
4273 // FADD ST,$src /* D8 C0+i */
4274 emit_opcode(cbuf, 0xD8);
4275 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4276
4277 // FMUL ST,src2 /* D8 C*+i */
4278 emit_opcode(cbuf, 0xD8);
4279 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4280 %}
4281
4282
4283 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4284 // Operand was loaded from memory into fp ST (stack top)
4285 // FADD ST,$src /* D8 C0+i */
4286 emit_opcode(cbuf, 0xD8);
4287 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4288
4289 // FMULP src2,ST /* DE C8+i */
4290 emit_opcode(cbuf, 0xDE);
4291 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4292 %}
4293
4294 enc_class enc_membar_acquire %{
4295 // Doug Lea believes this is not needed with current Sparcs and TSO.
4296 // MacroAssembler masm(&cbuf);
4297 // masm.membar();
4298 %}
4299
4300 enc_class enc_membar_release %{
4301 // Doug Lea believes this is not needed with current Sparcs and TSO.
4302 // MacroAssembler masm(&cbuf);
4303 // masm.membar();
4304 %}
4305
4306 enc_class enc_membar_volatile %{
4307 MacroAssembler masm(&cbuf);
4308 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4309 Assembler::StoreStore));
4310 %}
4311
4312 // Atomically load the volatile long
4313 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4314 emit_opcode(cbuf,0xDF);
4315 int rm_byte_opcode = 0x05;
4316 int base = $mem$$base;
4317 int index = $mem$$index;
4318 int scale = $mem$$scale;
4319 int displace = $mem$$disp;
4320 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4321 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4322 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4323 %}
4324
4325 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4326 { // Atomic long load
4327 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4328 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4329 emit_opcode(cbuf,0x0F);
4330 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4331 int base = $mem$$base;
4332 int index = $mem$$index;
4333 int scale = $mem$$scale;
4334 int displace = $mem$$disp;
4335 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4336 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4337 }
4338 { // MOVSD $dst,$tmp ! atomic long store
4339 emit_opcode(cbuf,0xF2);
4340 emit_opcode(cbuf,0x0F);
4341 emit_opcode(cbuf,0x11);
4342 int base = $dst$$base;
4343 int index = $dst$$index;
4344 int scale = $dst$$scale;
4345 int displace = $dst$$disp;
4346 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4347 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4348 }
4349 %}
4350
4351 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4352 { // Atomic long load
4353 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4354 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4355 emit_opcode(cbuf,0x0F);
4356 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4357 int base = $mem$$base;
4358 int index = $mem$$index;
4359 int scale = $mem$$scale;
4360 int displace = $mem$$disp;
4361 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4362 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4363 }
4364 { // MOVD $dst.lo,$tmp
4365 emit_opcode(cbuf,0x66);
4366 emit_opcode(cbuf,0x0F);
4367 emit_opcode(cbuf,0x7E);
4368 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4369 }
4370 { // PSRLQ $tmp,32
4371 emit_opcode(cbuf,0x66);
4372 emit_opcode(cbuf,0x0F);
4373 emit_opcode(cbuf,0x73);
4374 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4375 emit_d8(cbuf, 0x20);
4376 }
4377 { // MOVD $dst.hi,$tmp
4378 emit_opcode(cbuf,0x66);
4379 emit_opcode(cbuf,0x0F);
4380 emit_opcode(cbuf,0x7E);
4381 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4382 }
4383 %}
4384
4385 // Volatile Store Long. Must be atomic, so move it into
4386 // the FP TOS and then do a 64-bit FIST. Has to probe the
4387 // target address before the store (for null-ptr checks)
4388 // so the memory operand is used twice in the encoding.
4389 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4390 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4391 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4392 emit_opcode(cbuf,0xDF);
4393 int rm_byte_opcode = 0x07;
4394 int base = $mem$$base;
4395 int index = $mem$$index;
4396 int scale = $mem$$scale;
4397 int displace = $mem$$disp;
4398 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4399 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4400 %}
4401
4402 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4403 { // Atomic long load
4404 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4405 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4406 emit_opcode(cbuf,0x0F);
4407 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4408 int base = $src$$base;
4409 int index = $src$$index;
4410 int scale = $src$$scale;
4411 int displace = $src$$disp;
4412 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4413 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4414 }
4415 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4416 { // MOVSD $mem,$tmp ! atomic long store
4417 emit_opcode(cbuf,0xF2);
4418 emit_opcode(cbuf,0x0F);
4419 emit_opcode(cbuf,0x11);
4420 int base = $mem$$base;
4421 int index = $mem$$index;
4422 int scale = $mem$$scale;
4423 int displace = $mem$$disp;
4424 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4425 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4426 }
4427 %}
4428
4429 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4430 { // MOVD $tmp,$src.lo
4431 emit_opcode(cbuf,0x66);
4432 emit_opcode(cbuf,0x0F);
4433 emit_opcode(cbuf,0x6E);
4434 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4435 }
4436 { // MOVD $tmp2,$src.hi
4437 emit_opcode(cbuf,0x66);
4438 emit_opcode(cbuf,0x0F);
4439 emit_opcode(cbuf,0x6E);
4440 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4441 }
4442 { // PUNPCKLDQ $tmp,$tmp2
4443 emit_opcode(cbuf,0x66);
4444 emit_opcode(cbuf,0x0F);
4445 emit_opcode(cbuf,0x62);
4446 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4447 }
4448 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4449 { // MOVSD $mem,$tmp ! atomic long store
4450 emit_opcode(cbuf,0xF2);
4451 emit_opcode(cbuf,0x0F);
4452 emit_opcode(cbuf,0x11);
4453 int base = $mem$$base;
4454 int index = $mem$$index;
4455 int scale = $mem$$scale;
4456 int displace = $mem$$disp;
4457 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4458 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4459 }
4460 %}
4461
4462 // Safepoint Poll. This polls the safepoint page, and causes an
4463 // exception if it is not readable. Unfortunately, it kills the condition code
4464 // in the process
4465 // We current use TESTL [spp],EDI
4466 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4467
4468 enc_class Safepoint_Poll() %{
4469 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4470 emit_opcode(cbuf,0x85);
4471 emit_rm (cbuf, 0x0, 0x7, 0x5);
4472 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4473 %}
4474 %}
4475
4476
4477 //----------FRAME--------------------------------------------------------------
4478 // Definition of frame structure and management information.
4479 //
4480 // S T A C K L A Y O U T Allocators stack-slot number
4481 // | (to get allocators register number
4482 // G Owned by | | v add OptoReg::stack0())
4483 // r CALLER | |
4484 // o | +--------+ pad to even-align allocators stack-slot
4485 // w V | pad0 | numbers; owned by CALLER
4486 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4487 // h ^ | in | 5
4488 // | | args | 4 Holes in incoming args owned by SELF
4489 // | | | | 3
4490 // | | +--------+
4491 // V | | old out| Empty on Intel, window on Sparc
4492 // | old |preserve| Must be even aligned.
4493 // | SP-+--------+----> Matcher::_old_SP, even aligned
4494 // | | in | 3 area for Intel ret address
4495 // Owned by |preserve| Empty on Sparc.
4496 // SELF +--------+
4497 // | | pad2 | 2 pad to align old SP
4498 // | +--------+ 1
4499 // | | locks | 0
4500 // | +--------+----> OptoReg::stack0(), even aligned
4501 // | | pad1 | 11 pad to align new SP
4502 // | +--------+
4503 // | | | 10
4504 // | | spills | 9 spills
4505 // V | | 8 (pad0 slot for callee)
4506 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4507 // ^ | out | 7
4508 // | | args | 6 Holes in outgoing args owned by CALLEE
4509 // Owned by +--------+
4510 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4511 // | new |preserve| Must be even-aligned.
4512 // | SP-+--------+----> Matcher::_new_SP, even aligned
4513 // | | |
4514 //
4515 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4516 // known from SELF's arguments and the Java calling convention.
4517 // Region 6-7 is determined per call site.
4518 // Note 2: If the calling convention leaves holes in the incoming argument
4519 // area, those holes are owned by SELF. Holes in the outgoing area
4520 // are owned by the CALLEE. Holes should not be nessecary in the
4521 // incoming area, as the Java calling convention is completely under
4522 // the control of the AD file. Doubles can be sorted and packed to
4523 // avoid holes. Holes in the outgoing arguments may be nessecary for
4524 // varargs C calling conventions.
4525 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4526 // even aligned with pad0 as needed.
4527 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4528 // region 6-11 is even aligned; it may be padded out more so that
4529 // the region from SP to FP meets the minimum stack alignment.
4530
4531 frame %{
4532 // What direction does stack grow in (assumed to be same for C & Java)
4533 stack_direction(TOWARDS_LOW);
4534
4535 // These three registers define part of the calling convention
4536 // between compiled code and the interpreter.
4537 inline_cache_reg(EAX); // Inline Cache Register
4538 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4539
4540 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4541 cisc_spilling_operand_name(indOffset32);
4542
4543 // Number of stack slots consumed by locking an object
4544 sync_stack_slots(1);
4545
4546 // Compiled code's Frame Pointer
4547 frame_pointer(ESP);
4548 // Interpreter stores its frame pointer in a register which is
4549 // stored to the stack by I2CAdaptors.
4550 // I2CAdaptors convert from interpreted java to compiled java.
4551 interpreter_frame_pointer(EBP);
4552
4553 // Stack alignment requirement
4554 // Alignment size in bytes (128-bit -> 16 bytes)
4555 stack_alignment(StackAlignmentInBytes);
4556
4557 // Number of stack slots between incoming argument block and the start of
4558 // a new frame. The PROLOG must add this many slots to the stack. The
4559 // EPILOG must remove this many slots. Intel needs one slot for
4560 // return address and one for rbp, (must save rbp)
4561 in_preserve_stack_slots(2+VerifyStackAtCalls);
4562
4563 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4564 // for calls to C. Supports the var-args backing area for register parms.
4565 varargs_C_out_slots_killed(0);
4566
4567 // The after-PROLOG location of the return address. Location of
4568 // return address specifies a type (REG or STACK) and a number
4569 // representing the register number (i.e. - use a register name) or
4570 // stack slot.
4571 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4572 // Otherwise, it is above the locks and verification slot and alignment word
4573 return_addr(STACK - 1 +
4574 round_to(1+VerifyStackAtCalls+
4575 Compile::current()->fixed_slots(),
4576 (StackAlignmentInBytes/wordSize)));
4577
4578 // Body of function which returns an integer array locating
4579 // arguments either in registers or in stack slots. Passed an array
4580 // of ideal registers called "sig" and a "length" count. Stack-slot
4581 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4582 // arguments for a CALLEE. Incoming stack arguments are
4583 // automatically biased by the preserve_stack_slots field above.
4584 calling_convention %{
4585 // No difference between ingoing/outgoing just pass false
4586 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4587 %}
4588
4589
4590 // Body of function which returns an integer array locating
4591 // arguments either in registers or in stack slots. Passed an array
4592 // of ideal registers called "sig" and a "length" count. Stack-slot
4593 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4594 // arguments for a CALLEE. Incoming stack arguments are
4595 // automatically biased by the preserve_stack_slots field above.
4596 c_calling_convention %{
4597 // This is obviously always outgoing
4598 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4599 %}
4600
4601 // Location of C & interpreter return values
4602 c_return_value %{
4603 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4604 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4605 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4606
4607 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4608 // that C functions return float and double results in XMM0.
4609 if( ideal_reg == Op_RegD && UseSSE>=2 )
4610 return OptoRegPair(XMM0b_num,XMM0a_num);
4611 if( ideal_reg == Op_RegF && UseSSE>=2 )
4612 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4613
4614 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4615 %}
4616
4617 // Location of return values
4618 return_value %{
4619 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4620 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4621 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4622 if( ideal_reg == Op_RegD && UseSSE>=2 )
4623 return OptoRegPair(XMM0b_num,XMM0a_num);
4624 if( ideal_reg == Op_RegF && UseSSE>=1 )
4625 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4626 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4627 %}
4628
4629 %}
4630
4631 //----------ATTRIBUTES---------------------------------------------------------
4632 //----------Operand Attributes-------------------------------------------------
4633 op_attrib op_cost(0); // Required cost attribute
4634
4635 //----------Instruction Attributes---------------------------------------------
4636 ins_attrib ins_cost(100); // Required cost attribute
4637 ins_attrib ins_size(8); // Required size attribute (in bits)
4638 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4639 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4640 // non-matching short branch variant of some
4641 // long branch?
4642 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4643 // specifies the alignment that some part of the instruction (not
4644 // necessarily the start) requires. If > 1, a compute_padding()
4645 // function must be provided for the instruction
4646
4647 //----------OPERANDS-----------------------------------------------------------
4648 // Operand definitions must precede instruction definitions for correct parsing
4649 // in the ADLC because operands constitute user defined types which are used in
4650 // instruction definitions.
4651
4652 //----------Simple Operands----------------------------------------------------
4653 // Immediate Operands
4654 // Integer Immediate
4655 operand immI() %{
4656 match(ConI);
4657
4658 op_cost(10);
4659 format %{ %}
4660 interface(CONST_INTER);
4661 %}
4662
4663 // Constant for test vs zero
4664 operand immI0() %{
4665 predicate(n->get_int() == 0);
4666 match(ConI);
4667
4668 op_cost(0);
4669 format %{ %}
4670 interface(CONST_INTER);
4671 %}
4672
4673 // Constant for increment
4674 operand immI1() %{
4675 predicate(n->get_int() == 1);
4676 match(ConI);
4677
4678 op_cost(0);
4679 format %{ %}
4680 interface(CONST_INTER);
4681 %}
4682
4683 // Constant for decrement
4684 operand immI_M1() %{
4685 predicate(n->get_int() == -1);
4686 match(ConI);
4687
4688 op_cost(0);
4689 format %{ %}
4690 interface(CONST_INTER);
4691 %}
4692
4693 // Valid scale values for addressing modes
4694 operand immI2() %{
4695 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4696 match(ConI);
4697
4698 format %{ %}
4699 interface(CONST_INTER);
4700 %}
4701
4702 operand immI8() %{
4703 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4704 match(ConI);
4705
4706 op_cost(5);
4707 format %{ %}
4708 interface(CONST_INTER);
4709 %}
4710
4711 operand immI16() %{
4712 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4713 match(ConI);
4714
4715 op_cost(10);
4716 format %{ %}
4717 interface(CONST_INTER);
4718 %}
4719
4720 // Constant for long shifts
4721 operand immI_32() %{
4722 predicate( n->get_int() == 32 );
4723 match(ConI);
4724
4725 op_cost(0);
4726 format %{ %}
4727 interface(CONST_INTER);
4728 %}
4729
4730 operand immI_1_31() %{
4731 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
4732 match(ConI);
4733
4734 op_cost(0);
4735 format %{ %}
4736 interface(CONST_INTER);
4737 %}
4738
4739 operand immI_32_63() %{
4740 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
4741 match(ConI);
4742 op_cost(0);
4743
4744 format %{ %}
4745 interface(CONST_INTER);
4746 %}
4747
4748 operand immI_1() %{
4749 predicate( n->get_int() == 1 );
4750 match(ConI);
4751
4752 op_cost(0);
4753 format %{ %}
4754 interface(CONST_INTER);
4755 %}
4756
4757 operand immI_2() %{
4758 predicate( n->get_int() == 2 );
4759 match(ConI);
4760
4761 op_cost(0);
4762 format %{ %}
4763 interface(CONST_INTER);
4764 %}
4765
4766 operand immI_3() %{
4767 predicate( n->get_int() == 3 );
4768 match(ConI);
4769
4770 op_cost(0);
4771 format %{ %}
4772 interface(CONST_INTER);
4773 %}
4774
4775 // Pointer Immediate
4776 operand immP() %{
4777 match(ConP);
4778
4779 op_cost(10);
4780 format %{ %}
4781 interface(CONST_INTER);
4782 %}
4783
4784 // NULL Pointer Immediate
4785 operand immP0() %{
4786 predicate( n->get_ptr() == 0 );
4787 match(ConP);
4788 op_cost(0);
4789
4790 format %{ %}
4791 interface(CONST_INTER);
4792 %}
4793
4794 // Long Immediate
4795 operand immL() %{
4796 match(ConL);
4797
4798 op_cost(20);
4799 format %{ %}
4800 interface(CONST_INTER);
4801 %}
4802
4803 // Long Immediate zero
4804 operand immL0() %{
4805 predicate( n->get_long() == 0L );
4806 match(ConL);
4807 op_cost(0);
4808
4809 format %{ %}
4810 interface(CONST_INTER);
4811 %}
4812
4813 // Long immediate from 0 to 127.
4814 // Used for a shorter form of long mul by 10.
4815 operand immL_127() %{
4816 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4817 match(ConL);
4818 op_cost(0);
4819
4820 format %{ %}
4821 interface(CONST_INTER);
4822 %}
4823
4824 // Long Immediate: low 32-bit mask
4825 operand immL_32bits() %{
4826 predicate(n->get_long() == 0xFFFFFFFFL);
4827 match(ConL);
4828 op_cost(0);
4829
4830 format %{ %}
4831 interface(CONST_INTER);
4832 %}
4833
4834 // Long Immediate: low 32-bit mask
4835 operand immL32() %{
4836 predicate(n->get_long() == (int)(n->get_long()));
4837 match(ConL);
4838 op_cost(20);
4839
4840 format %{ %}
4841 interface(CONST_INTER);
4842 %}
4843
4844 //Double Immediate zero
4845 operand immD0() %{
4846 // Do additional (and counter-intuitive) test against NaN to work around VC++
4847 // bug that generates code such that NaNs compare equal to 0.0
4848 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4849 match(ConD);
4850
4851 op_cost(5);
4852 format %{ %}
4853 interface(CONST_INTER);
4854 %}
4855
4856 // Double Immediate
4857 operand immD1() %{
4858 predicate( UseSSE<=1 && n->getd() == 1.0 );
4859 match(ConD);
4860
4861 op_cost(5);
4862 format %{ %}
4863 interface(CONST_INTER);
4864 %}
4865
4866 // Double Immediate
4867 operand immD() %{
4868 predicate(UseSSE<=1);
4869 match(ConD);
4870
4871 op_cost(5);
4872 format %{ %}
4873 interface(CONST_INTER);
4874 %}
4875
4876 operand immXD() %{
4877 predicate(UseSSE>=2);
4878 match(ConD);
4879
4880 op_cost(5);
4881 format %{ %}
4882 interface(CONST_INTER);
4883 %}
4884
4885 // Double Immediate zero
4886 operand immXD0() %{
4887 // Do additional (and counter-intuitive) test against NaN to work around VC++
4888 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4889 // compare equal to -0.0.
4890 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4891 match(ConD);
4892
4893 format %{ %}
4894 interface(CONST_INTER);
4895 %}
4896
4897 // Float Immediate zero
4898 operand immF0() %{
4899 predicate( UseSSE == 0 && n->getf() == 0.0 );
4900 match(ConF);
4901
4902 op_cost(5);
4903 format %{ %}
4904 interface(CONST_INTER);
4905 %}
4906
4907 // Float Immediate
4908 operand immF() %{
4909 predicate( UseSSE == 0 );
4910 match(ConF);
4911
4912 op_cost(5);
4913 format %{ %}
4914 interface(CONST_INTER);
4915 %}
4916
4917 // Float Immediate
4918 operand immXF() %{
4919 predicate(UseSSE >= 1);
4920 match(ConF);
4921
4922 op_cost(5);
4923 format %{ %}
4924 interface(CONST_INTER);
4925 %}
4926
4927 // Float Immediate zero. Zero and not -0.0
4928 operand immXF0() %{
4929 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4930 match(ConF);
4931
4932 op_cost(5);
4933 format %{ %}
4934 interface(CONST_INTER);
4935 %}
4936
4937 // Immediates for special shifts (sign extend)
4938
4939 // Constants for increment
4940 operand immI_16() %{
4941 predicate( n->get_int() == 16 );
4942 match(ConI);
4943
4944 format %{ %}
4945 interface(CONST_INTER);
4946 %}
4947
4948 operand immI_24() %{
4949 predicate( n->get_int() == 24 );
4950 match(ConI);
4951
4952 format %{ %}
4953 interface(CONST_INTER);
4954 %}
4955
4956 // Constant for byte-wide masking
4957 operand immI_255() %{
4958 predicate( n->get_int() == 255 );
4959 match(ConI);
4960
4961 format %{ %}
4962 interface(CONST_INTER);
4963 %}
4964
4965 // Register Operands
4966 // Integer Register
4967 operand eRegI() %{
4968 constraint(ALLOC_IN_RC(e_reg));
4969 match(RegI);
4970 match(xRegI);
4971 match(eAXRegI);
4972 match(eBXRegI);
4973 match(eCXRegI);
4974 match(eDXRegI);
4975 match(eDIRegI);
4976 match(eSIRegI);
4977
4978 format %{ %}
4979 interface(REG_INTER);
4980 %}
4981
4982 // Subset of Integer Register
4983 operand xRegI(eRegI reg) %{
4984 constraint(ALLOC_IN_RC(x_reg));
4985 match(reg);
4986 match(eAXRegI);
4987 match(eBXRegI);
4988 match(eCXRegI);
4989 match(eDXRegI);
4990
4991 format %{ %}
4992 interface(REG_INTER);
4993 %}
4994
4995 // Special Registers
4996 operand eAXRegI(xRegI reg) %{
4997 constraint(ALLOC_IN_RC(eax_reg));
4998 match(reg);
4999 match(eRegI);
5000
5001 format %{ "EAX" %}
5002 interface(REG_INTER);
5003 %}
5004
5005 // Special Registers
5006 operand eBXRegI(xRegI reg) %{
5007 constraint(ALLOC_IN_RC(ebx_reg));
5008 match(reg);
5009 match(eRegI);
5010
5011 format %{ "EBX" %}
5012 interface(REG_INTER);
5013 %}
5014
5015 operand eCXRegI(xRegI reg) %{
5016 constraint(ALLOC_IN_RC(ecx_reg));
5017 match(reg);
5018 match(eRegI);
5019
5020 format %{ "ECX" %}
5021 interface(REG_INTER);
5022 %}
5023
5024 operand eDXRegI(xRegI reg) %{
5025 constraint(ALLOC_IN_RC(edx_reg));
5026 match(reg);
5027 match(eRegI);
5028
5029 format %{ "EDX" %}
5030 interface(REG_INTER);
5031 %}
5032
5033 operand eDIRegI(xRegI reg) %{
5034 constraint(ALLOC_IN_RC(edi_reg));
5035 match(reg);
5036 match(eRegI);
5037
5038 format %{ "EDI" %}
5039 interface(REG_INTER);
5040 %}
5041
5042 operand naxRegI() %{
5043 constraint(ALLOC_IN_RC(nax_reg));
5044 match(RegI);
5045 match(eCXRegI);
5046 match(eDXRegI);
5047 match(eSIRegI);
5048 match(eDIRegI);
5049
5050 format %{ %}
5051 interface(REG_INTER);
5052 %}
5053
5054 operand nadxRegI() %{
5055 constraint(ALLOC_IN_RC(nadx_reg));
5056 match(RegI);
5057 match(eBXRegI);
5058 match(eCXRegI);
5059 match(eSIRegI);
5060 match(eDIRegI);
5061
5062 format %{ %}
5063 interface(REG_INTER);
5064 %}
5065
5066 operand ncxRegI() %{
5067 constraint(ALLOC_IN_RC(ncx_reg));
5068 match(RegI);
5069 match(eAXRegI);
5070 match(eDXRegI);
5071 match(eSIRegI);
5072 match(eDIRegI);
5073
5074 format %{ %}
5075 interface(REG_INTER);
5076 %}
5077
5078 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5079 // //
5080 operand eSIRegI(xRegI reg) %{
5081 constraint(ALLOC_IN_RC(esi_reg));
5082 match(reg);
5083 match(eRegI);
5084
5085 format %{ "ESI" %}
5086 interface(REG_INTER);
5087 %}
5088
5089 // Pointer Register
5090 operand anyRegP() %{
5091 constraint(ALLOC_IN_RC(any_reg));
5092 match(RegP);
5093 match(eAXRegP);
5094 match(eBXRegP);
5095 match(eCXRegP);
5096 match(eDIRegP);
5097 match(eRegP);
5098
5099 format %{ %}
5100 interface(REG_INTER);
5101 %}
5102
5103 operand eRegP() %{
5104 constraint(ALLOC_IN_RC(e_reg));
5105 match(RegP);
5106 match(eAXRegP);
5107 match(eBXRegP);
5108 match(eCXRegP);
5109 match(eDIRegP);
5110
5111 format %{ %}
5112 interface(REG_INTER);
5113 %}
5114
5115 // On windows95, EBP is not safe to use for implicit null tests.
5116 operand eRegP_no_EBP() %{
5117 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5118 match(RegP);
5119 match(eAXRegP);
5120 match(eBXRegP);
5121 match(eCXRegP);
5122 match(eDIRegP);
5123
5124 op_cost(100);
5125 format %{ %}
5126 interface(REG_INTER);
5127 %}
5128
5129 operand naxRegP() %{
5130 constraint(ALLOC_IN_RC(nax_reg));
5131 match(RegP);
5132 match(eBXRegP);
5133 match(eDXRegP);
5134 match(eCXRegP);
5135 match(eSIRegP);
5136 match(eDIRegP);
5137
5138 format %{ %}
5139 interface(REG_INTER);
5140 %}
5141
5142 operand nabxRegP() %{
5143 constraint(ALLOC_IN_RC(nabx_reg));
5144 match(RegP);
5145 match(eCXRegP);
5146 match(eDXRegP);
5147 match(eSIRegP);
5148 match(eDIRegP);
5149
5150 format %{ %}
5151 interface(REG_INTER);
5152 %}
5153
5154 operand pRegP() %{
5155 constraint(ALLOC_IN_RC(p_reg));
5156 match(RegP);
5157 match(eBXRegP);
5158 match(eDXRegP);
5159 match(eSIRegP);
5160 match(eDIRegP);
5161
5162 format %{ %}
5163 interface(REG_INTER);
5164 %}
5165
5166 // Special Registers
5167 // Return a pointer value
5168 operand eAXRegP(eRegP reg) %{
5169 constraint(ALLOC_IN_RC(eax_reg));
5170 match(reg);
5171 format %{ "EAX" %}
5172 interface(REG_INTER);
5173 %}
5174
5175 // Used in AtomicAdd
5176 operand eBXRegP(eRegP reg) %{
5177 constraint(ALLOC_IN_RC(ebx_reg));
5178 match(reg);
5179 format %{ "EBX" %}
5180 interface(REG_INTER);
5181 %}
5182
5183 // Tail-call (interprocedural jump) to interpreter
5184 operand eCXRegP(eRegP reg) %{
5185 constraint(ALLOC_IN_RC(ecx_reg));
5186 match(reg);
5187 format %{ "ECX" %}
5188 interface(REG_INTER);
5189 %}
5190
5191 operand eSIRegP(eRegP reg) %{
5192 constraint(ALLOC_IN_RC(esi_reg));
5193 match(reg);
5194 format %{ "ESI" %}
5195 interface(REG_INTER);
5196 %}
5197
5198 // Used in rep stosw
5199 operand eDIRegP(eRegP reg) %{
5200 constraint(ALLOC_IN_RC(edi_reg));
5201 match(reg);
5202 format %{ "EDI" %}
5203 interface(REG_INTER);
5204 %}
5205
5206 operand eBPRegP() %{
5207 constraint(ALLOC_IN_RC(ebp_reg));
5208 match(RegP);
5209 format %{ "EBP" %}
5210 interface(REG_INTER);
5211 %}
5212
5213 operand eRegL() %{
5214 constraint(ALLOC_IN_RC(long_reg));
5215 match(RegL);
5216 match(eADXRegL);
5217
5218 format %{ %}
5219 interface(REG_INTER);
5220 %}
5221
5222 operand eADXRegL( eRegL reg ) %{
5223 constraint(ALLOC_IN_RC(eadx_reg));
5224 match(reg);
5225
5226 format %{ "EDX:EAX" %}
5227 interface(REG_INTER);
5228 %}
5229
5230 operand eBCXRegL( eRegL reg ) %{
5231 constraint(ALLOC_IN_RC(ebcx_reg));
5232 match(reg);
5233
5234 format %{ "EBX:ECX" %}
5235 interface(REG_INTER);
5236 %}
5237
5238 // Special case for integer high multiply
5239 operand eADXRegL_low_only() %{
5240 constraint(ALLOC_IN_RC(eadx_reg));
5241 match(RegL);
5242
5243 format %{ "EAX" %}
5244 interface(REG_INTER);
5245 %}
5246
5247 // Flags register, used as output of compare instructions
5248 operand eFlagsReg() %{
5249 constraint(ALLOC_IN_RC(int_flags));
5250 match(RegFlags);
5251
5252 format %{ "EFLAGS" %}
5253 interface(REG_INTER);
5254 %}
5255
5256 // Flags register, used as output of FLOATING POINT compare instructions
5257 operand eFlagsRegU() %{
5258 constraint(ALLOC_IN_RC(int_flags));
5259 match(RegFlags);
5260
5261 format %{ "EFLAGS_U" %}
5262 interface(REG_INTER);
5263 %}
5264
5265 // Condition Code Register used by long compare
5266 operand flagsReg_long_LTGE() %{
5267 constraint(ALLOC_IN_RC(int_flags));
5268 match(RegFlags);
5269 format %{ "FLAGS_LTGE" %}
5270 interface(REG_INTER);
5271 %}
5272 operand flagsReg_long_EQNE() %{
5273 constraint(ALLOC_IN_RC(int_flags));
5274 match(RegFlags);
5275 format %{ "FLAGS_EQNE" %}
5276 interface(REG_INTER);
5277 %}
5278 operand flagsReg_long_LEGT() %{
5279 constraint(ALLOC_IN_RC(int_flags));
5280 match(RegFlags);
5281 format %{ "FLAGS_LEGT" %}
5282 interface(REG_INTER);
5283 %}
5284
5285 // Float register operands
5286 operand regD() %{
5287 predicate( UseSSE < 2 );
5288 constraint(ALLOC_IN_RC(dbl_reg));
5289 match(RegD);
5290 match(regDPR1);
5291 match(regDPR2);
5292 format %{ %}
5293 interface(REG_INTER);
5294 %}
5295
5296 operand regDPR1(regD reg) %{
5297 predicate( UseSSE < 2 );
5298 constraint(ALLOC_IN_RC(dbl_reg0));
5299 match(reg);
5300 format %{ "FPR1" %}
5301 interface(REG_INTER);
5302 %}
5303
5304 operand regDPR2(regD reg) %{
5305 predicate( UseSSE < 2 );
5306 constraint(ALLOC_IN_RC(dbl_reg1));
5307 match(reg);
5308 format %{ "FPR2" %}
5309 interface(REG_INTER);
5310 %}
5311
5312 operand regnotDPR1(regD reg) %{
5313 predicate( UseSSE < 2 );
5314 constraint(ALLOC_IN_RC(dbl_notreg0));
5315 match(reg);
5316 format %{ %}
5317 interface(REG_INTER);
5318 %}
5319
5320 // XMM Double register operands
5321 operand regXD() %{
5322 predicate( UseSSE>=2 );
5323 constraint(ALLOC_IN_RC(xdb_reg));
5324 match(RegD);
5325 match(regXD6);
5326 match(regXD7);
5327 format %{ %}
5328 interface(REG_INTER);
5329 %}
5330
5331 // XMM6 double register operands
5332 operand regXD6(regXD reg) %{
5333 predicate( UseSSE>=2 );
5334 constraint(ALLOC_IN_RC(xdb_reg6));
5335 match(reg);
5336 format %{ "XMM6" %}
5337 interface(REG_INTER);
5338 %}
5339
5340 // XMM7 double register operands
5341 operand regXD7(regXD reg) %{
5342 predicate( UseSSE>=2 );
5343 constraint(ALLOC_IN_RC(xdb_reg7));
5344 match(reg);
5345 format %{ "XMM7" %}
5346 interface(REG_INTER);
5347 %}
5348
5349 // Float register operands
5350 operand regF() %{
5351 predicate( UseSSE < 2 );
5352 constraint(ALLOC_IN_RC(flt_reg));
5353 match(RegF);
5354 match(regFPR1);
5355 format %{ %}
5356 interface(REG_INTER);
5357 %}
5358
5359 // Float register operands
5360 operand regFPR1(regF reg) %{
5361 predicate( UseSSE < 2 );
5362 constraint(ALLOC_IN_RC(flt_reg0));
5363 match(reg);
5364 format %{ "FPR1" %}
5365 interface(REG_INTER);
5366 %}
5367
5368 // XMM register operands
5369 operand regX() %{
5370 predicate( UseSSE>=1 );
5371 constraint(ALLOC_IN_RC(xmm_reg));
5372 match(RegF);
5373 format %{ %}
5374 interface(REG_INTER);
5375 %}
5376
5377
5378 //----------Memory Operands----------------------------------------------------
5379 // Direct Memory Operand
5380 operand direct(immP addr) %{
5381 match(addr);
5382
5383 format %{ "[$addr]" %}
5384 interface(MEMORY_INTER) %{
5385 base(0xFFFFFFFF);
5386 index(0x4);
5387 scale(0x0);
5388 disp($addr);
5389 %}
5390 %}
5391
5392 // Indirect Memory Operand
5393 operand indirect(eRegP reg) %{
5394 constraint(ALLOC_IN_RC(e_reg));
5395 match(reg);
5396
5397 format %{ "[$reg]" %}
5398 interface(MEMORY_INTER) %{
5399 base($reg);
5400 index(0x4);
5401 scale(0x0);
5402 disp(0x0);
5403 %}
5404 %}
5405
5406 // Indirect Memory Plus Short Offset Operand
5407 operand indOffset8(eRegP reg, immI8 off) %{
5408 match(AddP reg off);
5409
5410 format %{ "[$reg + $off]" %}
5411 interface(MEMORY_INTER) %{
5412 base($reg);
5413 index(0x4);
5414 scale(0x0);
5415 disp($off);
5416 %}
5417 %}
5418
5419 // Indirect Memory Plus Long Offset Operand
5420 operand indOffset32(eRegP reg, immI off) %{
5421 match(AddP reg off);
5422
5423 format %{ "[$reg + $off]" %}
5424 interface(MEMORY_INTER) %{
5425 base($reg);
5426 index(0x4);
5427 scale(0x0);
5428 disp($off);
5429 %}
5430 %}
5431
5432 // Indirect Memory Plus Long Offset Operand
5433 operand indOffset32X(eRegI reg, immP off) %{
5434 match(AddP off reg);
5435
5436 format %{ "[$reg + $off]" %}
5437 interface(MEMORY_INTER) %{
5438 base($reg);
5439 index(0x4);
5440 scale(0x0);
5441 disp($off);
5442 %}
5443 %}
5444
5445 // Indirect Memory Plus Index Register Plus Offset Operand
5446 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5447 match(AddP (AddP reg ireg) off);
5448
5449 op_cost(10);
5450 format %{"[$reg + $off + $ireg]" %}
5451 interface(MEMORY_INTER) %{
5452 base($reg);
5453 index($ireg);
5454 scale(0x0);
5455 disp($off);
5456 %}
5457 %}
5458
5459 // Indirect Memory Plus Index Register Plus Offset Operand
5460 operand indIndex(eRegP reg, eRegI ireg) %{
5461 match(AddP reg ireg);
5462
5463 op_cost(10);
5464 format %{"[$reg + $ireg]" %}
5465 interface(MEMORY_INTER) %{
5466 base($reg);
5467 index($ireg);
5468 scale(0x0);
5469 disp(0x0);
5470 %}
5471 %}
5472
5473 // // -------------------------------------------------------------------------
5474 // // 486 architecture doesn't support "scale * index + offset" with out a base
5475 // // -------------------------------------------------------------------------
5476 // // Scaled Memory Operands
5477 // // Indirect Memory Times Scale Plus Offset Operand
5478 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5479 // match(AddP off (LShiftI ireg scale));
5480 //
5481 // op_cost(10);
5482 // format %{"[$off + $ireg << $scale]" %}
5483 // interface(MEMORY_INTER) %{
5484 // base(0x4);
5485 // index($ireg);
5486 // scale($scale);
5487 // disp($off);
5488 // %}
5489 // %}
5490
5491 // Indirect Memory Times Scale Plus Index Register
5492 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5493 match(AddP reg (LShiftI ireg scale));
5494
5495 op_cost(10);
5496 format %{"[$reg + $ireg << $scale]" %}
5497 interface(MEMORY_INTER) %{
5498 base($reg);
5499 index($ireg);
5500 scale($scale);
5501 disp(0x0);
5502 %}
5503 %}
5504
5505 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5506 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5507 match(AddP (AddP reg (LShiftI ireg scale)) off);
5508
5509 op_cost(10);
5510 format %{"[$reg + $off + $ireg << $scale]" %}
5511 interface(MEMORY_INTER) %{
5512 base($reg);
5513 index($ireg);
5514 scale($scale);
5515 disp($off);
5516 %}
5517 %}
5518
5519 //----------Load Long Memory Operands------------------------------------------
5520 // The load-long idiom will use it's address expression again after loading
5521 // the first word of the long. If the load-long destination overlaps with
5522 // registers used in the addressing expression, the 2nd half will be loaded
5523 // from a clobbered address. Fix this by requiring that load-long use
5524 // address registers that do not overlap with the load-long target.
5525
5526 // load-long support
5527 operand load_long_RegP() %{
5528 constraint(ALLOC_IN_RC(esi_reg));
5529 match(RegP);
5530 match(eSIRegP);
5531 op_cost(100);
5532 format %{ %}
5533 interface(REG_INTER);
5534 %}
5535
5536 // Indirect Memory Operand Long
5537 operand load_long_indirect(load_long_RegP reg) %{
5538 constraint(ALLOC_IN_RC(esi_reg));
5539 match(reg);
5540
5541 format %{ "[$reg]" %}
5542 interface(MEMORY_INTER) %{
5543 base($reg);
5544 index(0x4);
5545 scale(0x0);
5546 disp(0x0);
5547 %}
5548 %}
5549
5550 // Indirect Memory Plus Long Offset Operand
5551 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5552 match(AddP reg off);
5553
5554 format %{ "[$reg + $off]" %}
5555 interface(MEMORY_INTER) %{
5556 base($reg);
5557 index(0x4);
5558 scale(0x0);
5559 disp($off);
5560 %}
5561 %}
5562
5563 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5564
5565
5566 //----------Special Memory Operands--------------------------------------------
5567 // Stack Slot Operand - This operand is used for loading and storing temporary
5568 // values on the stack where a match requires a value to
5569 // flow through memory.
5570 operand stackSlotP(sRegP reg) %{
5571 constraint(ALLOC_IN_RC(stack_slots));
5572 // No match rule because this operand is only generated in matching
5573 format %{ "[$reg]" %}
5574 interface(MEMORY_INTER) %{
5575 base(0x4); // ESP
5576 index(0x4); // No Index
5577 scale(0x0); // No Scale
5578 disp($reg); // Stack Offset
5579 %}
5580 %}
5581
5582 operand stackSlotI(sRegI reg) %{
5583 constraint(ALLOC_IN_RC(stack_slots));
5584 // No match rule because this operand is only generated in matching
5585 format %{ "[$reg]" %}
5586 interface(MEMORY_INTER) %{
5587 base(0x4); // ESP
5588 index(0x4); // No Index
5589 scale(0x0); // No Scale
5590 disp($reg); // Stack Offset
5591 %}
5592 %}
5593
5594 operand stackSlotF(sRegF reg) %{
5595 constraint(ALLOC_IN_RC(stack_slots));
5596 // No match rule because this operand is only generated in matching
5597 format %{ "[$reg]" %}
5598 interface(MEMORY_INTER) %{
5599 base(0x4); // ESP
5600 index(0x4); // No Index
5601 scale(0x0); // No Scale
5602 disp($reg); // Stack Offset
5603 %}
5604 %}
5605
5606 operand stackSlotD(sRegD reg) %{
5607 constraint(ALLOC_IN_RC(stack_slots));
5608 // No match rule because this operand is only generated in matching
5609 format %{ "[$reg]" %}
5610 interface(MEMORY_INTER) %{
5611 base(0x4); // ESP
5612 index(0x4); // No Index
5613 scale(0x0); // No Scale
5614 disp($reg); // Stack Offset
5615 %}
5616 %}
5617
5618 operand stackSlotL(sRegL reg) %{
5619 constraint(ALLOC_IN_RC(stack_slots));
5620 // No match rule because this operand is only generated in matching
5621 format %{ "[$reg]" %}
5622 interface(MEMORY_INTER) %{
5623 base(0x4); // ESP
5624 index(0x4); // No Index
5625 scale(0x0); // No Scale
5626 disp($reg); // Stack Offset
5627 %}
5628 %}
5629
5630 //----------Memory Operands - Win95 Implicit Null Variants----------------
5631 // Indirect Memory Operand
5632 operand indirect_win95_safe(eRegP_no_EBP reg)
5633 %{
5634 constraint(ALLOC_IN_RC(e_reg));
5635 match(reg);
5636
5637 op_cost(100);
5638 format %{ "[$reg]" %}
5639 interface(MEMORY_INTER) %{
5640 base($reg);
5641 index(0x4);
5642 scale(0x0);
5643 disp(0x0);
5644 %}
5645 %}
5646
5647 // Indirect Memory Plus Short Offset Operand
5648 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5649 %{
5650 match(AddP reg off);
5651
5652 op_cost(100);
5653 format %{ "[$reg + $off]" %}
5654 interface(MEMORY_INTER) %{
5655 base($reg);
5656 index(0x4);
5657 scale(0x0);
5658 disp($off);
5659 %}
5660 %}
5661
5662 // Indirect Memory Plus Long Offset Operand
5663 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5664 %{
5665 match(AddP reg off);
5666
5667 op_cost(100);
5668 format %{ "[$reg + $off]" %}
5669 interface(MEMORY_INTER) %{
5670 base($reg);
5671 index(0x4);
5672 scale(0x0);
5673 disp($off);
5674 %}
5675 %}
5676
5677 // Indirect Memory Plus Index Register Plus Offset Operand
5678 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5679 %{
5680 match(AddP (AddP reg ireg) off);
5681
5682 op_cost(100);
5683 format %{"[$reg + $off + $ireg]" %}
5684 interface(MEMORY_INTER) %{
5685 base($reg);
5686 index($ireg);
5687 scale(0x0);
5688 disp($off);
5689 %}
5690 %}
5691
5692 // Indirect Memory Times Scale Plus Index Register
5693 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5694 %{
5695 match(AddP reg (LShiftI ireg scale));
5696
5697 op_cost(100);
5698 format %{"[$reg + $ireg << $scale]" %}
5699 interface(MEMORY_INTER) %{
5700 base($reg);
5701 index($ireg);
5702 scale($scale);
5703 disp(0x0);
5704 %}
5705 %}
5706
5707 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5708 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
5709 %{
5710 match(AddP (AddP reg (LShiftI ireg scale)) off);
5711
5712 op_cost(100);
5713 format %{"[$reg + $off + $ireg << $scale]" %}
5714 interface(MEMORY_INTER) %{
5715 base($reg);
5716 index($ireg);
5717 scale($scale);
5718 disp($off);
5719 %}
5720 %}
5721
5722 //----------Conditional Branch Operands----------------------------------------
5723 // Comparison Op - This is the operation of the comparison, and is limited to
5724 // the following set of codes:
5725 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5726 //
5727 // Other attributes of the comparison, such as unsignedness, are specified
5728 // by the comparison instruction that sets a condition code flags register.
5729 // That result is represented by a flags operand whose subtype is appropriate
5730 // to the unsignedness (etc.) of the comparison.
5731 //
5732 // Later, the instruction which matches both the Comparison Op (a Bool) and
5733 // the flags (produced by the Cmp) specifies the coding of the comparison op
5734 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5735
5736 // Comparision Code
5737 operand cmpOp() %{
5738 match(Bool);
5739
5740 format %{ "" %}
5741 interface(COND_INTER) %{
5742 equal(0x4);
5743 not_equal(0x5);
5744 less(0xC);
5745 greater_equal(0xD);
5746 less_equal(0xE);
5747 greater(0xF);
5748 %}
5749 %}
5750
5751 // Comparison Code, unsigned compare. Used by FP also, with
5752 // C2 (unordered) turned into GT or LT already. The other bits
5753 // C0 and C3 are turned into Carry & Zero flags.
5754 operand cmpOpU() %{
5755 match(Bool);
5756
5757 format %{ "" %}
5758 interface(COND_INTER) %{
5759 equal(0x4);
5760 not_equal(0x5);
5761 less(0x2);
5762 greater_equal(0x3);
5763 less_equal(0x6);
5764 greater(0x7);
5765 %}
5766 %}
5767
5768 // Comparison Code for FP conditional move
5769 operand cmpOp_fcmov() %{
5770 match(Bool);
5771
5772 format %{ "" %}
5773 interface(COND_INTER) %{
5774 equal (0x0C8);
5775 not_equal (0x1C8);
5776 less (0x0C0);
5777 greater_equal(0x1C0);
5778 less_equal (0x0D0);
5779 greater (0x1D0);
5780 %}
5781 %}
5782
5783 // Comparision Code used in long compares
5784 operand cmpOp_commute() %{
5785 match(Bool);
5786
5787 format %{ "" %}
5788 interface(COND_INTER) %{
5789 equal(0x4);
5790 not_equal(0x5);
5791 less(0xF);
5792 greater_equal(0xE);
5793 less_equal(0xD);
5794 greater(0xC);
5795 %}
5796 %}
5797
5798 //----------OPERAND CLASSES----------------------------------------------------
5799 // Operand Classes are groups of operands that are used as to simplify
5800 // instruction definitions by not requiring the AD writer to specify seperate
5801 // instructions for every form of operand when the instruction accepts
5802 // multiple operand types with the same basic encoding and format. The classic
5803 // case of this is memory operands.
5804
5805 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5806 indIndex, indIndexScale, indIndexScaleOffset);
5807
5808 // Long memory operations are encoded in 2 instructions and a +4 offset.
5809 // This means some kind of offset is always required and you cannot use
5810 // an oop as the offset (done when working on static globals).
5811 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5812 indIndex, indIndexScale, indIndexScaleOffset);
5813
5814
5815 //----------PIPELINE-----------------------------------------------------------
5816 // Rules which define the behavior of the target architectures pipeline.
5817 pipeline %{
5818
5819 //----------ATTRIBUTES---------------------------------------------------------
5820 attributes %{
5821 variable_size_instructions; // Fixed size instructions
5822 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5823 instruction_unit_size = 1; // An instruction is 1 bytes long
5824 instruction_fetch_unit_size = 16; // The processor fetches one line
5825 instruction_fetch_units = 1; // of 16 bytes
5826
5827 // List of nop instructions
5828 nops( MachNop );
5829 %}
5830
5831 //----------RESOURCES----------------------------------------------------------
5832 // Resources are the functional units available to the machine
5833
5834 // Generic P2/P3 pipeline
5835 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5836 // 3 instructions decoded per cycle.
5837 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5838 // 2 ALU op, only ALU0 handles mul/div instructions.
5839 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5840 MS0, MS1, MEM = MS0 | MS1,
5841 BR, FPU,
5842 ALU0, ALU1, ALU = ALU0 | ALU1 );
5843
5844 //----------PIPELINE DESCRIPTION-----------------------------------------------
5845 // Pipeline Description specifies the stages in the machine's pipeline
5846
5847 // Generic P2/P3 pipeline
5848 pipe_desc(S0, S1, S2, S3, S4, S5);
5849
5850 //----------PIPELINE CLASSES---------------------------------------------------
5851 // Pipeline Classes describe the stages in which input and output are
5852 // referenced by the hardware pipeline.
5853
5854 // Naming convention: ialu or fpu
5855 // Then: _reg
5856 // Then: _reg if there is a 2nd register
5857 // Then: _long if it's a pair of instructions implementing a long
5858 // Then: _fat if it requires the big decoder
5859 // Or: _mem if it requires the big decoder and a memory unit.
5860
5861 // Integer ALU reg operation
5862 pipe_class ialu_reg(eRegI dst) %{
5863 single_instruction;
5864 dst : S4(write);
5865 dst : S3(read);
5866 DECODE : S0; // any decoder
5867 ALU : S3; // any alu
5868 %}
5869
5870 // Long ALU reg operation
5871 pipe_class ialu_reg_long(eRegL dst) %{
5872 instruction_count(2);
5873 dst : S4(write);
5874 dst : S3(read);
5875 DECODE : S0(2); // any 2 decoders
5876 ALU : S3(2); // both alus
5877 %}
5878
5879 // Integer ALU reg operation using big decoder
5880 pipe_class ialu_reg_fat(eRegI dst) %{
5881 single_instruction;
5882 dst : S4(write);
5883 dst : S3(read);
5884 D0 : S0; // big decoder only
5885 ALU : S3; // any alu
5886 %}
5887
5888 // Long ALU reg operation using big decoder
5889 pipe_class ialu_reg_long_fat(eRegL dst) %{
5890 instruction_count(2);
5891 dst : S4(write);
5892 dst : S3(read);
5893 D0 : S0(2); // big decoder only; twice
5894 ALU : S3(2); // any 2 alus
5895 %}
5896
5897 // Integer ALU reg-reg operation
5898 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
5899 single_instruction;
5900 dst : S4(write);
5901 src : S3(read);
5902 DECODE : S0; // any decoder
5903 ALU : S3; // any alu
5904 %}
5905
5906 // Long ALU reg-reg operation
5907 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5908 instruction_count(2);
5909 dst : S4(write);
5910 src : S3(read);
5911 DECODE : S0(2); // any 2 decoders
5912 ALU : S3(2); // both alus
5913 %}
5914
5915 // Integer ALU reg-reg operation
5916 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
5917 single_instruction;
5918 dst : S4(write);
5919 src : S3(read);
5920 D0 : S0; // big decoder only
5921 ALU : S3; // any alu
5922 %}
5923
5924 // Long ALU reg-reg operation
5925 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5926 instruction_count(2);
5927 dst : S4(write);
5928 src : S3(read);
5929 D0 : S0(2); // big decoder only; twice
5930 ALU : S3(2); // both alus
5931 %}
5932
5933 // Integer ALU reg-mem operation
5934 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
5935 single_instruction;
5936 dst : S5(write);
5937 mem : S3(read);
5938 D0 : S0; // big decoder only
5939 ALU : S4; // any alu
5940 MEM : S3; // any mem
5941 %}
5942
5943 // Long ALU reg-mem operation
5944 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5945 instruction_count(2);
5946 dst : S5(write);
5947 mem : S3(read);
5948 D0 : S0(2); // big decoder only; twice
5949 ALU : S4(2); // any 2 alus
5950 MEM : S3(2); // both mems
5951 %}
5952
5953 // Integer mem operation (prefetch)
5954 pipe_class ialu_mem(memory mem)
5955 %{
5956 single_instruction;
5957 mem : S3(read);
5958 D0 : S0; // big decoder only
5959 MEM : S3; // any mem
5960 %}
5961
5962 // Integer Store to Memory
5963 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
5964 single_instruction;
5965 mem : S3(read);
5966 src : S5(read);
5967 D0 : S0; // big decoder only
5968 ALU : S4; // any alu
5969 MEM : S3;
5970 %}
5971
5972 // Long Store to Memory
5973 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5974 instruction_count(2);
5975 mem : S3(read);
5976 src : S5(read);
5977 D0 : S0(2); // big decoder only; twice
5978 ALU : S4(2); // any 2 alus
5979 MEM : S3(2); // Both mems
5980 %}
5981
5982 // Integer Store to Memory
5983 pipe_class ialu_mem_imm(memory mem) %{
5984 single_instruction;
5985 mem : S3(read);
5986 D0 : S0; // big decoder only
5987 ALU : S4; // any alu
5988 MEM : S3;
5989 %}
5990
5991 // Integer ALU0 reg-reg operation
5992 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
5993 single_instruction;
5994 dst : S4(write);
5995 src : S3(read);
5996 D0 : S0; // Big decoder only
5997 ALU0 : S3; // only alu0
5998 %}
5999
6000 // Integer ALU0 reg-mem operation
6001 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6002 single_instruction;
6003 dst : S5(write);
6004 mem : S3(read);
6005 D0 : S0; // big decoder only
6006 ALU0 : S4; // ALU0 only
6007 MEM : S3; // any mem
6008 %}
6009
6010 // Integer ALU reg-reg operation
6011 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6012 single_instruction;
6013 cr : S4(write);
6014 src1 : S3(read);
6015 src2 : S3(read);
6016 DECODE : S0; // any decoder
6017 ALU : S3; // any alu
6018 %}
6019
6020 // Integer ALU reg-imm operation
6021 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6022 single_instruction;
6023 cr : S4(write);
6024 src1 : S3(read);
6025 DECODE : S0; // any decoder
6026 ALU : S3; // any alu
6027 %}
6028
6029 // Integer ALU reg-mem operation
6030 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6031 single_instruction;
6032 cr : S4(write);
6033 src1 : S3(read);
6034 src2 : S3(read);
6035 D0 : S0; // big decoder only
6036 ALU : S4; // any alu
6037 MEM : S3;
6038 %}
6039
6040 // Conditional move reg-reg
6041 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6042 instruction_count(4);
6043 y : S4(read);
6044 q : S3(read);
6045 p : S3(read);
6046 DECODE : S0(4); // any decoder
6047 %}
6048
6049 // Conditional move reg-reg
6050 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6051 single_instruction;
6052 dst : S4(write);
6053 src : S3(read);
6054 cr : S3(read);
6055 DECODE : S0; // any decoder
6056 %}
6057
6058 // Conditional move reg-mem
6059 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6060 single_instruction;
6061 dst : S4(write);
6062 src : S3(read);
6063 cr : S3(read);
6064 DECODE : S0; // any decoder
6065 MEM : S3;
6066 %}
6067
6068 // Conditional move reg-reg long
6069 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6070 single_instruction;
6071 dst : S4(write);
6072 src : S3(read);
6073 cr : S3(read);
6074 DECODE : S0(2); // any 2 decoders
6075 %}
6076
6077 // Conditional move double reg-reg
6078 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6079 single_instruction;
6080 dst : S4(write);
6081 src : S3(read);
6082 cr : S3(read);
6083 DECODE : S0; // any decoder
6084 %}
6085
6086 // Float reg-reg operation
6087 pipe_class fpu_reg(regD dst) %{
6088 instruction_count(2);
6089 dst : S3(read);
6090 DECODE : S0(2); // any 2 decoders
6091 FPU : S3;
6092 %}
6093
6094 // Float reg-reg operation
6095 pipe_class fpu_reg_reg(regD dst, regD src) %{
6096 instruction_count(2);
6097 dst : S4(write);
6098 src : S3(read);
6099 DECODE : S0(2); // any 2 decoders
6100 FPU : S3;
6101 %}
6102
6103 // Float reg-reg operation
6104 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6105 instruction_count(3);
6106 dst : S4(write);
6107 src1 : S3(read);
6108 src2 : S3(read);
6109 DECODE : S0(3); // any 3 decoders
6110 FPU : S3(2);
6111 %}
6112
6113 // Float reg-reg operation
6114 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6115 instruction_count(4);
6116 dst : S4(write);
6117 src1 : S3(read);
6118 src2 : S3(read);
6119 src3 : S3(read);
6120 DECODE : S0(4); // any 3 decoders
6121 FPU : S3(2);
6122 %}
6123
6124 // Float reg-reg operation
6125 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6126 instruction_count(4);
6127 dst : S4(write);
6128 src1 : S3(read);
6129 src2 : S3(read);
6130 src3 : S3(read);
6131 DECODE : S1(3); // any 3 decoders
6132 D0 : S0; // Big decoder only
6133 FPU : S3(2);
6134 MEM : S3;
6135 %}
6136
6137 // Float reg-mem operation
6138 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6139 instruction_count(2);
6140 dst : S5(write);
6141 mem : S3(read);
6142 D0 : S0; // big decoder only
6143 DECODE : S1; // any decoder for FPU POP
6144 FPU : S4;
6145 MEM : S3; // any mem
6146 %}
6147
6148 // Float reg-mem operation
6149 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6150 instruction_count(3);
6151 dst : S5(write);
6152 src1 : S3(read);
6153 mem : S3(read);
6154 D0 : S0; // big decoder only
6155 DECODE : S1(2); // any decoder for FPU POP
6156 FPU : S4;
6157 MEM : S3; // any mem
6158 %}
6159
6160 // Float mem-reg operation
6161 pipe_class fpu_mem_reg(memory mem, regD src) %{
6162 instruction_count(2);
6163 src : S5(read);
6164 mem : S3(read);
6165 DECODE : S0; // any decoder for FPU PUSH
6166 D0 : S1; // big decoder only
6167 FPU : S4;
6168 MEM : S3; // any mem
6169 %}
6170
6171 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6172 instruction_count(3);
6173 src1 : S3(read);
6174 src2 : S3(read);
6175 mem : S3(read);
6176 DECODE : S0(2); // any decoder for FPU PUSH
6177 D0 : S1; // big decoder only
6178 FPU : S4;
6179 MEM : S3; // any mem
6180 %}
6181
6182 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6183 instruction_count(3);
6184 src1 : S3(read);
6185 src2 : S3(read);
6186 mem : S4(read);
6187 DECODE : S0; // any decoder for FPU PUSH
6188 D0 : S0(2); // big decoder only
6189 FPU : S4;
6190 MEM : S3(2); // any mem
6191 %}
6192
6193 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6194 instruction_count(2);
6195 src1 : S3(read);
6196 dst : S4(read);
6197 D0 : S0(2); // big decoder only
6198 MEM : S3(2); // any mem
6199 %}
6200
6201 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6202 instruction_count(3);
6203 src1 : S3(read);
6204 src2 : S3(read);
6205 dst : S4(read);
6206 D0 : S0(3); // big decoder only
6207 FPU : S4;
6208 MEM : S3(3); // any mem
6209 %}
6210
6211 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6212 instruction_count(3);
6213 src1 : S4(read);
6214 mem : S4(read);
6215 DECODE : S0; // any decoder for FPU PUSH
6216 D0 : S0(2); // big decoder only
6217 FPU : S4;
6218 MEM : S3(2); // any mem
6219 %}
6220
6221 // Float load constant
6222 pipe_class fpu_reg_con(regD dst) %{
6223 instruction_count(2);
6224 dst : S5(write);
6225 D0 : S0; // big decoder only for the load
6226 DECODE : S1; // any decoder for FPU POP
6227 FPU : S4;
6228 MEM : S3; // any mem
6229 %}
6230
6231 // Float load constant
6232 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6233 instruction_count(3);
6234 dst : S5(write);
6235 src : S3(read);
6236 D0 : S0; // big decoder only for the load
6237 DECODE : S1(2); // any decoder for FPU POP
6238 FPU : S4;
6239 MEM : S3; // any mem
6240 %}
6241
6242 // UnConditional branch
6243 pipe_class pipe_jmp( label labl ) %{
6244 single_instruction;
6245 BR : S3;
6246 %}
6247
6248 // Conditional branch
6249 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6250 single_instruction;
6251 cr : S1(read);
6252 BR : S3;
6253 %}
6254
6255 // Allocation idiom
6256 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6257 instruction_count(1); force_serialization;
6258 fixed_latency(6);
6259 heap_ptr : S3(read);
6260 DECODE : S0(3);
6261 D0 : S2;
6262 MEM : S3;
6263 ALU : S3(2);
6264 dst : S5(write);
6265 BR : S5;
6266 %}
6267
6268 // Generic big/slow expanded idiom
6269 pipe_class pipe_slow( ) %{
6270 instruction_count(10); multiple_bundles; force_serialization;
6271 fixed_latency(100);
6272 D0 : S0(2);
6273 MEM : S3(2);
6274 %}
6275
6276 // The real do-nothing guy
6277 pipe_class empty( ) %{
6278 instruction_count(0);
6279 %}
6280
6281 // Define the class for the Nop node
6282 define %{
6283 MachNop = empty;
6284 %}
6285
6286 %}
6287
6288 //----------INSTRUCTIONS-------------------------------------------------------
6289 //
6290 // match -- States which machine-independent subtree may be replaced
6291 // by this instruction.
6292 // ins_cost -- The estimated cost of this instruction is used by instruction
6293 // selection to identify a minimum cost tree of machine
6294 // instructions that matches a tree of machine-independent
6295 // instructions.
6296 // format -- A string providing the disassembly for this instruction.
6297 // The value of an instruction's operand may be inserted
6298 // by referring to it with a '$' prefix.
6299 // opcode -- Three instruction opcodes may be provided. These are referred
6300 // to within an encode class as $primary, $secondary, and $tertiary
6301 // respectively. The primary opcode is commonly used to
6302 // indicate the type of machine instruction, while secondary
6303 // and tertiary are often used for prefix options or addressing
6304 // modes.
6305 // ins_encode -- A list of encode classes with parameters. The encode class
6306 // name must have been defined in an 'enc_class' specification
6307 // in the encode section of the architecture description.
6308
6309 //----------BSWAP-Instruction--------------------------------------------------
6310 instruct bytes_reverse_int(eRegI dst) %{
6311 match(Set dst (ReverseBytesI dst));
6312
6313 format %{ "BSWAP $dst" %}
6314 opcode(0x0F, 0xC8);
6315 ins_encode( OpcP, OpcSReg(dst) );
6316 ins_pipe( ialu_reg );
6317 %}
6318
6319 instruct bytes_reverse_long(eRegL dst) %{
6320 match(Set dst (ReverseBytesL dst));
6321
6322 format %{ "BSWAP $dst.lo\n\t"
6323 "BSWAP $dst.hi\n\t"
6324 "XCHG $dst.lo $dst.hi" %}
6325
6326 ins_cost(125);
6327 ins_encode( bswap_long_bytes(dst) );
6328 ins_pipe( ialu_reg_reg);
6329 %}
6330
6331
6332 //----------Load/Store/Move Instructions---------------------------------------
6333 //----------Load Instructions--------------------------------------------------
6334 // Load Byte (8bit signed)
6335 instruct loadB(xRegI dst, memory mem) %{
6336 match(Set dst (LoadB mem));
6337
6338 ins_cost(125);
6339 format %{ "MOVSX8 $dst,$mem" %}
6340 opcode(0xBE, 0x0F);
6341 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6342 ins_pipe( ialu_reg_mem );
6343 %}
6344
6345 // Load Byte (8bit UNsigned)
6346 instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{
6347 match(Set dst (AndI (LoadB mem) bytemask));
6348
6349 ins_cost(125);
6350 format %{ "MOVZX8 $dst,$mem" %}
6351 opcode(0xB6, 0x0F);
6352 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6353 ins_pipe( ialu_reg_mem );
6354 %}
6355
6356 // Load Char (16bit unsigned)
6357 instruct loadC(eRegI dst, memory mem) %{
6358 match(Set dst (LoadC mem));
6359
6360 ins_cost(125);
6361 format %{ "MOVZX $dst,$mem" %}
6362 opcode(0xB7, 0x0F);
6363 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6364 ins_pipe( ialu_reg_mem );
6365 %}
6366
6367 // Load Integer
6368 instruct loadI(eRegI dst, memory mem) %{
6369 match(Set dst (LoadI mem));
6370
6371 ins_cost(125);
6372 format %{ "MOV $dst,$mem" %}
6373 opcode(0x8B);
6374 ins_encode( OpcP, RegMem(dst,mem));
6375 ins_pipe( ialu_reg_mem );
6376 %}
6377
6378 // Load Long. Cannot clobber address while loading, so restrict address
6379 // register to ESI
6380 instruct loadL(eRegL dst, load_long_memory mem) %{
6381 predicate(!((LoadLNode*)n)->require_atomic_access());
6382 match(Set dst (LoadL mem));
6383
6384 ins_cost(250);
6385 format %{ "MOV $dst.lo,$mem\n\t"
6386 "MOV $dst.hi,$mem+4" %}
6387 opcode(0x8B, 0x8B);
6388 ins_encode( OpcP, RegMem(dst,mem), OpcS, RegMem_Hi(dst,mem));
6389 ins_pipe( ialu_reg_long_mem );
6390 %}
6391
6392 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6393 // then store it down to the stack and reload on the int
6394 // side.
6395 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6396 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6397 match(Set dst (LoadL mem));
6398
6399 ins_cost(200);
6400 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6401 "FISTp $dst" %}
6402 ins_encode(enc_loadL_volatile(mem,dst));
6403 ins_pipe( fpu_reg_mem );
6404 %}
6405
6406 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6407 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6408 match(Set dst (LoadL mem));
6409 effect(TEMP tmp);
6410 ins_cost(180);
6411 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6412 "MOVSD $dst,$tmp" %}
6413 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6414 ins_pipe( pipe_slow );
6415 %}
6416
6417 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6418 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6419 match(Set dst (LoadL mem));
6420 effect(TEMP tmp);
6421 ins_cost(160);
6422 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6423 "MOVD $dst.lo,$tmp\n\t"
6424 "PSRLQ $tmp,32\n\t"
6425 "MOVD $dst.hi,$tmp" %}
6426 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6427 ins_pipe( pipe_slow );
6428 %}
6429
6430 // Load Range
6431 instruct loadRange(eRegI dst, memory mem) %{
6432 match(Set dst (LoadRange mem));
6433
6434 ins_cost(125);
6435 format %{ "MOV $dst,$mem" %}
6436 opcode(0x8B);
6437 ins_encode( OpcP, RegMem(dst,mem));
6438 ins_pipe( ialu_reg_mem );
6439 %}
6440
6441
6442 // Load Pointer
6443 instruct loadP(eRegP dst, memory mem) %{
6444 match(Set dst (LoadP mem));
6445
6446 ins_cost(125);
6447 format %{ "MOV $dst,$mem" %}
6448 opcode(0x8B);
6449 ins_encode( OpcP, RegMem(dst,mem));
6450 ins_pipe( ialu_reg_mem );
6451 %}
6452
6453 // Load Klass Pointer
6454 instruct loadKlass(eRegP dst, memory mem) %{
6455 match(Set dst (LoadKlass mem));
6456
6457 ins_cost(125);
6458 format %{ "MOV $dst,$mem" %}
6459 opcode(0x8B);
6460 ins_encode( OpcP, RegMem(dst,mem));
6461 ins_pipe( ialu_reg_mem );
6462 %}
6463
6464 // Load Short (16bit signed)
6465 instruct loadS(eRegI dst, memory mem) %{
6466 match(Set dst (LoadS mem));
6467
6468 ins_cost(125);
6469 format %{ "MOVSX $dst,$mem" %}
6470 opcode(0xBF, 0x0F);
6471 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6472 ins_pipe( ialu_reg_mem );
6473 %}
6474
6475 // Load Double
6476 instruct loadD(regD dst, memory mem) %{
6477 predicate(UseSSE<=1);
6478 match(Set dst (LoadD mem));
6479
6480 ins_cost(150);
6481 format %{ "FLD_D ST,$mem\n\t"
6482 "FSTP $dst" %}
6483 opcode(0xDD); /* DD /0 */
6484 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6485 Pop_Reg_D(dst) );
6486 ins_pipe( fpu_reg_mem );
6487 %}
6488
6489 // Load Double to XMM
6490 instruct loadXD(regXD dst, memory mem) %{
6491 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6492 match(Set dst (LoadD mem));
6493 ins_cost(145);
6494 format %{ "MOVSD $dst,$mem" %}
6495 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6496 ins_pipe( pipe_slow );
6497 %}
6498
6499 instruct loadXD_partial(regXD dst, memory mem) %{
6500 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6501 match(Set dst (LoadD mem));
6502 ins_cost(145);
6503 format %{ "MOVLPD $dst,$mem" %}
6504 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6505 ins_pipe( pipe_slow );
6506 %}
6507
6508 // Load to XMM register (single-precision floating point)
6509 // MOVSS instruction
6510 instruct loadX(regX dst, memory mem) %{
6511 predicate(UseSSE>=1);
6512 match(Set dst (LoadF mem));
6513 ins_cost(145);
6514 format %{ "MOVSS $dst,$mem" %}
6515 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6516 ins_pipe( pipe_slow );
6517 %}
6518
6519 // Load Float
6520 instruct loadF(regF dst, memory mem) %{
6521 predicate(UseSSE==0);
6522 match(Set dst (LoadF mem));
6523
6524 ins_cost(150);
6525 format %{ "FLD_S ST,$mem\n\t"
6526 "FSTP $dst" %}
6527 opcode(0xD9); /* D9 /0 */
6528 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6529 Pop_Reg_F(dst) );
6530 ins_pipe( fpu_reg_mem );
6531 %}
6532
6533 // Load Aligned Packed Byte to XMM register
6534 instruct loadA8B(regXD dst, memory mem) %{
6535 predicate(UseSSE>=1);
6536 match(Set dst (Load8B mem));
6537 ins_cost(125);
6538 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6539 ins_encode( movq_ld(dst, mem));
6540 ins_pipe( pipe_slow );
6541 %}
6542
6543 // Load Aligned Packed Short to XMM register
6544 instruct loadA4S(regXD dst, memory mem) %{
6545 predicate(UseSSE>=1);
6546 match(Set dst (Load4S mem));
6547 ins_cost(125);
6548 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6549 ins_encode( movq_ld(dst, mem));
6550 ins_pipe( pipe_slow );
6551 %}
6552
6553 // Load Aligned Packed Char to XMM register
6554 instruct loadA4C(regXD dst, memory mem) %{
6555 predicate(UseSSE>=1);
6556 match(Set dst (Load4C mem));
6557 ins_cost(125);
6558 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6559 ins_encode( movq_ld(dst, mem));
6560 ins_pipe( pipe_slow );
6561 %}
6562
6563 // Load Aligned Packed Integer to XMM register
6564 instruct load2IU(regXD dst, memory mem) %{
6565 predicate(UseSSE>=1);
6566 match(Set dst (Load2I mem));
6567 ins_cost(125);
6568 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6569 ins_encode( movq_ld(dst, mem));
6570 ins_pipe( pipe_slow );
6571 %}
6572
6573 // Load Aligned Packed Single to XMM
6574 instruct loadA2F(regXD dst, memory mem) %{
6575 predicate(UseSSE>=1);
6576 match(Set dst (Load2F mem));
6577 ins_cost(145);
6578 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6579 ins_encode( movq_ld(dst, mem));
6580 ins_pipe( pipe_slow );
6581 %}
6582
6583 // Load Effective Address
6584 instruct leaP8(eRegP dst, indOffset8 mem) %{
6585 match(Set dst mem);
6586
6587 ins_cost(110);
6588 format %{ "LEA $dst,$mem" %}
6589 opcode(0x8D);
6590 ins_encode( OpcP, RegMem(dst,mem));
6591 ins_pipe( ialu_reg_reg_fat );
6592 %}
6593
6594 instruct leaP32(eRegP dst, indOffset32 mem) %{
6595 match(Set dst mem);
6596
6597 ins_cost(110);
6598 format %{ "LEA $dst,$mem" %}
6599 opcode(0x8D);
6600 ins_encode( OpcP, RegMem(dst,mem));
6601 ins_pipe( ialu_reg_reg_fat );
6602 %}
6603
6604 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6605 match(Set dst mem);
6606
6607 ins_cost(110);
6608 format %{ "LEA $dst,$mem" %}
6609 opcode(0x8D);
6610 ins_encode( OpcP, RegMem(dst,mem));
6611 ins_pipe( ialu_reg_reg_fat );
6612 %}
6613
6614 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6615 match(Set dst mem);
6616
6617 ins_cost(110);
6618 format %{ "LEA $dst,$mem" %}
6619 opcode(0x8D);
6620 ins_encode( OpcP, RegMem(dst,mem));
6621 ins_pipe( ialu_reg_reg_fat );
6622 %}
6623
6624 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6625 match(Set dst mem);
6626
6627 ins_cost(110);
6628 format %{ "LEA $dst,$mem" %}
6629 opcode(0x8D);
6630 ins_encode( OpcP, RegMem(dst,mem));
6631 ins_pipe( ialu_reg_reg_fat );
6632 %}
6633
6634 // Load Constant
6635 instruct loadConI(eRegI dst, immI src) %{
6636 match(Set dst src);
6637
6638 format %{ "MOV $dst,$src" %}
6639 ins_encode( LdImmI(dst, src) );
6640 ins_pipe( ialu_reg_fat );
6641 %}
6642
6643 // Load Constant zero
6644 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6645 match(Set dst src);
6646 effect(KILL cr);
6647
6648 ins_cost(50);
6649 format %{ "XOR $dst,$dst" %}
6650 opcode(0x33); /* + rd */
6651 ins_encode( OpcP, RegReg( dst, dst ) );
6652 ins_pipe( ialu_reg );
6653 %}
6654
6655 instruct loadConP(eRegP dst, immP src) %{
6656 match(Set dst src);
6657
6658 format %{ "MOV $dst,$src" %}
6659 opcode(0xB8); /* + rd */
6660 ins_encode( LdImmP(dst, src) );
6661 ins_pipe( ialu_reg_fat );
6662 %}
6663
6664 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6665 match(Set dst src);
6666 effect(KILL cr);
6667 ins_cost(200);
6668 format %{ "MOV $dst.lo,$src.lo\n\t"
6669 "MOV $dst.hi,$src.hi" %}
6670 opcode(0xB8);
6671 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6672 ins_pipe( ialu_reg_long_fat );
6673 %}
6674
6675 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6676 match(Set dst src);
6677 effect(KILL cr);
6678 ins_cost(150);
6679 format %{ "XOR $dst.lo,$dst.lo\n\t"
6680 "XOR $dst.hi,$dst.hi" %}
6681 opcode(0x33,0x33);
6682 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6683 ins_pipe( ialu_reg_long );
6684 %}
6685
6686 // The instruction usage is guarded by predicate in operand immF().
6687 instruct loadConF(regF dst, immF src) %{
6688 match(Set dst src);
6689 ins_cost(125);
6690
6691 format %{ "FLD_S ST,$src\n\t"
6692 "FSTP $dst" %}
6693 opcode(0xD9, 0x00); /* D9 /0 */
6694 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
6695 ins_pipe( fpu_reg_con );
6696 %}
6697
6698 // The instruction usage is guarded by predicate in operand immXF().
6699 instruct loadConX(regX dst, immXF con) %{
6700 match(Set dst con);
6701 ins_cost(125);
6702 format %{ "MOVSS $dst,[$con]" %}
6703 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
6704 ins_pipe( pipe_slow );
6705 %}
6706
6707 // The instruction usage is guarded by predicate in operand immXF0().
6708 instruct loadConX0(regX dst, immXF0 src) %{
6709 match(Set dst src);
6710 ins_cost(100);
6711 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6712 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6713 ins_pipe( pipe_slow );
6714 %}
6715
6716 // The instruction usage is guarded by predicate in operand immD().
6717 instruct loadConD(regD dst, immD src) %{
6718 match(Set dst src);
6719 ins_cost(125);
6720
6721 format %{ "FLD_D ST,$src\n\t"
6722 "FSTP $dst" %}
6723 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
6724 ins_pipe( fpu_reg_con );
6725 %}
6726
6727 // The instruction usage is guarded by predicate in operand immXD().
6728 instruct loadConXD(regXD dst, immXD con) %{
6729 match(Set dst con);
6730 ins_cost(125);
6731 format %{ "MOVSD $dst,[$con]" %}
6732 ins_encode(load_conXD(dst, con));
6733 ins_pipe( pipe_slow );
6734 %}
6735
6736 // The instruction usage is guarded by predicate in operand immXD0().
6737 instruct loadConXD0(regXD dst, immXD0 src) %{
6738 match(Set dst src);
6739 ins_cost(100);
6740 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6741 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
6742 ins_pipe( pipe_slow );
6743 %}
6744
6745 // Load Stack Slot
6746 instruct loadSSI(eRegI dst, stackSlotI src) %{
6747 match(Set dst src);
6748 ins_cost(125);
6749
6750 format %{ "MOV $dst,$src" %}
6751 opcode(0x8B);
6752 ins_encode( OpcP, RegMem(dst,src));
6753 ins_pipe( ialu_reg_mem );
6754 %}
6755
6756 instruct loadSSL(eRegL dst, stackSlotL src) %{
6757 match(Set dst src);
6758
6759 ins_cost(200);
6760 format %{ "MOV $dst,$src.lo\n\t"
6761 "MOV $dst+4,$src.hi" %}
6762 opcode(0x8B, 0x8B);
6763 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6764 ins_pipe( ialu_mem_long_reg );
6765 %}
6766
6767 // Load Stack Slot
6768 instruct loadSSP(eRegP dst, stackSlotP src) %{
6769 match(Set dst src);
6770 ins_cost(125);
6771
6772 format %{ "MOV $dst,$src" %}
6773 opcode(0x8B);
6774 ins_encode( OpcP, RegMem(dst,src));
6775 ins_pipe( ialu_reg_mem );
6776 %}
6777
6778 // Load Stack Slot
6779 instruct loadSSF(regF dst, stackSlotF src) %{
6780 match(Set dst src);
6781 ins_cost(125);
6782
6783 format %{ "FLD_S $src\n\t"
6784 "FSTP $dst" %}
6785 opcode(0xD9); /* D9 /0, FLD m32real */
6786 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6787 Pop_Reg_F(dst) );
6788 ins_pipe( fpu_reg_mem );
6789 %}
6790
6791 // Load Stack Slot
6792 instruct loadSSD(regD dst, stackSlotD src) %{
6793 match(Set dst src);
6794 ins_cost(125);
6795
6796 format %{ "FLD_D $src\n\t"
6797 "FSTP $dst" %}
6798 opcode(0xDD); /* DD /0, FLD m64real */
6799 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6800 Pop_Reg_D(dst) );
6801 ins_pipe( fpu_reg_mem );
6802 %}
6803
6804 // Prefetch instructions.
6805 // Must be safe to execute with invalid address (cannot fault).
6806
6807 instruct prefetchr0( memory mem ) %{
6808 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
6809 match(PrefetchRead mem);
6810 ins_cost(0);
6811 size(0);
6812 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6813 ins_encode();
6814 ins_pipe(empty);
6815 %}
6816
6817 instruct prefetchr( memory mem ) %{
6818 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
6819 match(PrefetchRead mem);
6820 ins_cost(100);
6821
6822 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6823 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
6824 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6825 ins_pipe(ialu_mem);
6826 %}
6827
6828 instruct prefetchrNTA( memory mem ) %{
6829 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6830 match(PrefetchRead mem);
6831 ins_cost(100);
6832
6833 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6834 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6835 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6836 ins_pipe(ialu_mem);
6837 %}
6838
6839 instruct prefetchrT0( memory mem ) %{
6840 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6841 match(PrefetchRead mem);
6842 ins_cost(100);
6843
6844 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6845 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6846 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6847 ins_pipe(ialu_mem);
6848 %}
6849
6850 instruct prefetchrT2( memory mem ) %{
6851 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6852 match(PrefetchRead mem);
6853 ins_cost(100);
6854
6855 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6856 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6857 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
6858 ins_pipe(ialu_mem);
6859 %}
6860
6861 instruct prefetchw0( memory mem ) %{
6862 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
6863 match(PrefetchWrite mem);
6864 ins_cost(0);
6865 size(0);
6866 format %{ "Prefetch (non-SSE is empty encoding)" %}
6867 ins_encode();
6868 ins_pipe(empty);
6869 %}
6870
6871 instruct prefetchw( memory mem ) %{
6872 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
6873 match( PrefetchWrite mem );
6874 ins_cost(100);
6875
6876 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6877 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6878 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6879 ins_pipe(ialu_mem);
6880 %}
6881
6882 instruct prefetchwNTA( memory mem ) %{
6883 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6884 match(PrefetchWrite mem);
6885 ins_cost(100);
6886
6887 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6888 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6889 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
6890 ins_pipe(ialu_mem);
6891 %}
6892
6893 instruct prefetchwT0( memory mem ) %{
6894 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6895 match(PrefetchWrite mem);
6896 ins_cost(100);
6897
6898 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
6899 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6900 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
6901 ins_pipe(ialu_mem);
6902 %}
6903
6904 instruct prefetchwT2( memory mem ) %{
6905 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6906 match(PrefetchWrite mem);
6907 ins_cost(100);
6908
6909 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
6910 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6911 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
6912 ins_pipe(ialu_mem);
6913 %}
6914
6915 //----------Store Instructions-------------------------------------------------
6916
6917 // Store Byte
6918 instruct storeB(memory mem, xRegI src) %{
6919 match(Set mem (StoreB mem src));
6920
6921 ins_cost(125);
6922 format %{ "MOV8 $mem,$src" %}
6923 opcode(0x88);
6924 ins_encode( OpcP, RegMem( src, mem ) );
6925 ins_pipe( ialu_mem_reg );
6926 %}
6927
6928 // Store Char/Short
6929 instruct storeC(memory mem, eRegI src) %{
6930 match(Set mem (StoreC mem src));
6931
6932 ins_cost(125);
6933 format %{ "MOV16 $mem,$src" %}
6934 opcode(0x89, 0x66);
6935 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6936 ins_pipe( ialu_mem_reg );
6937 %}
6938
6939 // Store Integer
6940 instruct storeI(memory mem, eRegI src) %{
6941 match(Set mem (StoreI mem src));
6942
6943 ins_cost(125);
6944 format %{ "MOV $mem,$src" %}
6945 opcode(0x89);
6946 ins_encode( OpcP, RegMem( src, mem ) );
6947 ins_pipe( ialu_mem_reg );
6948 %}
6949
6950 // Store Long
6951 instruct storeL(long_memory mem, eRegL src) %{
6952 predicate(!((StoreLNode*)n)->require_atomic_access());
6953 match(Set mem (StoreL mem src));
6954
6955 ins_cost(200);
6956 format %{ "MOV $mem,$src.lo\n\t"
6957 "MOV $mem+4,$src.hi" %}
6958 opcode(0x89, 0x89);
6959 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6960 ins_pipe( ialu_mem_long_reg );
6961 %}
6962
6963 // Volatile Store Long. Must be atomic, so move it into
6964 // the FP TOS and then do a 64-bit FIST. Has to probe the
6965 // target address before the store (for null-ptr checks)
6966 // so the memory operand is used twice in the encoding.
6967 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6968 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6969 match(Set mem (StoreL mem src));
6970 effect( KILL cr );
6971 ins_cost(400);
6972 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6973 "FILD $src\n\t"
6974 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6975 opcode(0x3B);
6976 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6977 ins_pipe( fpu_reg_mem );
6978 %}
6979
6980 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
6981 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6982 match(Set mem (StoreL mem src));
6983 effect( TEMP tmp, KILL cr );
6984 ins_cost(380);
6985 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6986 "MOVSD $tmp,$src\n\t"
6987 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6988 opcode(0x3B);
6989 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
6990 ins_pipe( pipe_slow );
6991 %}
6992
6993 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
6994 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6995 match(Set mem (StoreL mem src));
6996 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6997 ins_cost(360);
6998 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6999 "MOVD $tmp,$src.lo\n\t"
7000 "MOVD $tmp2,$src.hi\n\t"
7001 "PUNPCKLDQ $tmp,$tmp2\n\t"
7002 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7003 opcode(0x3B);
7004 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7005 ins_pipe( pipe_slow );
7006 %}
7007
7008 // Store Pointer; for storing unknown oops and raw pointers
7009 instruct storeP(memory mem, anyRegP src) %{
7010 match(Set mem (StoreP mem src));
7011
7012 ins_cost(125);
7013 format %{ "MOV $mem,$src" %}
7014 opcode(0x89);
7015 ins_encode( OpcP, RegMem( src, mem ) );
7016 ins_pipe( ialu_mem_reg );
7017 %}
7018
7019 // Store Integer Immediate
7020 instruct storeImmI(memory mem, immI src) %{
7021 match(Set mem (StoreI mem src));
7022
7023 ins_cost(150);
7024 format %{ "MOV $mem,$src" %}
7025 opcode(0xC7); /* C7 /0 */
7026 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7027 ins_pipe( ialu_mem_imm );
7028 %}
7029
7030 // Store Short/Char Immediate
7031 instruct storeImmI16(memory mem, immI16 src) %{
7032 predicate(UseStoreImmI16);
7033 match(Set mem (StoreC mem src));
7034
7035 ins_cost(150);
7036 format %{ "MOV16 $mem,$src" %}
7037 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7038 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7039 ins_pipe( ialu_mem_imm );
7040 %}
7041
7042 // Store Pointer Immediate; null pointers or constant oops that do not
7043 // need card-mark barriers.
7044 instruct storeImmP(memory mem, immP src) %{
7045 match(Set mem (StoreP mem src));
7046
7047 ins_cost(150);
7048 format %{ "MOV $mem,$src" %}
7049 opcode(0xC7); /* C7 /0 */
7050 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7051 ins_pipe( ialu_mem_imm );
7052 %}
7053
7054 // Store Byte Immediate
7055 instruct storeImmB(memory mem, immI8 src) %{
7056 match(Set mem (StoreB mem src));
7057
7058 ins_cost(150);
7059 format %{ "MOV8 $mem,$src" %}
7060 opcode(0xC6); /* C6 /0 */
7061 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7062 ins_pipe( ialu_mem_imm );
7063 %}
7064
7065 // Store Aligned Packed Byte XMM register to memory
7066 instruct storeA8B(memory mem, regXD src) %{
7067 predicate(UseSSE>=1);
7068 match(Set mem (Store8B mem src));
7069 ins_cost(145);
7070 format %{ "MOVQ $mem,$src\t! packed8B" %}
7071 ins_encode( movq_st(mem, src));
7072 ins_pipe( pipe_slow );
7073 %}
7074
7075 // Store Aligned Packed Char/Short XMM register to memory
7076 instruct storeA4C(memory mem, regXD src) %{
7077 predicate(UseSSE>=1);
7078 match(Set mem (Store4C mem src));
7079 ins_cost(145);
7080 format %{ "MOVQ $mem,$src\t! packed4C" %}
7081 ins_encode( movq_st(mem, src));
7082 ins_pipe( pipe_slow );
7083 %}
7084
7085 // Store Aligned Packed Integer XMM register to memory
7086 instruct storeA2I(memory mem, regXD src) %{
7087 predicate(UseSSE>=1);
7088 match(Set mem (Store2I mem src));
7089 ins_cost(145);
7090 format %{ "MOVQ $mem,$src\t! packed2I" %}
7091 ins_encode( movq_st(mem, src));
7092 ins_pipe( pipe_slow );
7093 %}
7094
7095 // Store CMS card-mark Immediate
7096 instruct storeImmCM(memory mem, immI8 src) %{
7097 match(Set mem (StoreCM mem src));
7098
7099 ins_cost(150);
7100 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7101 opcode(0xC6); /* C6 /0 */
7102 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7103 ins_pipe( ialu_mem_imm );
7104 %}
7105
7106 // Store Double
7107 instruct storeD( memory mem, regDPR1 src) %{
7108 predicate(UseSSE<=1);
7109 match(Set mem (StoreD mem src));
7110
7111 ins_cost(100);
7112 format %{ "FST_D $mem,$src" %}
7113 opcode(0xDD); /* DD /2 */
7114 ins_encode( enc_FP_store(mem,src) );
7115 ins_pipe( fpu_mem_reg );
7116 %}
7117
7118 // Store double does rounding on x86
7119 instruct storeD_rounded( memory mem, regDPR1 src) %{
7120 predicate(UseSSE<=1);
7121 match(Set mem (StoreD mem (RoundDouble src)));
7122
7123 ins_cost(100);
7124 format %{ "FST_D $mem,$src\t# round" %}
7125 opcode(0xDD); /* DD /2 */
7126 ins_encode( enc_FP_store(mem,src) );
7127 ins_pipe( fpu_mem_reg );
7128 %}
7129
7130 // Store XMM register to memory (double-precision floating points)
7131 // MOVSD instruction
7132 instruct storeXD(memory mem, regXD src) %{
7133 predicate(UseSSE>=2);
7134 match(Set mem (StoreD mem src));
7135 ins_cost(95);
7136 format %{ "MOVSD $mem,$src" %}
7137 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7138 ins_pipe( pipe_slow );
7139 %}
7140
7141 // Store XMM register to memory (single-precision floating point)
7142 // MOVSS instruction
7143 instruct storeX(memory mem, regX src) %{
7144 predicate(UseSSE>=1);
7145 match(Set mem (StoreF mem src));
7146 ins_cost(95);
7147 format %{ "MOVSS $mem,$src" %}
7148 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7149 ins_pipe( pipe_slow );
7150 %}
7151
7152 // Store Aligned Packed Single Float XMM register to memory
7153 instruct storeA2F(memory mem, regXD src) %{
7154 predicate(UseSSE>=1);
7155 match(Set mem (Store2F mem src));
7156 ins_cost(145);
7157 format %{ "MOVQ $mem,$src\t! packed2F" %}
7158 ins_encode( movq_st(mem, src));
7159 ins_pipe( pipe_slow );
7160 %}
7161
7162 // Store Float
7163 instruct storeF( memory mem, regFPR1 src) %{
7164 predicate(UseSSE==0);
7165 match(Set mem (StoreF mem src));
7166
7167 ins_cost(100);
7168 format %{ "FST_S $mem,$src" %}
7169 opcode(0xD9); /* D9 /2 */
7170 ins_encode( enc_FP_store(mem,src) );
7171 ins_pipe( fpu_mem_reg );
7172 %}
7173
7174 // Store Float does rounding on x86
7175 instruct storeF_rounded( memory mem, regFPR1 src) %{
7176 predicate(UseSSE==0);
7177 match(Set mem (StoreF mem (RoundFloat src)));
7178
7179 ins_cost(100);
7180 format %{ "FST_S $mem,$src\t# round" %}
7181 opcode(0xD9); /* D9 /2 */
7182 ins_encode( enc_FP_store(mem,src) );
7183 ins_pipe( fpu_mem_reg );
7184 %}
7185
7186 // Store Float does rounding on x86
7187 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7188 predicate(UseSSE<=1);
7189 match(Set mem (StoreF mem (ConvD2F src)));
7190
7191 ins_cost(100);
7192 format %{ "FST_S $mem,$src\t# D-round" %}
7193 opcode(0xD9); /* D9 /2 */
7194 ins_encode( enc_FP_store(mem,src) );
7195 ins_pipe( fpu_mem_reg );
7196 %}
7197
7198 // Store immediate Float value (it is faster than store from FPU register)
7199 // The instruction usage is guarded by predicate in operand immF().
7200 instruct storeF_imm( memory mem, immF src) %{
7201 match(Set mem (StoreF mem src));
7202
7203 ins_cost(50);
7204 format %{ "MOV $mem,$src\t# store float" %}
7205 opcode(0xC7); /* C7 /0 */
7206 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7207 ins_pipe( ialu_mem_imm );
7208 %}
7209
7210 // Store immediate Float value (it is faster than store from XMM register)
7211 // The instruction usage is guarded by predicate in operand immXF().
7212 instruct storeX_imm( memory mem, immXF src) %{
7213 match(Set mem (StoreF mem src));
7214
7215 ins_cost(50);
7216 format %{ "MOV $mem,$src\t# store float" %}
7217 opcode(0xC7); /* C7 /0 */
7218 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7219 ins_pipe( ialu_mem_imm );
7220 %}
7221
7222 // Store Integer to stack slot
7223 instruct storeSSI(stackSlotI dst, eRegI src) %{
7224 match(Set dst src);
7225
7226 ins_cost(100);
7227 format %{ "MOV $dst,$src" %}
7228 opcode(0x89);
7229 ins_encode( OpcPRegSS( dst, src ) );
7230 ins_pipe( ialu_mem_reg );
7231 %}
7232
7233 // Store Integer to stack slot
7234 instruct storeSSP(stackSlotP dst, eRegP src) %{
7235 match(Set dst src);
7236
7237 ins_cost(100);
7238 format %{ "MOV $dst,$src" %}
7239 opcode(0x89);
7240 ins_encode( OpcPRegSS( dst, src ) );
7241 ins_pipe( ialu_mem_reg );
7242 %}
7243
7244 // Store Long to stack slot
7245 instruct storeSSL(stackSlotL dst, eRegL src) %{
7246 match(Set dst src);
7247
7248 ins_cost(200);
7249 format %{ "MOV $dst,$src.lo\n\t"
7250 "MOV $dst+4,$src.hi" %}
7251 opcode(0x89, 0x89);
7252 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7253 ins_pipe( ialu_mem_long_reg );
7254 %}
7255
7256 //----------MemBar Instructions-----------------------------------------------
7257 // Memory barrier flavors
7258
7259 instruct membar_acquire() %{
7260 match(MemBarAcquire);
7261 ins_cost(400);
7262
7263 size(0);
7264 format %{ "MEMBAR-acquire" %}
7265 ins_encode( enc_membar_acquire );
7266 ins_pipe(pipe_slow);
7267 %}
7268
7269 instruct membar_acquire_lock() %{
7270 match(MemBarAcquire);
7271 predicate(Matcher::prior_fast_lock(n));
7272 ins_cost(0);
7273
7274 size(0);
7275 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7276 ins_encode( );
7277 ins_pipe(empty);
7278 %}
7279
7280 instruct membar_release() %{
7281 match(MemBarRelease);
7282 ins_cost(400);
7283
7284 size(0);
7285 format %{ "MEMBAR-release" %}
7286 ins_encode( enc_membar_release );
7287 ins_pipe(pipe_slow);
7288 %}
7289
7290 instruct membar_release_lock() %{
7291 match(MemBarRelease);
7292 predicate(Matcher::post_fast_unlock(n));
7293 ins_cost(0);
7294
7295 size(0);
7296 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7297 ins_encode( );
7298 ins_pipe(empty);
7299 %}
7300
7301 instruct membar_volatile() %{
7302 match(MemBarVolatile);
7303 ins_cost(400);
7304
7305 format %{ "MEMBAR-volatile" %}
7306 ins_encode( enc_membar_volatile );
7307 ins_pipe(pipe_slow);
7308 %}
7309
7310 instruct unnecessary_membar_volatile() %{
7311 match(MemBarVolatile);
7312 predicate(Matcher::post_store_load_barrier(n));
7313 ins_cost(0);
7314
7315 size(0);
7316 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7317 ins_encode( );
7318 ins_pipe(empty);
7319 %}
7320
7321 //----------Move Instructions--------------------------------------------------
7322 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7323 match(Set dst (CastX2P src));
7324 format %{ "# X2P $dst, $src" %}
7325 ins_encode( /*empty encoding*/ );
7326 ins_cost(0);
7327 ins_pipe(empty);
7328 %}
7329
7330 instruct castP2X(eRegI dst, eRegP src ) %{
7331 match(Set dst (CastP2X src));
7332 ins_cost(50);
7333 format %{ "MOV $dst, $src\t# CastP2X" %}
7334 ins_encode( enc_Copy( dst, src) );
7335 ins_pipe( ialu_reg_reg );
7336 %}
7337
7338 //----------Conditional Move---------------------------------------------------
7339 // Conditional move
7340 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7341 predicate(VM_Version::supports_cmov() );
7342 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7343 ins_cost(200);
7344 format %{ "CMOV$cop $dst,$src" %}
7345 opcode(0x0F,0x40);
7346 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7347 ins_pipe( pipe_cmov_reg );
7348 %}
7349
7350 instruct cmovI_regU( eRegI dst, eRegI src, eFlagsRegU cr, cmpOpU cop ) %{
7351 predicate(VM_Version::supports_cmov() );
7352 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7353 ins_cost(200);
7354 format %{ "CMOV$cop $dst,$src" %}
7355 opcode(0x0F,0x40);
7356 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7357 ins_pipe( pipe_cmov_reg );
7358 %}
7359
7360 // Conditional move
7361 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7362 predicate(VM_Version::supports_cmov() );
7363 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7364 ins_cost(250);
7365 format %{ "CMOV$cop $dst,$src" %}
7366 opcode(0x0F,0x40);
7367 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7368 ins_pipe( pipe_cmov_mem );
7369 %}
7370
7371 // Conditional move
7372 instruct cmovI_memu(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7373 predicate(VM_Version::supports_cmov() );
7374 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7375 ins_cost(250);
7376 format %{ "CMOV$cop $dst,$src" %}
7377 opcode(0x0F,0x40);
7378 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7379 ins_pipe( pipe_cmov_mem );
7380 %}
7381
7382 // Conditional move
7383 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7384 predicate(VM_Version::supports_cmov() );
7385 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7386 ins_cost(200);
7387 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7388 opcode(0x0F,0x40);
7389 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7390 ins_pipe( pipe_cmov_reg );
7391 %}
7392
7393 // Conditional move (non-P6 version)
7394 // Note: a CMoveP is generated for stubs and native wrappers
7395 // regardless of whether we are on a P6, so we
7396 // emulate a cmov here
7397 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7398 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7399 ins_cost(300);
7400 format %{ "Jn$cop skip\n\t"
7401 "MOV $dst,$src\t# pointer\n"
7402 "skip:" %}
7403 opcode(0x8b);
7404 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7405 ins_pipe( pipe_cmov_reg );
7406 %}
7407
7408 // Conditional move
7409 instruct cmovP_regU(eRegP dst, eRegP src, eFlagsRegU cr, cmpOpU cop ) %{
7410 predicate(VM_Version::supports_cmov() );
7411 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7412 ins_cost(200);
7413 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7414 opcode(0x0F,0x40);
7415 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7416 ins_pipe( pipe_cmov_reg );
7417 %}
7418
7419 // DISABLED: Requires the ADLC to emit a bottom_type call that
7420 // correctly meets the two pointer arguments; one is an incoming
7421 // register but the other is a memory operand. ALSO appears to
7422 // be buggy with implicit null checks.
7423 //
7424 //// Conditional move
7425 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7426 // predicate(VM_Version::supports_cmov() );
7427 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7428 // ins_cost(250);
7429 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7430 // opcode(0x0F,0x40);
7431 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7432 // ins_pipe( pipe_cmov_mem );
7433 //%}
7434 //
7435 //// Conditional move
7436 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7437 // predicate(VM_Version::supports_cmov() );
7438 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7439 // ins_cost(250);
7440 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7441 // opcode(0x0F,0x40);
7442 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7443 // ins_pipe( pipe_cmov_mem );
7444 //%}
7445
7446 // Conditional move
7447 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7448 predicate(UseSSE<=1);
7449 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7450 ins_cost(200);
7451 format %{ "FCMOV$cop $dst,$src\t# double" %}
7452 opcode(0xDA);
7453 ins_encode( enc_cmov_d(cop,src) );
7454 ins_pipe( pipe_cmovD_reg );
7455 %}
7456
7457 // Conditional move
7458 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7459 predicate(UseSSE==0);
7460 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7461 ins_cost(200);
7462 format %{ "FCMOV$cop $dst,$src\t# float" %}
7463 opcode(0xDA);
7464 ins_encode( enc_cmov_d(cop,src) );
7465 ins_pipe( pipe_cmovD_reg );
7466 %}
7467
7468 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7469 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7470 predicate(UseSSE<=1);
7471 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7472 ins_cost(200);
7473 format %{ "Jn$cop skip\n\t"
7474 "MOV $dst,$src\t# double\n"
7475 "skip:" %}
7476 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7477 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7478 ins_pipe( pipe_cmovD_reg );
7479 %}
7480
7481 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7482 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7483 predicate(UseSSE==0);
7484 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7485 ins_cost(200);
7486 format %{ "Jn$cop skip\n\t"
7487 "MOV $dst,$src\t# float\n"
7488 "skip:" %}
7489 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7490 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7491 ins_pipe( pipe_cmovD_reg );
7492 %}
7493
7494 // No CMOVE with SSE/SSE2
7495 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7496 predicate (UseSSE>=1);
7497 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7498 ins_cost(200);
7499 format %{ "Jn$cop skip\n\t"
7500 "MOVSS $dst,$src\t# float\n"
7501 "skip:" %}
7502 ins_encode %{
7503 Label skip;
7504 // Invert sense of branch from sense of CMOV
7505 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7506 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7507 __ bind(skip);
7508 %}
7509 ins_pipe( pipe_slow );
7510 %}
7511
7512 // No CMOVE with SSE/SSE2
7513 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7514 predicate (UseSSE>=2);
7515 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7516 ins_cost(200);
7517 format %{ "Jn$cop skip\n\t"
7518 "MOVSD $dst,$src\t# float\n"
7519 "skip:" %}
7520 ins_encode %{
7521 Label skip;
7522 // Invert sense of branch from sense of CMOV
7523 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7524 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7525 __ bind(skip);
7526 %}
7527 ins_pipe( pipe_slow );
7528 %}
7529
7530 // unsigned version
7531 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7532 predicate (UseSSE>=1);
7533 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7534 ins_cost(200);
7535 format %{ "Jn$cop skip\n\t"
7536 "MOVSS $dst,$src\t# float\n"
7537 "skip:" %}
7538 ins_encode %{
7539 Label skip;
7540 // Invert sense of branch from sense of CMOV
7541 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7542 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7543 __ bind(skip);
7544 %}
7545 ins_pipe( pipe_slow );
7546 %}
7547
7548 // unsigned version
7549 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7550 predicate (UseSSE>=2);
7551 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7552 ins_cost(200);
7553 format %{ "Jn$cop skip\n\t"
7554 "MOVSD $dst,$src\t# float\n"
7555 "skip:" %}
7556 ins_encode %{
7557 Label skip;
7558 // Invert sense of branch from sense of CMOV
7559 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7560 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7561 __ bind(skip);
7562 %}
7563 ins_pipe( pipe_slow );
7564 %}
7565
7566 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7567 predicate(VM_Version::supports_cmov() );
7568 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7569 ins_cost(200);
7570 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7571 "CMOV$cop $dst.hi,$src.hi" %}
7572 opcode(0x0F,0x40);
7573 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7574 ins_pipe( pipe_cmov_reg_long );
7575 %}
7576
7577 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7578 predicate(VM_Version::supports_cmov() );
7579 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7580 ins_cost(200);
7581 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7582 "CMOV$cop $dst.hi,$src.hi" %}
7583 opcode(0x0F,0x40);
7584 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7585 ins_pipe( pipe_cmov_reg_long );
7586 %}
7587
7588 //----------Arithmetic Instructions--------------------------------------------
7589 //----------Addition Instructions----------------------------------------------
7590 // Integer Addition Instructions
7591 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7592 match(Set dst (AddI dst src));
7593 effect(KILL cr);
7594
7595 size(2);
7596 format %{ "ADD $dst,$src" %}
7597 opcode(0x03);
7598 ins_encode( OpcP, RegReg( dst, src) );
7599 ins_pipe( ialu_reg_reg );
7600 %}
7601
7602 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7603 match(Set dst (AddI dst src));
7604 effect(KILL cr);
7605
7606 format %{ "ADD $dst,$src" %}
7607 opcode(0x81, 0x00); /* /0 id */
7608 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7609 ins_pipe( ialu_reg );
7610 %}
7611
7612 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7613 predicate(UseIncDec);
7614 match(Set dst (AddI dst src));
7615 effect(KILL cr);
7616
7617 size(1);
7618 format %{ "INC $dst" %}
7619 opcode(0x40); /* */
7620 ins_encode( Opc_plus( primary, dst ) );
7621 ins_pipe( ialu_reg );
7622 %}
7623
7624 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
7625 match(Set dst (AddI src0 src1));
7626 ins_cost(110);
7627
7628 format %{ "LEA $dst,[$src0 + $src1]" %}
7629 opcode(0x8D); /* 0x8D /r */
7630 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7631 ins_pipe( ialu_reg_reg );
7632 %}
7633
7634 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7635 match(Set dst (AddP src0 src1));
7636 ins_cost(110);
7637
7638 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7639 opcode(0x8D); /* 0x8D /r */
7640 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7641 ins_pipe( ialu_reg_reg );
7642 %}
7643
7644 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
7645 predicate(UseIncDec);
7646 match(Set dst (AddI dst src));
7647 effect(KILL cr);
7648
7649 size(1);
7650 format %{ "DEC $dst" %}
7651 opcode(0x48); /* */
7652 ins_encode( Opc_plus( primary, dst ) );
7653 ins_pipe( ialu_reg );
7654 %}
7655
7656 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
7657 match(Set dst (AddP dst src));
7658 effect(KILL cr);
7659
7660 size(2);
7661 format %{ "ADD $dst,$src" %}
7662 opcode(0x03);
7663 ins_encode( OpcP, RegReg( dst, src) );
7664 ins_pipe( ialu_reg_reg );
7665 %}
7666
7667 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7668 match(Set dst (AddP dst src));
7669 effect(KILL cr);
7670
7671 format %{ "ADD $dst,$src" %}
7672 opcode(0x81,0x00); /* Opcode 81 /0 id */
7673 // ins_encode( RegImm( dst, src) );
7674 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7675 ins_pipe( ialu_reg );
7676 %}
7677
7678 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7679 match(Set dst (AddI dst (LoadI src)));
7680 effect(KILL cr);
7681
7682 ins_cost(125);
7683 format %{ "ADD $dst,$src" %}
7684 opcode(0x03);
7685 ins_encode( OpcP, RegMem( dst, src) );
7686 ins_pipe( ialu_reg_mem );
7687 %}
7688
7689 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7690 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7691 effect(KILL cr);
7692
7693 ins_cost(150);
7694 format %{ "ADD $dst,$src" %}
7695 opcode(0x01); /* Opcode 01 /r */
7696 ins_encode( OpcP, RegMem( src, dst ) );
7697 ins_pipe( ialu_mem_reg );
7698 %}
7699
7700 // Add Memory with Immediate
7701 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7702 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7703 effect(KILL cr);
7704
7705 ins_cost(125);
7706 format %{ "ADD $dst,$src" %}
7707 opcode(0x81); /* Opcode 81 /0 id */
7708 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7709 ins_pipe( ialu_mem_imm );
7710 %}
7711
7712 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7713 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7714 effect(KILL cr);
7715
7716 ins_cost(125);
7717 format %{ "INC $dst" %}
7718 opcode(0xFF); /* Opcode FF /0 */
7719 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7720 ins_pipe( ialu_mem_imm );
7721 %}
7722
7723 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7724 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7725 effect(KILL cr);
7726
7727 ins_cost(125);
7728 format %{ "DEC $dst" %}
7729 opcode(0xFF); /* Opcode FF /1 */
7730 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7731 ins_pipe( ialu_mem_imm );
7732 %}
7733
7734
7735 instruct checkCastPP( eRegP dst ) %{
7736 match(Set dst (CheckCastPP dst));
7737
7738 size(0);
7739 format %{ "#checkcastPP of $dst" %}
7740 ins_encode( /*empty encoding*/ );
7741 ins_pipe( empty );
7742 %}
7743
7744 instruct castPP( eRegP dst ) %{
7745 match(Set dst (CastPP dst));
7746 format %{ "#castPP of $dst" %}
7747 ins_encode( /*empty encoding*/ );
7748 ins_pipe( empty );
7749 %}
7750
7751 instruct castII( eRegI dst ) %{
7752 match(Set dst (CastII dst));
7753 format %{ "#castII of $dst" %}
7754 ins_encode( /*empty encoding*/ );
7755 ins_cost(0);
7756 ins_pipe( empty );
7757 %}
7758
7759
7760 // Load-locked - same as a regular pointer load when used with compare-swap
7761 instruct loadPLocked(eRegP dst, memory mem) %{
7762 match(Set dst (LoadPLocked mem));
7763
7764 ins_cost(125);
7765 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7766 opcode(0x8B);
7767 ins_encode( OpcP, RegMem(dst,mem));
7768 ins_pipe( ialu_reg_mem );
7769 %}
7770
7771 // LoadLong-locked - same as a volatile long load when used with compare-swap
7772 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
7773 predicate(UseSSE<=1);
7774 match(Set dst (LoadLLocked mem));
7775
7776 ins_cost(200);
7777 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7778 "FISTp $dst" %}
7779 ins_encode(enc_loadL_volatile(mem,dst));
7780 ins_pipe( fpu_reg_mem );
7781 %}
7782
7783 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
7784 predicate(UseSSE>=2);
7785 match(Set dst (LoadLLocked mem));
7786 effect(TEMP tmp);
7787 ins_cost(180);
7788 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7789 "MOVSD $dst,$tmp" %}
7790 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
7791 ins_pipe( pipe_slow );
7792 %}
7793
7794 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
7795 predicate(UseSSE>=2);
7796 match(Set dst (LoadLLocked mem));
7797 effect(TEMP tmp);
7798 ins_cost(160);
7799 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7800 "MOVD $dst.lo,$tmp\n\t"
7801 "PSRLQ $tmp,32\n\t"
7802 "MOVD $dst.hi,$tmp" %}
7803 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
7804 ins_pipe( pipe_slow );
7805 %}
7806
7807 // Conditional-store of the updated heap-top.
7808 // Used during allocation of the shared heap.
7809 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7810 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7811 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7812 // EAX is killed if there is contention, but then it's also unused.
7813 // In the common case of no contention, EAX holds the new oop address.
7814 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7815 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7816 ins_pipe( pipe_cmpxchg );
7817 %}
7818
7819 // Conditional-store of a long value
7820 // Returns a boolean value (0/1) on success. Implemented with a CMPXCHG8 on Intel.
7821 // mem_ptr can actually be in either ESI or EDI
7822 instruct storeLConditional( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7823 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
7824 effect(KILL cr);
7825 // EDX:EAX is killed if there is contention, but then it's also unused.
7826 // In the common case of no contention, EDX:EAX holds the new oop address.
7827 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7828 "MOV $res,0\n\t"
7829 "JNE,s fail\n\t"
7830 "MOV $res,1\n"
7831 "fail:" %}
7832 ins_encode( enc_cmpxchg8(mem_ptr),
7833 enc_flags_ne_to_boolean(res) );
7834 ins_pipe( pipe_cmpxchg );
7835 %}
7836
7837 // Conditional-store of a long value
7838 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7839 // mem_ptr can actually be in either ESI or EDI
7840 instruct storeLConditional_flags( eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr, immI0 zero ) %{
7841 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
7842 // EDX:EAX is killed if there is contention, but then it's also unused.
7843 // In the common case of no contention, EDX:EAX holds the new oop address.
7844 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" %}
7845 ins_encode( enc_cmpxchg8(mem_ptr) );
7846 ins_pipe( pipe_cmpxchg );
7847 %}
7848
7849 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7850
7851 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7852 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7853 effect(KILL cr, KILL oldval);
7854 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7855 "MOV $res,0\n\t"
7856 "JNE,s fail\n\t"
7857 "MOV $res,1\n"
7858 "fail:" %}
7859 ins_encode( enc_cmpxchg8(mem_ptr),
7860 enc_flags_ne_to_boolean(res) );
7861 ins_pipe( pipe_cmpxchg );
7862 %}
7863
7864 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7865 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7866 effect(KILL cr, KILL oldval);
7867 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7868 "MOV $res,0\n\t"
7869 "JNE,s fail\n\t"
7870 "MOV $res,1\n"
7871 "fail:" %}
7872 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7873 ins_pipe( pipe_cmpxchg );
7874 %}
7875
7876 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7877 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7878 effect(KILL cr, KILL oldval);
7879 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7880 "MOV $res,0\n\t"
7881 "JNE,s fail\n\t"
7882 "MOV $res,1\n"
7883 "fail:" %}
7884 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7885 ins_pipe( pipe_cmpxchg );
7886 %}
7887
7888 //----------Subtraction Instructions-------------------------------------------
7889 // Integer Subtraction Instructions
7890 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7891 match(Set dst (SubI dst src));
7892 effect(KILL cr);
7893
7894 size(2);
7895 format %{ "SUB $dst,$src" %}
7896 opcode(0x2B);
7897 ins_encode( OpcP, RegReg( dst, src) );
7898 ins_pipe( ialu_reg_reg );
7899 %}
7900
7901 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7902 match(Set dst (SubI dst src));
7903 effect(KILL cr);
7904
7905 format %{ "SUB $dst,$src" %}
7906 opcode(0x81,0x05); /* Opcode 81 /5 */
7907 // ins_encode( RegImm( dst, src) );
7908 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7909 ins_pipe( ialu_reg );
7910 %}
7911
7912 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
7913 match(Set dst (SubI dst (LoadI src)));
7914 effect(KILL cr);
7915
7916 ins_cost(125);
7917 format %{ "SUB $dst,$src" %}
7918 opcode(0x2B);
7919 ins_encode( OpcP, RegMem( dst, src) );
7920 ins_pipe( ialu_reg_mem );
7921 %}
7922
7923 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
7924 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7925 effect(KILL cr);
7926
7927 ins_cost(150);
7928 format %{ "SUB $dst,$src" %}
7929 opcode(0x29); /* Opcode 29 /r */
7930 ins_encode( OpcP, RegMem( src, dst ) );
7931 ins_pipe( ialu_mem_reg );
7932 %}
7933
7934 // Subtract from a pointer
7935 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
7936 match(Set dst (AddP dst (SubI zero src)));
7937 effect(KILL cr);
7938
7939 size(2);
7940 format %{ "SUB $dst,$src" %}
7941 opcode(0x2B);
7942 ins_encode( OpcP, RegReg( dst, src) );
7943 ins_pipe( ialu_reg_reg );
7944 %}
7945
7946 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
7947 match(Set dst (SubI zero dst));
7948 effect(KILL cr);
7949
7950 size(2);
7951 format %{ "NEG $dst" %}
7952 opcode(0xF7,0x03); // Opcode F7 /3
7953 ins_encode( OpcP, RegOpc( dst ) );
7954 ins_pipe( ialu_reg );
7955 %}
7956
7957
7958 //----------Multiplication/Division Instructions-------------------------------
7959 // Integer Multiplication Instructions
7960 // Multiply Register
7961 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7962 match(Set dst (MulI dst src));
7963 effect(KILL cr);
7964
7965 size(3);
7966 ins_cost(300);
7967 format %{ "IMUL $dst,$src" %}
7968 opcode(0xAF, 0x0F);
7969 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7970 ins_pipe( ialu_reg_reg_alu0 );
7971 %}
7972
7973 // Multiply 32-bit Immediate
7974 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
7975 match(Set dst (MulI src imm));
7976 effect(KILL cr);
7977
7978 ins_cost(300);
7979 format %{ "IMUL $dst,$src,$imm" %}
7980 opcode(0x69); /* 69 /r id */
7981 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
7982 ins_pipe( ialu_reg_reg_alu0 );
7983 %}
7984
7985 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
7986 match(Set dst src);
7987 effect(KILL cr);
7988
7989 // Note that this is artificially increased to make it more expensive than loadConL
7990 ins_cost(250);
7991 format %{ "MOV EAX,$src\t// low word only" %}
7992 opcode(0xB8);
7993 ins_encode( LdImmL_Lo(dst, src) );
7994 ins_pipe( ialu_reg_fat );
7995 %}
7996
7997 // Multiply by 32-bit Immediate, taking the shifted high order results
7998 // (special case for shift by 32)
7999 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8000 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8001 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8002 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8003 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8004 effect(USE src1, KILL cr);
8005
8006 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8007 ins_cost(0*100 + 1*400 - 150);
8008 format %{ "IMUL EDX:EAX,$src1" %}
8009 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8010 ins_pipe( pipe_slow );
8011 %}
8012
8013 // Multiply by 32-bit Immediate, taking the shifted high order results
8014 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8015 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8016 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8017 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8018 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8019 effect(USE src1, KILL cr);
8020
8021 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8022 ins_cost(1*100 + 1*400 - 150);
8023 format %{ "IMUL EDX:EAX,$src1\n\t"
8024 "SAR EDX,$cnt-32" %}
8025 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8026 ins_pipe( pipe_slow );
8027 %}
8028
8029 // Multiply Memory 32-bit Immediate
8030 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8031 match(Set dst (MulI (LoadI src) imm));
8032 effect(KILL cr);
8033
8034 ins_cost(300);
8035 format %{ "IMUL $dst,$src,$imm" %}
8036 opcode(0x69); /* 69 /r id */
8037 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8038 ins_pipe( ialu_reg_mem_alu0 );
8039 %}
8040
8041 // Multiply Memory
8042 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8043 match(Set dst (MulI dst (LoadI src)));
8044 effect(KILL cr);
8045
8046 ins_cost(350);
8047 format %{ "IMUL $dst,$src" %}
8048 opcode(0xAF, 0x0F);
8049 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8050 ins_pipe( ialu_reg_mem_alu0 );
8051 %}
8052
8053 // Multiply Register Int to Long
8054 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8055 // Basic Idea: long = (long)int * (long)int
8056 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8057 effect(DEF dst, USE src, USE src1, KILL flags);
8058
8059 ins_cost(300);
8060 format %{ "IMUL $dst,$src1" %}
8061
8062 ins_encode( long_int_multiply( dst, src1 ) );
8063 ins_pipe( ialu_reg_reg_alu0 );
8064 %}
8065
8066 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8067 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8068 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8069 effect(KILL flags);
8070
8071 ins_cost(300);
8072 format %{ "MUL $dst,$src1" %}
8073
8074 ins_encode( long_uint_multiply(dst, src1) );
8075 ins_pipe( ialu_reg_reg_alu0 );
8076 %}
8077
8078 // Multiply Register Long
8079 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8080 match(Set dst (MulL dst src));
8081 effect(KILL cr, TEMP tmp);
8082 ins_cost(4*100+3*400);
8083 // Basic idea: lo(result) = lo(x_lo * y_lo)
8084 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8085 format %{ "MOV $tmp,$src.lo\n\t"
8086 "IMUL $tmp,EDX\n\t"
8087 "MOV EDX,$src.hi\n\t"
8088 "IMUL EDX,EAX\n\t"
8089 "ADD $tmp,EDX\n\t"
8090 "MUL EDX:EAX,$src.lo\n\t"
8091 "ADD EDX,$tmp" %}
8092 ins_encode( long_multiply( dst, src, tmp ) );
8093 ins_pipe( pipe_slow );
8094 %}
8095
8096 // Multiply Register Long by small constant
8097 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8098 match(Set dst (MulL dst src));
8099 effect(KILL cr, TEMP tmp);
8100 ins_cost(2*100+2*400);
8101 size(12);
8102 // Basic idea: lo(result) = lo(src * EAX)
8103 // hi(result) = hi(src * EAX) + lo(src * EDX)
8104 format %{ "IMUL $tmp,EDX,$src\n\t"
8105 "MOV EDX,$src\n\t"
8106 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8107 "ADD EDX,$tmp" %}
8108 ins_encode( long_multiply_con( dst, src, tmp ) );
8109 ins_pipe( pipe_slow );
8110 %}
8111
8112 // Integer DIV with Register
8113 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8114 match(Set rax (DivI rax div));
8115 effect(KILL rdx, KILL cr);
8116 size(26);
8117 ins_cost(30*100+10*100);
8118 format %{ "CMP EAX,0x80000000\n\t"
8119 "JNE,s normal\n\t"
8120 "XOR EDX,EDX\n\t"
8121 "CMP ECX,-1\n\t"
8122 "JE,s done\n"
8123 "normal: CDQ\n\t"
8124 "IDIV $div\n\t"
8125 "done:" %}
8126 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8127 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8128 ins_pipe( ialu_reg_reg_alu0 );
8129 %}
8130
8131 // Divide Register Long
8132 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8133 match(Set dst (DivL src1 src2));
8134 effect( KILL cr, KILL cx, KILL bx );
8135 ins_cost(10000);
8136 format %{ "PUSH $src1.hi\n\t"
8137 "PUSH $src1.lo\n\t"
8138 "PUSH $src2.hi\n\t"
8139 "PUSH $src2.lo\n\t"
8140 "CALL SharedRuntime::ldiv\n\t"
8141 "ADD ESP,16" %}
8142 ins_encode( long_div(src1,src2) );
8143 ins_pipe( pipe_slow );
8144 %}
8145
8146 // Integer DIVMOD with Register, both quotient and mod results
8147 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8148 match(DivModI rax div);
8149 effect(KILL cr);
8150 size(26);
8151 ins_cost(30*100+10*100);
8152 format %{ "CMP EAX,0x80000000\n\t"
8153 "JNE,s normal\n\t"
8154 "XOR EDX,EDX\n\t"
8155 "CMP ECX,-1\n\t"
8156 "JE,s done\n"
8157 "normal: CDQ\n\t"
8158 "IDIV $div\n\t"
8159 "done:" %}
8160 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8161 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8162 ins_pipe( pipe_slow );
8163 %}
8164
8165 // Integer MOD with Register
8166 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8167 match(Set rdx (ModI rax div));
8168 effect(KILL rax, KILL cr);
8169
8170 size(26);
8171 ins_cost(300);
8172 format %{ "CDQ\n\t"
8173 "IDIV $div" %}
8174 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8175 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8176 ins_pipe( ialu_reg_reg_alu0 );
8177 %}
8178
8179 // Remainder Register Long
8180 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8181 match(Set dst (ModL src1 src2));
8182 effect( KILL cr, KILL cx, KILL bx );
8183 ins_cost(10000);
8184 format %{ "PUSH $src1.hi\n\t"
8185 "PUSH $src1.lo\n\t"
8186 "PUSH $src2.hi\n\t"
8187 "PUSH $src2.lo\n\t"
8188 "CALL SharedRuntime::lrem\n\t"
8189 "ADD ESP,16" %}
8190 ins_encode( long_mod(src1,src2) );
8191 ins_pipe( pipe_slow );
8192 %}
8193
8194 // Integer Shift Instructions
8195 // Shift Left by one
8196 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8197 match(Set dst (LShiftI dst shift));
8198 effect(KILL cr);
8199
8200 size(2);
8201 format %{ "SHL $dst,$shift" %}
8202 opcode(0xD1, 0x4); /* D1 /4 */
8203 ins_encode( OpcP, RegOpc( dst ) );
8204 ins_pipe( ialu_reg );
8205 %}
8206
8207 // Shift Left by 8-bit immediate
8208 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8209 match(Set dst (LShiftI dst shift));
8210 effect(KILL cr);
8211
8212 size(3);
8213 format %{ "SHL $dst,$shift" %}
8214 opcode(0xC1, 0x4); /* C1 /4 ib */
8215 ins_encode( RegOpcImm( dst, shift) );
8216 ins_pipe( ialu_reg );
8217 %}
8218
8219 // Shift Left by variable
8220 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8221 match(Set dst (LShiftI dst shift));
8222 effect(KILL cr);
8223
8224 size(2);
8225 format %{ "SHL $dst,$shift" %}
8226 opcode(0xD3, 0x4); /* D3 /4 */
8227 ins_encode( OpcP, RegOpc( dst ) );
8228 ins_pipe( ialu_reg_reg );
8229 %}
8230
8231 // Arithmetic shift right by one
8232 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8233 match(Set dst (RShiftI dst shift));
8234 effect(KILL cr);
8235
8236 size(2);
8237 format %{ "SAR $dst,$shift" %}
8238 opcode(0xD1, 0x7); /* D1 /7 */
8239 ins_encode( OpcP, RegOpc( dst ) );
8240 ins_pipe( ialu_reg );
8241 %}
8242
8243 // Arithmetic shift right by one
8244 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8245 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8246 effect(KILL cr);
8247 format %{ "SAR $dst,$shift" %}
8248 opcode(0xD1, 0x7); /* D1 /7 */
8249 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8250 ins_pipe( ialu_mem_imm );
8251 %}
8252
8253 // Arithmetic Shift Right by 8-bit immediate
8254 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8255 match(Set dst (RShiftI dst shift));
8256 effect(KILL cr);
8257
8258 size(3);
8259 format %{ "SAR $dst,$shift" %}
8260 opcode(0xC1, 0x7); /* C1 /7 ib */
8261 ins_encode( RegOpcImm( dst, shift ) );
8262 ins_pipe( ialu_mem_imm );
8263 %}
8264
8265 // Arithmetic Shift Right by 8-bit immediate
8266 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8267 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8268 effect(KILL cr);
8269
8270 format %{ "SAR $dst,$shift" %}
8271 opcode(0xC1, 0x7); /* C1 /7 ib */
8272 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8273 ins_pipe( ialu_mem_imm );
8274 %}
8275
8276 // Arithmetic Shift Right by variable
8277 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8278 match(Set dst (RShiftI dst shift));
8279 effect(KILL cr);
8280
8281 size(2);
8282 format %{ "SAR $dst,$shift" %}
8283 opcode(0xD3, 0x7); /* D3 /7 */
8284 ins_encode( OpcP, RegOpc( dst ) );
8285 ins_pipe( ialu_reg_reg );
8286 %}
8287
8288 // Logical shift right by one
8289 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8290 match(Set dst (URShiftI dst shift));
8291 effect(KILL cr);
8292
8293 size(2);
8294 format %{ "SHR $dst,$shift" %}
8295 opcode(0xD1, 0x5); /* D1 /5 */
8296 ins_encode( OpcP, RegOpc( dst ) );
8297 ins_pipe( ialu_reg );
8298 %}
8299
8300 // Logical Shift Right by 8-bit immediate
8301 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8302 match(Set dst (URShiftI dst shift));
8303 effect(KILL cr);
8304
8305 size(3);
8306 format %{ "SHR $dst,$shift" %}
8307 opcode(0xC1, 0x5); /* C1 /5 ib */
8308 ins_encode( RegOpcImm( dst, shift) );
8309 ins_pipe( ialu_reg );
8310 %}
8311
8312 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8313 // This idiom is used by the compiler for the i2b bytecode.
8314 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8315 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8316 effect(KILL cr);
8317
8318 size(3);
8319 format %{ "MOVSX $dst,$src :8" %}
8320 opcode(0xBE, 0x0F);
8321 ins_encode( OpcS, OpcP, RegReg( dst, src));
8322 ins_pipe( ialu_reg_reg );
8323 %}
8324
8325 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8326 // This idiom is used by the compiler the i2s bytecode.
8327 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8328 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8329 effect(KILL cr);
8330
8331 size(3);
8332 format %{ "MOVSX $dst,$src :16" %}
8333 opcode(0xBF, 0x0F);
8334 ins_encode( OpcS, OpcP, RegReg( dst, src));
8335 ins_pipe( ialu_reg_reg );
8336 %}
8337
8338
8339 // Logical Shift Right by variable
8340 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8341 match(Set dst (URShiftI dst shift));
8342 effect(KILL cr);
8343
8344 size(2);
8345 format %{ "SHR $dst,$shift" %}
8346 opcode(0xD3, 0x5); /* D3 /5 */
8347 ins_encode( OpcP, RegOpc( dst ) );
8348 ins_pipe( ialu_reg_reg );
8349 %}
8350
8351
8352 //----------Logical Instructions-----------------------------------------------
8353 //----------Integer Logical Instructions---------------------------------------
8354 // And Instructions
8355 // And Register with Register
8356 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8357 match(Set dst (AndI dst src));
8358 effect(KILL cr);
8359
8360 size(2);
8361 format %{ "AND $dst,$src" %}
8362 opcode(0x23);
8363 ins_encode( OpcP, RegReg( dst, src) );
8364 ins_pipe( ialu_reg_reg );
8365 %}
8366
8367 // And Register with Immediate
8368 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8369 match(Set dst (AndI dst src));
8370 effect(KILL cr);
8371
8372 format %{ "AND $dst,$src" %}
8373 opcode(0x81,0x04); /* Opcode 81 /4 */
8374 // ins_encode( RegImm( dst, src) );
8375 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8376 ins_pipe( ialu_reg );
8377 %}
8378
8379 // And Register with Memory
8380 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8381 match(Set dst (AndI dst (LoadI src)));
8382 effect(KILL cr);
8383
8384 ins_cost(125);
8385 format %{ "AND $dst,$src" %}
8386 opcode(0x23);
8387 ins_encode( OpcP, RegMem( dst, src) );
8388 ins_pipe( ialu_reg_mem );
8389 %}
8390
8391 // And Memory with Register
8392 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8393 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8394 effect(KILL cr);
8395
8396 ins_cost(150);
8397 format %{ "AND $dst,$src" %}
8398 opcode(0x21); /* Opcode 21 /r */
8399 ins_encode( OpcP, RegMem( src, dst ) );
8400 ins_pipe( ialu_mem_reg );
8401 %}
8402
8403 // And Memory with Immediate
8404 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8405 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8406 effect(KILL cr);
8407
8408 ins_cost(125);
8409 format %{ "AND $dst,$src" %}
8410 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8411 // ins_encode( MemImm( dst, src) );
8412 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8413 ins_pipe( ialu_mem_imm );
8414 %}
8415
8416 // Or Instructions
8417 // Or Register with Register
8418 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8419 match(Set dst (OrI dst src));
8420 effect(KILL cr);
8421
8422 size(2);
8423 format %{ "OR $dst,$src" %}
8424 opcode(0x0B);
8425 ins_encode( OpcP, RegReg( dst, src) );
8426 ins_pipe( ialu_reg_reg );
8427 %}
8428
8429 // Or Register with Immediate
8430 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8431 match(Set dst (OrI dst src));
8432 effect(KILL cr);
8433
8434 format %{ "OR $dst,$src" %}
8435 opcode(0x81,0x01); /* Opcode 81 /1 id */
8436 // ins_encode( RegImm( dst, src) );
8437 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8438 ins_pipe( ialu_reg );
8439 %}
8440
8441 // Or Register with Memory
8442 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8443 match(Set dst (OrI dst (LoadI src)));
8444 effect(KILL cr);
8445
8446 ins_cost(125);
8447 format %{ "OR $dst,$src" %}
8448 opcode(0x0B);
8449 ins_encode( OpcP, RegMem( dst, src) );
8450 ins_pipe( ialu_reg_mem );
8451 %}
8452
8453 // Or Memory with Register
8454 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8455 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8456 effect(KILL cr);
8457
8458 ins_cost(150);
8459 format %{ "OR $dst,$src" %}
8460 opcode(0x09); /* Opcode 09 /r */
8461 ins_encode( OpcP, RegMem( src, dst ) );
8462 ins_pipe( ialu_mem_reg );
8463 %}
8464
8465 // Or Memory with Immediate
8466 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8467 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8468 effect(KILL cr);
8469
8470 ins_cost(125);
8471 format %{ "OR $dst,$src" %}
8472 opcode(0x81,0x1); /* Opcode 81 /1 id */
8473 // ins_encode( MemImm( dst, src) );
8474 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8475 ins_pipe( ialu_mem_imm );
8476 %}
8477
8478 // ROL/ROR
8479 // ROL expand
8480 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8481 effect(USE_DEF dst, USE shift, KILL cr);
8482
8483 format %{ "ROL $dst, $shift" %}
8484 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8485 ins_encode( OpcP, RegOpc( dst ));
8486 ins_pipe( ialu_reg );
8487 %}
8488
8489 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8490 effect(USE_DEF dst, USE shift, KILL cr);
8491
8492 format %{ "ROL $dst, $shift" %}
8493 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8494 ins_encode( RegOpcImm(dst, shift) );
8495 ins_pipe(ialu_reg);
8496 %}
8497
8498 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8499 effect(USE_DEF dst, USE shift, KILL cr);
8500
8501 format %{ "ROL $dst, $shift" %}
8502 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8503 ins_encode(OpcP, RegOpc(dst));
8504 ins_pipe( ialu_reg_reg );
8505 %}
8506 // end of ROL expand
8507
8508 // ROL 32bit by one once
8509 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8510 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8511
8512 expand %{
8513 rolI_eReg_imm1(dst, lshift, cr);
8514 %}
8515 %}
8516
8517 // ROL 32bit var by imm8 once
8518 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8519 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8520 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8521
8522 expand %{
8523 rolI_eReg_imm8(dst, lshift, cr);
8524 %}
8525 %}
8526
8527 // ROL 32bit var by var once
8528 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8529 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8530
8531 expand %{
8532 rolI_eReg_CL(dst, shift, cr);
8533 %}
8534 %}
8535
8536 // ROL 32bit var by var once
8537 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8538 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8539
8540 expand %{
8541 rolI_eReg_CL(dst, shift, cr);
8542 %}
8543 %}
8544
8545 // ROR expand
8546 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8547 effect(USE_DEF dst, USE shift, KILL cr);
8548
8549 format %{ "ROR $dst, $shift" %}
8550 opcode(0xD1,0x1); /* Opcode D1 /1 */
8551 ins_encode( OpcP, RegOpc( dst ) );
8552 ins_pipe( ialu_reg );
8553 %}
8554
8555 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8556 effect (USE_DEF dst, USE shift, KILL cr);
8557
8558 format %{ "ROR $dst, $shift" %}
8559 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8560 ins_encode( RegOpcImm(dst, shift) );
8561 ins_pipe( ialu_reg );
8562 %}
8563
8564 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8565 effect(USE_DEF dst, USE shift, KILL cr);
8566
8567 format %{ "ROR $dst, $shift" %}
8568 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8569 ins_encode(OpcP, RegOpc(dst));
8570 ins_pipe( ialu_reg_reg );
8571 %}
8572 // end of ROR expand
8573
8574 // ROR right once
8575 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8576 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8577
8578 expand %{
8579 rorI_eReg_imm1(dst, rshift, cr);
8580 %}
8581 %}
8582
8583 // ROR 32bit by immI8 once
8584 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8585 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8586 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8587
8588 expand %{
8589 rorI_eReg_imm8(dst, rshift, cr);
8590 %}
8591 %}
8592
8593 // ROR 32bit var by var once
8594 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8595 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8596
8597 expand %{
8598 rorI_eReg_CL(dst, shift, cr);
8599 %}
8600 %}
8601
8602 // ROR 32bit var by var once
8603 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8604 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8605
8606 expand %{
8607 rorI_eReg_CL(dst, shift, cr);
8608 %}
8609 %}
8610
8611 // Xor Instructions
8612 // Xor Register with Register
8613 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8614 match(Set dst (XorI dst src));
8615 effect(KILL cr);
8616
8617 size(2);
8618 format %{ "XOR $dst,$src" %}
8619 opcode(0x33);
8620 ins_encode( OpcP, RegReg( dst, src) );
8621 ins_pipe( ialu_reg_reg );
8622 %}
8623
8624 // Xor Register with Immediate
8625 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8626 match(Set dst (XorI dst src));
8627 effect(KILL cr);
8628
8629 format %{ "XOR $dst,$src" %}
8630 opcode(0x81,0x06); /* Opcode 81 /6 id */
8631 // ins_encode( RegImm( dst, src) );
8632 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8633 ins_pipe( ialu_reg );
8634 %}
8635
8636 // Xor Register with Memory
8637 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8638 match(Set dst (XorI dst (LoadI src)));
8639 effect(KILL cr);
8640
8641 ins_cost(125);
8642 format %{ "XOR $dst,$src" %}
8643 opcode(0x33);
8644 ins_encode( OpcP, RegMem(dst, src) );
8645 ins_pipe( ialu_reg_mem );
8646 %}
8647
8648 // Xor Memory with Register
8649 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8650 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8651 effect(KILL cr);
8652
8653 ins_cost(150);
8654 format %{ "XOR $dst,$src" %}
8655 opcode(0x31); /* Opcode 31 /r */
8656 ins_encode( OpcP, RegMem( src, dst ) );
8657 ins_pipe( ialu_mem_reg );
8658 %}
8659
8660 // Xor Memory with Immediate
8661 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8662 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8663 effect(KILL cr);
8664
8665 ins_cost(125);
8666 format %{ "XOR $dst,$src" %}
8667 opcode(0x81,0x6); /* Opcode 81 /6 id */
8668 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8669 ins_pipe( ialu_mem_imm );
8670 %}
8671
8672 //----------Convert Int to Boolean---------------------------------------------
8673
8674 instruct movI_nocopy(eRegI dst, eRegI src) %{
8675 effect( DEF dst, USE src );
8676 format %{ "MOV $dst,$src" %}
8677 ins_encode( enc_Copy( dst, src) );
8678 ins_pipe( ialu_reg_reg );
8679 %}
8680
8681 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
8682 effect( USE_DEF dst, USE src, KILL cr );
8683
8684 size(4);
8685 format %{ "NEG $dst\n\t"
8686 "ADC $dst,$src" %}
8687 ins_encode( neg_reg(dst),
8688 OpcRegReg(0x13,dst,src) );
8689 ins_pipe( ialu_reg_reg_long );
8690 %}
8691
8692 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
8693 match(Set dst (Conv2B src));
8694
8695 expand %{
8696 movI_nocopy(dst,src);
8697 ci2b(dst,src,cr);
8698 %}
8699 %}
8700
8701 instruct movP_nocopy(eRegI dst, eRegP src) %{
8702 effect( DEF dst, USE src );
8703 format %{ "MOV $dst,$src" %}
8704 ins_encode( enc_Copy( dst, src) );
8705 ins_pipe( ialu_reg_reg );
8706 %}
8707
8708 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
8709 effect( USE_DEF dst, USE src, KILL cr );
8710 format %{ "NEG $dst\n\t"
8711 "ADC $dst,$src" %}
8712 ins_encode( neg_reg(dst),
8713 OpcRegReg(0x13,dst,src) );
8714 ins_pipe( ialu_reg_reg_long );
8715 %}
8716
8717 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
8718 match(Set dst (Conv2B src));
8719
8720 expand %{
8721 movP_nocopy(dst,src);
8722 cp2b(dst,src,cr);
8723 %}
8724 %}
8725
8726 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
8727 match(Set dst (CmpLTMask p q));
8728 effect( KILL cr );
8729 ins_cost(400);
8730
8731 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8732 format %{ "XOR $dst,$dst\n\t"
8733 "CMP $p,$q\n\t"
8734 "SETlt $dst\n\t"
8735 "NEG $dst" %}
8736 ins_encode( OpcRegReg(0x33,dst,dst),
8737 OpcRegReg(0x3B,p,q),
8738 setLT_reg(dst), neg_reg(dst) );
8739 ins_pipe( pipe_slow );
8740 %}
8741
8742 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
8743 match(Set dst (CmpLTMask dst zero));
8744 effect( DEF dst, KILL cr );
8745 ins_cost(100);
8746
8747 format %{ "SAR $dst,31" %}
8748 opcode(0xC1, 0x7); /* C1 /7 ib */
8749 ins_encode( RegOpcImm( dst, 0x1F ) );
8750 ins_pipe( ialu_reg );
8751 %}
8752
8753
8754 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
8755 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8756 effect( KILL tmp, KILL cr );
8757 ins_cost(400);
8758 // annoyingly, $tmp has no edges so you cant ask for it in
8759 // any format or encoding
8760 format %{ "SUB $p,$q\n\t"
8761 "SBB ECX,ECX\n\t"
8762 "AND ECX,$y\n\t"
8763 "ADD $p,ECX" %}
8764 ins_encode( enc_cmpLTP(p,q,y,tmp) );
8765 ins_pipe( pipe_cmplt );
8766 %}
8767
8768 /* If I enable this, I encourage spilling in the inner loop of compress.
8769 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
8770 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
8771 effect( USE_KILL tmp, KILL cr );
8772 ins_cost(400);
8773
8774 format %{ "SUB $p,$q\n\t"
8775 "SBB ECX,ECX\n\t"
8776 "AND ECX,$y\n\t"
8777 "ADD $p,ECX" %}
8778 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
8779 %}
8780 */
8781
8782 //----------Long Instructions------------------------------------------------
8783 // Add Long Register with Register
8784 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8785 match(Set dst (AddL dst src));
8786 effect(KILL cr);
8787 ins_cost(200);
8788 format %{ "ADD $dst.lo,$src.lo\n\t"
8789 "ADC $dst.hi,$src.hi" %}
8790 opcode(0x03, 0x13);
8791 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8792 ins_pipe( ialu_reg_reg_long );
8793 %}
8794
8795 // Add Long Register with Immediate
8796 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8797 match(Set dst (AddL dst src));
8798 effect(KILL cr);
8799 format %{ "ADD $dst.lo,$src.lo\n\t"
8800 "ADC $dst.hi,$src.hi" %}
8801 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
8802 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8803 ins_pipe( ialu_reg_long );
8804 %}
8805
8806 // Add Long Register with Memory
8807 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8808 match(Set dst (AddL dst (LoadL mem)));
8809 effect(KILL cr);
8810 ins_cost(125);
8811 format %{ "ADD $dst.lo,$mem\n\t"
8812 "ADC $dst.hi,$mem+4" %}
8813 opcode(0x03, 0x13);
8814 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8815 ins_pipe( ialu_reg_long_mem );
8816 %}
8817
8818 // Subtract Long Register with Register.
8819 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8820 match(Set dst (SubL dst src));
8821 effect(KILL cr);
8822 ins_cost(200);
8823 format %{ "SUB $dst.lo,$src.lo\n\t"
8824 "SBB $dst.hi,$src.hi" %}
8825 opcode(0x2B, 0x1B);
8826 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
8827 ins_pipe( ialu_reg_reg_long );
8828 %}
8829
8830 // Subtract Long Register with Immediate
8831 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8832 match(Set dst (SubL dst src));
8833 effect(KILL cr);
8834 format %{ "SUB $dst.lo,$src.lo\n\t"
8835 "SBB $dst.hi,$src.hi" %}
8836 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
8837 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8838 ins_pipe( ialu_reg_long );
8839 %}
8840
8841 // Subtract Long Register with Memory
8842 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8843 match(Set dst (SubL dst (LoadL mem)));
8844 effect(KILL cr);
8845 ins_cost(125);
8846 format %{ "SUB $dst.lo,$mem\n\t"
8847 "SBB $dst.hi,$mem+4" %}
8848 opcode(0x2B, 0x1B);
8849 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8850 ins_pipe( ialu_reg_long_mem );
8851 %}
8852
8853 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
8854 match(Set dst (SubL zero dst));
8855 effect(KILL cr);
8856 ins_cost(300);
8857 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
8858 ins_encode( neg_long(dst) );
8859 ins_pipe( ialu_reg_reg_long );
8860 %}
8861
8862 // And Long Register with Register
8863 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8864 match(Set dst (AndL dst src));
8865 effect(KILL cr);
8866 format %{ "AND $dst.lo,$src.lo\n\t"
8867 "AND $dst.hi,$src.hi" %}
8868 opcode(0x23,0x23);
8869 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8870 ins_pipe( ialu_reg_reg_long );
8871 %}
8872
8873 // And Long Register with Immediate
8874 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8875 match(Set dst (AndL dst src));
8876 effect(KILL cr);
8877 format %{ "AND $dst.lo,$src.lo\n\t"
8878 "AND $dst.hi,$src.hi" %}
8879 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
8880 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8881 ins_pipe( ialu_reg_long );
8882 %}
8883
8884 // And Long Register with Memory
8885 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8886 match(Set dst (AndL dst (LoadL mem)));
8887 effect(KILL cr);
8888 ins_cost(125);
8889 format %{ "AND $dst.lo,$mem\n\t"
8890 "AND $dst.hi,$mem+4" %}
8891 opcode(0x23, 0x23);
8892 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8893 ins_pipe( ialu_reg_long_mem );
8894 %}
8895
8896 // Or Long Register with Register
8897 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8898 match(Set dst (OrL dst src));
8899 effect(KILL cr);
8900 format %{ "OR $dst.lo,$src.lo\n\t"
8901 "OR $dst.hi,$src.hi" %}
8902 opcode(0x0B,0x0B);
8903 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8904 ins_pipe( ialu_reg_reg_long );
8905 %}
8906
8907 // Or Long Register with Immediate
8908 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8909 match(Set dst (OrL dst src));
8910 effect(KILL cr);
8911 format %{ "OR $dst.lo,$src.lo\n\t"
8912 "OR $dst.hi,$src.hi" %}
8913 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
8914 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8915 ins_pipe( ialu_reg_long );
8916 %}
8917
8918 // Or Long Register with Memory
8919 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8920 match(Set dst (OrL dst (LoadL mem)));
8921 effect(KILL cr);
8922 ins_cost(125);
8923 format %{ "OR $dst.lo,$mem\n\t"
8924 "OR $dst.hi,$mem+4" %}
8925 opcode(0x0B,0x0B);
8926 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8927 ins_pipe( ialu_reg_long_mem );
8928 %}
8929
8930 // Xor Long Register with Register
8931 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
8932 match(Set dst (XorL dst src));
8933 effect(KILL cr);
8934 format %{ "XOR $dst.lo,$src.lo\n\t"
8935 "XOR $dst.hi,$src.hi" %}
8936 opcode(0x33,0x33);
8937 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
8938 ins_pipe( ialu_reg_reg_long );
8939 %}
8940
8941 // Xor Long Register with Immediate
8942 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
8943 match(Set dst (XorL dst src));
8944 effect(KILL cr);
8945 format %{ "XOR $dst.lo,$src.lo\n\t"
8946 "XOR $dst.hi,$src.hi" %}
8947 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
8948 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
8949 ins_pipe( ialu_reg_long );
8950 %}
8951
8952 // Xor Long Register with Memory
8953 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
8954 match(Set dst (XorL dst (LoadL mem)));
8955 effect(KILL cr);
8956 ins_cost(125);
8957 format %{ "XOR $dst.lo,$mem\n\t"
8958 "XOR $dst.hi,$mem+4" %}
8959 opcode(0x33,0x33);
8960 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
8961 ins_pipe( ialu_reg_long_mem );
8962 %}
8963
8964 // Shift Left Long by 1
8965 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
8966 predicate(UseNewLongLShift);
8967 match(Set dst (LShiftL dst cnt));
8968 effect(KILL cr);
8969 ins_cost(100);
8970 format %{ "ADD $dst.lo,$dst.lo\n\t"
8971 "ADC $dst.hi,$dst.hi" %}
8972 ins_encode %{
8973 __ addl($dst$$Register,$dst$$Register);
8974 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8975 %}
8976 ins_pipe( ialu_reg_long );
8977 %}
8978
8979 // Shift Left Long by 2
8980 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
8981 predicate(UseNewLongLShift);
8982 match(Set dst (LShiftL dst cnt));
8983 effect(KILL cr);
8984 ins_cost(100);
8985 format %{ "ADD $dst.lo,$dst.lo\n\t"
8986 "ADC $dst.hi,$dst.hi\n\t"
8987 "ADD $dst.lo,$dst.lo\n\t"
8988 "ADC $dst.hi,$dst.hi" %}
8989 ins_encode %{
8990 __ addl($dst$$Register,$dst$$Register);
8991 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8992 __ addl($dst$$Register,$dst$$Register);
8993 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
8994 %}
8995 ins_pipe( ialu_reg_long );
8996 %}
8997
8998 // Shift Left Long by 3
8999 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9000 predicate(UseNewLongLShift);
9001 match(Set dst (LShiftL dst cnt));
9002 effect(KILL cr);
9003 ins_cost(100);
9004 format %{ "ADD $dst.lo,$dst.lo\n\t"
9005 "ADC $dst.hi,$dst.hi\n\t"
9006 "ADD $dst.lo,$dst.lo\n\t"
9007 "ADC $dst.hi,$dst.hi\n\t"
9008 "ADD $dst.lo,$dst.lo\n\t"
9009 "ADC $dst.hi,$dst.hi" %}
9010 ins_encode %{
9011 __ addl($dst$$Register,$dst$$Register);
9012 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9013 __ addl($dst$$Register,$dst$$Register);
9014 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9015 __ addl($dst$$Register,$dst$$Register);
9016 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9017 %}
9018 ins_pipe( ialu_reg_long );
9019 %}
9020
9021 // Shift Left Long by 1-31
9022 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9023 match(Set dst (LShiftL dst cnt));
9024 effect(KILL cr);
9025 ins_cost(200);
9026 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9027 "SHL $dst.lo,$cnt" %}
9028 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9029 ins_encode( move_long_small_shift(dst,cnt) );
9030 ins_pipe( ialu_reg_long );
9031 %}
9032
9033 // Shift Left Long by 32-63
9034 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9035 match(Set dst (LShiftL dst cnt));
9036 effect(KILL cr);
9037 ins_cost(300);
9038 format %{ "MOV $dst.hi,$dst.lo\n"
9039 "\tSHL $dst.hi,$cnt-32\n"
9040 "\tXOR $dst.lo,$dst.lo" %}
9041 opcode(0xC1, 0x4); /* C1 /4 ib */
9042 ins_encode( move_long_big_shift_clr(dst,cnt) );
9043 ins_pipe( ialu_reg_long );
9044 %}
9045
9046 // Shift Left Long by variable
9047 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9048 match(Set dst (LShiftL dst shift));
9049 effect(KILL cr);
9050 ins_cost(500+200);
9051 size(17);
9052 format %{ "TEST $shift,32\n\t"
9053 "JEQ,s small\n\t"
9054 "MOV $dst.hi,$dst.lo\n\t"
9055 "XOR $dst.lo,$dst.lo\n"
9056 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9057 "SHL $dst.lo,$shift" %}
9058 ins_encode( shift_left_long( dst, shift ) );
9059 ins_pipe( pipe_slow );
9060 %}
9061
9062 // Shift Right Long by 1-31
9063 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9064 match(Set dst (URShiftL dst cnt));
9065 effect(KILL cr);
9066 ins_cost(200);
9067 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9068 "SHR $dst.hi,$cnt" %}
9069 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9070 ins_encode( move_long_small_shift(dst,cnt) );
9071 ins_pipe( ialu_reg_long );
9072 %}
9073
9074 // Shift Right Long by 32-63
9075 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9076 match(Set dst (URShiftL dst cnt));
9077 effect(KILL cr);
9078 ins_cost(300);
9079 format %{ "MOV $dst.lo,$dst.hi\n"
9080 "\tSHR $dst.lo,$cnt-32\n"
9081 "\tXOR $dst.hi,$dst.hi" %}
9082 opcode(0xC1, 0x5); /* C1 /5 ib */
9083 ins_encode( move_long_big_shift_clr(dst,cnt) );
9084 ins_pipe( ialu_reg_long );
9085 %}
9086
9087 // Shift Right Long by variable
9088 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9089 match(Set dst (URShiftL dst shift));
9090 effect(KILL cr);
9091 ins_cost(600);
9092 size(17);
9093 format %{ "TEST $shift,32\n\t"
9094 "JEQ,s small\n\t"
9095 "MOV $dst.lo,$dst.hi\n\t"
9096 "XOR $dst.hi,$dst.hi\n"
9097 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9098 "SHR $dst.hi,$shift" %}
9099 ins_encode( shift_right_long( dst, shift ) );
9100 ins_pipe( pipe_slow );
9101 %}
9102
9103 // Shift Right Long by 1-31
9104 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9105 match(Set dst (RShiftL dst cnt));
9106 effect(KILL cr);
9107 ins_cost(200);
9108 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9109 "SAR $dst.hi,$cnt" %}
9110 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9111 ins_encode( move_long_small_shift(dst,cnt) );
9112 ins_pipe( ialu_reg_long );
9113 %}
9114
9115 // Shift Right Long by 32-63
9116 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9117 match(Set dst (RShiftL dst cnt));
9118 effect(KILL cr);
9119 ins_cost(300);
9120 format %{ "MOV $dst.lo,$dst.hi\n"
9121 "\tSAR $dst.lo,$cnt-32\n"
9122 "\tSAR $dst.hi,31" %}
9123 opcode(0xC1, 0x7); /* C1 /7 ib */
9124 ins_encode( move_long_big_shift_sign(dst,cnt) );
9125 ins_pipe( ialu_reg_long );
9126 %}
9127
9128 // Shift Right arithmetic Long by variable
9129 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9130 match(Set dst (RShiftL dst shift));
9131 effect(KILL cr);
9132 ins_cost(600);
9133 size(18);
9134 format %{ "TEST $shift,32\n\t"
9135 "JEQ,s small\n\t"
9136 "MOV $dst.lo,$dst.hi\n\t"
9137 "SAR $dst.hi,31\n"
9138 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9139 "SAR $dst.hi,$shift" %}
9140 ins_encode( shift_right_arith_long( dst, shift ) );
9141 ins_pipe( pipe_slow );
9142 %}
9143
9144
9145 //----------Double Instructions------------------------------------------------
9146 // Double Math
9147
9148 // Compare & branch
9149
9150 // P6 version of float compare, sets condition codes in EFLAGS
9151 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9152 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9153 match(Set cr (CmpD src1 src2));
9154 effect(KILL rax);
9155 ins_cost(150);
9156 format %{ "FLD $src1\n\t"
9157 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9158 "JNP exit\n\t"
9159 "MOV ah,1 // saw a NaN, set CF\n\t"
9160 "SAHF\n"
9161 "exit:\tNOP // avoid branch to branch" %}
9162 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9163 ins_encode( Push_Reg_D(src1),
9164 OpcP, RegOpc(src2),
9165 cmpF_P6_fixup );
9166 ins_pipe( pipe_slow );
9167 %}
9168
9169 // Compare & branch
9170 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9171 predicate(UseSSE<=1);
9172 match(Set cr (CmpD src1 src2));
9173 effect(KILL rax);
9174 ins_cost(200);
9175 format %{ "FLD $src1\n\t"
9176 "FCOMp $src2\n\t"
9177 "FNSTSW AX\n\t"
9178 "TEST AX,0x400\n\t"
9179 "JZ,s flags\n\t"
9180 "MOV AH,1\t# unordered treat as LT\n"
9181 "flags:\tSAHF" %}
9182 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9183 ins_encode( Push_Reg_D(src1),
9184 OpcP, RegOpc(src2),
9185 fpu_flags);
9186 ins_pipe( pipe_slow );
9187 %}
9188
9189 // Compare vs zero into -1,0,1
9190 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9191 predicate(UseSSE<=1);
9192 match(Set dst (CmpD3 src1 zero));
9193 effect(KILL cr, KILL rax);
9194 ins_cost(280);
9195 format %{ "FTSTD $dst,$src1" %}
9196 opcode(0xE4, 0xD9);
9197 ins_encode( Push_Reg_D(src1),
9198 OpcS, OpcP, PopFPU,
9199 CmpF_Result(dst));
9200 ins_pipe( pipe_slow );
9201 %}
9202
9203 // Compare into -1,0,1
9204 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9205 predicate(UseSSE<=1);
9206 match(Set dst (CmpD3 src1 src2));
9207 effect(KILL cr, KILL rax);
9208 ins_cost(300);
9209 format %{ "FCMPD $dst,$src1,$src2" %}
9210 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9211 ins_encode( Push_Reg_D(src1),
9212 OpcP, RegOpc(src2),
9213 CmpF_Result(dst));
9214 ins_pipe( pipe_slow );
9215 %}
9216
9217 // float compare and set condition codes in EFLAGS by XMM regs
9218 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9219 predicate(UseSSE>=2);
9220 match(Set cr (CmpD dst src));
9221 effect(KILL rax);
9222 ins_cost(125);
9223 format %{ "COMISD $dst,$src\n"
9224 "\tJNP exit\n"
9225 "\tMOV ah,1 // saw a NaN, set CF\n"
9226 "\tSAHF\n"
9227 "exit:\tNOP // avoid branch to branch" %}
9228 opcode(0x66, 0x0F, 0x2F);
9229 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9230 ins_pipe( pipe_slow );
9231 %}
9232
9233 // float compare and set condition codes in EFLAGS by XMM regs
9234 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9235 predicate(UseSSE>=2);
9236 match(Set cr (CmpD dst (LoadD src)));
9237 effect(KILL rax);
9238 ins_cost(145);
9239 format %{ "COMISD $dst,$src\n"
9240 "\tJNP exit\n"
9241 "\tMOV ah,1 // saw a NaN, set CF\n"
9242 "\tSAHF\n"
9243 "exit:\tNOP // avoid branch to branch" %}
9244 opcode(0x66, 0x0F, 0x2F);
9245 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9246 ins_pipe( pipe_slow );
9247 %}
9248
9249 // Compare into -1,0,1 in XMM
9250 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9251 predicate(UseSSE>=2);
9252 match(Set dst (CmpD3 src1 src2));
9253 effect(KILL cr);
9254 ins_cost(255);
9255 format %{ "XOR $dst,$dst\n"
9256 "\tCOMISD $src1,$src2\n"
9257 "\tJP,s nan\n"
9258 "\tJEQ,s exit\n"
9259 "\tJA,s inc\n"
9260 "nan:\tDEC $dst\n"
9261 "\tJMP,s exit\n"
9262 "inc:\tINC $dst\n"
9263 "exit:"
9264 %}
9265 opcode(0x66, 0x0F, 0x2F);
9266 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9267 CmpX_Result(dst));
9268 ins_pipe( pipe_slow );
9269 %}
9270
9271 // Compare into -1,0,1 in XMM and memory
9272 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9273 predicate(UseSSE>=2);
9274 match(Set dst (CmpD3 src1 (LoadD mem)));
9275 effect(KILL cr);
9276 ins_cost(275);
9277 format %{ "COMISD $src1,$mem\n"
9278 "\tMOV $dst,0\t\t# do not blow flags\n"
9279 "\tJP,s nan\n"
9280 "\tJEQ,s exit\n"
9281 "\tJA,s inc\n"
9282 "nan:\tDEC $dst\n"
9283 "\tJMP,s exit\n"
9284 "inc:\tINC $dst\n"
9285 "exit:"
9286 %}
9287 opcode(0x66, 0x0F, 0x2F);
9288 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9289 LdImmI(dst,0x0), CmpX_Result(dst));
9290 ins_pipe( pipe_slow );
9291 %}
9292
9293
9294 instruct subD_reg(regD dst, regD src) %{
9295 predicate (UseSSE <=1);
9296 match(Set dst (SubD dst src));
9297
9298 format %{ "FLD $src\n\t"
9299 "DSUBp $dst,ST" %}
9300 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9301 ins_cost(150);
9302 ins_encode( Push_Reg_D(src),
9303 OpcP, RegOpc(dst) );
9304 ins_pipe( fpu_reg_reg );
9305 %}
9306
9307 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9308 predicate (UseSSE <=1);
9309 match(Set dst (RoundDouble (SubD src1 src2)));
9310 ins_cost(250);
9311
9312 format %{ "FLD $src2\n\t"
9313 "DSUB ST,$src1\n\t"
9314 "FSTP_D $dst\t# D-round" %}
9315 opcode(0xD8, 0x5);
9316 ins_encode( Push_Reg_D(src2),
9317 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9318 ins_pipe( fpu_mem_reg_reg );
9319 %}
9320
9321
9322 instruct subD_reg_mem(regD dst, memory src) %{
9323 predicate (UseSSE <=1);
9324 match(Set dst (SubD dst (LoadD src)));
9325 ins_cost(150);
9326
9327 format %{ "FLD $src\n\t"
9328 "DSUBp $dst,ST" %}
9329 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9330 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9331 OpcP, RegOpc(dst) );
9332 ins_pipe( fpu_reg_mem );
9333 %}
9334
9335 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9336 predicate (UseSSE<=1);
9337 match(Set dst (AbsD src));
9338 ins_cost(100);
9339 format %{ "FABS" %}
9340 opcode(0xE1, 0xD9);
9341 ins_encode( OpcS, OpcP );
9342 ins_pipe( fpu_reg_reg );
9343 %}
9344
9345 instruct absXD_reg( regXD dst ) %{
9346 predicate(UseSSE>=2);
9347 match(Set dst (AbsD dst));
9348 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9349 ins_encode( AbsXD_encoding(dst));
9350 ins_pipe( pipe_slow );
9351 %}
9352
9353 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9354 predicate(UseSSE<=1);
9355 match(Set dst (NegD src));
9356 ins_cost(100);
9357 format %{ "FCHS" %}
9358 opcode(0xE0, 0xD9);
9359 ins_encode( OpcS, OpcP );
9360 ins_pipe( fpu_reg_reg );
9361 %}
9362
9363 instruct negXD_reg( regXD dst ) %{
9364 predicate(UseSSE>=2);
9365 match(Set dst (NegD dst));
9366 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9367 ins_encode %{
9368 __ xorpd($dst$$XMMRegister,
9369 ExternalAddress((address)double_signflip_pool));
9370 %}
9371 ins_pipe( pipe_slow );
9372 %}
9373
9374 instruct addD_reg(regD dst, regD src) %{
9375 predicate(UseSSE<=1);
9376 match(Set dst (AddD dst src));
9377 format %{ "FLD $src\n\t"
9378 "DADD $dst,ST" %}
9379 size(4);
9380 ins_cost(150);
9381 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9382 ins_encode( Push_Reg_D(src),
9383 OpcP, RegOpc(dst) );
9384 ins_pipe( fpu_reg_reg );
9385 %}
9386
9387
9388 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9389 predicate(UseSSE<=1);
9390 match(Set dst (RoundDouble (AddD src1 src2)));
9391 ins_cost(250);
9392
9393 format %{ "FLD $src2\n\t"
9394 "DADD ST,$src1\n\t"
9395 "FSTP_D $dst\t# D-round" %}
9396 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9397 ins_encode( Push_Reg_D(src2),
9398 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9399 ins_pipe( fpu_mem_reg_reg );
9400 %}
9401
9402
9403 instruct addD_reg_mem(regD dst, memory src) %{
9404 predicate(UseSSE<=1);
9405 match(Set dst (AddD dst (LoadD src)));
9406 ins_cost(150);
9407
9408 format %{ "FLD $src\n\t"
9409 "DADDp $dst,ST" %}
9410 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9411 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9412 OpcP, RegOpc(dst) );
9413 ins_pipe( fpu_reg_mem );
9414 %}
9415
9416 // add-to-memory
9417 instruct addD_mem_reg(memory dst, regD src) %{
9418 predicate(UseSSE<=1);
9419 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9420 ins_cost(150);
9421
9422 format %{ "FLD_D $dst\n\t"
9423 "DADD ST,$src\n\t"
9424 "FST_D $dst" %}
9425 opcode(0xDD, 0x0);
9426 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9427 Opcode(0xD8), RegOpc(src),
9428 set_instruction_start,
9429 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9430 ins_pipe( fpu_reg_mem );
9431 %}
9432
9433 instruct addD_reg_imm1(regD dst, immD1 src) %{
9434 predicate(UseSSE<=1);
9435 match(Set dst (AddD dst src));
9436 ins_cost(125);
9437 format %{ "FLD1\n\t"
9438 "DADDp $dst,ST" %}
9439 opcode(0xDE, 0x00);
9440 ins_encode( LdImmD(src),
9441 OpcP, RegOpc(dst) );
9442 ins_pipe( fpu_reg );
9443 %}
9444
9445 instruct addD_reg_imm(regD dst, immD src) %{
9446 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9447 match(Set dst (AddD dst src));
9448 ins_cost(200);
9449 format %{ "FLD_D [$src]\n\t"
9450 "DADDp $dst,ST" %}
9451 opcode(0xDE, 0x00); /* DE /0 */
9452 ins_encode( LdImmD(src),
9453 OpcP, RegOpc(dst));
9454 ins_pipe( fpu_reg_mem );
9455 %}
9456
9457 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9458 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9459 match(Set dst (RoundDouble (AddD src con)));
9460 ins_cost(200);
9461 format %{ "FLD_D [$con]\n\t"
9462 "DADD ST,$src\n\t"
9463 "FSTP_D $dst\t# D-round" %}
9464 opcode(0xD8, 0x00); /* D8 /0 */
9465 ins_encode( LdImmD(con),
9466 OpcP, RegOpc(src), Pop_Mem_D(dst));
9467 ins_pipe( fpu_mem_reg_con );
9468 %}
9469
9470 // Add two double precision floating point values in xmm
9471 instruct addXD_reg(regXD dst, regXD src) %{
9472 predicate(UseSSE>=2);
9473 match(Set dst (AddD dst src));
9474 format %{ "ADDSD $dst,$src" %}
9475 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
9476 ins_pipe( pipe_slow );
9477 %}
9478
9479 instruct addXD_imm(regXD dst, immXD con) %{
9480 predicate(UseSSE>=2);
9481 match(Set dst (AddD dst con));
9482 format %{ "ADDSD $dst,[$con]" %}
9483 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
9484 ins_pipe( pipe_slow );
9485 %}
9486
9487 instruct addXD_mem(regXD dst, memory mem) %{
9488 predicate(UseSSE>=2);
9489 match(Set dst (AddD dst (LoadD mem)));
9490 format %{ "ADDSD $dst,$mem" %}
9491 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
9492 ins_pipe( pipe_slow );
9493 %}
9494
9495 // Sub two double precision floating point values in xmm
9496 instruct subXD_reg(regXD dst, regXD src) %{
9497 predicate(UseSSE>=2);
9498 match(Set dst (SubD dst src));
9499 format %{ "SUBSD $dst,$src" %}
9500 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
9501 ins_pipe( pipe_slow );
9502 %}
9503
9504 instruct subXD_imm(regXD dst, immXD con) %{
9505 predicate(UseSSE>=2);
9506 match(Set dst (SubD dst con));
9507 format %{ "SUBSD $dst,[$con]" %}
9508 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
9509 ins_pipe( pipe_slow );
9510 %}
9511
9512 instruct subXD_mem(regXD dst, memory mem) %{
9513 predicate(UseSSE>=2);
9514 match(Set dst (SubD dst (LoadD mem)));
9515 format %{ "SUBSD $dst,$mem" %}
9516 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
9517 ins_pipe( pipe_slow );
9518 %}
9519
9520 // Mul two double precision floating point values in xmm
9521 instruct mulXD_reg(regXD dst, regXD src) %{
9522 predicate(UseSSE>=2);
9523 match(Set dst (MulD dst src));
9524 format %{ "MULSD $dst,$src" %}
9525 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
9526 ins_pipe( pipe_slow );
9527 %}
9528
9529 instruct mulXD_imm(regXD dst, immXD con) %{
9530 predicate(UseSSE>=2);
9531 match(Set dst (MulD dst con));
9532 format %{ "MULSD $dst,[$con]" %}
9533 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
9534 ins_pipe( pipe_slow );
9535 %}
9536
9537 instruct mulXD_mem(regXD dst, memory mem) %{
9538 predicate(UseSSE>=2);
9539 match(Set dst (MulD dst (LoadD mem)));
9540 format %{ "MULSD $dst,$mem" %}
9541 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
9542 ins_pipe( pipe_slow );
9543 %}
9544
9545 // Div two double precision floating point values in xmm
9546 instruct divXD_reg(regXD dst, regXD src) %{
9547 predicate(UseSSE>=2);
9548 match(Set dst (DivD dst src));
9549 format %{ "DIVSD $dst,$src" %}
9550 opcode(0xF2, 0x0F, 0x5E);
9551 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
9552 ins_pipe( pipe_slow );
9553 %}
9554
9555 instruct divXD_imm(regXD dst, immXD con) %{
9556 predicate(UseSSE>=2);
9557 match(Set dst (DivD dst con));
9558 format %{ "DIVSD $dst,[$con]" %}
9559 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
9560 ins_pipe( pipe_slow );
9561 %}
9562
9563 instruct divXD_mem(regXD dst, memory mem) %{
9564 predicate(UseSSE>=2);
9565 match(Set dst (DivD dst (LoadD mem)));
9566 format %{ "DIVSD $dst,$mem" %}
9567 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
9568 ins_pipe( pipe_slow );
9569 %}
9570
9571
9572 instruct mulD_reg(regD dst, regD src) %{
9573 predicate(UseSSE<=1);
9574 match(Set dst (MulD dst src));
9575 format %{ "FLD $src\n\t"
9576 "DMULp $dst,ST" %}
9577 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9578 ins_cost(150);
9579 ins_encode( Push_Reg_D(src),
9580 OpcP, RegOpc(dst) );
9581 ins_pipe( fpu_reg_reg );
9582 %}
9583
9584 // Strict FP instruction biases argument before multiply then
9585 // biases result to avoid double rounding of subnormals.
9586 //
9587 // scale arg1 by multiplying arg1 by 2^(-15360)
9588 // load arg2
9589 // multiply scaled arg1 by arg2
9590 // rescale product by 2^(15360)
9591 //
9592 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
9593 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9594 match(Set dst (MulD dst src));
9595 ins_cost(1); // Select this instruction for all strict FP double multiplies
9596
9597 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9598 "DMULp $dst,ST\n\t"
9599 "FLD $src\n\t"
9600 "DMULp $dst,ST\n\t"
9601 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9602 "DMULp $dst,ST\n\t" %}
9603 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9604 ins_encode( strictfp_bias1(dst),
9605 Push_Reg_D(src),
9606 OpcP, RegOpc(dst),
9607 strictfp_bias2(dst) );
9608 ins_pipe( fpu_reg_reg );
9609 %}
9610
9611 instruct mulD_reg_imm(regD dst, immD src) %{
9612 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9613 match(Set dst (MulD dst src));
9614 ins_cost(200);
9615 format %{ "FLD_D [$src]\n\t"
9616 "DMULp $dst,ST" %}
9617 opcode(0xDE, 0x1); /* DE /1 */
9618 ins_encode( LdImmD(src),
9619 OpcP, RegOpc(dst) );
9620 ins_pipe( fpu_reg_mem );
9621 %}
9622
9623
9624 instruct mulD_reg_mem(regD dst, memory src) %{
9625 predicate( UseSSE<=1 );
9626 match(Set dst (MulD dst (LoadD src)));
9627 ins_cost(200);
9628 format %{ "FLD_D $src\n\t"
9629 "DMULp $dst,ST" %}
9630 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9631 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9632 OpcP, RegOpc(dst) );
9633 ins_pipe( fpu_reg_mem );
9634 %}
9635
9636 //
9637 // Cisc-alternate to reg-reg multiply
9638 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
9639 predicate( UseSSE<=1 );
9640 match(Set dst (MulD src (LoadD mem)));
9641 ins_cost(250);
9642 format %{ "FLD_D $mem\n\t"
9643 "DMUL ST,$src\n\t"
9644 "FSTP_D $dst" %}
9645 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9646 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9647 OpcReg_F(src),
9648 Pop_Reg_D(dst) );
9649 ins_pipe( fpu_reg_reg_mem );
9650 %}
9651
9652
9653 // MACRO3 -- addD a mulD
9654 // This instruction is a '2-address' instruction in that the result goes
9655 // back to src2. This eliminates a move from the macro; possibly the
9656 // register allocator will have to add it back (and maybe not).
9657 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
9658 predicate( UseSSE<=1 );
9659 match(Set src2 (AddD (MulD src0 src1) src2));
9660 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9661 "DMUL ST,$src1\n\t"
9662 "DADDp $src2,ST" %}
9663 ins_cost(250);
9664 opcode(0xDD); /* LoadD DD /0 */
9665 ins_encode( Push_Reg_F(src0),
9666 FMul_ST_reg(src1),
9667 FAddP_reg_ST(src2) );
9668 ins_pipe( fpu_reg_reg_reg );
9669 %}
9670
9671
9672 // MACRO3 -- subD a mulD
9673 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
9674 predicate( UseSSE<=1 );
9675 match(Set src2 (SubD (MulD src0 src1) src2));
9676 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9677 "DMUL ST,$src1\n\t"
9678 "DSUBRp $src2,ST" %}
9679 ins_cost(250);
9680 ins_encode( Push_Reg_F(src0),
9681 FMul_ST_reg(src1),
9682 Opcode(0xDE), Opc_plus(0xE0,src2));
9683 ins_pipe( fpu_reg_reg_reg );
9684 %}
9685
9686
9687 instruct divD_reg(regD dst, regD src) %{
9688 predicate( UseSSE<=1 );
9689 match(Set dst (DivD dst src));
9690
9691 format %{ "FLD $src\n\t"
9692 "FDIVp $dst,ST" %}
9693 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9694 ins_cost(150);
9695 ins_encode( Push_Reg_D(src),
9696 OpcP, RegOpc(dst) );
9697 ins_pipe( fpu_reg_reg );
9698 %}
9699
9700 // Strict FP instruction biases argument before division then
9701 // biases result, to avoid double rounding of subnormals.
9702 //
9703 // scale dividend by multiplying dividend by 2^(-15360)
9704 // load divisor
9705 // divide scaled dividend by divisor
9706 // rescale quotient by 2^(15360)
9707 //
9708 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
9709 predicate (UseSSE<=1);
9710 match(Set dst (DivD dst src));
9711 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9712 ins_cost(01);
9713
9714 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9715 "DMULp $dst,ST\n\t"
9716 "FLD $src\n\t"
9717 "FDIVp $dst,ST\n\t"
9718 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9719 "DMULp $dst,ST\n\t" %}
9720 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9721 ins_encode( strictfp_bias1(dst),
9722 Push_Reg_D(src),
9723 OpcP, RegOpc(dst),
9724 strictfp_bias2(dst) );
9725 ins_pipe( fpu_reg_reg );
9726 %}
9727
9728 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9729 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9730 match(Set dst (RoundDouble (DivD src1 src2)));
9731
9732 format %{ "FLD $src1\n\t"
9733 "FDIV ST,$src2\n\t"
9734 "FSTP_D $dst\t# D-round" %}
9735 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9736 ins_encode( Push_Reg_D(src1),
9737 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
9738 ins_pipe( fpu_mem_reg_reg );
9739 %}
9740
9741
9742 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
9743 predicate(UseSSE<=1);
9744 match(Set dst (ModD dst src));
9745 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
9746
9747 format %{ "DMOD $dst,$src" %}
9748 ins_cost(250);
9749 ins_encode(Push_Reg_Mod_D(dst, src),
9750 emitModD(),
9751 Push_Result_Mod_D(src),
9752 Pop_Reg_D(dst));
9753 ins_pipe( pipe_slow );
9754 %}
9755
9756 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
9757 predicate(UseSSE>=2);
9758 match(Set dst (ModD src0 src1));
9759 effect(KILL rax, KILL cr);
9760
9761 format %{ "SUB ESP,8\t # DMOD\n"
9762 "\tMOVSD [ESP+0],$src1\n"
9763 "\tFLD_D [ESP+0]\n"
9764 "\tMOVSD [ESP+0],$src0\n"
9765 "\tFLD_D [ESP+0]\n"
9766 "loop:\tFPREM\n"
9767 "\tFWAIT\n"
9768 "\tFNSTSW AX\n"
9769 "\tSAHF\n"
9770 "\tJP loop\n"
9771 "\tFSTP_D [ESP+0]\n"
9772 "\tMOVSD $dst,[ESP+0]\n"
9773 "\tADD ESP,8\n"
9774 "\tFSTP ST0\t # Restore FPU Stack"
9775 %}
9776 ins_cost(250);
9777 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
9778 ins_pipe( pipe_slow );
9779 %}
9780
9781 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
9782 predicate (UseSSE<=1);
9783 match(Set dst (SinD src));
9784 ins_cost(1800);
9785 format %{ "DSIN $dst" %}
9786 opcode(0xD9, 0xFE);
9787 ins_encode( OpcP, OpcS );
9788 ins_pipe( pipe_slow );
9789 %}
9790
9791 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
9792 predicate (UseSSE>=2);
9793 match(Set dst (SinD dst));
9794 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9795 ins_cost(1800);
9796 format %{ "DSIN $dst" %}
9797 opcode(0xD9, 0xFE);
9798 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9799 ins_pipe( pipe_slow );
9800 %}
9801
9802 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
9803 predicate (UseSSE<=1);
9804 match(Set dst (CosD src));
9805 ins_cost(1800);
9806 format %{ "DCOS $dst" %}
9807 opcode(0xD9, 0xFF);
9808 ins_encode( OpcP, OpcS );
9809 ins_pipe( pipe_slow );
9810 %}
9811
9812 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
9813 predicate (UseSSE>=2);
9814 match(Set dst (CosD dst));
9815 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9816 ins_cost(1800);
9817 format %{ "DCOS $dst" %}
9818 opcode(0xD9, 0xFF);
9819 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9820 ins_pipe( pipe_slow );
9821 %}
9822
9823 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
9824 predicate (UseSSE<=1);
9825 match(Set dst(TanD src));
9826 format %{ "DTAN $dst" %}
9827 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9828 Opcode(0xDD), Opcode(0xD8)); // fstp st
9829 ins_pipe( pipe_slow );
9830 %}
9831
9832 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
9833 predicate (UseSSE>=2);
9834 match(Set dst(TanD dst));
9835 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9836 format %{ "DTAN $dst" %}
9837 ins_encode( Push_SrcXD(dst),
9838 Opcode(0xD9), Opcode(0xF2), // fptan
9839 Opcode(0xDD), Opcode(0xD8), // fstp st
9840 Push_ResultXD(dst) );
9841 ins_pipe( pipe_slow );
9842 %}
9843
9844 instruct atanD_reg(regD dst, regD src) %{
9845 predicate (UseSSE<=1);
9846 match(Set dst(AtanD dst src));
9847 format %{ "DATA $dst,$src" %}
9848 opcode(0xD9, 0xF3);
9849 ins_encode( Push_Reg_D(src),
9850 OpcP, OpcS, RegOpc(dst) );
9851 ins_pipe( pipe_slow );
9852 %}
9853
9854 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
9855 predicate (UseSSE>=2);
9856 match(Set dst(AtanD dst src));
9857 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
9858 format %{ "DATA $dst,$src" %}
9859 opcode(0xD9, 0xF3);
9860 ins_encode( Push_SrcXD(src),
9861 OpcP, OpcS, Push_ResultXD(dst) );
9862 ins_pipe( pipe_slow );
9863 %}
9864
9865 instruct sqrtD_reg(regD dst, regD src) %{
9866 predicate (UseSSE<=1);
9867 match(Set dst (SqrtD src));
9868 format %{ "DSQRT $dst,$src" %}
9869 opcode(0xFA, 0xD9);
9870 ins_encode( Push_Reg_D(src),
9871 OpcS, OpcP, Pop_Reg_D(dst) );
9872 ins_pipe( pipe_slow );
9873 %}
9874
9875 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9876 predicate (UseSSE<=1);
9877 match(Set Y (PowD X Y)); // Raise X to the Yth power
9878 effect(KILL rax, KILL rbx, KILL rcx);
9879 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
9880 "FLD_D $X\n\t"
9881 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
9882
9883 "FDUP \t\t\t# Q Q\n\t"
9884 "FRNDINT\t\t\t# int(Q) Q\n\t"
9885 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9886 "FISTP dword [ESP]\n\t"
9887 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9888 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9889 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9890 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9891 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9892 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9893 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9894 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9895 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9896 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9897 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9898 "MOV [ESP+0],0\n\t"
9899 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9900
9901 "ADD ESP,8"
9902 %}
9903 ins_encode( push_stack_temp_qword,
9904 Push_Reg_D(X),
9905 Opcode(0xD9), Opcode(0xF1), // fyl2x
9906 pow_exp_core_encoding,
9907 pop_stack_temp_qword);
9908 ins_pipe( pipe_slow );
9909 %}
9910
9911 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
9912 predicate (UseSSE>=2);
9913 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9914 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
9915 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
9916 "MOVSD [ESP],$src1\n\t"
9917 "FLD FPR1,$src1\n\t"
9918 "MOVSD [ESP],$src0\n\t"
9919 "FLD FPR1,$src0\n\t"
9920 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
9921
9922 "FDUP \t\t\t# Q Q\n\t"
9923 "FRNDINT\t\t\t# int(Q) Q\n\t"
9924 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9925 "FISTP dword [ESP]\n\t"
9926 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9927 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9928 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9929 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9930 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9931 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9932 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9933 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9934 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9935 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9936 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9937 "MOV [ESP+0],0\n\t"
9938 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9939
9940 "FST_D [ESP]\n\t"
9941 "MOVSD $dst,[ESP]\n\t"
9942 "ADD ESP,8"
9943 %}
9944 ins_encode( push_stack_temp_qword,
9945 push_xmm_to_fpr1(src1),
9946 push_xmm_to_fpr1(src0),
9947 Opcode(0xD9), Opcode(0xF1), // fyl2x
9948 pow_exp_core_encoding,
9949 Push_ResultXD(dst) );
9950 ins_pipe( pipe_slow );
9951 %}
9952
9953
9954 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9955 predicate (UseSSE<=1);
9956 match(Set dpr1 (ExpD dpr1));
9957 effect(KILL rax, KILL rbx, KILL rcx);
9958 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
9959 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
9960 "FMULP \t\t\t# Q=X*log2(e)\n\t"
9961
9962 "FDUP \t\t\t# Q Q\n\t"
9963 "FRNDINT\t\t\t# int(Q) Q\n\t"
9964 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
9965 "FISTP dword [ESP]\n\t"
9966 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
9967 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
9968 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
9969 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
9970 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
9971 "ADD EAX,1023\t\t# Double exponent bias\n\t"
9972 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
9973 "SHL EAX,20\t\t# Shift exponent into place\n\t"
9974 "TEST EBX,ECX\t\t# Check for overflow\n\t"
9975 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
9976 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
9977 "MOV [ESP+0],0\n\t"
9978 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
9979
9980 "ADD ESP,8"
9981 %}
9982 ins_encode( push_stack_temp_qword,
9983 Opcode(0xD9), Opcode(0xEA), // fldl2e
9984 Opcode(0xDE), Opcode(0xC9), // fmulp
9985 pow_exp_core_encoding,
9986 pop_stack_temp_qword);
9987 ins_pipe( pipe_slow );
9988 %}
9989
9990 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
9991 predicate (UseSSE>=2);
9992 match(Set dst (ExpD src));
9993 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
9994 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
9995 "MOVSD [ESP],$src\n\t"
9996 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
9997 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
9998
9999 "FDUP \t\t\t# Q Q\n\t"
10000 "FRNDINT\t\t\t# int(Q) Q\n\t"
10001 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10002 "FISTP dword [ESP]\n\t"
10003 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10004 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10005 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10006 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10007 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10008 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10009 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10010 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10011 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10012 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10013 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10014 "MOV [ESP+0],0\n\t"
10015 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10016
10017 "FST_D [ESP]\n\t"
10018 "MOVSD $dst,[ESP]\n\t"
10019 "ADD ESP,8"
10020 %}
10021 ins_encode( Push_SrcXD(src),
10022 Opcode(0xD9), Opcode(0xEA), // fldl2e
10023 Opcode(0xDE), Opcode(0xC9), // fmulp
10024 pow_exp_core_encoding,
10025 Push_ResultXD(dst) );
10026 ins_pipe( pipe_slow );
10027 %}
10028
10029
10030
10031 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10032 predicate (UseSSE<=1);
10033 // The source Double operand on FPU stack
10034 match(Set dst (Log10D src));
10035 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10036 // fxch ; swap ST(0) with ST(1)
10037 // fyl2x ; compute log_10(2) * log_2(x)
10038 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10039 "FXCH \n\t"
10040 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10041 %}
10042 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10043 Opcode(0xD9), Opcode(0xC9), // fxch
10044 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10045
10046 ins_pipe( pipe_slow );
10047 %}
10048
10049 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10050 predicate (UseSSE>=2);
10051 effect(KILL cr);
10052 match(Set dst (Log10D src));
10053 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10054 // fyl2x ; compute log_10(2) * log_2(x)
10055 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10056 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10057 %}
10058 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10059 Push_SrcXD(src),
10060 Opcode(0xD9), Opcode(0xF1), // fyl2x
10061 Push_ResultXD(dst));
10062
10063 ins_pipe( pipe_slow );
10064 %}
10065
10066 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10067 predicate (UseSSE<=1);
10068 // The source Double operand on FPU stack
10069 match(Set dst (LogD src));
10070 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10071 // fxch ; swap ST(0) with ST(1)
10072 // fyl2x ; compute log_e(2) * log_2(x)
10073 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10074 "FXCH \n\t"
10075 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10076 %}
10077 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10078 Opcode(0xD9), Opcode(0xC9), // fxch
10079 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10080
10081 ins_pipe( pipe_slow );
10082 %}
10083
10084 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10085 predicate (UseSSE>=2);
10086 effect(KILL cr);
10087 // The source and result Double operands in XMM registers
10088 match(Set dst (LogD src));
10089 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10090 // fyl2x ; compute log_e(2) * log_2(x)
10091 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10092 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10093 %}
10094 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10095 Push_SrcXD(src),
10096 Opcode(0xD9), Opcode(0xF1), // fyl2x
10097 Push_ResultXD(dst));
10098 ins_pipe( pipe_slow );
10099 %}
10100
10101 //-------------Float Instructions-------------------------------
10102 // Float Math
10103
10104 // Code for float compare:
10105 // fcompp();
10106 // fwait(); fnstsw_ax();
10107 // sahf();
10108 // movl(dst, unordered_result);
10109 // jcc(Assembler::parity, exit);
10110 // movl(dst, less_result);
10111 // jcc(Assembler::below, exit);
10112 // movl(dst, equal_result);
10113 // jcc(Assembler::equal, exit);
10114 // movl(dst, greater_result);
10115 // exit:
10116
10117 // P6 version of float compare, sets condition codes in EFLAGS
10118 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10119 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10120 match(Set cr (CmpF src1 src2));
10121 effect(KILL rax);
10122 ins_cost(150);
10123 format %{ "FLD $src1\n\t"
10124 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10125 "JNP exit\n\t"
10126 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10127 "SAHF\n"
10128 "exit:\tNOP // avoid branch to branch" %}
10129 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10130 ins_encode( Push_Reg_D(src1),
10131 OpcP, RegOpc(src2),
10132 cmpF_P6_fixup );
10133 ins_pipe( pipe_slow );
10134 %}
10135
10136
10137 // Compare & branch
10138 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10139 predicate(UseSSE == 0);
10140 match(Set cr (CmpF src1 src2));
10141 effect(KILL rax);
10142 ins_cost(200);
10143 format %{ "FLD $src1\n\t"
10144 "FCOMp $src2\n\t"
10145 "FNSTSW AX\n\t"
10146 "TEST AX,0x400\n\t"
10147 "JZ,s flags\n\t"
10148 "MOV AH,1\t# unordered treat as LT\n"
10149 "flags:\tSAHF" %}
10150 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10151 ins_encode( Push_Reg_D(src1),
10152 OpcP, RegOpc(src2),
10153 fpu_flags);
10154 ins_pipe( pipe_slow );
10155 %}
10156
10157 // Compare vs zero into -1,0,1
10158 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10159 predicate(UseSSE == 0);
10160 match(Set dst (CmpF3 src1 zero));
10161 effect(KILL cr, KILL rax);
10162 ins_cost(280);
10163 format %{ "FTSTF $dst,$src1" %}
10164 opcode(0xE4, 0xD9);
10165 ins_encode( Push_Reg_D(src1),
10166 OpcS, OpcP, PopFPU,
10167 CmpF_Result(dst));
10168 ins_pipe( pipe_slow );
10169 %}
10170
10171 // Compare into -1,0,1
10172 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10173 predicate(UseSSE == 0);
10174 match(Set dst (CmpF3 src1 src2));
10175 effect(KILL cr, KILL rax);
10176 ins_cost(300);
10177 format %{ "FCMPF $dst,$src1,$src2" %}
10178 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10179 ins_encode( Push_Reg_D(src1),
10180 OpcP, RegOpc(src2),
10181 CmpF_Result(dst));
10182 ins_pipe( pipe_slow );
10183 %}
10184
10185 // float compare and set condition codes in EFLAGS by XMM regs
10186 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10187 predicate(UseSSE>=1);
10188 match(Set cr (CmpF dst src));
10189 effect(KILL rax);
10190 ins_cost(145);
10191 format %{ "COMISS $dst,$src\n"
10192 "\tJNP exit\n"
10193 "\tMOV ah,1 // saw a NaN, set CF\n"
10194 "\tSAHF\n"
10195 "exit:\tNOP // avoid branch to branch" %}
10196 opcode(0x0F, 0x2F);
10197 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10198 ins_pipe( pipe_slow );
10199 %}
10200
10201 // float compare and set condition codes in EFLAGS by XMM regs
10202 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10203 predicate(UseSSE>=1);
10204 match(Set cr (CmpF dst (LoadF src)));
10205 effect(KILL rax);
10206 ins_cost(165);
10207 format %{ "COMISS $dst,$src\n"
10208 "\tJNP exit\n"
10209 "\tMOV ah,1 // saw a NaN, set CF\n"
10210 "\tSAHF\n"
10211 "exit:\tNOP // avoid branch to branch" %}
10212 opcode(0x0F, 0x2F);
10213 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10214 ins_pipe( pipe_slow );
10215 %}
10216
10217 // Compare into -1,0,1 in XMM
10218 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10219 predicate(UseSSE>=1);
10220 match(Set dst (CmpF3 src1 src2));
10221 effect(KILL cr);
10222 ins_cost(255);
10223 format %{ "XOR $dst,$dst\n"
10224 "\tCOMISS $src1,$src2\n"
10225 "\tJP,s nan\n"
10226 "\tJEQ,s exit\n"
10227 "\tJA,s inc\n"
10228 "nan:\tDEC $dst\n"
10229 "\tJMP,s exit\n"
10230 "inc:\tINC $dst\n"
10231 "exit:"
10232 %}
10233 opcode(0x0F, 0x2F);
10234 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10235 ins_pipe( pipe_slow );
10236 %}
10237
10238 // Compare into -1,0,1 in XMM and memory
10239 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10240 predicate(UseSSE>=1);
10241 match(Set dst (CmpF3 src1 (LoadF mem)));
10242 effect(KILL cr);
10243 ins_cost(275);
10244 format %{ "COMISS $src1,$mem\n"
10245 "\tMOV $dst,0\t\t# do not blow flags\n"
10246 "\tJP,s nan\n"
10247 "\tJEQ,s exit\n"
10248 "\tJA,s inc\n"
10249 "nan:\tDEC $dst\n"
10250 "\tJMP,s exit\n"
10251 "inc:\tINC $dst\n"
10252 "exit:"
10253 %}
10254 opcode(0x0F, 0x2F);
10255 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10256 ins_pipe( pipe_slow );
10257 %}
10258
10259 // Spill to obtain 24-bit precision
10260 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10261 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10262 match(Set dst (SubF src1 src2));
10263
10264 format %{ "FSUB $dst,$src1 - $src2" %}
10265 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10266 ins_encode( Push_Reg_F(src1),
10267 OpcReg_F(src2),
10268 Pop_Mem_F(dst) );
10269 ins_pipe( fpu_mem_reg_reg );
10270 %}
10271 //
10272 // This instruction does not round to 24-bits
10273 instruct subF_reg(regF dst, regF src) %{
10274 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10275 match(Set dst (SubF dst src));
10276
10277 format %{ "FSUB $dst,$src" %}
10278 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10279 ins_encode( Push_Reg_F(src),
10280 OpcP, RegOpc(dst) );
10281 ins_pipe( fpu_reg_reg );
10282 %}
10283
10284 // Spill to obtain 24-bit precision
10285 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10286 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10287 match(Set dst (AddF src1 src2));
10288
10289 format %{ "FADD $dst,$src1,$src2" %}
10290 opcode(0xD8, 0x0); /* D8 C0+i */
10291 ins_encode( Push_Reg_F(src2),
10292 OpcReg_F(src1),
10293 Pop_Mem_F(dst) );
10294 ins_pipe( fpu_mem_reg_reg );
10295 %}
10296 //
10297 // This instruction does not round to 24-bits
10298 instruct addF_reg(regF dst, regF src) %{
10299 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10300 match(Set dst (AddF dst src));
10301
10302 format %{ "FLD $src\n\t"
10303 "FADDp $dst,ST" %}
10304 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10305 ins_encode( Push_Reg_F(src),
10306 OpcP, RegOpc(dst) );
10307 ins_pipe( fpu_reg_reg );
10308 %}
10309
10310 // Add two single precision floating point values in xmm
10311 instruct addX_reg(regX dst, regX src) %{
10312 predicate(UseSSE>=1);
10313 match(Set dst (AddF dst src));
10314 format %{ "ADDSS $dst,$src" %}
10315 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10316 ins_pipe( pipe_slow );
10317 %}
10318
10319 instruct addX_imm(regX dst, immXF con) %{
10320 predicate(UseSSE>=1);
10321 match(Set dst (AddF dst con));
10322 format %{ "ADDSS $dst,[$con]" %}
10323 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10324 ins_pipe( pipe_slow );
10325 %}
10326
10327 instruct addX_mem(regX dst, memory mem) %{
10328 predicate(UseSSE>=1);
10329 match(Set dst (AddF dst (LoadF mem)));
10330 format %{ "ADDSS $dst,$mem" %}
10331 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10332 ins_pipe( pipe_slow );
10333 %}
10334
10335 // Subtract two single precision floating point values in xmm
10336 instruct subX_reg(regX dst, regX src) %{
10337 predicate(UseSSE>=1);
10338 match(Set dst (SubF dst src));
10339 format %{ "SUBSS $dst,$src" %}
10340 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10341 ins_pipe( pipe_slow );
10342 %}
10343
10344 instruct subX_imm(regX dst, immXF con) %{
10345 predicate(UseSSE>=1);
10346 match(Set dst (SubF dst con));
10347 format %{ "SUBSS $dst,[$con]" %}
10348 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10349 ins_pipe( pipe_slow );
10350 %}
10351
10352 instruct subX_mem(regX dst, memory mem) %{
10353 predicate(UseSSE>=1);
10354 match(Set dst (SubF dst (LoadF mem)));
10355 format %{ "SUBSS $dst,$mem" %}
10356 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10357 ins_pipe( pipe_slow );
10358 %}
10359
10360 // Multiply two single precision floating point values in xmm
10361 instruct mulX_reg(regX dst, regX src) %{
10362 predicate(UseSSE>=1);
10363 match(Set dst (MulF dst src));
10364 format %{ "MULSS $dst,$src" %}
10365 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10366 ins_pipe( pipe_slow );
10367 %}
10368
10369 instruct mulX_imm(regX dst, immXF con) %{
10370 predicate(UseSSE>=1);
10371 match(Set dst (MulF dst con));
10372 format %{ "MULSS $dst,[$con]" %}
10373 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10374 ins_pipe( pipe_slow );
10375 %}
10376
10377 instruct mulX_mem(regX dst, memory mem) %{
10378 predicate(UseSSE>=1);
10379 match(Set dst (MulF dst (LoadF mem)));
10380 format %{ "MULSS $dst,$mem" %}
10381 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10382 ins_pipe( pipe_slow );
10383 %}
10384
10385 // Divide two single precision floating point values in xmm
10386 instruct divX_reg(regX dst, regX src) %{
10387 predicate(UseSSE>=1);
10388 match(Set dst (DivF dst src));
10389 format %{ "DIVSS $dst,$src" %}
10390 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10391 ins_pipe( pipe_slow );
10392 %}
10393
10394 instruct divX_imm(regX dst, immXF con) %{
10395 predicate(UseSSE>=1);
10396 match(Set dst (DivF dst con));
10397 format %{ "DIVSS $dst,[$con]" %}
10398 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10399 ins_pipe( pipe_slow );
10400 %}
10401
10402 instruct divX_mem(regX dst, memory mem) %{
10403 predicate(UseSSE>=1);
10404 match(Set dst (DivF dst (LoadF mem)));
10405 format %{ "DIVSS $dst,$mem" %}
10406 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10407 ins_pipe( pipe_slow );
10408 %}
10409
10410 // Get the square root of a single precision floating point values in xmm
10411 instruct sqrtX_reg(regX dst, regX src) %{
10412 predicate(UseSSE>=1);
10413 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10414 format %{ "SQRTSS $dst,$src" %}
10415 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10416 ins_pipe( pipe_slow );
10417 %}
10418
10419 instruct sqrtX_mem(regX dst, memory mem) %{
10420 predicate(UseSSE>=1);
10421 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10422 format %{ "SQRTSS $dst,$mem" %}
10423 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10424 ins_pipe( pipe_slow );
10425 %}
10426
10427 // Get the square root of a double precision floating point values in xmm
10428 instruct sqrtXD_reg(regXD dst, regXD src) %{
10429 predicate(UseSSE>=2);
10430 match(Set dst (SqrtD src));
10431 format %{ "SQRTSD $dst,$src" %}
10432 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10433 ins_pipe( pipe_slow );
10434 %}
10435
10436 instruct sqrtXD_mem(regXD dst, memory mem) %{
10437 predicate(UseSSE>=2);
10438 match(Set dst (SqrtD (LoadD mem)));
10439 format %{ "SQRTSD $dst,$mem" %}
10440 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10441 ins_pipe( pipe_slow );
10442 %}
10443
10444 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10445 predicate(UseSSE==0);
10446 match(Set dst (AbsF src));
10447 ins_cost(100);
10448 format %{ "FABS" %}
10449 opcode(0xE1, 0xD9);
10450 ins_encode( OpcS, OpcP );
10451 ins_pipe( fpu_reg_reg );
10452 %}
10453
10454 instruct absX_reg(regX dst ) %{
10455 predicate(UseSSE>=1);
10456 match(Set dst (AbsF dst));
10457 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
10458 ins_encode( AbsXF_encoding(dst));
10459 ins_pipe( pipe_slow );
10460 %}
10461
10462 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
10463 predicate(UseSSE==0);
10464 match(Set dst (NegF src));
10465 ins_cost(100);
10466 format %{ "FCHS" %}
10467 opcode(0xE0, 0xD9);
10468 ins_encode( OpcS, OpcP );
10469 ins_pipe( fpu_reg_reg );
10470 %}
10471
10472 instruct negX_reg( regX dst ) %{
10473 predicate(UseSSE>=1);
10474 match(Set dst (NegF dst));
10475 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
10476 ins_encode( NegXF_encoding(dst));
10477 ins_pipe( pipe_slow );
10478 %}
10479
10480 // Cisc-alternate to addF_reg
10481 // Spill to obtain 24-bit precision
10482 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10483 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10484 match(Set dst (AddF src1 (LoadF src2)));
10485
10486 format %{ "FLD $src2\n\t"
10487 "FADD ST,$src1\n\t"
10488 "FSTP_S $dst" %}
10489 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10490 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10491 OpcReg_F(src1),
10492 Pop_Mem_F(dst) );
10493 ins_pipe( fpu_mem_reg_mem );
10494 %}
10495 //
10496 // Cisc-alternate to addF_reg
10497 // This instruction does not round to 24-bits
10498 instruct addF_reg_mem(regF dst, memory src) %{
10499 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10500 match(Set dst (AddF dst (LoadF src)));
10501
10502 format %{ "FADD $dst,$src" %}
10503 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10504 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10505 OpcP, RegOpc(dst) );
10506 ins_pipe( fpu_reg_mem );
10507 %}
10508
10509 // // Following two instructions for _222_mpegaudio
10510 // Spill to obtain 24-bit precision
10511 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
10512 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10513 match(Set dst (AddF src1 src2));
10514
10515 format %{ "FADD $dst,$src1,$src2" %}
10516 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10517 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10518 OpcReg_F(src2),
10519 Pop_Mem_F(dst) );
10520 ins_pipe( fpu_mem_reg_mem );
10521 %}
10522
10523 // Cisc-spill variant
10524 // Spill to obtain 24-bit precision
10525 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10526 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10527 match(Set dst (AddF src1 (LoadF src2)));
10528
10529 format %{ "FADD $dst,$src1,$src2 cisc" %}
10530 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10531 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10532 set_instruction_start,
10533 OpcP, RMopc_Mem(secondary,src1),
10534 Pop_Mem_F(dst) );
10535 ins_pipe( fpu_mem_mem_mem );
10536 %}
10537
10538 // Spill to obtain 24-bit precision
10539 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10540 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10541 match(Set dst (AddF src1 src2));
10542
10543 format %{ "FADD $dst,$src1,$src2" %}
10544 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10545 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10546 set_instruction_start,
10547 OpcP, RMopc_Mem(secondary,src1),
10548 Pop_Mem_F(dst) );
10549 ins_pipe( fpu_mem_mem_mem );
10550 %}
10551
10552
10553 // Spill to obtain 24-bit precision
10554 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10555 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10556 match(Set dst (AddF src1 src2));
10557 format %{ "FLD $src1\n\t"
10558 "FADD $src2\n\t"
10559 "FSTP_S $dst" %}
10560 opcode(0xD8, 0x00); /* D8 /0 */
10561 ins_encode( Push_Reg_F(src1),
10562 Opc_MemImm_F(src2),
10563 Pop_Mem_F(dst));
10564 ins_pipe( fpu_mem_reg_con );
10565 %}
10566 //
10567 // This instruction does not round to 24-bits
10568 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
10569 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10570 match(Set dst (AddF src1 src2));
10571 format %{ "FLD $src1\n\t"
10572 "FADD $src2\n\t"
10573 "FSTP_S $dst" %}
10574 opcode(0xD8, 0x00); /* D8 /0 */
10575 ins_encode( Push_Reg_F(src1),
10576 Opc_MemImm_F(src2),
10577 Pop_Reg_F(dst));
10578 ins_pipe( fpu_reg_reg_con );
10579 %}
10580
10581 // Spill to obtain 24-bit precision
10582 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
10583 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10584 match(Set dst (MulF src1 src2));
10585
10586 format %{ "FLD $src1\n\t"
10587 "FMUL $src2\n\t"
10588 "FSTP_S $dst" %}
10589 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10590 ins_encode( Push_Reg_F(src1),
10591 OpcReg_F(src2),
10592 Pop_Mem_F(dst) );
10593 ins_pipe( fpu_mem_reg_reg );
10594 %}
10595 //
10596 // This instruction does not round to 24-bits
10597 instruct mulF_reg(regF dst, regF src1, regF src2) %{
10598 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10599 match(Set dst (MulF src1 src2));
10600
10601 format %{ "FLD $src1\n\t"
10602 "FMUL $src2\n\t"
10603 "FSTP_S $dst" %}
10604 opcode(0xD8, 0x1); /* D8 C8+i */
10605 ins_encode( Push_Reg_F(src2),
10606 OpcReg_F(src1),
10607 Pop_Reg_F(dst) );
10608 ins_pipe( fpu_reg_reg_reg );
10609 %}
10610
10611
10612 // Spill to obtain 24-bit precision
10613 // Cisc-alternate to reg-reg multiply
10614 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10615 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10616 match(Set dst (MulF src1 (LoadF src2)));
10617
10618 format %{ "FLD_S $src2\n\t"
10619 "FMUL $src1\n\t"
10620 "FSTP_S $dst" %}
10621 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10622 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10623 OpcReg_F(src1),
10624 Pop_Mem_F(dst) );
10625 ins_pipe( fpu_mem_reg_mem );
10626 %}
10627 //
10628 // This instruction does not round to 24-bits
10629 // Cisc-alternate to reg-reg multiply
10630 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
10631 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10632 match(Set dst (MulF src1 (LoadF src2)));
10633
10634 format %{ "FMUL $dst,$src1,$src2" %}
10635 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10636 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10637 OpcReg_F(src1),
10638 Pop_Reg_F(dst) );
10639 ins_pipe( fpu_reg_reg_mem );
10640 %}
10641
10642 // Spill to obtain 24-bit precision
10643 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10644 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10645 match(Set dst (MulF src1 src2));
10646
10647 format %{ "FMUL $dst,$src1,$src2" %}
10648 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10649 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10650 set_instruction_start,
10651 OpcP, RMopc_Mem(secondary,src1),
10652 Pop_Mem_F(dst) );
10653 ins_pipe( fpu_mem_mem_mem );
10654 %}
10655
10656 // Spill to obtain 24-bit precision
10657 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
10658 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10659 match(Set dst (MulF src1 src2));
10660
10661 format %{ "FMULc $dst,$src1,$src2" %}
10662 opcode(0xD8, 0x1); /* D8 /1*/
10663 ins_encode( Push_Reg_F(src1),
10664 Opc_MemImm_F(src2),
10665 Pop_Mem_F(dst));
10666 ins_pipe( fpu_mem_reg_con );
10667 %}
10668 //
10669 // This instruction does not round to 24-bits
10670 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
10671 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10672 match(Set dst (MulF src1 src2));
10673
10674 format %{ "FMULc $dst. $src1, $src2" %}
10675 opcode(0xD8, 0x1); /* D8 /1*/
10676 ins_encode( Push_Reg_F(src1),
10677 Opc_MemImm_F(src2),
10678 Pop_Reg_F(dst));
10679 ins_pipe( fpu_reg_reg_con );
10680 %}
10681
10682
10683 //
10684 // MACRO1 -- subsume unshared load into mulF
10685 // This instruction does not round to 24-bits
10686 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
10687 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10688 match(Set dst (MulF (LoadF mem1) src));
10689
10690 format %{ "FLD $mem1 ===MACRO1===\n\t"
10691 "FMUL ST,$src\n\t"
10692 "FSTP $dst" %}
10693 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10694 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10695 OpcReg_F(src),
10696 Pop_Reg_F(dst) );
10697 ins_pipe( fpu_reg_reg_mem );
10698 %}
10699 //
10700 // MACRO2 -- addF a mulF which subsumed an unshared load
10701 // This instruction does not round to 24-bits
10702 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
10703 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10704 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10705 ins_cost(95);
10706
10707 format %{ "FLD $mem1 ===MACRO2===\n\t"
10708 "FMUL ST,$src1 subsume mulF left load\n\t"
10709 "FADD ST,$src2\n\t"
10710 "FSTP $dst" %}
10711 opcode(0xD9); /* LoadF D9 /0 */
10712 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10713 FMul_ST_reg(src1),
10714 FAdd_ST_reg(src2),
10715 Pop_Reg_F(dst) );
10716 ins_pipe( fpu_reg_mem_reg_reg );
10717 %}
10718
10719 // MACRO3 -- addF a mulF
10720 // This instruction does not round to 24-bits. It is a '2-address'
10721 // instruction in that the result goes back to src2. This eliminates
10722 // a move from the macro; possibly the register allocator will have
10723 // to add it back (and maybe not).
10724 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
10725 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10726 match(Set src2 (AddF (MulF src0 src1) src2));
10727
10728 format %{ "FLD $src0 ===MACRO3===\n\t"
10729 "FMUL ST,$src1\n\t"
10730 "FADDP $src2,ST" %}
10731 opcode(0xD9); /* LoadF D9 /0 */
10732 ins_encode( Push_Reg_F(src0),
10733 FMul_ST_reg(src1),
10734 FAddP_reg_ST(src2) );
10735 ins_pipe( fpu_reg_reg_reg );
10736 %}
10737
10738 // MACRO4 -- divF subF
10739 // This instruction does not round to 24-bits
10740 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
10741 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10742 match(Set dst (DivF (SubF src2 src1) src3));
10743
10744 format %{ "FLD $src2 ===MACRO4===\n\t"
10745 "FSUB ST,$src1\n\t"
10746 "FDIV ST,$src3\n\t"
10747 "FSTP $dst" %}
10748 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10749 ins_encode( Push_Reg_F(src2),
10750 subF_divF_encode(src1,src3),
10751 Pop_Reg_F(dst) );
10752 ins_pipe( fpu_reg_reg_reg_reg );
10753 %}
10754
10755 // Spill to obtain 24-bit precision
10756 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
10757 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10758 match(Set dst (DivF src1 src2));
10759
10760 format %{ "FDIV $dst,$src1,$src2" %}
10761 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10762 ins_encode( Push_Reg_F(src1),
10763 OpcReg_F(src2),
10764 Pop_Mem_F(dst) );
10765 ins_pipe( fpu_mem_reg_reg );
10766 %}
10767 //
10768 // This instruction does not round to 24-bits
10769 instruct divF_reg(regF dst, regF src) %{
10770 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10771 match(Set dst (DivF dst src));
10772
10773 format %{ "FDIV $dst,$src" %}
10774 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10775 ins_encode( Push_Reg_F(src),
10776 OpcP, RegOpc(dst) );
10777 ins_pipe( fpu_reg_reg );
10778 %}
10779
10780
10781 // Spill to obtain 24-bit precision
10782 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10783 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10784 match(Set dst (ModF src1 src2));
10785 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10786
10787 format %{ "FMOD $dst,$src1,$src2" %}
10788 ins_encode( Push_Reg_Mod_D(src1, src2),
10789 emitModD(),
10790 Push_Result_Mod_D(src2),
10791 Pop_Mem_F(dst));
10792 ins_pipe( pipe_slow );
10793 %}
10794 //
10795 // This instruction does not round to 24-bits
10796 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
10797 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10798 match(Set dst (ModF dst src));
10799 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10800
10801 format %{ "FMOD $dst,$src" %}
10802 ins_encode(Push_Reg_Mod_D(dst, src),
10803 emitModD(),
10804 Push_Result_Mod_D(src),
10805 Pop_Reg_F(dst));
10806 ins_pipe( pipe_slow );
10807 %}
10808
10809 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
10810 predicate(UseSSE>=1);
10811 match(Set dst (ModF src0 src1));
10812 effect(KILL rax, KILL cr);
10813 format %{ "SUB ESP,4\t # FMOD\n"
10814 "\tMOVSS [ESP+0],$src1\n"
10815 "\tFLD_S [ESP+0]\n"
10816 "\tMOVSS [ESP+0],$src0\n"
10817 "\tFLD_S [ESP+0]\n"
10818 "loop:\tFPREM\n"
10819 "\tFWAIT\n"
10820 "\tFNSTSW AX\n"
10821 "\tSAHF\n"
10822 "\tJP loop\n"
10823 "\tFSTP_S [ESP+0]\n"
10824 "\tMOVSS $dst,[ESP+0]\n"
10825 "\tADD ESP,4\n"
10826 "\tFSTP ST0\t # Restore FPU Stack"
10827 %}
10828 ins_cost(250);
10829 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
10830 ins_pipe( pipe_slow );
10831 %}
10832
10833
10834 //----------Arithmetic Conversion Instructions---------------------------------
10835 // The conversions operations are all Alpha sorted. Please keep it that way!
10836
10837 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
10838 predicate(UseSSE==0);
10839 match(Set dst (RoundFloat src));
10840 ins_cost(125);
10841 format %{ "FST_S $dst,$src\t# F-round" %}
10842 ins_encode( Pop_Mem_Reg_F(dst, src) );
10843 ins_pipe( fpu_mem_reg );
10844 %}
10845
10846 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
10847 predicate(UseSSE<=1);
10848 match(Set dst (RoundDouble src));
10849 ins_cost(125);
10850 format %{ "FST_D $dst,$src\t# D-round" %}
10851 ins_encode( Pop_Mem_Reg_D(dst, src) );
10852 ins_pipe( fpu_mem_reg );
10853 %}
10854
10855 // Force rounding to 24-bit precision and 6-bit exponent
10856 instruct convD2F_reg(stackSlotF dst, regD src) %{
10857 predicate(UseSSE==0);
10858 match(Set dst (ConvD2F src));
10859 format %{ "FST_S $dst,$src\t# F-round" %}
10860 expand %{
10861 roundFloat_mem_reg(dst,src);
10862 %}
10863 %}
10864
10865 // Force rounding to 24-bit precision and 6-bit exponent
10866 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
10867 predicate(UseSSE==1);
10868 match(Set dst (ConvD2F src));
10869 effect( KILL cr );
10870 format %{ "SUB ESP,4\n\t"
10871 "FST_S [ESP],$src\t# F-round\n\t"
10872 "MOVSS $dst,[ESP]\n\t"
10873 "ADD ESP,4" %}
10874 ins_encode( D2X_encoding(dst, src) );
10875 ins_pipe( pipe_slow );
10876 %}
10877
10878 // Force rounding double precision to single precision
10879 instruct convXD2X_reg(regX dst, regXD src) %{
10880 predicate(UseSSE>=2);
10881 match(Set dst (ConvD2F src));
10882 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10883 opcode(0xF2, 0x0F, 0x5A);
10884 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10885 ins_pipe( pipe_slow );
10886 %}
10887
10888 instruct convF2D_reg_reg(regD dst, regF src) %{
10889 predicate(UseSSE==0);
10890 match(Set dst (ConvF2D src));
10891 format %{ "FST_S $dst,$src\t# D-round" %}
10892 ins_encode( Pop_Reg_Reg_D(dst, src));
10893 ins_pipe( fpu_reg_reg );
10894 %}
10895
10896 instruct convF2D_reg(stackSlotD dst, regF src) %{
10897 predicate(UseSSE==1);
10898 match(Set dst (ConvF2D src));
10899 format %{ "FST_D $dst,$src\t# D-round" %}
10900 expand %{
10901 roundDouble_mem_reg(dst,src);
10902 %}
10903 %}
10904
10905 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
10906 predicate(UseSSE==1);
10907 match(Set dst (ConvF2D src));
10908 effect( KILL cr );
10909 format %{ "SUB ESP,4\n\t"
10910 "MOVSS [ESP] $src\n\t"
10911 "FLD_S [ESP]\n\t"
10912 "ADD ESP,4\n\t"
10913 "FSTP $dst\t# D-round" %}
10914 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
10915 ins_pipe( pipe_slow );
10916 %}
10917
10918 instruct convX2XD_reg(regXD dst, regX src) %{
10919 predicate(UseSSE>=2);
10920 match(Set dst (ConvF2D src));
10921 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10922 opcode(0xF3, 0x0F, 0x5A);
10923 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
10924 ins_pipe( pipe_slow );
10925 %}
10926
10927 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10928 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10929 predicate(UseSSE<=1);
10930 match(Set dst (ConvD2I src));
10931 effect( KILL tmp, KILL cr );
10932 format %{ "FLD $src\t# Convert double to int \n\t"
10933 "FLDCW trunc mode\n\t"
10934 "SUB ESP,4\n\t"
10935 "FISTp [ESP + #0]\n\t"
10936 "FLDCW std/24-bit mode\n\t"
10937 "POP EAX\n\t"
10938 "CMP EAX,0x80000000\n\t"
10939 "JNE,s fast\n\t"
10940 "FLD_D $src\n\t"
10941 "CALL d2i_wrapper\n"
10942 "fast:" %}
10943 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
10944 ins_pipe( pipe_slow );
10945 %}
10946
10947 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10948 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
10949 predicate(UseSSE>=2);
10950 match(Set dst (ConvD2I src));
10951 effect( KILL tmp, KILL cr );
10952 format %{ "CVTTSD2SI $dst, $src\n\t"
10953 "CMP $dst,0x80000000\n\t"
10954 "JNE,s fast\n\t"
10955 "SUB ESP, 8\n\t"
10956 "MOVSD [ESP], $src\n\t"
10957 "FLD_D [ESP]\n\t"
10958 "ADD ESP, 8\n\t"
10959 "CALL d2i_wrapper\n"
10960 "fast:" %}
10961 opcode(0x1); // double-precision conversion
10962 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
10963 ins_pipe( pipe_slow );
10964 %}
10965
10966 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
10967 predicate(UseSSE<=1);
10968 match(Set dst (ConvD2L src));
10969 effect( KILL cr );
10970 format %{ "FLD $src\t# Convert double to long\n\t"
10971 "FLDCW trunc mode\n\t"
10972 "SUB ESP,8\n\t"
10973 "FISTp [ESP + #0]\n\t"
10974 "FLDCW std/24-bit mode\n\t"
10975 "POP EAX\n\t"
10976 "POP EDX\n\t"
10977 "CMP EDX,0x80000000\n\t"
10978 "JNE,s fast\n\t"
10979 "TEST EAX,EAX\n\t"
10980 "JNE,s fast\n\t"
10981 "FLD $src\n\t"
10982 "CALL d2l_wrapper\n"
10983 "fast:" %}
10984 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
10985 ins_pipe( pipe_slow );
10986 %}
10987
10988 // XMM lacks a float/double->long conversion, so use the old FPU stack.
10989 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
10990 predicate (UseSSE>=2);
10991 match(Set dst (ConvD2L src));
10992 effect( KILL cr );
10993 format %{ "SUB ESP,8\t# Convert double to long\n\t"
10994 "MOVSD [ESP],$src\n\t"
10995 "FLD_D [ESP]\n\t"
10996 "FLDCW trunc mode\n\t"
10997 "FISTp [ESP + #0]\n\t"
10998 "FLDCW std/24-bit mode\n\t"
10999 "POP EAX\n\t"
11000 "POP EDX\n\t"
11001 "CMP EDX,0x80000000\n\t"
11002 "JNE,s fast\n\t"
11003 "TEST EAX,EAX\n\t"
11004 "JNE,s fast\n\t"
11005 "SUB ESP,8\n\t"
11006 "MOVSD [ESP],$src\n\t"
11007 "FLD_D [ESP]\n\t"
11008 "CALL d2l_wrapper\n"
11009 "fast:" %}
11010 ins_encode( XD2L_encoding(src) );
11011 ins_pipe( pipe_slow );
11012 %}
11013
11014 // Convert a double to an int. Java semantics require we do complex
11015 // manglations in the corner cases. So we set the rounding mode to
11016 // 'zero', store the darned double down as an int, and reset the
11017 // rounding mode to 'nearest'. The hardware stores a flag value down
11018 // if we would overflow or converted a NAN; we check for this and
11019 // and go the slow path if needed.
11020 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11021 predicate(UseSSE==0);
11022 match(Set dst (ConvF2I src));
11023 effect( KILL tmp, KILL cr );
11024 format %{ "FLD $src\t# Convert float to int \n\t"
11025 "FLDCW trunc mode\n\t"
11026 "SUB ESP,4\n\t"
11027 "FISTp [ESP + #0]\n\t"
11028 "FLDCW std/24-bit mode\n\t"
11029 "POP EAX\n\t"
11030 "CMP EAX,0x80000000\n\t"
11031 "JNE,s fast\n\t"
11032 "FLD $src\n\t"
11033 "CALL d2i_wrapper\n"
11034 "fast:" %}
11035 // D2I_encoding works for F2I
11036 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11037 ins_pipe( pipe_slow );
11038 %}
11039
11040 // Convert a float in xmm to an int reg.
11041 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11042 predicate(UseSSE>=1);
11043 match(Set dst (ConvF2I src));
11044 effect( KILL tmp, KILL cr );
11045 format %{ "CVTTSS2SI $dst, $src\n\t"
11046 "CMP $dst,0x80000000\n\t"
11047 "JNE,s fast\n\t"
11048 "SUB ESP, 4\n\t"
11049 "MOVSS [ESP], $src\n\t"
11050 "FLD [ESP]\n\t"
11051 "ADD ESP, 4\n\t"
11052 "CALL d2i_wrapper\n"
11053 "fast:" %}
11054 opcode(0x0); // single-precision conversion
11055 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11056 ins_pipe( pipe_slow );
11057 %}
11058
11059 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11060 predicate(UseSSE==0);
11061 match(Set dst (ConvF2L src));
11062 effect( KILL cr );
11063 format %{ "FLD $src\t# Convert float to long\n\t"
11064 "FLDCW trunc mode\n\t"
11065 "SUB ESP,8\n\t"
11066 "FISTp [ESP + #0]\n\t"
11067 "FLDCW std/24-bit mode\n\t"
11068 "POP EAX\n\t"
11069 "POP EDX\n\t"
11070 "CMP EDX,0x80000000\n\t"
11071 "JNE,s fast\n\t"
11072 "TEST EAX,EAX\n\t"
11073 "JNE,s fast\n\t"
11074 "FLD $src\n\t"
11075 "CALL d2l_wrapper\n"
11076 "fast:" %}
11077 // D2L_encoding works for F2L
11078 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11079 ins_pipe( pipe_slow );
11080 %}
11081
11082 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11083 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11084 predicate (UseSSE>=1);
11085 match(Set dst (ConvF2L src));
11086 effect( KILL cr );
11087 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11088 "MOVSS [ESP],$src\n\t"
11089 "FLD_S [ESP]\n\t"
11090 "FLDCW trunc mode\n\t"
11091 "FISTp [ESP + #0]\n\t"
11092 "FLDCW std/24-bit mode\n\t"
11093 "POP EAX\n\t"
11094 "POP EDX\n\t"
11095 "CMP EDX,0x80000000\n\t"
11096 "JNE,s fast\n\t"
11097 "TEST EAX,EAX\n\t"
11098 "JNE,s fast\n\t"
11099 "SUB ESP,4\t# Convert float to long\n\t"
11100 "MOVSS [ESP],$src\n\t"
11101 "FLD_S [ESP]\n\t"
11102 "ADD ESP,4\n\t"
11103 "CALL d2l_wrapper\n"
11104 "fast:" %}
11105 ins_encode( X2L_encoding(src) );
11106 ins_pipe( pipe_slow );
11107 %}
11108
11109 instruct convI2D_reg(regD dst, stackSlotI src) %{
11110 predicate( UseSSE<=1 );
11111 match(Set dst (ConvI2D src));
11112 format %{ "FILD $src\n\t"
11113 "FSTP $dst" %}
11114 opcode(0xDB, 0x0); /* DB /0 */
11115 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11116 ins_pipe( fpu_reg_mem );
11117 %}
11118
11119 instruct convI2XD_reg(regXD dst, eRegI src) %{
11120 predicate( UseSSE>=2 && !UseXmmI2D );
11121 match(Set dst (ConvI2D src));
11122 format %{ "CVTSI2SD $dst,$src" %}
11123 opcode(0xF2, 0x0F, 0x2A);
11124 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11125 ins_pipe( pipe_slow );
11126 %}
11127
11128 instruct convI2XD_mem(regXD dst, memory mem) %{
11129 predicate( UseSSE>=2 );
11130 match(Set dst (ConvI2D (LoadI mem)));
11131 format %{ "CVTSI2SD $dst,$mem" %}
11132 opcode(0xF2, 0x0F, 0x2A);
11133 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11134 ins_pipe( pipe_slow );
11135 %}
11136
11137 instruct convXI2XD_reg(regXD dst, eRegI src)
11138 %{
11139 predicate( UseSSE>=2 && UseXmmI2D );
11140 match(Set dst (ConvI2D src));
11141
11142 format %{ "MOVD $dst,$src\n\t"
11143 "CVTDQ2PD $dst,$dst\t# i2d" %}
11144 ins_encode %{
11145 __ movdl($dst$$XMMRegister, $src$$Register);
11146 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11147 %}
11148 ins_pipe(pipe_slow); // XXX
11149 %}
11150
11151 instruct convI2D_mem(regD dst, memory mem) %{
11152 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11153 match(Set dst (ConvI2D (LoadI mem)));
11154 format %{ "FILD $mem\n\t"
11155 "FSTP $dst" %}
11156 opcode(0xDB); /* DB /0 */
11157 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11158 Pop_Reg_D(dst));
11159 ins_pipe( fpu_reg_mem );
11160 %}
11161
11162 // Convert a byte to a float; no rounding step needed.
11163 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11164 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11165 match(Set dst (ConvI2F src));
11166 format %{ "FILD $src\n\t"
11167 "FSTP $dst" %}
11168
11169 opcode(0xDB, 0x0); /* DB /0 */
11170 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11171 ins_pipe( fpu_reg_mem );
11172 %}
11173
11174 // In 24-bit mode, force exponent rounding by storing back out
11175 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11176 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11177 match(Set dst (ConvI2F src));
11178 ins_cost(200);
11179 format %{ "FILD $src\n\t"
11180 "FSTP_S $dst" %}
11181 opcode(0xDB, 0x0); /* DB /0 */
11182 ins_encode( Push_Mem_I(src),
11183 Pop_Mem_F(dst));
11184 ins_pipe( fpu_mem_mem );
11185 %}
11186
11187 // In 24-bit mode, force exponent rounding by storing back out
11188 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11189 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11190 match(Set dst (ConvI2F (LoadI mem)));
11191 ins_cost(200);
11192 format %{ "FILD $mem\n\t"
11193 "FSTP_S $dst" %}
11194 opcode(0xDB); /* DB /0 */
11195 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11196 Pop_Mem_F(dst));
11197 ins_pipe( fpu_mem_mem );
11198 %}
11199
11200 // This instruction does not round to 24-bits
11201 instruct convI2F_reg(regF dst, stackSlotI src) %{
11202 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11203 match(Set dst (ConvI2F src));
11204 format %{ "FILD $src\n\t"
11205 "FSTP $dst" %}
11206 opcode(0xDB, 0x0); /* DB /0 */
11207 ins_encode( Push_Mem_I(src),
11208 Pop_Reg_F(dst));
11209 ins_pipe( fpu_reg_mem );
11210 %}
11211
11212 // This instruction does not round to 24-bits
11213 instruct convI2F_mem(regF dst, memory mem) %{
11214 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11215 match(Set dst (ConvI2F (LoadI mem)));
11216 format %{ "FILD $mem\n\t"
11217 "FSTP $dst" %}
11218 opcode(0xDB); /* DB /0 */
11219 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11220 Pop_Reg_F(dst));
11221 ins_pipe( fpu_reg_mem );
11222 %}
11223
11224 // Convert an int to a float in xmm; no rounding step needed.
11225 instruct convI2X_reg(regX dst, eRegI src) %{
11226 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11227 match(Set dst (ConvI2F src));
11228 format %{ "CVTSI2SS $dst, $src" %}
11229
11230 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11231 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11232 ins_pipe( pipe_slow );
11233 %}
11234
11235 instruct convXI2X_reg(regX dst, eRegI src)
11236 %{
11237 predicate( UseSSE>=2 && UseXmmI2F );
11238 match(Set dst (ConvI2F src));
11239
11240 format %{ "MOVD $dst,$src\n\t"
11241 "CVTDQ2PS $dst,$dst\t# i2f" %}
11242 ins_encode %{
11243 __ movdl($dst$$XMMRegister, $src$$Register);
11244 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11245 %}
11246 ins_pipe(pipe_slow); // XXX
11247 %}
11248
11249 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11250 match(Set dst (ConvI2L src));
11251 effect(KILL cr);
11252 format %{ "MOV $dst.lo,$src\n\t"
11253 "MOV $dst.hi,$src\n\t"
11254 "SAR $dst.hi,31" %}
11255 ins_encode(convert_int_long(dst,src));
11256 ins_pipe( ialu_reg_reg_long );
11257 %}
11258
11259 // Zero-extend convert int to long
11260 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11261 match(Set dst (AndL (ConvI2L src) mask) );
11262 effect( KILL flags );
11263 format %{ "MOV $dst.lo,$src\n\t"
11264 "XOR $dst.hi,$dst.hi" %}
11265 opcode(0x33); // XOR
11266 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11267 ins_pipe( ialu_reg_reg_long );
11268 %}
11269
11270 // Zero-extend long
11271 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11272 match(Set dst (AndL src mask) );
11273 effect( KILL flags );
11274 format %{ "MOV $dst.lo,$src.lo\n\t"
11275 "XOR $dst.hi,$dst.hi\n\t" %}
11276 opcode(0x33); // XOR
11277 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11278 ins_pipe( ialu_reg_reg_long );
11279 %}
11280
11281 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11282 predicate (UseSSE<=1);
11283 match(Set dst (ConvL2D src));
11284 effect( KILL cr );
11285 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11286 "PUSH $src.lo\n\t"
11287 "FILD ST,[ESP + #0]\n\t"
11288 "ADD ESP,8\n\t"
11289 "FSTP_D $dst\t# D-round" %}
11290 opcode(0xDF, 0x5); /* DF /5 */
11291 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11292 ins_pipe( pipe_slow );
11293 %}
11294
11295 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11296 predicate (UseSSE>=2);
11297 match(Set dst (ConvL2D src));
11298 effect( KILL cr );
11299 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11300 "PUSH $src.lo\n\t"
11301 "FILD_D [ESP]\n\t"
11302 "FSTP_D [ESP]\n\t"
11303 "MOVSD $dst,[ESP]\n\t"
11304 "ADD ESP,8" %}
11305 opcode(0xDF, 0x5); /* DF /5 */
11306 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11307 ins_pipe( pipe_slow );
11308 %}
11309
11310 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11311 predicate (UseSSE>=1);
11312 match(Set dst (ConvL2F src));
11313 effect( KILL cr );
11314 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11315 "PUSH $src.lo\n\t"
11316 "FILD_D [ESP]\n\t"
11317 "FSTP_S [ESP]\n\t"
11318 "MOVSS $dst,[ESP]\n\t"
11319 "ADD ESP,8" %}
11320 opcode(0xDF, 0x5); /* DF /5 */
11321 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11322 ins_pipe( pipe_slow );
11323 %}
11324
11325 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11326 match(Set dst (ConvL2F src));
11327 effect( KILL cr );
11328 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11329 "PUSH $src.lo\n\t"
11330 "FILD ST,[ESP + #0]\n\t"
11331 "ADD ESP,8\n\t"
11332 "FSTP_S $dst\t# F-round" %}
11333 opcode(0xDF, 0x5); /* DF /5 */
11334 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11335 ins_pipe( pipe_slow );
11336 %}
11337
11338 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11339 match(Set dst (ConvL2I src));
11340 effect( DEF dst, USE src );
11341 format %{ "MOV $dst,$src.lo" %}
11342 ins_encode(enc_CopyL_Lo(dst,src));
11343 ins_pipe( ialu_reg_reg );
11344 %}
11345
11346
11347 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11348 match(Set dst (MoveF2I src));
11349 effect( DEF dst, USE src );
11350 ins_cost(100);
11351 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11352 opcode(0x8B);
11353 ins_encode( OpcP, RegMem(dst,src));
11354 ins_pipe( ialu_reg_mem );
11355 %}
11356
11357 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11358 predicate(UseSSE==0);
11359 match(Set dst (MoveF2I src));
11360 effect( DEF dst, USE src );
11361
11362 ins_cost(125);
11363 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11364 ins_encode( Pop_Mem_Reg_F(dst, src) );
11365 ins_pipe( fpu_mem_reg );
11366 %}
11367
11368 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11369 predicate(UseSSE>=1);
11370 match(Set dst (MoveF2I src));
11371 effect( DEF dst, USE src );
11372
11373 ins_cost(95);
11374 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11375 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11376 ins_pipe( pipe_slow );
11377 %}
11378
11379 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11380 predicate(UseSSE>=2);
11381 match(Set dst (MoveF2I src));
11382 effect( DEF dst, USE src );
11383 ins_cost(85);
11384 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11385 ins_encode( MovX2I_reg(dst, src));
11386 ins_pipe( pipe_slow );
11387 %}
11388
11389 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11390 match(Set dst (MoveI2F src));
11391 effect( DEF dst, USE src );
11392
11393 ins_cost(100);
11394 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11395 opcode(0x89);
11396 ins_encode( OpcPRegSS( dst, src ) );
11397 ins_pipe( ialu_mem_reg );
11398 %}
11399
11400
11401 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11402 predicate(UseSSE==0);
11403 match(Set dst (MoveI2F src));
11404 effect(DEF dst, USE src);
11405
11406 ins_cost(125);
11407 format %{ "FLD_S $src\n\t"
11408 "FSTP $dst\t# MoveI2F_stack_reg" %}
11409 opcode(0xD9); /* D9 /0, FLD m32real */
11410 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11411 Pop_Reg_F(dst) );
11412 ins_pipe( fpu_reg_mem );
11413 %}
11414
11415 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11416 predicate(UseSSE>=1);
11417 match(Set dst (MoveI2F src));
11418 effect( DEF dst, USE src );
11419
11420 ins_cost(95);
11421 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11422 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11423 ins_pipe( pipe_slow );
11424 %}
11425
11426 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11427 predicate(UseSSE>=2);
11428 match(Set dst (MoveI2F src));
11429 effect( DEF dst, USE src );
11430
11431 ins_cost(85);
11432 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11433 ins_encode( MovI2X_reg(dst, src) );
11434 ins_pipe( pipe_slow );
11435 %}
11436
11437 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11438 match(Set dst (MoveD2L src));
11439 effect(DEF dst, USE src);
11440
11441 ins_cost(250);
11442 format %{ "MOV $dst.lo,$src\n\t"
11443 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11444 opcode(0x8B, 0x8B);
11445 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11446 ins_pipe( ialu_mem_long_reg );
11447 %}
11448
11449 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11450 predicate(UseSSE<=1);
11451 match(Set dst (MoveD2L src));
11452 effect(DEF dst, USE src);
11453
11454 ins_cost(125);
11455 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11456 ins_encode( Pop_Mem_Reg_D(dst, src) );
11457 ins_pipe( fpu_mem_reg );
11458 %}
11459
11460 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
11461 predicate(UseSSE>=2);
11462 match(Set dst (MoveD2L src));
11463 effect(DEF dst, USE src);
11464 ins_cost(95);
11465
11466 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11467 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
11468 ins_pipe( pipe_slow );
11469 %}
11470
11471 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
11472 predicate(UseSSE>=2);
11473 match(Set dst (MoveD2L src));
11474 effect(DEF dst, USE src, TEMP tmp);
11475 ins_cost(85);
11476 format %{ "MOVD $dst.lo,$src\n\t"
11477 "PSHUFLW $tmp,$src,0x4E\n\t"
11478 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11479 ins_encode( MovXD2L_reg(dst, src, tmp) );
11480 ins_pipe( pipe_slow );
11481 %}
11482
11483 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11484 match(Set dst (MoveL2D src));
11485 effect(DEF dst, USE src);
11486
11487 ins_cost(200);
11488 format %{ "MOV $dst,$src.lo\n\t"
11489 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11490 opcode(0x89, 0x89);
11491 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11492 ins_pipe( ialu_mem_long_reg );
11493 %}
11494
11495
11496 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11497 predicate(UseSSE<=1);
11498 match(Set dst (MoveL2D src));
11499 effect(DEF dst, USE src);
11500 ins_cost(125);
11501
11502 format %{ "FLD_D $src\n\t"
11503 "FSTP $dst\t# MoveL2D_stack_reg" %}
11504 opcode(0xDD); /* DD /0, FLD m64real */
11505 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11506 Pop_Reg_D(dst) );
11507 ins_pipe( fpu_reg_mem );
11508 %}
11509
11510
11511 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
11512 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11513 match(Set dst (MoveL2D src));
11514 effect(DEF dst, USE src);
11515
11516 ins_cost(95);
11517 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11518 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11519 ins_pipe( pipe_slow );
11520 %}
11521
11522 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
11523 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11524 match(Set dst (MoveL2D src));
11525 effect(DEF dst, USE src);
11526
11527 ins_cost(95);
11528 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11529 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
11530 ins_pipe( pipe_slow );
11531 %}
11532
11533 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
11534 predicate(UseSSE>=2);
11535 match(Set dst (MoveL2D src));
11536 effect(TEMP dst, USE src, TEMP tmp);
11537 ins_cost(85);
11538 format %{ "MOVD $dst,$src.lo\n\t"
11539 "MOVD $tmp,$src.hi\n\t"
11540 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11541 ins_encode( MovL2XD_reg(dst, src, tmp) );
11542 ins_pipe( pipe_slow );
11543 %}
11544
11545 // Replicate scalar to packed byte (1 byte) values in xmm
11546 instruct Repl8B_reg(regXD dst, regXD src) %{
11547 predicate(UseSSE>=2);
11548 match(Set dst (Replicate8B src));
11549 format %{ "MOVDQA $dst,$src\n\t"
11550 "PUNPCKLBW $dst,$dst\n\t"
11551 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11552 ins_encode( pshufd_8x8(dst, src));
11553 ins_pipe( pipe_slow );
11554 %}
11555
11556 // Replicate scalar to packed byte (1 byte) values in xmm
11557 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
11558 predicate(UseSSE>=2);
11559 match(Set dst (Replicate8B src));
11560 format %{ "MOVD $dst,$src\n\t"
11561 "PUNPCKLBW $dst,$dst\n\t"
11562 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11563 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11564 ins_pipe( pipe_slow );
11565 %}
11566
11567 // Replicate scalar zero to packed byte (1 byte) values in xmm
11568 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
11569 predicate(UseSSE>=2);
11570 match(Set dst (Replicate8B zero));
11571 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11572 ins_encode( pxor(dst, dst));
11573 ins_pipe( fpu_reg_reg );
11574 %}
11575
11576 // Replicate scalar to packed shore (2 byte) values in xmm
11577 instruct Repl4S_reg(regXD dst, regXD src) %{
11578 predicate(UseSSE>=2);
11579 match(Set dst (Replicate4S src));
11580 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11581 ins_encode( pshufd_4x16(dst, src));
11582 ins_pipe( fpu_reg_reg );
11583 %}
11584
11585 // Replicate scalar to packed shore (2 byte) values in xmm
11586 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
11587 predicate(UseSSE>=2);
11588 match(Set dst (Replicate4S src));
11589 format %{ "MOVD $dst,$src\n\t"
11590 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11591 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11592 ins_pipe( fpu_reg_reg );
11593 %}
11594
11595 // Replicate scalar zero to packed short (2 byte) values in xmm
11596 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
11597 predicate(UseSSE>=2);
11598 match(Set dst (Replicate4S zero));
11599 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11600 ins_encode( pxor(dst, dst));
11601 ins_pipe( fpu_reg_reg );
11602 %}
11603
11604 // Replicate scalar to packed char (2 byte) values in xmm
11605 instruct Repl4C_reg(regXD dst, regXD src) %{
11606 predicate(UseSSE>=2);
11607 match(Set dst (Replicate4C src));
11608 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11609 ins_encode( pshufd_4x16(dst, src));
11610 ins_pipe( fpu_reg_reg );
11611 %}
11612
11613 // Replicate scalar to packed char (2 byte) values in xmm
11614 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
11615 predicate(UseSSE>=2);
11616 match(Set dst (Replicate4C src));
11617 format %{ "MOVD $dst,$src\n\t"
11618 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11619 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11620 ins_pipe( fpu_reg_reg );
11621 %}
11622
11623 // Replicate scalar zero to packed char (2 byte) values in xmm
11624 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
11625 predicate(UseSSE>=2);
11626 match(Set dst (Replicate4C zero));
11627 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11628 ins_encode( pxor(dst, dst));
11629 ins_pipe( fpu_reg_reg );
11630 %}
11631
11632 // Replicate scalar to packed integer (4 byte) values in xmm
11633 instruct Repl2I_reg(regXD dst, regXD src) %{
11634 predicate(UseSSE>=2);
11635 match(Set dst (Replicate2I src));
11636 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11637 ins_encode( pshufd(dst, src, 0x00));
11638 ins_pipe( fpu_reg_reg );
11639 %}
11640
11641 // Replicate scalar to packed integer (4 byte) values in xmm
11642 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
11643 predicate(UseSSE>=2);
11644 match(Set dst (Replicate2I src));
11645 format %{ "MOVD $dst,$src\n\t"
11646 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11647 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
11648 ins_pipe( fpu_reg_reg );
11649 %}
11650
11651 // Replicate scalar zero to packed integer (2 byte) values in xmm
11652 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
11653 predicate(UseSSE>=2);
11654 match(Set dst (Replicate2I zero));
11655 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11656 ins_encode( pxor(dst, dst));
11657 ins_pipe( fpu_reg_reg );
11658 %}
11659
11660 // Replicate scalar to packed single precision floating point values in xmm
11661 instruct Repl2F_reg(regXD dst, regXD src) %{
11662 predicate(UseSSE>=2);
11663 match(Set dst (Replicate2F src));
11664 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11665 ins_encode( pshufd(dst, src, 0xe0));
11666 ins_pipe( fpu_reg_reg );
11667 %}
11668
11669 // Replicate scalar to packed single precision floating point values in xmm
11670 instruct Repl2F_regX(regXD dst, regX src) %{
11671 predicate(UseSSE>=2);
11672 match(Set dst (Replicate2F src));
11673 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11674 ins_encode( pshufd(dst, src, 0xe0));
11675 ins_pipe( fpu_reg_reg );
11676 %}
11677
11678 // Replicate scalar to packed single precision floating point values in xmm
11679 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
11680 predicate(UseSSE>=2);
11681 match(Set dst (Replicate2F zero));
11682 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11683 ins_encode( pxor(dst, dst));
11684 ins_pipe( fpu_reg_reg );
11685 %}
11686
11687
11688
11689 // =======================================================================
11690 // fast clearing of an array
11691
11692 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11693 match(Set dummy (ClearArray cnt base));
11694 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11695 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
11696 "XOR EAX,EAX\n\t"
11697 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11698 opcode(0,0x4);
11699 ins_encode( Opcode(0xD1), RegOpc(ECX),
11700 OpcRegReg(0x33,EAX,EAX),
11701 Opcode(0xF3), Opcode(0xAB) );
11702 ins_pipe( pipe_slow );
11703 %}
11704
11705 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
11706 match(Set result (StrComp str1 str2));
11707 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
11708 //ins_cost(300);
11709
11710 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %}
11711 ins_encode( enc_String_Compare() );
11712 ins_pipe( pipe_slow );
11713 %}
11714
11715 // fast array equals
11716 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{
11717 match(Set result (AryEq ary1 ary2));
11718 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr);
11719 //ins_cost(300);
11720
11721 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %}
11722 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) );
11723 ins_pipe( pipe_slow );
11724 %}
11725
11726 //----------Control Flow Instructions------------------------------------------
11727 // Signed compare Instructions
11728 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
11729 match(Set cr (CmpI op1 op2));
11730 effect( DEF cr, USE op1, USE op2 );
11731 format %{ "CMP $op1,$op2" %}
11732 opcode(0x3B); /* Opcode 3B /r */
11733 ins_encode( OpcP, RegReg( op1, op2) );
11734 ins_pipe( ialu_cr_reg_reg );
11735 %}
11736
11737 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
11738 match(Set cr (CmpI op1 op2));
11739 effect( DEF cr, USE op1 );
11740 format %{ "CMP $op1,$op2" %}
11741 opcode(0x81,0x07); /* Opcode 81 /7 */
11742 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11743 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11744 ins_pipe( ialu_cr_reg_imm );
11745 %}
11746
11747 // Cisc-spilled version of cmpI_eReg
11748 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
11749 match(Set cr (CmpI op1 (LoadI op2)));
11750
11751 format %{ "CMP $op1,$op2" %}
11752 ins_cost(500);
11753 opcode(0x3B); /* Opcode 3B /r */
11754 ins_encode( OpcP, RegMem( op1, op2) );
11755 ins_pipe( ialu_cr_reg_mem );
11756 %}
11757
11758 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
11759 match(Set cr (CmpI src zero));
11760 effect( DEF cr, USE src );
11761
11762 format %{ "TEST $src,$src" %}
11763 opcode(0x85);
11764 ins_encode( OpcP, RegReg( src, src ) );
11765 ins_pipe( ialu_cr_reg_imm );
11766 %}
11767
11768 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
11769 match(Set cr (CmpI (AndI src con) zero));
11770
11771 format %{ "TEST $src,$con" %}
11772 opcode(0xF7,0x00);
11773 ins_encode( OpcP, RegOpc(src), Con32(con) );
11774 ins_pipe( ialu_cr_reg_imm );
11775 %}
11776
11777 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
11778 match(Set cr (CmpI (AndI src mem) zero));
11779
11780 format %{ "TEST $src,$mem" %}
11781 opcode(0x85);
11782 ins_encode( OpcP, RegMem( src, mem ) );
11783 ins_pipe( ialu_cr_reg_mem );
11784 %}
11785
11786 // Unsigned compare Instructions; really, same as signed except they
11787 // produce an eFlagsRegU instead of eFlagsReg.
11788 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
11789 match(Set cr (CmpU op1 op2));
11790
11791 format %{ "CMPu $op1,$op2" %}
11792 opcode(0x3B); /* Opcode 3B /r */
11793 ins_encode( OpcP, RegReg( op1, op2) );
11794 ins_pipe( ialu_cr_reg_reg );
11795 %}
11796
11797 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
11798 match(Set cr (CmpU op1 op2));
11799
11800 format %{ "CMPu $op1,$op2" %}
11801 opcode(0x81,0x07); /* Opcode 81 /7 */
11802 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11803 ins_pipe( ialu_cr_reg_imm );
11804 %}
11805
11806 // // Cisc-spilled version of cmpU_eReg
11807 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
11808 match(Set cr (CmpU op1 (LoadI op2)));
11809
11810 format %{ "CMPu $op1,$op2" %}
11811 ins_cost(500);
11812 opcode(0x3B); /* Opcode 3B /r */
11813 ins_encode( OpcP, RegMem( op1, op2) );
11814 ins_pipe( ialu_cr_reg_mem );
11815 %}
11816
11817 // // Cisc-spilled version of cmpU_eReg
11818 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
11819 // match(Set cr (CmpU (LoadI op1) op2));
11820 //
11821 // format %{ "CMPu $op1,$op2" %}
11822 // ins_cost(500);
11823 // opcode(0x39); /* Opcode 39 /r */
11824 // ins_encode( OpcP, RegMem( op1, op2) );
11825 //%}
11826
11827 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
11828 match(Set cr (CmpU src zero));
11829
11830 format %{ "TESTu $src,$src" %}
11831 opcode(0x85);
11832 ins_encode( OpcP, RegReg( src, src ) );
11833 ins_pipe( ialu_cr_reg_imm );
11834 %}
11835
11836 // Unsigned pointer compare Instructions
11837 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11838 match(Set cr (CmpP op1 op2));
11839
11840 format %{ "CMPu $op1,$op2" %}
11841 opcode(0x3B); /* Opcode 3B /r */
11842 ins_encode( OpcP, RegReg( op1, op2) );
11843 ins_pipe( ialu_cr_reg_reg );
11844 %}
11845
11846 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11847 match(Set cr (CmpP op1 op2));
11848
11849 format %{ "CMPu $op1,$op2" %}
11850 opcode(0x81,0x07); /* Opcode 81 /7 */
11851 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11852 ins_pipe( ialu_cr_reg_imm );
11853 %}
11854
11855 // // Cisc-spilled version of cmpP_eReg
11856 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11857 match(Set cr (CmpP op1 (LoadP op2)));
11858
11859 format %{ "CMPu $op1,$op2" %}
11860 ins_cost(500);
11861 opcode(0x3B); /* Opcode 3B /r */
11862 ins_encode( OpcP, RegMem( op1, op2) );
11863 ins_pipe( ialu_cr_reg_mem );
11864 %}
11865
11866 // // Cisc-spilled version of cmpP_eReg
11867 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11868 // match(Set cr (CmpP (LoadP op1) op2));
11869 //
11870 // format %{ "CMPu $op1,$op2" %}
11871 // ins_cost(500);
11872 // opcode(0x39); /* Opcode 39 /r */
11873 // ins_encode( OpcP, RegMem( op1, op2) );
11874 //%}
11875
11876 // Compare raw pointer (used in out-of-heap check).
11877 // Only works because non-oop pointers must be raw pointers
11878 // and raw pointers have no anti-dependencies.
11879 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11880 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11881 match(Set cr (CmpP op1 (LoadP op2)));
11882
11883 format %{ "CMPu $op1,$op2" %}
11884 opcode(0x3B); /* Opcode 3B /r */
11885 ins_encode( OpcP, RegMem( op1, op2) );
11886 ins_pipe( ialu_cr_reg_mem );
11887 %}
11888
11889 //
11890 // This will generate a signed flags result. This should be ok
11891 // since any compare to a zero should be eq/neq.
11892 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11893 match(Set cr (CmpP src zero));
11894
11895 format %{ "TEST $src,$src" %}
11896 opcode(0x85);
11897 ins_encode( OpcP, RegReg( src, src ) );
11898 ins_pipe( ialu_cr_reg_imm );
11899 %}
11900
11901 // Cisc-spilled version of testP_reg
11902 // This will generate a signed flags result. This should be ok
11903 // since any compare to a zero should be eq/neq.
11904 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11905 match(Set cr (CmpP (LoadP op) zero));
11906
11907 format %{ "TEST $op,0xFFFFFFFF" %}
11908 ins_cost(500);
11909 opcode(0xF7); /* Opcode F7 /0 */
11910 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11911 ins_pipe( ialu_cr_reg_imm );
11912 %}
11913
11914 // Yanked all unsigned pointer compare operations.
11915 // Pointer compares are done with CmpP which is already unsigned.
11916
11917 //----------Max and Min--------------------------------------------------------
11918 // Min Instructions
11919 ////
11920 // *** Min and Max using the conditional move are slower than the
11921 // *** branch version on a Pentium III.
11922 // // Conditional move for min
11923 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
11924 // effect( USE_DEF op2, USE op1, USE cr );
11925 // format %{ "CMOVlt $op2,$op1\t! min" %}
11926 // opcode(0x4C,0x0F);
11927 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11928 // ins_pipe( pipe_cmov_reg );
11929 //%}
11930 //
11931 //// Min Register with Register (P6 version)
11932 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
11933 // predicate(VM_Version::supports_cmov() );
11934 // match(Set op2 (MinI op1 op2));
11935 // ins_cost(200);
11936 // expand %{
11937 // eFlagsReg cr;
11938 // compI_eReg(cr,op1,op2);
11939 // cmovI_reg_lt(op2,op1,cr);
11940 // %}
11941 //%}
11942
11943 // Min Register with Register (generic version)
11944 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
11945 match(Set dst (MinI dst src));
11946 effect(KILL flags);
11947 ins_cost(300);
11948
11949 format %{ "MIN $dst,$src" %}
11950 opcode(0xCC);
11951 ins_encode( min_enc(dst,src) );
11952 ins_pipe( pipe_slow );
11953 %}
11954
11955 // Max Register with Register
11956 // *** Min and Max using the conditional move are slower than the
11957 // *** branch version on a Pentium III.
11958 // // Conditional move for max
11959 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
11960 // effect( USE_DEF op2, USE op1, USE cr );
11961 // format %{ "CMOVgt $op2,$op1\t! max" %}
11962 // opcode(0x4F,0x0F);
11963 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11964 // ins_pipe( pipe_cmov_reg );
11965 //%}
11966 //
11967 // // Max Register with Register (P6 version)
11968 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
11969 // predicate(VM_Version::supports_cmov() );
11970 // match(Set op2 (MaxI op1 op2));
11971 // ins_cost(200);
11972 // expand %{
11973 // eFlagsReg cr;
11974 // compI_eReg(cr,op1,op2);
11975 // cmovI_reg_gt(op2,op1,cr);
11976 // %}
11977 //%}
11978
11979 // Max Register with Register (generic version)
11980 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
11981 match(Set dst (MaxI dst src));
11982 effect(KILL flags);
11983 ins_cost(300);
11984
11985 format %{ "MAX $dst,$src" %}
11986 opcode(0xCC);
11987 ins_encode( max_enc(dst,src) );
11988 ins_pipe( pipe_slow );
11989 %}
11990
11991 // ============================================================================
11992 // Branch Instructions
11993 // Jump Table
11994 instruct jumpXtnd(eRegI switch_val) %{
11995 match(Jump switch_val);
11996 ins_cost(350);
11997
11998 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
11999
12000 ins_encode %{
12001 address table_base = __ address_table_constant(_index2label);
12002
12003 // Jump to Address(table_base + switch_reg)
12004 InternalAddress table(table_base);
12005 Address index(noreg, $switch_val$$Register, Address::times_1);
12006 __ jump(ArrayAddress(table, index));
12007 %}
12008 ins_pc_relative(1);
12009 ins_pipe(pipe_jmp);
12010 %}
12011
12012 // Jump Direct - Label defines a relative address from JMP+1
12013 instruct jmpDir(label labl) %{
12014 match(Goto);
12015 effect(USE labl);
12016
12017 ins_cost(300);
12018 format %{ "JMP $labl" %}
12019 size(5);
12020 opcode(0xE9);
12021 ins_encode( OpcP, Lbl( labl ) );
12022 ins_pipe( pipe_jmp );
12023 ins_pc_relative(1);
12024 %}
12025
12026 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12027 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12028 match(If cop cr);
12029 effect(USE labl);
12030
12031 ins_cost(300);
12032 format %{ "J$cop $labl" %}
12033 size(6);
12034 opcode(0x0F, 0x80);
12035 ins_encode( Jcc( cop, labl) );
12036 ins_pipe( pipe_jcc );
12037 ins_pc_relative(1);
12038 %}
12039
12040 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12041 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12042 match(CountedLoopEnd cop cr);
12043 effect(USE labl);
12044
12045 ins_cost(300);
12046 format %{ "J$cop $labl\t# Loop end" %}
12047 size(6);
12048 opcode(0x0F, 0x80);
12049 ins_encode( Jcc( cop, labl) );
12050 ins_pipe( pipe_jcc );
12051 ins_pc_relative(1);
12052 %}
12053
12054 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12055 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12056 match(CountedLoopEnd cop cmp);
12057 effect(USE labl);
12058
12059 ins_cost(300);
12060 format %{ "J$cop,u $labl\t# Loop end" %}
12061 size(6);
12062 opcode(0x0F, 0x80);
12063 ins_encode( Jcc( cop, labl) );
12064 ins_pipe( pipe_jcc );
12065 ins_pc_relative(1);
12066 %}
12067
12068 // Jump Direct Conditional - using unsigned comparison
12069 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12070 match(If cop cmp);
12071 effect(USE labl);
12072
12073 ins_cost(300);
12074 format %{ "J$cop,u $labl" %}
12075 size(6);
12076 opcode(0x0F, 0x80);
12077 ins_encode( Jcc( cop, labl) );
12078 ins_pipe( pipe_jcc );
12079 ins_pc_relative(1);
12080 %}
12081
12082 // ============================================================================
12083 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12084 // array for an instance of the superklass. Set a hidden internal cache on a
12085 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12086 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12087 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12088 match(Set result (PartialSubtypeCheck sub super));
12089 effect( KILL rcx, KILL cr );
12090
12091 ins_cost(1100); // slightly larger than the next version
12092 format %{ "CMPL EAX,ESI\n\t"
12093 "JEQ,s hit\n\t"
12094 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12095 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12096 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12097 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12098 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12099 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12100 "hit:\n\t"
12101 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12102 "miss:\t" %}
12103
12104 opcode(0x1); // Force a XOR of EDI
12105 ins_encode( enc_PartialSubtypeCheck() );
12106 ins_pipe( pipe_slow );
12107 %}
12108
12109 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12110 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12111 effect( KILL rcx, KILL result );
12112
12113 ins_cost(1000);
12114 format %{ "CMPL EAX,ESI\n\t"
12115 "JEQ,s miss\t# Actually a hit; we are done.\n\t"
12116 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12117 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12118 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12119 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12120 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12121 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12122 "miss:\t" %}
12123
12124 opcode(0x0); // No need to XOR EDI
12125 ins_encode( enc_PartialSubtypeCheck() );
12126 ins_pipe( pipe_slow );
12127 %}
12128
12129 // ============================================================================
12130 // Branch Instructions -- short offset versions
12131 //
12132 // These instructions are used to replace jumps of a long offset (the default
12133 // match) with jumps of a shorter offset. These instructions are all tagged
12134 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12135 // match rules in general matching. Instead, the ADLC generates a conversion
12136 // method in the MachNode which can be used to do in-place replacement of the
12137 // long variant with the shorter variant. The compiler will determine if a
12138 // branch can be taken by the is_short_branch_offset() predicate in the machine
12139 // specific code section of the file.
12140
12141 // Jump Direct - Label defines a relative address from JMP+1
12142 instruct jmpDir_short(label labl) %{
12143 match(Goto);
12144 effect(USE labl);
12145
12146 ins_cost(300);
12147 format %{ "JMP,s $labl" %}
12148 size(2);
12149 opcode(0xEB);
12150 ins_encode( OpcP, LblShort( labl ) );
12151 ins_pipe( pipe_jmp );
12152 ins_pc_relative(1);
12153 ins_short_branch(1);
12154 %}
12155
12156 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12157 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12158 match(If cop cr);
12159 effect(USE labl);
12160
12161 ins_cost(300);
12162 format %{ "J$cop,s $labl" %}
12163 size(2);
12164 opcode(0x70);
12165 ins_encode( JccShort( cop, labl) );
12166 ins_pipe( pipe_jcc );
12167 ins_pc_relative(1);
12168 ins_short_branch(1);
12169 %}
12170
12171 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12172 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12173 match(CountedLoopEnd cop cr);
12174 effect(USE labl);
12175
12176 ins_cost(300);
12177 format %{ "J$cop,s $labl" %}
12178 size(2);
12179 opcode(0x70);
12180 ins_encode( JccShort( cop, labl) );
12181 ins_pipe( pipe_jcc );
12182 ins_pc_relative(1);
12183 ins_short_branch(1);
12184 %}
12185
12186 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12187 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12188 match(CountedLoopEnd cop cmp);
12189 effect(USE labl);
12190
12191 ins_cost(300);
12192 format %{ "J$cop,us $labl" %}
12193 size(2);
12194 opcode(0x70);
12195 ins_encode( JccShort( cop, labl) );
12196 ins_pipe( pipe_jcc );
12197 ins_pc_relative(1);
12198 ins_short_branch(1);
12199 %}
12200
12201 // Jump Direct Conditional - using unsigned comparison
12202 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12203 match(If cop cmp);
12204 effect(USE labl);
12205
12206 ins_cost(300);
12207 format %{ "J$cop,us $labl" %}
12208 size(2);
12209 opcode(0x70);
12210 ins_encode( JccShort( cop, labl) );
12211 ins_pipe( pipe_jcc );
12212 ins_pc_relative(1);
12213 ins_short_branch(1);
12214 %}
12215
12216 // ============================================================================
12217 // Long Compare
12218 //
12219 // Currently we hold longs in 2 registers. Comparing such values efficiently
12220 // is tricky. The flavor of compare used depends on whether we are testing
12221 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12222 // The GE test is the negated LT test. The LE test can be had by commuting
12223 // the operands (yielding a GE test) and then negating; negate again for the
12224 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12225 // NE test is negated from that.
12226
12227 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12228 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12229 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12230 // are collapsed internally in the ADLC's dfa-gen code. The match for
12231 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12232 // foo match ends up with the wrong leaf. One fix is to not match both
12233 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12234 // both forms beat the trinary form of long-compare and both are very useful
12235 // on Intel which has so few registers.
12236
12237 // Manifest a CmpL result in an integer register. Very painful.
12238 // This is the test to avoid.
12239 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12240 match(Set dst (CmpL3 src1 src2));
12241 effect( KILL flags );
12242 ins_cost(1000);
12243 format %{ "XOR $dst,$dst\n\t"
12244 "CMP $src1.hi,$src2.hi\n\t"
12245 "JLT,s m_one\n\t"
12246 "JGT,s p_one\n\t"
12247 "CMP $src1.lo,$src2.lo\n\t"
12248 "JB,s m_one\n\t"
12249 "JEQ,s done\n"
12250 "p_one:\tINC $dst\n\t"
12251 "JMP,s done\n"
12252 "m_one:\tDEC $dst\n"
12253 "done:" %}
12254 ins_encode %{
12255 Label p_one, m_one, done;
12256 __ xorptr($dst$$Register, $dst$$Register);
12257 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12258 __ jccb(Assembler::less, m_one);
12259 __ jccb(Assembler::greater, p_one);
12260 __ cmpl($src1$$Register, $src2$$Register);
12261 __ jccb(Assembler::below, m_one);
12262 __ jccb(Assembler::equal, done);
12263 __ bind(p_one);
12264 __ incrementl($dst$$Register);
12265 __ jmpb(done);
12266 __ bind(m_one);
12267 __ decrementl($dst$$Register);
12268 __ bind(done);
12269 %}
12270 ins_pipe( pipe_slow );
12271 %}
12272
12273 //======
12274 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12275 // compares. Can be used for LE or GT compares by reversing arguments.
12276 // NOT GOOD FOR EQ/NE tests.
12277 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12278 match( Set flags (CmpL src zero ));
12279 ins_cost(100);
12280 format %{ "TEST $src.hi,$src.hi" %}
12281 opcode(0x85);
12282 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12283 ins_pipe( ialu_cr_reg_reg );
12284 %}
12285
12286 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12287 // compares. Can be used for LE or GT compares by reversing arguments.
12288 // NOT GOOD FOR EQ/NE tests.
12289 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12290 match( Set flags (CmpL src1 src2 ));
12291 effect( TEMP tmp );
12292 ins_cost(300);
12293 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12294 "MOV $tmp,$src1.hi\n\t"
12295 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12296 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12297 ins_pipe( ialu_cr_reg_reg );
12298 %}
12299
12300 // Long compares reg < zero/req OR reg >= zero/req.
12301 // Just a wrapper for a normal branch, plus the predicate test.
12302 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12303 match(If cmp flags);
12304 effect(USE labl);
12305 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12306 expand %{
12307 jmpCon(cmp,flags,labl); // JLT or JGE...
12308 %}
12309 %}
12310
12311 // Compare 2 longs and CMOVE longs.
12312 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12313 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12314 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12315 ins_cost(400);
12316 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12317 "CMOV$cmp $dst.hi,$src.hi" %}
12318 opcode(0x0F,0x40);
12319 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12320 ins_pipe( pipe_cmov_reg_long );
12321 %}
12322
12323 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12324 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12325 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12326 ins_cost(500);
12327 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12328 "CMOV$cmp $dst.hi,$src.hi" %}
12329 opcode(0x0F,0x40);
12330 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12331 ins_pipe( pipe_cmov_reg_long );
12332 %}
12333
12334 // Compare 2 longs and CMOVE ints.
12335 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12336 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12337 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12338 ins_cost(200);
12339 format %{ "CMOV$cmp $dst,$src" %}
12340 opcode(0x0F,0x40);
12341 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12342 ins_pipe( pipe_cmov_reg );
12343 %}
12344
12345 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12346 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12347 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12348 ins_cost(250);
12349 format %{ "CMOV$cmp $dst,$src" %}
12350 opcode(0x0F,0x40);
12351 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12352 ins_pipe( pipe_cmov_mem );
12353 %}
12354
12355 // Compare 2 longs and CMOVE ints.
12356 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12357 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12358 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12359 ins_cost(200);
12360 format %{ "CMOV$cmp $dst,$src" %}
12361 opcode(0x0F,0x40);
12362 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12363 ins_pipe( pipe_cmov_reg );
12364 %}
12365
12366 // Compare 2 longs and CMOVE doubles
12367 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12368 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12369 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12370 ins_cost(200);
12371 expand %{
12372 fcmovD_regS(cmp,flags,dst,src);
12373 %}
12374 %}
12375
12376 // Compare 2 longs and CMOVE doubles
12377 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
12378 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12379 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12380 ins_cost(200);
12381 expand %{
12382 fcmovXD_regS(cmp,flags,dst,src);
12383 %}
12384 %}
12385
12386 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12387 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12388 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12389 ins_cost(200);
12390 expand %{
12391 fcmovF_regS(cmp,flags,dst,src);
12392 %}
12393 %}
12394
12395 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
12396 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12397 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12398 ins_cost(200);
12399 expand %{
12400 fcmovX_regS(cmp,flags,dst,src);
12401 %}
12402 %}
12403
12404 //======
12405 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12406 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
12407 match( Set flags (CmpL src zero ));
12408 effect(TEMP tmp);
12409 ins_cost(200);
12410 format %{ "MOV $tmp,$src.lo\n\t"
12411 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12412 ins_encode( long_cmp_flags0( src, tmp ) );
12413 ins_pipe( ialu_reg_reg_long );
12414 %}
12415
12416 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12417 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12418 match( Set flags (CmpL src1 src2 ));
12419 ins_cost(200+300);
12420 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12421 "JNE,s skip\n\t"
12422 "CMP $src1.hi,$src2.hi\n\t"
12423 "skip:\t" %}
12424 ins_encode( long_cmp_flags1( src1, src2 ) );
12425 ins_pipe( ialu_cr_reg_reg );
12426 %}
12427
12428 // Long compare reg == zero/reg OR reg != zero/reg
12429 // Just a wrapper for a normal branch, plus the predicate test.
12430 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12431 match(If cmp flags);
12432 effect(USE labl);
12433 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12434 expand %{
12435 jmpCon(cmp,flags,labl); // JEQ or JNE...
12436 %}
12437 %}
12438
12439 // Compare 2 longs and CMOVE longs.
12440 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12441 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12442 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12443 ins_cost(400);
12444 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12445 "CMOV$cmp $dst.hi,$src.hi" %}
12446 opcode(0x0F,0x40);
12447 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12448 ins_pipe( pipe_cmov_reg_long );
12449 %}
12450
12451 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12452 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12453 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12454 ins_cost(500);
12455 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12456 "CMOV$cmp $dst.hi,$src.hi" %}
12457 opcode(0x0F,0x40);
12458 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12459 ins_pipe( pipe_cmov_reg_long );
12460 %}
12461
12462 // Compare 2 longs and CMOVE ints.
12463 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
12464 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12465 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12466 ins_cost(200);
12467 format %{ "CMOV$cmp $dst,$src" %}
12468 opcode(0x0F,0x40);
12469 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12470 ins_pipe( pipe_cmov_reg );
12471 %}
12472
12473 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
12474 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12475 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12476 ins_cost(250);
12477 format %{ "CMOV$cmp $dst,$src" %}
12478 opcode(0x0F,0x40);
12479 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12480 ins_pipe( pipe_cmov_mem );
12481 %}
12482
12483 // Compare 2 longs and CMOVE ints.
12484 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12485 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12486 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12487 ins_cost(200);
12488 format %{ "CMOV$cmp $dst,$src" %}
12489 opcode(0x0F,0x40);
12490 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12491 ins_pipe( pipe_cmov_reg );
12492 %}
12493
12494 // Compare 2 longs and CMOVE doubles
12495 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12496 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12497 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12498 ins_cost(200);
12499 expand %{
12500 fcmovD_regS(cmp,flags,dst,src);
12501 %}
12502 %}
12503
12504 // Compare 2 longs and CMOVE doubles
12505 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
12506 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12507 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12508 ins_cost(200);
12509 expand %{
12510 fcmovXD_regS(cmp,flags,dst,src);
12511 %}
12512 %}
12513
12514 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12515 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12516 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12517 ins_cost(200);
12518 expand %{
12519 fcmovF_regS(cmp,flags,dst,src);
12520 %}
12521 %}
12522
12523 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
12524 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12525 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12526 ins_cost(200);
12527 expand %{
12528 fcmovX_regS(cmp,flags,dst,src);
12529 %}
12530 %}
12531
12532 //======
12533 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12534 // Same as cmpL_reg_flags_LEGT except must negate src
12535 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
12536 match( Set flags (CmpL src zero ));
12537 effect( TEMP tmp );
12538 ins_cost(300);
12539 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12540 "CMP $tmp,$src.lo\n\t"
12541 "SBB $tmp,$src.hi\n\t" %}
12542 ins_encode( long_cmp_flags3(src, tmp) );
12543 ins_pipe( ialu_reg_reg_long );
12544 %}
12545
12546 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12547 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12548 // requires a commuted test to get the same result.
12549 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12550 match( Set flags (CmpL src1 src2 ));
12551 effect( TEMP tmp );
12552 ins_cost(300);
12553 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12554 "MOV $tmp,$src2.hi\n\t"
12555 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12556 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12557 ins_pipe( ialu_cr_reg_reg );
12558 %}
12559
12560 // Long compares reg < zero/req OR reg >= zero/req.
12561 // Just a wrapper for a normal branch, plus the predicate test
12562 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12563 match(If cmp flags);
12564 effect(USE labl);
12565 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12566 ins_cost(300);
12567 expand %{
12568 jmpCon(cmp,flags,labl); // JGT or JLE...
12569 %}
12570 %}
12571
12572 // Compare 2 longs and CMOVE longs.
12573 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12574 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12575 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12576 ins_cost(400);
12577 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12578 "CMOV$cmp $dst.hi,$src.hi" %}
12579 opcode(0x0F,0x40);
12580 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12581 ins_pipe( pipe_cmov_reg_long );
12582 %}
12583
12584 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12585 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12586 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12587 ins_cost(500);
12588 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12589 "CMOV$cmp $dst.hi,$src.hi+4" %}
12590 opcode(0x0F,0x40);
12591 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12592 ins_pipe( pipe_cmov_reg_long );
12593 %}
12594
12595 // Compare 2 longs and CMOVE ints.
12596 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
12597 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12598 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12599 ins_cost(200);
12600 format %{ "CMOV$cmp $dst,$src" %}
12601 opcode(0x0F,0x40);
12602 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12603 ins_pipe( pipe_cmov_reg );
12604 %}
12605
12606 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
12607 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12608 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12609 ins_cost(250);
12610 format %{ "CMOV$cmp $dst,$src" %}
12611 opcode(0x0F,0x40);
12612 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12613 ins_pipe( pipe_cmov_mem );
12614 %}
12615
12616 // Compare 2 longs and CMOVE ptrs.
12617 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12618 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12619 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12620 ins_cost(200);
12621 format %{ "CMOV$cmp $dst,$src" %}
12622 opcode(0x0F,0x40);
12623 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12624 ins_pipe( pipe_cmov_reg );
12625 %}
12626
12627 // Compare 2 longs and CMOVE doubles
12628 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12629 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12630 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12631 ins_cost(200);
12632 expand %{
12633 fcmovD_regS(cmp,flags,dst,src);
12634 %}
12635 %}
12636
12637 // Compare 2 longs and CMOVE doubles
12638 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
12639 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12640 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12641 ins_cost(200);
12642 expand %{
12643 fcmovXD_regS(cmp,flags,dst,src);
12644 %}
12645 %}
12646
12647 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
12648 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12649 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12650 ins_cost(200);
12651 expand %{
12652 fcmovF_regS(cmp,flags,dst,src);
12653 %}
12654 %}
12655
12656
12657 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
12658 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12659 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12660 ins_cost(200);
12661 expand %{
12662 fcmovX_regS(cmp,flags,dst,src);
12663 %}
12664 %}
12665
12666
12667 // ============================================================================
12668 // Procedure Call/Return Instructions
12669 // Call Java Static Instruction
12670 // Note: If this code changes, the corresponding ret_addr_offset() and
12671 // compute_padding() functions will have to be adjusted.
12672 instruct CallStaticJavaDirect(method meth) %{
12673 match(CallStaticJava);
12674 effect(USE meth);
12675
12676 ins_cost(300);
12677 format %{ "CALL,static " %}
12678 opcode(0xE8); /* E8 cd */
12679 ins_encode( pre_call_FPU,
12680 Java_Static_Call( meth ),
12681 call_epilog,
12682 post_call_FPU );
12683 ins_pipe( pipe_slow );
12684 ins_pc_relative(1);
12685 ins_alignment(4);
12686 %}
12687
12688 // Call Java Dynamic Instruction
12689 // Note: If this code changes, the corresponding ret_addr_offset() and
12690 // compute_padding() functions will have to be adjusted.
12691 instruct CallDynamicJavaDirect(method meth) %{
12692 match(CallDynamicJava);
12693 effect(USE meth);
12694
12695 ins_cost(300);
12696 format %{ "MOV EAX,(oop)-1\n\t"
12697 "CALL,dynamic" %}
12698 opcode(0xE8); /* E8 cd */
12699 ins_encode( pre_call_FPU,
12700 Java_Dynamic_Call( meth ),
12701 call_epilog,
12702 post_call_FPU );
12703 ins_pipe( pipe_slow );
12704 ins_pc_relative(1);
12705 ins_alignment(4);
12706 %}
12707
12708 // Call Runtime Instruction
12709 instruct CallRuntimeDirect(method meth) %{
12710 match(CallRuntime );
12711 effect(USE meth);
12712
12713 ins_cost(300);
12714 format %{ "CALL,runtime " %}
12715 opcode(0xE8); /* E8 cd */
12716 // Use FFREEs to clear entries in float stack
12717 ins_encode( pre_call_FPU,
12718 FFree_Float_Stack_All,
12719 Java_To_Runtime( meth ),
12720 post_call_FPU );
12721 ins_pipe( pipe_slow );
12722 ins_pc_relative(1);
12723 %}
12724
12725 // Call runtime without safepoint
12726 instruct CallLeafDirect(method meth) %{
12727 match(CallLeaf);
12728 effect(USE meth);
12729
12730 ins_cost(300);
12731 format %{ "CALL_LEAF,runtime " %}
12732 opcode(0xE8); /* E8 cd */
12733 ins_encode( pre_call_FPU,
12734 FFree_Float_Stack_All,
12735 Java_To_Runtime( meth ),
12736 Verify_FPU_For_Leaf, post_call_FPU );
12737 ins_pipe( pipe_slow );
12738 ins_pc_relative(1);
12739 %}
12740
12741 instruct CallLeafNoFPDirect(method meth) %{
12742 match(CallLeafNoFP);
12743 effect(USE meth);
12744
12745 ins_cost(300);
12746 format %{ "CALL_LEAF_NOFP,runtime " %}
12747 opcode(0xE8); /* E8 cd */
12748 ins_encode(Java_To_Runtime(meth));
12749 ins_pipe( pipe_slow );
12750 ins_pc_relative(1);
12751 %}
12752
12753
12754 // Return Instruction
12755 // Remove the return address & jump to it.
12756 instruct Ret() %{
12757 match(Return);
12758 format %{ "RET" %}
12759 opcode(0xC3);
12760 ins_encode(OpcP);
12761 ins_pipe( pipe_jmp );
12762 %}
12763
12764 // Tail Call; Jump from runtime stub to Java code.
12765 // Also known as an 'interprocedural jump'.
12766 // Target of jump will eventually return to caller.
12767 // TailJump below removes the return address.
12768 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
12769 match(TailCall jump_target method_oop );
12770 ins_cost(300);
12771 format %{ "JMP $jump_target \t# EBX holds method oop" %}
12772 opcode(0xFF, 0x4); /* Opcode FF /4 */
12773 ins_encode( OpcP, RegOpc(jump_target) );
12774 ins_pipe( pipe_jmp );
12775 %}
12776
12777
12778 // Tail Jump; remove the return address; jump to target.
12779 // TailCall above leaves the return address around.
12780 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
12781 match( TailJump jump_target ex_oop );
12782 ins_cost(300);
12783 format %{ "POP EDX\t# pop return address into dummy\n\t"
12784 "JMP $jump_target " %}
12785 opcode(0xFF, 0x4); /* Opcode FF /4 */
12786 ins_encode( enc_pop_rdx,
12787 OpcP, RegOpc(jump_target) );
12788 ins_pipe( pipe_jmp );
12789 %}
12790
12791 // Create exception oop: created by stack-crawling runtime code.
12792 // Created exception is now available to this handler, and is setup
12793 // just prior to jumping to this handler. No code emitted.
12794 instruct CreateException( eAXRegP ex_oop )
12795 %{
12796 match(Set ex_oop (CreateEx));
12797
12798 size(0);
12799 // use the following format syntax
12800 format %{ "# exception oop is in EAX; no code emitted" %}
12801 ins_encode();
12802 ins_pipe( empty );
12803 %}
12804
12805
12806 // Rethrow exception:
12807 // The exception oop will come in the first argument position.
12808 // Then JUMP (not call) to the rethrow stub code.
12809 instruct RethrowException()
12810 %{
12811 match(Rethrow);
12812
12813 // use the following format syntax
12814 format %{ "JMP rethrow_stub" %}
12815 ins_encode(enc_rethrow);
12816 ins_pipe( pipe_jmp );
12817 %}
12818
12819 // inlined locking and unlocking
12820
12821
12822 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
12823 match( Set cr (FastLock object box) );
12824 effect( TEMP tmp, TEMP scr );
12825 ins_cost(300);
12826 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
12827 ins_encode( Fast_Lock(object,box,tmp,scr) );
12828 ins_pipe( pipe_slow );
12829 ins_pc_relative(1);
12830 %}
12831
12832 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
12833 match( Set cr (FastUnlock object box) );
12834 effect( TEMP tmp );
12835 ins_cost(300);
12836 format %{ "FASTUNLOCK $object, $box, $tmp" %}
12837 ins_encode( Fast_Unlock(object,box,tmp) );
12838 ins_pipe( pipe_slow );
12839 ins_pc_relative(1);
12840 %}
12841
12842
12843
12844 // ============================================================================
12845 // Safepoint Instruction
12846 instruct safePoint_poll(eFlagsReg cr) %{
12847 match(SafePoint);
12848 effect(KILL cr);
12849
12850 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
12851 // On SPARC that might be acceptable as we can generate the address with
12852 // just a sethi, saving an or. By polling at offset 0 we can end up
12853 // putting additional pressure on the index-0 in the D$. Because of
12854 // alignment (just like the situation at hand) the lower indices tend
12855 // to see more traffic. It'd be better to change the polling address
12856 // to offset 0 of the last $line in the polling page.
12857
12858 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
12859 ins_cost(125);
12860 size(6) ;
12861 ins_encode( Safepoint_Poll() );
12862 ins_pipe( ialu_reg_mem );
12863 %}
12864
12865 //----------PEEPHOLE RULES-----------------------------------------------------
12866 // These must follow all instruction definitions as they use the names
12867 // defined in the instructions definitions.
12868 //
12869 // peepmatch ( root_instr_name [preceeding_instruction]* );
12870 //
12871 // peepconstraint %{
12872 // (instruction_number.operand_name relational_op instruction_number.operand_name
12873 // [, ...] );
12874 // // instruction numbers are zero-based using left to right order in peepmatch
12875 //
12876 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12877 // // provide an instruction_number.operand_name for each operand that appears
12878 // // in the replacement instruction's match rule
12879 //
12880 // ---------VM FLAGS---------------------------------------------------------
12881 //
12882 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12883 //
12884 // Each peephole rule is given an identifying number starting with zero and
12885 // increasing by one in the order seen by the parser. An individual peephole
12886 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12887 // on the command-line.
12888 //
12889 // ---------CURRENT LIMITATIONS----------------------------------------------
12890 //
12891 // Only match adjacent instructions in same basic block
12892 // Only equality constraints
12893 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12894 // Only one replacement instruction
12895 //
12896 // ---------EXAMPLE----------------------------------------------------------
12897 //
12898 // // pertinent parts of existing instructions in architecture description
12899 // instruct movI(eRegI dst, eRegI src) %{
12900 // match(Set dst (CopyI src));
12901 // %}
12902 //
12903 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12904 // match(Set dst (AddI dst src));
12905 // effect(KILL cr);
12906 // %}
12907 //
12908 // // Change (inc mov) to lea
12909 // peephole %{
12910 // // increment preceeded by register-register move
12911 // peepmatch ( incI_eReg movI );
12912 // // require that the destination register of the increment
12913 // // match the destination register of the move
12914 // peepconstraint ( 0.dst == 1.dst );
12915 // // construct a replacement instruction that sets
12916 // // the destination to ( move's source register + one )
12917 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12918 // %}
12919 //
12920 // Implementation no longer uses movX instructions since
12921 // machine-independent system no longer uses CopyX nodes.
12922 //
12923 // peephole %{
12924 // peepmatch ( incI_eReg movI );
12925 // peepconstraint ( 0.dst == 1.dst );
12926 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12927 // %}
12928 //
12929 // peephole %{
12930 // peepmatch ( decI_eReg movI );
12931 // peepconstraint ( 0.dst == 1.dst );
12932 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12933 // %}
12934 //
12935 // peephole %{
12936 // peepmatch ( addI_eReg_imm movI );
12937 // peepconstraint ( 0.dst == 1.dst );
12938 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12939 // %}
12940 //
12941 // peephole %{
12942 // peepmatch ( addP_eReg_imm movP );
12943 // peepconstraint ( 0.dst == 1.dst );
12944 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12945 // %}
12946
12947 // // Change load of spilled value to only a spill
12948 // instruct storeI(memory mem, eRegI src) %{
12949 // match(Set mem (StoreI mem src));
12950 // %}
12951 //
12952 // instruct loadI(eRegI dst, memory mem) %{
12953 // match(Set dst (LoadI mem));
12954 // %}
12955 //
12956 peephole %{
12957 peepmatch ( loadI storeI );
12958 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12959 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12960 %}
12961
12962 //----------SMARTSPILL RULES---------------------------------------------------
12963 // These must follow all instruction definitions as they use the names
12964 // defined in the instructions definitions.