1 /*
2 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_chaitin.cpp.incl"
27
28 //=============================================================================
29
30 #ifndef PRODUCT
31 void LRG::dump( ) const {
32 ttyLocker ttyl;
33 tty->print("%d ",num_regs());
34 _mask.dump();
35 if( _msize_valid ) {
36 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
37 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
38 } else {
39 tty->print(", #?(%d) ",_mask.Size());
40 }
41
42 tty->print("EffDeg: ");
43 if( _degree_valid ) tty->print( "%d ", _eff_degree );
44 else tty->print("? ");
45
46 if( is_multidef() ) {
47 tty->print("MultiDef ");
48 if (_defs != NULL) {
49 tty->print("(");
50 for (int i = 0; i < _defs->length(); i++) {
51 tty->print("N%d ", _defs->at(i)->_idx);
52 }
53 tty->print(") ");
54 }
55 }
56 else if( _def == 0 ) tty->print("Dead ");
57 else tty->print("Def: N%d ",_def->_idx);
58
59 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
60 // Flags
61 if( _is_oop ) tty->print("Oop ");
62 if( _is_float ) tty->print("Float ");
63 if( _was_spilled1 ) tty->print("Spilled ");
64 if( _was_spilled2 ) tty->print("Spilled2 ");
65 if( _direct_conflict ) tty->print("Direct_conflict ");
66 if( _fat_proj ) tty->print("Fat ");
67 if( _was_lo ) tty->print("Lo ");
68 if( _has_copy ) tty->print("Copy ");
69 if( _at_risk ) tty->print("Risk ");
70
71 if( _must_spill ) tty->print("Must_spill ");
72 if( _is_bound ) tty->print("Bound ");
73 if( _msize_valid ) {
74 if( _degree_valid && lo_degree() ) tty->print("Trivial ");
75 }
76
77 tty->cr();
78 }
79 #endif
80
81 //------------------------------score------------------------------------------
82 // Compute score from cost and area. Low score is best to spill.
83 static double raw_score( double cost, double area ) {
84 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
85 }
86
87 double LRG::score() const {
88 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
89 // Bigger area lowers score, encourages spilling this live range.
90 // Bigger cost raise score, prevents spilling this live range.
91 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
92 // to turn a divide by a constant into a multiply by the reciprical).
93 double score = raw_score( _cost, _area);
94
95 // Account for area. Basically, LRGs covering large areas are better
96 // to spill because more other LRGs get freed up.
97 if( _area == 0.0 ) // No area? Then no progress to spill
98 return 1e35;
99
100 if( _was_spilled2 ) // If spilled once before, we are unlikely
101 return score + 1e30; // to make progress again.
102
103 if( _cost >= _area*3.0 ) // Tiny area relative to cost
104 return score + 1e17; // Probably no progress to spill
105
106 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
107 return score + 1e10; // Likely no progress to spill
108
109 return score;
110 }
111
112 //------------------------------LRG_List---------------------------------------
113 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
114 memset( _lidxs, 0, sizeof(uint)*max );
115 }
116
117 void LRG_List::extend( uint nidx, uint lidx ) {
118 _nesting.check();
119 if( nidx >= _max ) {
120 uint size = 16;
121 while( size <= nidx ) size <<=1;
122 _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size );
123 _max = size;
124 }
125 while( _cnt <= nidx )
126 _lidxs[_cnt++] = 0;
127 _lidxs[nidx] = lidx;
128 }
129
130 #define NUMBUCKS 3
131
132 //------------------------------Chaitin----------------------------------------
133 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
134 : PhaseRegAlloc(unique, cfg, matcher,
135 #ifndef PRODUCT
136 print_chaitin_statistics
137 #else
138 NULL
139 #endif
140 ),
141 _names(unique), _uf_map(unique),
142 _maxlrg(0), _live(0),
143 _spilled_once(Thread::current()->resource_area()),
144 _spilled_twice(Thread::current()->resource_area()),
145 _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0),
146 _oldphi(unique)
147 #ifndef PRODUCT
148 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
149 #endif
150 {
151 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
152 uint i,j;
153 // Build a list of basic blocks, sorted by frequency
154 _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
155 // Experiment with sorting strategies to speed compilation
156 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
157 Block **buckets[NUMBUCKS]; // Array of buckets
158 uint buckcnt[NUMBUCKS]; // Array of bucket counters
159 double buckval[NUMBUCKS]; // Array of bucket value cutoffs
160 for( i = 0; i < NUMBUCKS; i++ ) {
161 buckets[i] = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
162 buckcnt[i] = 0;
163 // Bump by three orders of magnitude each time
164 cutoff *= 0.001;
165 buckval[i] = cutoff;
166 for( j = 0; j < _cfg._num_blocks; j++ ) {
167 buckets[i][j] = NULL;
168 }
169 }
170 // Sort blocks into buckets
171 for( i = 0; i < _cfg._num_blocks; i++ ) {
172 for( j = 0; j < NUMBUCKS; j++ ) {
173 if( (j == NUMBUCKS-1) || (_cfg._blocks[i]->_freq > buckval[j]) ) {
174 // Assign block to end of list for appropriate bucket
175 buckets[j][buckcnt[j]++] = _cfg._blocks[i];
176 break; // kick out of inner loop
177 }
178 }
179 }
180 // Dump buckets into final block array
181 uint blkcnt = 0;
182 for( i = 0; i < NUMBUCKS; i++ ) {
183 for( j = 0; j < buckcnt[i]; j++ ) {
184 _blks[blkcnt++] = buckets[i][j];
185 }
186 }
187
188 assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");
189 }
190
191 void PhaseChaitin::Register_Allocate() {
192
193 // Above the OLD FP (and in registers) are the incoming arguments. Stack
194 // slots in this area are called "arg_slots". Above the NEW FP (and in
195 // registers) is the outgoing argument area; above that is the spill/temp
196 // area. These are all "frame_slots". Arg_slots start at the zero
197 // stack_slots and count up to the known arg_size. Frame_slots start at
198 // the stack_slot #arg_size and go up. After allocation I map stack
199 // slots to actual offsets. Stack-slots in the arg_slot area are biased
200 // by the frame_size; stack-slots in the frame_slot area are biased by 0.
201
202 _trip_cnt = 0;
203 _alternate = 0;
204 _matcher._allocation_started = true;
205
206 ResourceArea live_arena; // Arena for liveness & IFG info
207 ResourceMark rm(&live_arena);
208
209 // Need live-ness for the IFG; need the IFG for coalescing. If the
210 // liveness is JUST for coalescing, then I can get some mileage by renaming
211 // all copy-related live ranges low and then using the max copy-related
212 // live range as a cut-off for LIVE and the IFG. In other words, I can
213 // build a subset of LIVE and IFG just for copies.
214 PhaseLive live(_cfg,_names,&live_arena);
215
216 // Need IFG for coalescing and coloring
217 PhaseIFG ifg( &live_arena );
218 _ifg = &ifg;
219
220 if (C->unique() > _names.Size()) _names.extend(C->unique()-1, 0);
221
222 // Come out of SSA world to the Named world. Assign (virtual) registers to
223 // Nodes. Use the same register for all inputs and the output of PhiNodes
224 // - effectively ending SSA form. This requires either coalescing live
225 // ranges or inserting copies. For the moment, we insert "virtual copies"
226 // - we pretend there is a copy prior to each Phi in predecessor blocks.
227 // We will attempt to coalesce such "virtual copies" before we manifest
228 // them for real.
229 de_ssa();
230
231 {
232 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
233 _live = NULL; // Mark live as being not available
234 rm.reset_to_mark(); // Reclaim working storage
235 IndexSet::reset_memory(C, &live_arena);
236 ifg.init(_maxlrg); // Empty IFG
237 gather_lrg_masks( false ); // Collect LRG masks
238 live.compute( _maxlrg ); // Compute liveness
239 _live = &live; // Mark LIVE as being available
240 }
241
242 // Base pointers are currently "used" by instructions which define new
243 // derived pointers. This makes base pointers live up to the where the
244 // derived pointer is made, but not beyond. Really, they need to be live
245 // across any GC point where the derived value is live. So this code looks
246 // at all the GC points, and "stretches" the live range of any base pointer
247 // to the GC point.
248 if( stretch_base_pointer_live_ranges(&live_arena) ) {
249 NOT_PRODUCT( Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler); )
250 // Since some live range stretched, I need to recompute live
251 _live = NULL;
252 rm.reset_to_mark(); // Reclaim working storage
253 IndexSet::reset_memory(C, &live_arena);
254 ifg.init(_maxlrg);
255 gather_lrg_masks( false );
256 live.compute( _maxlrg );
257 _live = &live;
258 }
259 // Create the interference graph using virtual copies
260 build_ifg_virtual( ); // Include stack slots this time
261
262 // Aggressive (but pessimistic) copy coalescing.
263 // This pass works on virtual copies. Any virtual copies which are not
264 // coalesced get manifested as actual copies
265 {
266 // The IFG is/was triangular. I am 'squaring it up' so Union can run
267 // faster. Union requires a 'for all' operation which is slow on the
268 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
269 // meaning I can visit all the Nodes neighbors less than a Node in time
270 // O(# of neighbors), but I have to visit all the Nodes greater than a
271 // given Node and search them for an instance, i.e., time O(#MaxLRG)).
272 _ifg->SquareUp();
273
274 PhaseAggressiveCoalesce coalesce( *this );
275 coalesce.coalesce_driver( );
276 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do
277 // not match the Phi itself, insert a copy.
278 coalesce.insert_copies(_matcher);
279 }
280
281 // After aggressive coalesce, attempt a first cut at coloring.
282 // To color, we need the IFG and for that we need LIVE.
283 {
284 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
285 _live = NULL;
286 rm.reset_to_mark(); // Reclaim working storage
287 IndexSet::reset_memory(C, &live_arena);
288 ifg.init(_maxlrg);
289 gather_lrg_masks( true );
290 live.compute( _maxlrg );
291 _live = &live;
292 }
293
294 // Build physical interference graph
295 uint must_spill = 0;
296 must_spill = build_ifg_physical( &live_arena );
297 // If we have a guaranteed spill, might as well spill now
298 if( must_spill ) {
299 if( !_maxlrg ) return;
300 // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
301 C->check_node_count(10*must_spill, "out of nodes before split");
302 if (C->failing()) return;
303 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere
304 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
305 // or we failed to split
306 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
307 if (C->failing()) return;
308
309 #ifdef ASSERT
310 if( VerifyOpto ) {
311 _cfg.verify();
312 verify_base_ptrs(&live_arena);
313 }
314 #endif
315 NOT_PRODUCT( C->verify_graph_edges(); )
316
317 compact(); // Compact LRGs; return new lower max lrg
318
319 {
320 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
321 _live = NULL;
322 rm.reset_to_mark(); // Reclaim working storage
323 IndexSet::reset_memory(C, &live_arena);
324 ifg.init(_maxlrg); // Build a new interference graph
325 gather_lrg_masks( true ); // Collect intersect mask
326 live.compute( _maxlrg ); // Compute LIVE
327 _live = &live;
328 }
329 build_ifg_physical( &live_arena );
330 _ifg->SquareUp();
331 _ifg->Compute_Effective_Degree();
332 // Only do conservative coalescing if requested
333 if( OptoCoalesce ) {
334 // Conservative (and pessimistic) copy coalescing of those spills
335 PhaseConservativeCoalesce coalesce( *this );
336 // If max live ranges greater than cutoff, don't color the stack.
337 // This cutoff can be larger than below since it is only done once.
338 coalesce.coalesce_driver( );
339 }
340 compress_uf_map_for_nodes();
341
342 #ifdef ASSERT
343 if( VerifyOpto ) _ifg->verify(this);
344 #endif
345 } else {
346 ifg.SquareUp();
347 ifg.Compute_Effective_Degree();
348 #ifdef ASSERT
349 set_was_low();
350 #endif
351 }
352
353 // Prepare for Simplify & Select
354 cache_lrg_info(); // Count degree of LRGs
355
356 // Simplify the InterFerence Graph by removing LRGs of low degree.
357 // LRGs of low degree are trivially colorable.
358 Simplify();
359
360 // Select colors by re-inserting LRGs back into the IFG in reverse order.
361 // Return whether or not something spills.
362 uint spills = Select( );
363
364 // If we spill, split and recycle the entire thing
365 while( spills ) {
366 if( _trip_cnt++ > 24 ) {
367 DEBUG_ONLY( dump_for_spill_split_recycle(); )
368 if( _trip_cnt > 27 ) {
369 C->record_method_not_compilable("failed spill-split-recycle sanity check");
370 return;
371 }
372 }
373
374 if( !_maxlrg ) return;
375 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere
376 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
377 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after split");
378 if (C->failing()) return;
379 #ifdef ASSERT
380 if( VerifyOpto ) {
381 _cfg.verify();
382 verify_base_ptrs(&live_arena);
383 }
384 #endif
385
386 compact(); // Compact LRGs; return new lower max lrg
387
388 // Nuke the live-ness and interference graph and LiveRanGe info
389 {
390 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
391 _live = NULL;
392 rm.reset_to_mark(); // Reclaim working storage
393 IndexSet::reset_memory(C, &live_arena);
394 ifg.init(_maxlrg);
395
396 // Create LiveRanGe array.
397 // Intersect register masks for all USEs and DEFs
398 gather_lrg_masks( true );
399 live.compute( _maxlrg );
400 _live = &live;
401 }
402 must_spill = build_ifg_physical( &live_arena );
403 _ifg->SquareUp();
404 _ifg->Compute_Effective_Degree();
405
406 // Only do conservative coalescing if requested
407 if( OptoCoalesce ) {
408 // Conservative (and pessimistic) copy coalescing
409 PhaseConservativeCoalesce coalesce( *this );
410 // Check for few live ranges determines how aggressive coalesce is.
411 coalesce.coalesce_driver( );
412 }
413 compress_uf_map_for_nodes();
414 #ifdef ASSERT
415 if( VerifyOpto ) _ifg->verify(this);
416 #endif
417 cache_lrg_info(); // Count degree of LRGs
418
419 // Simplify the InterFerence Graph by removing LRGs of low degree.
420 // LRGs of low degree are trivially colorable.
421 Simplify();
422
423 // Select colors by re-inserting LRGs back into the IFG in reverse order.
424 // Return whether or not something spills.
425 spills = Select( );
426 }
427
428 // Count number of Simplify-Select trips per coloring success.
429 _allocator_attempts += _trip_cnt + 1;
430 _allocator_successes += 1;
431
432 // Peephole remove copies
433 post_allocate_copy_removal();
434
435 // max_reg is past the largest *register* used.
436 // Convert that to a frame_slot number.
437 if( _max_reg <= _matcher._new_SP )
438 _framesize = C->out_preserve_stack_slots();
439 else _framesize = _max_reg -_matcher._new_SP;
440 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
441
442 // This frame must preserve the required fp alignment
443 const int stack_alignment_in_words = Matcher::stack_alignment_in_slots();
444 if (stack_alignment_in_words > 0)
445 _framesize = round_to(_framesize, Matcher::stack_alignment_in_bytes());
446 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
447 #ifndef PRODUCT
448 _total_framesize += _framesize;
449 if( (int)_framesize > _max_framesize )
450 _max_framesize = _framesize;
451 #endif
452
453 // Convert CISC spills
454 fixup_spills();
455
456 // Log regalloc results
457 CompileLog* log = Compile::current()->log();
458 if (log != NULL) {
459 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
460 }
461
462 if (C->failing()) return;
463
464 NOT_PRODUCT( C->verify_graph_edges(); )
465
466 // Move important info out of the live_arena to longer lasting storage.
467 alloc_node_regs(_names.Size());
468 for( uint i=0; i < _names.Size(); i++ ) {
469 if( _names[i] ) { // Live range associated with Node?
470 LRG &lrg = lrgs( _names[i] );
471 if( lrg.num_regs() == 1 ) {
472 _node_regs[i].set1( lrg.reg() );
473 } else { // Must be a register-pair
474 if( !lrg._fat_proj ) { // Must be aligned adjacent register pair
475 // Live ranges record the highest register in their mask.
476 // We want the low register for the AD file writer's convenience.
477 _node_regs[i].set2( OptoReg::add(lrg.reg(),-1) );
478 } else { // Misaligned; extract 2 bits
479 OptoReg::Name hi = lrg.reg(); // Get hi register
480 lrg.Remove(hi); // Yank from mask
481 int lo = lrg.mask().find_first_elem(); // Find lo
482 _node_regs[i].set_pair( hi, lo );
483 }
484 }
485 if( lrg._is_oop ) _node_oops.set(i);
486 } else {
487 _node_regs[i].set_bad();
488 }
489 }
490
491 // Done!
492 _live = NULL;
493 _ifg = NULL;
494 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope
495 }
496
497 //------------------------------de_ssa-----------------------------------------
498 void PhaseChaitin::de_ssa() {
499 // Set initial Names for all Nodes. Most Nodes get the virtual register
500 // number. A few get the ZERO live range number. These do not
501 // get allocated, but instead rely on correct scheduling to ensure that
502 // only one instance is simultaneously live at a time.
503 uint lr_counter = 1;
504 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
505 Block *b = _cfg._blocks[i];
506 uint cnt = b->_nodes.size();
507
508 // Handle all the normal Nodes in the block
509 for( uint j = 0; j < cnt; j++ ) {
510 Node *n = b->_nodes[j];
511 // Pre-color to the zero live range, or pick virtual register
512 const RegMask &rm = n->out_RegMask();
513 _names.map( n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0 );
514 }
515 }
516 // Reset the Union-Find mapping to be identity
517 reset_uf_map(lr_counter);
518 }
519
520
521 //------------------------------gather_lrg_masks-------------------------------
522 // Gather LiveRanGe information, including register masks. Modification of
523 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
524 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
525
526 // Nail down the frame pointer live range
527 uint fp_lrg = n2lidx(_cfg._root->in(1)->in(TypeFunc::FramePtr));
528 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
529
530 // For all blocks
531 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
532 Block *b = _cfg._blocks[i];
533
534 // For all instructions
535 for( uint j = 1; j < b->_nodes.size(); j++ ) {
536 Node *n = b->_nodes[j];
537 uint input_edge_start =1; // Skip control most nodes
538 if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base();
539 uint idx = n->is_Copy();
540
541 // Get virtual register number, same as LiveRanGe index
542 uint vreg = n2lidx(n);
543 LRG &lrg = lrgs(vreg);
544 if( vreg ) { // No vreg means un-allocable (e.g. memory)
545
546 // Collect has-copy bit
547 if( idx ) {
548 lrg._has_copy = 1;
549 uint clidx = n2lidx(n->in(idx));
550 LRG ©_src = lrgs(clidx);
551 copy_src._has_copy = 1;
552 }
553
554 // Check for float-vs-int live range (used in register-pressure
555 // calculations)
556 const Type *n_type = n->bottom_type();
557 if( n_type->is_floatingpoint() )
558 lrg._is_float = 1;
559
560 // Check for twice prior spilling. Once prior spilling might have
561 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
562 // further spilling is unlikely to make progress.
563 if( _spilled_once.test(n->_idx) ) {
564 lrg._was_spilled1 = 1;
565 if( _spilled_twice.test(n->_idx) )
566 lrg._was_spilled2 = 1;
567 }
568
569 #ifndef PRODUCT
570 if (trace_spilling() && lrg._def != NULL) {
571 // collect defs for MultiDef printing
572 if (lrg._defs == NULL) {
573 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>();
574 lrg._defs->append(lrg._def);
575 }
576 lrg._defs->append(n);
577 }
578 #endif
579
580 // Check for a single def LRG; these can spill nicely
581 // via rematerialization. Flag as NULL for no def found
582 // yet, or 'n' for single def or -1 for many defs.
583 lrg._def = lrg._def ? NodeSentinel : n;
584
585 // Limit result register mask to acceptable registers
586 const RegMask &rm = n->out_RegMask();
587 lrg.AND( rm );
588 // Check for bound register masks
589 const RegMask &lrgmask = lrg.mask();
590 if( lrgmask.is_bound1() || lrgmask.is_bound2() )
591 lrg._is_bound = 1;
592
593 // Check for maximum frequency value
594 if( lrg._maxfreq < b->_freq )
595 lrg._maxfreq = b->_freq;
596
597 int ireg = n->ideal_reg();
598 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
599 "oops must be in Op_RegP's" );
600 // Check for oop-iness, or long/double
601 // Check for multi-kill projection
602 switch( ireg ) {
603 case MachProjNode::fat_proj:
604 // Fat projections have size equal to number of registers killed
605 lrg.set_num_regs(rm.Size());
606 lrg.set_reg_pressure(lrg.num_regs());
607 lrg._fat_proj = 1;
608 lrg._is_bound = 1;
609 break;
610 case Op_RegP:
611 #ifdef _LP64
612 lrg.set_num_regs(2); // Size is 2 stack words
613 #else
614 lrg.set_num_regs(1); // Size is 1 stack word
615 #endif
616 // Register pressure is tracked relative to the maximum values
617 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
618 // and relative to other types which compete for the same regs.
619 //
620 // The following table contains suggested values based on the
621 // architectures as defined in each .ad file.
622 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
623 // compile-speed or performance.
624 // Note1:
625 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
626 // since .ad registers are defined as high and low halves.
627 // These reg_pressure values remain compatible with the code
628 // in is_high_pressure() which relates get_invalid_mask_size(),
629 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
630 // Note2:
631 // SPARC -d32 has 24 registers available for integral values,
632 // but only 10 of these are safe for 64-bit longs.
633 // Using set_reg_pressure(2) for both int and long means
634 // the allocator will believe it can fit 26 longs into
635 // registers. Using 2 for longs and 1 for ints means the
636 // allocator will attempt to put 52 integers into registers.
637 // The settings below limit this problem to methods with
638 // many long values which are being run on 32-bit SPARC.
639 //
640 // ------------------- reg_pressure --------------------
641 // Each entry is reg_pressure_per_value,number_of_regs
642 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
643 // IA32 2 1 1 1 1 6 6
644 // IA64 1 1 1 1 1 50 41
645 // SPARC 2 2 2 2 2 48 (24) 52 (26)
646 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
647 // AMD64 1 1 1 1 1 14 15
648 // -----------------------------------------------------
649 #if defined(SPARC)
650 lrg.set_reg_pressure(2); // use for v9 as well
651 #else
652 lrg.set_reg_pressure(1); // normally one value per register
653 #endif
654 if( n_type->isa_oop_ptr() ) {
655 lrg._is_oop = 1;
656 }
657 break;
658 case Op_RegL: // Check for long or double
659 case Op_RegD:
660 lrg.set_num_regs(2);
661 // Define platform specific register pressure
662 #ifdef SPARC
663 lrg.set_reg_pressure(2);
664 #elif defined(IA32)
665 if( ireg == Op_RegL ) {
666 lrg.set_reg_pressure(2);
667 } else {
668 lrg.set_reg_pressure(1);
669 }
670 #else
671 lrg.set_reg_pressure(1); // normally one value per register
672 #endif
673 // If this def of a double forces a mis-aligned double,
674 // flag as '_fat_proj' - really flag as allowing misalignment
675 // AND changes how we count interferences. A mis-aligned
676 // double can interfere with TWO aligned pairs, or effectively
677 // FOUR registers!
678 if( rm.is_misaligned_Pair() ) {
679 lrg._fat_proj = 1;
680 lrg._is_bound = 1;
681 }
682 break;
683 case Op_RegF:
684 case Op_RegI:
685 case Op_RegN:
686 case Op_RegFlags:
687 case 0: // not an ideal register
688 lrg.set_num_regs(1);
689 #ifdef SPARC
690 lrg.set_reg_pressure(2);
691 #else
692 lrg.set_reg_pressure(1);
693 #endif
694 break;
695 default:
696 ShouldNotReachHere();
697 }
698 }
699
700 // Now do the same for inputs
701 uint cnt = n->req();
702 // Setup for CISC SPILLING
703 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
704 if( UseCISCSpill && after_aggressive ) {
705 inp = n->cisc_operand();
706 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
707 // Convert operand number to edge index number
708 inp = n->as_Mach()->operand_index(inp);
709 }
710 // Prepare register mask for each input
711 for( uint k = input_edge_start; k < cnt; k++ ) {
712 uint vreg = n2lidx(n->in(k));
713 if( !vreg ) continue;
714
715 // If this instruction is CISC Spillable, add the flags
716 // bit to its appropriate input
717 if( UseCISCSpill && after_aggressive && inp == k ) {
718 #ifndef PRODUCT
719 if( TraceCISCSpill ) {
720 tty->print(" use_cisc_RegMask: ");
721 n->dump();
722 }
723 #endif
724 n->as_Mach()->use_cisc_RegMask();
725 }
726
727 LRG &lrg = lrgs(vreg);
728 // // Testing for floating point code shape
729 // Node *test = n->in(k);
730 // if( test->is_Mach() ) {
731 // MachNode *m = test->as_Mach();
732 // int op = m->ideal_Opcode();
733 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
734 // int zzz = 1;
735 // }
736 // }
737
738 // Limit result register mask to acceptable registers.
739 // Do not limit registers from uncommon uses before
740 // AggressiveCoalesce. This effectively pre-virtual-splits
741 // around uncommon uses of common defs.
742 const RegMask &rm = n->in_RegMask(k);
743 if( !after_aggressive &&
744 _cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) {
745 // Since we are BEFORE aggressive coalesce, leave the register
746 // mask untrimmed by the call. This encourages more coalescing.
747 // Later, AFTER aggressive, this live range will have to spill
748 // but the spiller handles slow-path calls very nicely.
749 } else {
750 lrg.AND( rm );
751 }
752 // Check for bound register masks
753 const RegMask &lrgmask = lrg.mask();
754 if( lrgmask.is_bound1() || lrgmask.is_bound2() )
755 lrg._is_bound = 1;
756 // If this use of a double forces a mis-aligned double,
757 // flag as '_fat_proj' - really flag as allowing misalignment
758 // AND changes how we count interferences. A mis-aligned
759 // double can interfere with TWO aligned pairs, or effectively
760 // FOUR registers!
761 if( lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_Pair() ) {
762 lrg._fat_proj = 1;
763 lrg._is_bound = 1;
764 }
765 // if the LRG is an unaligned pair, we will have to spill
766 // so clear the LRG's register mask if it is not already spilled
767 if ( !n->is_SpillCopy() &&
768 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
769 lrgmask.is_misaligned_Pair()) {
770 lrg.Clear();
771 }
772
773 // Check for maximum frequency value
774 if( lrg._maxfreq < b->_freq )
775 lrg._maxfreq = b->_freq;
776
777 } // End for all allocated inputs
778 } // end for all instructions
779 } // end for all blocks
780
781 // Final per-liverange setup
782 for( uint i2=0; i2<_maxlrg; i2++ ) {
783 LRG &lrg = lrgs(i2);
784 if( lrg.num_regs() == 2 && !lrg._fat_proj )
785 lrg.ClearToPairs();
786 lrg.compute_set_mask_size();
787 if( lrg.not_free() ) { // Handle case where we lose from the start
788 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
789 lrg._direct_conflict = 1;
790 }
791 lrg.set_degree(0); // no neighbors in IFG yet
792 }
793 }
794
795 //------------------------------set_was_low------------------------------------
796 // Set the was-lo-degree bit. Conservative coalescing should not change the
797 // colorability of the graph. If any live range was of low-degree before
798 // coalescing, it should Simplify. This call sets the was-lo-degree bit.
799 // The bit is checked in Simplify.
800 void PhaseChaitin::set_was_low() {
801 #ifdef ASSERT
802 for( uint i = 1; i < _maxlrg; i++ ) {
803 int size = lrgs(i).num_regs();
804 uint old_was_lo = lrgs(i)._was_lo;
805 lrgs(i)._was_lo = 0;
806 if( lrgs(i).lo_degree() ) {
807 lrgs(i)._was_lo = 1; // Trivially of low degree
808 } else { // Else check the Brigg's assertion
809 // Brigg's observation is that the lo-degree neighbors of a
810 // hi-degree live range will not interfere with the color choices
811 // of said hi-degree live range. The Simplify reverse-stack-coloring
812 // order takes care of the details. Hence you do not have to count
813 // low-degree neighbors when determining if this guy colors.
814 int briggs_degree = 0;
815 IndexSet *s = _ifg->neighbors(i);
816 IndexSetIterator elements(s);
817 uint lidx;
818 while((lidx = elements.next()) != 0) {
819 if( !lrgs(lidx).lo_degree() )
820 briggs_degree += MAX2(size,lrgs(lidx).num_regs());
821 }
822 if( briggs_degree < lrgs(i).degrees_of_freedom() )
823 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion
824 }
825 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
826 }
827 #endif
828 }
829
830 #define REGISTER_CONSTRAINED 16
831
832 //------------------------------cache_lrg_info---------------------------------
833 // Compute cost/area ratio, in case we spill. Build the lo-degree list.
834 void PhaseChaitin::cache_lrg_info( ) {
835
836 for( uint i = 1; i < _maxlrg; i++ ) {
837 LRG &lrg = lrgs(i);
838
839 // Check for being of low degree: means we can be trivially colored.
840 // Low degree, dead or must-spill guys just get to simplify right away
841 if( lrg.lo_degree() ||
842 !lrg.alive() ||
843 lrg._must_spill ) {
844 // Split low degree list into those guys that must get a
845 // register and those that can go to register or stack.
846 // The idea is LRGs that can go register or stack color first when
847 // they have a good chance of getting a register. The register-only
848 // lo-degree live ranges always get a register.
849 OptoReg::Name hi_reg = lrg.mask().find_last_elem();
850 if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
851 lrg._next = _lo_stk_degree;
852 _lo_stk_degree = i;
853 } else {
854 lrg._next = _lo_degree;
855 _lo_degree = i;
856 }
857 } else { // Else high degree
858 lrgs(_hi_degree)._prev = i;
859 lrg._next = _hi_degree;
860 lrg._prev = 0;
861 _hi_degree = i;
862 }
863 }
864 }
865
866 //------------------------------Pre-Simplify-----------------------------------
867 // Simplify the IFG by removing LRGs of low degree that have NO copies
868 void PhaseChaitin::Pre_Simplify( ) {
869
870 // Warm up the lo-degree no-copy list
871 int lo_no_copy = 0;
872 for( uint i = 1; i < _maxlrg; i++ ) {
873 if( (lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
874 !lrgs(i).alive() ||
875 lrgs(i)._must_spill ) {
876 lrgs(i)._next = lo_no_copy;
877 lo_no_copy = i;
878 }
879 }
880
881 while( lo_no_copy ) {
882 uint lo = lo_no_copy;
883 lo_no_copy = lrgs(lo)._next;
884 int size = lrgs(lo).num_regs();
885
886 // Put the simplified guy on the simplified list.
887 lrgs(lo)._next = _simplified;
888 _simplified = lo;
889
890 // Yank this guy from the IFG.
891 IndexSet *adj = _ifg->remove_node( lo );
892
893 // If any neighbors' degrees fall below their number of
894 // allowed registers, then put that neighbor on the low degree
895 // list. Note that 'degree' can only fall and 'numregs' is
896 // unchanged by this action. Thus the two are equal at most once,
897 // so LRGs hit the lo-degree worklists at most once.
898 IndexSetIterator elements(adj);
899 uint neighbor;
900 while ((neighbor = elements.next()) != 0) {
901 LRG *n = &lrgs(neighbor);
902 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
903
904 // Check for just becoming of-low-degree
905 if( n->just_lo_degree() && !n->_has_copy ) {
906 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
907 // Put on lo-degree list
908 n->_next = lo_no_copy;
909 lo_no_copy = neighbor;
910 }
911 }
912 } // End of while lo-degree no_copy worklist not empty
913
914 // No more lo-degree no-copy live ranges to simplify
915 }
916
917 //------------------------------Simplify---------------------------------------
918 // Simplify the IFG by removing LRGs of low degree.
919 void PhaseChaitin::Simplify( ) {
920
921 while( 1 ) { // Repeat till simplified it all
922 // May want to explore simplifying lo_degree before _lo_stk_degree.
923 // This might result in more spills coloring into registers during
924 // Select().
925 while( _lo_degree || _lo_stk_degree ) {
926 // If possible, pull from lo_stk first
927 uint lo;
928 if( _lo_degree ) {
929 lo = _lo_degree;
930 _lo_degree = lrgs(lo)._next;
931 } else {
932 lo = _lo_stk_degree;
933 _lo_stk_degree = lrgs(lo)._next;
934 }
935
936 // Put the simplified guy on the simplified list.
937 lrgs(lo)._next = _simplified;
938 _simplified = lo;
939 // If this guy is "at risk" then mark his current neighbors
940 if( lrgs(lo)._at_risk ) {
941 IndexSetIterator elements(_ifg->neighbors(lo));
942 uint datum;
943 while ((datum = elements.next()) != 0) {
944 lrgs(datum)._risk_bias = lo;
945 }
946 }
947
948 // Yank this guy from the IFG.
949 IndexSet *adj = _ifg->remove_node( lo );
950
951 // If any neighbors' degrees fall below their number of
952 // allowed registers, then put that neighbor on the low degree
953 // list. Note that 'degree' can only fall and 'numregs' is
954 // unchanged by this action. Thus the two are equal at most once,
955 // so LRGs hit the lo-degree worklist at most once.
956 IndexSetIterator elements(adj);
957 uint neighbor;
958 while ((neighbor = elements.next()) != 0) {
959 LRG *n = &lrgs(neighbor);
960 #ifdef ASSERT
961 if( VerifyOpto ) {
962 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
963 }
964 #endif
965
966 // Check for just becoming of-low-degree just counting registers.
967 // _must_spill live ranges are already on the low degree list.
968 if( n->just_lo_degree() && !n->_must_spill ) {
969 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
970 // Pull from hi-degree list
971 uint prev = n->_prev;
972 uint next = n->_next;
973 if( prev ) lrgs(prev)._next = next;
974 else _hi_degree = next;
975 lrgs(next)._prev = prev;
976 n->_next = _lo_degree;
977 _lo_degree = neighbor;
978 }
979 }
980 } // End of while lo-degree/lo_stk_degree worklist not empty
981
982 // Check for got everything: is hi-degree list empty?
983 if( !_hi_degree ) break;
984
985 // Time to pick a potential spill guy
986 uint lo_score = _hi_degree;
987 double score = lrgs(lo_score).score();
988 double area = lrgs(lo_score)._area;
989
990 // Find cheapest guy
991 debug_only( int lo_no_simplify=0; );
992 for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
993 assert( !(*_ifg->_yanked)[i], "" );
994 // It's just vaguely possible to move hi-degree to lo-degree without
995 // going through a just-lo-degree stage: If you remove a double from
996 // a float live range it's degree will drop by 2 and you can skip the
997 // just-lo-degree stage. It's very rare (shows up after 5000+ methods
998 // in -Xcomp of Java2Demo). So just choose this guy to simplify next.
999 if( lrgs(i).lo_degree() ) {
1000 lo_score = i;
1001 break;
1002 }
1003 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1004 double iscore = lrgs(i).score();
1005 double iarea = lrgs(i)._area;
1006
1007 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area
1008 // wins. Ties happen because all live ranges in question have spilled
1009 // a few times before and the spill-score adds a huge number which
1010 // washes out the low order bits. We are choosing the lesser of 2
1011 // evils; in this case pick largest area to spill.
1012 if( iscore < score ||
1013 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ) {
1014 lo_score = i;
1015 score = iscore;
1016 area = iarea;
1017 }
1018 }
1019 LRG *lo_lrg = &lrgs(lo_score);
1020 // The live range we choose for spilling is either hi-degree, or very
1021 // rarely it can be low-degree. If we choose a hi-degree live range
1022 // there better not be any lo-degree choices.
1023 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1024
1025 // Pull from hi-degree list
1026 uint prev = lo_lrg->_prev;
1027 uint next = lo_lrg->_next;
1028 if( prev ) lrgs(prev)._next = next;
1029 else _hi_degree = next;
1030 lrgs(next)._prev = prev;
1031 // Jam him on the lo-degree list, despite his high degree.
1032 // Maybe he'll get a color, and maybe he'll spill.
1033 // Only Select() will know.
1034 lrgs(lo_score)._at_risk = true;
1035 _lo_degree = lo_score;
1036 lo_lrg->_next = 0;
1037
1038 } // End of while not simplified everything
1039
1040 }
1041
1042 //------------------------------bias_color-------------------------------------
1043 // Choose a color using the biasing heuristic
1044 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1045
1046 // Check for "at_risk" LRG's
1047 uint risk_lrg = Find(lrg._risk_bias);
1048 if( risk_lrg != 0 ) {
1049 // Walk the colored neighbors of the "at_risk" candidate
1050 // Choose a color which is both legal and already taken by a neighbor
1051 // of the "at_risk" candidate in order to improve the chances of the
1052 // "at_risk" candidate of coloring
1053 IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1054 uint datum;
1055 while ((datum = elements.next()) != 0) {
1056 OptoReg::Name reg = lrgs(datum).reg();
1057 // If this LRG's register is legal for us, choose it
1058 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE &&
1059 lrg.mask().Member(OptoReg::add(reg,-chunk)) &&
1060 (lrg.num_regs()==1 || // either size 1
1061 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs)
1062 return reg;
1063 }
1064 }
1065
1066 uint copy_lrg = Find(lrg._copy_bias);
1067 if( copy_lrg != 0 ) {
1068 // If he has a color,
1069 if( !(*(_ifg->_yanked))[copy_lrg] ) {
1070 OptoReg::Name reg = lrgs(copy_lrg).reg();
1071 // And it is legal for you,
1072 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE &&
1073 lrg.mask().Member(OptoReg::add(reg,-chunk)) &&
1074 (lrg.num_regs()==1 || // either size 1
1075 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs)
1076 return reg;
1077 } else if( chunk == 0 ) {
1078 // Choose a color which is legal for him
1079 RegMask tempmask = lrg.mask();
1080 tempmask.AND(lrgs(copy_lrg).mask());
1081 OptoReg::Name reg;
1082 if( lrg.num_regs() == 1 ) {
1083 reg = tempmask.find_first_elem();
1084 } else {
1085 tempmask.ClearToPairs();
1086 reg = tempmask.find_first_pair();
1087 }
1088 if( OptoReg::is_valid(reg) )
1089 return reg;
1090 }
1091 }
1092
1093 // If no bias info exists, just go with the register selection ordering
1094 if( lrg.num_regs() == 2 ) {
1095 // Find an aligned pair
1096 return OptoReg::add(lrg.mask().find_first_pair(),chunk);
1097 }
1098
1099 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
1100 // copy removal to remove many more copies, by preventing a just-assigned
1101 // register from being repeatedly assigned.
1102 OptoReg::Name reg = lrg.mask().find_first_elem();
1103 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1104 // This 'Remove; find; Insert' idiom is an expensive way to find the
1105 // SECOND element in the mask.
1106 lrg.Remove(reg);
1107 OptoReg::Name reg2 = lrg.mask().find_first_elem();
1108 lrg.Insert(reg);
1109 if( OptoReg::is_reg(reg2))
1110 reg = reg2;
1111 }
1112 return OptoReg::add( reg, chunk );
1113 }
1114
1115 //------------------------------choose_color-----------------------------------
1116 // Choose a color in the current chunk
1117 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1118 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1119 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1120
1121 if( lrg.num_regs() == 1 || // Common Case
1122 !lrg._fat_proj ) // Aligned+adjacent pairs ok
1123 // Use a heuristic to "bias" the color choice
1124 return bias_color(lrg, chunk);
1125
1126 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1127
1128 // Fat-proj case or misaligned double argument.
1129 assert(lrg.compute_mask_size() == lrg.num_regs() ||
1130 lrg.num_regs() == 2,"fat projs exactly color" );
1131 assert( !chunk, "always color in 1st chunk" );
1132 // Return the highest element in the set.
1133 return lrg.mask().find_last_elem();
1134 }
1135
1136 //------------------------------Select-----------------------------------------
1137 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
1138 // in reverse order of removal. As long as nothing of hi-degree was yanked,
1139 // everything going back is guaranteed a color. Select that color. If some
1140 // hi-degree LRG cannot get a color then we record that we must spill.
1141 uint PhaseChaitin::Select( ) {
1142 uint spill_reg = LRG::SPILL_REG;
1143 _max_reg = OptoReg::Name(0); // Past max register used
1144 while( _simplified ) {
1145 // Pull next LRG from the simplified list - in reverse order of removal
1146 uint lidx = _simplified;
1147 LRG *lrg = &lrgs(lidx);
1148 _simplified = lrg->_next;
1149
1150
1151 #ifndef PRODUCT
1152 if (trace_spilling()) {
1153 ttyLocker ttyl;
1154 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1155 lrg->degrees_of_freedom());
1156 lrg->dump();
1157 }
1158 #endif
1159
1160 // Re-insert into the IFG
1161 _ifg->re_insert(lidx);
1162 if( !lrg->alive() ) continue;
1163 // capture allstackedness flag before mask is hacked
1164 const int is_allstack = lrg->mask().is_AllStack();
1165
1166 // Yeah, yeah, yeah, I know, I know. I can refactor this
1167 // to avoid the GOTO, although the refactored code will not
1168 // be much clearer. We arrive here IFF we have a stack-based
1169 // live range that cannot color in the current chunk, and it
1170 // has to move into the next free stack chunk.
1171 int chunk = 0; // Current chunk is first chunk
1172 retry_next_chunk:
1173
1174 // Remove neighbor colors
1175 IndexSet *s = _ifg->neighbors(lidx);
1176
1177 debug_only(RegMask orig_mask = lrg->mask();)
1178 IndexSetIterator elements(s);
1179 uint neighbor;
1180 while ((neighbor = elements.next()) != 0) {
1181 // Note that neighbor might be a spill_reg. In this case, exclusion
1182 // of its color will be a no-op, since the spill_reg chunk is in outer
1183 // space. Also, if neighbor is in a different chunk, this exclusion
1184 // will be a no-op. (Later on, if lrg runs out of possible colors in
1185 // its chunk, a new chunk of color may be tried, in which case
1186 // examination of neighbors is started again, at retry_next_chunk.)
1187 LRG &nlrg = lrgs(neighbor);
1188 OptoReg::Name nreg = nlrg.reg();
1189 // Only subtract masks in the same chunk
1190 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1191 #ifndef PRODUCT
1192 uint size = lrg->mask().Size();
1193 RegMask rm = lrg->mask();
1194 #endif
1195 lrg->SUBTRACT(nlrg.mask());
1196 #ifndef PRODUCT
1197 if (trace_spilling() && lrg->mask().Size() != size) {
1198 ttyLocker ttyl;
1199 tty->print("L%d ", lidx);
1200 rm.dump();
1201 tty->print(" intersected L%d ", neighbor);
1202 nlrg.mask().dump();
1203 tty->print(" removed ");
1204 rm.SUBTRACT(lrg->mask());
1205 rm.dump();
1206 tty->print(" leaving ");
1207 lrg->mask().dump();
1208 tty->cr();
1209 }
1210 #endif
1211 }
1212 }
1213 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1214 // Aligned pairs need aligned masks
1215 if( lrg->num_regs() == 2 && !lrg->_fat_proj )
1216 lrg->ClearToPairs();
1217
1218 // Check if a color is available and if so pick the color
1219 OptoReg::Name reg = choose_color( *lrg, chunk );
1220 #ifdef SPARC
1221 debug_only(lrg->compute_set_mask_size());
1222 assert(lrg->num_regs() != 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1223 #endif
1224
1225 //---------------
1226 // If we fail to color and the AllStack flag is set, trigger
1227 // a chunk-rollover event
1228 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1229 // Bump register mask up to next stack chunk
1230 chunk += RegMask::CHUNK_SIZE;
1231 lrg->Set_All();
1232
1233 goto retry_next_chunk;
1234 }
1235
1236 //---------------
1237 // Did we get a color?
1238 else if( OptoReg::is_valid(reg)) {
1239 #ifndef PRODUCT
1240 RegMask avail_rm = lrg->mask();
1241 #endif
1242
1243 // Record selected register
1244 lrg->set_reg(reg);
1245
1246 if( reg >= _max_reg ) // Compute max register limit
1247 _max_reg = OptoReg::add(reg,1);
1248 // Fold reg back into normal space
1249 reg = OptoReg::add(reg,-chunk);
1250
1251 // If the live range is not bound, then we actually had some choices
1252 // to make. In this case, the mask has more bits in it than the colors
1253 // choosen. Restrict the mask to just what was picked.
1254 if( lrg->num_regs() == 1 ) { // Size 1 live range
1255 lrg->Clear(); // Clear the mask
1256 lrg->Insert(reg); // Set regmask to match selected reg
1257 lrg->set_mask_size(1);
1258 } else if( !lrg->_fat_proj ) {
1259 // For pairs, also insert the low bit of the pair
1260 assert( lrg->num_regs() == 2, "unbound fatproj???" );
1261 lrg->Clear(); // Clear the mask
1262 lrg->Insert(reg); // Set regmask to match selected reg
1263 lrg->Insert(OptoReg::add(reg,-1));
1264 lrg->set_mask_size(2);
1265 } else { // Else fatproj
1266 // mask must be equal to fatproj bits, by definition
1267 }
1268 #ifndef PRODUCT
1269 if (trace_spilling()) {
1270 ttyLocker ttyl;
1271 tty->print("L%d selected ", lidx);
1272 lrg->mask().dump();
1273 tty->print(" from ");
1274 avail_rm.dump();
1275 tty->cr();
1276 }
1277 #endif
1278 // Note that reg is the highest-numbered register in the newly-bound mask.
1279 } // end color available case
1280
1281 //---------------
1282 // Live range is live and no colors available
1283 else {
1284 assert( lrg->alive(), "" );
1285 assert( !lrg->_fat_proj || lrg->is_multidef() ||
1286 lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1287 assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1288
1289 // Assign the special spillreg register
1290 lrg->set_reg(OptoReg::Name(spill_reg++));
1291 // Do not empty the regmask; leave mask_size lying around
1292 // for use during Spilling
1293 #ifndef PRODUCT
1294 if( trace_spilling() ) {
1295 ttyLocker ttyl;
1296 tty->print("L%d spilling with neighbors: ", lidx);
1297 s->dump();
1298 debug_only(tty->print(" original mask: "));
1299 debug_only(orig_mask.dump());
1300 dump_lrg(lidx);
1301 }
1302 #endif
1303 } // end spill case
1304
1305 }
1306
1307 return spill_reg-LRG::SPILL_REG; // Return number of spills
1308 }
1309
1310
1311 //------------------------------copy_was_spilled-------------------------------
1312 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1313 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1314 if( _spilled_once.test(src->_idx) ) {
1315 _spilled_once.set(dst->_idx);
1316 lrgs(Find(dst))._was_spilled1 = 1;
1317 if( _spilled_twice.test(src->_idx) ) {
1318 _spilled_twice.set(dst->_idx);
1319 lrgs(Find(dst))._was_spilled2 = 1;
1320 }
1321 }
1322 }
1323
1324 //------------------------------set_was_spilled--------------------------------
1325 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1326 void PhaseChaitin::set_was_spilled( Node *n ) {
1327 if( _spilled_once.test_set(n->_idx) )
1328 _spilled_twice.set(n->_idx);
1329 }
1330
1331 //------------------------------fixup_spills-----------------------------------
1332 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1333 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1334 void PhaseChaitin::fixup_spills() {
1335 // This function does only cisc spill work.
1336 if( !UseCISCSpill ) return;
1337
1338 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
1339
1340 // Grab the Frame Pointer
1341 Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr);
1342
1343 // For all blocks
1344 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1345 Block *b = _cfg._blocks[i];
1346
1347 // For all instructions in block
1348 uint last_inst = b->end_idx();
1349 for( uint j = 1; j <= last_inst; j++ ) {
1350 Node *n = b->_nodes[j];
1351
1352 // Dead instruction???
1353 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1354 C->top() == n || // Or the random TOP node
1355 n->is_Proj(), // Or a fat-proj kill node
1356 "No dead instructions after post-alloc" );
1357
1358 int inp = n->cisc_operand();
1359 if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1360 // Convert operand number to edge index number
1361 MachNode *mach = n->as_Mach();
1362 inp = mach->operand_index(inp);
1363 Node *src = n->in(inp); // Value to load or store
1364 LRG &lrg_cisc = lrgs( Find_const(src) );
1365 OptoReg::Name src_reg = lrg_cisc.reg();
1366 // Doubles record the HIGH register of an adjacent pair.
1367 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1368 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1369 // This is a CISC Spill, get stack offset and construct new node
1370 #ifndef PRODUCT
1371 if( TraceCISCSpill ) {
1372 tty->print(" reg-instr: ");
1373 n->dump();
1374 }
1375 #endif
1376 int stk_offset = reg2offset(src_reg);
1377 // Bailout if we might exceed node limit when spilling this instruction
1378 C->check_node_count(0, "out of nodes fixing spills");
1379 if (C->failing()) return;
1380 // Transform node
1381 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
1382 cisc->set_req(inp,fp); // Base register is frame pointer
1383 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1384 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1385 cisc->ins_req(1,src); // Requires a memory edge
1386 }
1387 b->_nodes.map(j,cisc); // Insert into basic block
1388 n->subsume_by(cisc); // Correct graph
1389 //
1390 ++_used_cisc_instructions;
1391 #ifndef PRODUCT
1392 if( TraceCISCSpill ) {
1393 tty->print(" cisc-instr: ");
1394 cisc->dump();
1395 }
1396 #endif
1397 } else {
1398 #ifndef PRODUCT
1399 if( TraceCISCSpill ) {
1400 tty->print(" using reg-instr: ");
1401 n->dump();
1402 }
1403 #endif
1404 ++_unused_cisc_instructions; // input can be on stack
1405 }
1406 }
1407
1408 } // End of for all instructions
1409
1410 } // End of for all blocks
1411 }
1412
1413 //------------------------------find_base_for_derived--------------------------
1414 // Helper to stretch above; recursively discover the base Node for a
1415 // given derived Node. Easy for AddP-related machine nodes, but needs
1416 // to be recursive for derived Phis.
1417 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1418 // See if already computed; if so return it
1419 if( derived_base_map[derived->_idx] )
1420 return derived_base_map[derived->_idx];
1421
1422 // See if this happens to be a base.
1423 // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1424 // pointers derived from NULL! These are always along paths that
1425 // can't happen at run-time but the optimizer cannot deduce it so
1426 // we have to handle it gracefully.
1427 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1428 // If its an OOP with a non-zero offset, then it is derived.
1429 if( tj->_offset == 0 ) {
1430 derived_base_map[derived->_idx] = derived;
1431 return derived;
1432 }
1433 // Derived is NULL+offset? Base is NULL!
1434 if( derived->is_Con() ) {
1435 Node *base = new (C, 1) ConPNode( TypePtr::NULL_PTR );
1436 uint no_lidx = 0; // an unmatched constant in debug info has no LRG
1437 _names.extend(base->_idx, no_lidx);
1438 derived_base_map[derived->_idx] = base;
1439 return base;
1440 }
1441
1442 // Check for AddP-related opcodes
1443 if( !derived->is_Phi() ) {
1444 assert( derived->as_Mach()->ideal_Opcode() == Op_AddP, "" );
1445 Node *base = derived->in(AddPNode::Base);
1446 derived_base_map[derived->_idx] = base;
1447 return base;
1448 }
1449
1450 // Recursively find bases for Phis.
1451 // First check to see if we can avoid a base Phi here.
1452 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1453 uint i;
1454 for( i = 2; i < derived->req(); i++ )
1455 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1456 break;
1457 // Went to the end without finding any different bases?
1458 if( i == derived->req() ) { // No need for a base Phi here
1459 derived_base_map[derived->_idx] = base;
1460 return base;
1461 }
1462
1463 // Now we see we need a base-Phi here to merge the bases
1464 base = new (C, derived->req()) PhiNode( derived->in(0), base->bottom_type() );
1465 for( i = 1; i < derived->req(); i++ )
1466 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1467
1468 // Search the current block for an existing base-Phi
1469 Block *b = _cfg._bbs[derived->_idx];
1470 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1471 Node *phi = b->_nodes[i];
1472 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1473 b->_nodes.insert( i, base ); // Must insert created Phi here as base
1474 _cfg._bbs.map( base->_idx, b );
1475 new_lrg(base,maxlrg++);
1476 break;
1477 }
1478 // See if Phi matches.
1479 uint j;
1480 for( j = 1; j < base->req(); j++ )
1481 if( phi->in(j) != base->in(j) &&
1482 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1483 break;
1484 if( j == base->req() ) { // All inputs match?
1485 base = phi; // Then use existing 'phi' and drop 'base'
1486 break;
1487 }
1488 }
1489
1490
1491 // Cache info for later passes
1492 derived_base_map[derived->_idx] = base;
1493 return base;
1494 }
1495
1496
1497 //------------------------------stretch_base_pointer_live_ranges---------------
1498 // At each Safepoint, insert extra debug edges for each pair of derived value/
1499 // base pointer that is live across the Safepoint for oopmap building. The
1500 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1501 // required edge set.
1502 bool PhaseChaitin::stretch_base_pointer_live_ranges( ResourceArea *a ) {
1503 int must_recompute_live = false;
1504 uint maxlrg = _maxlrg;
1505 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1506 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1507
1508 // For all blocks in RPO do...
1509 for( uint i=0; i<_cfg._num_blocks; i++ ) {
1510 Block *b = _cfg._blocks[i];
1511 // Note use of deep-copy constructor. I cannot hammer the original
1512 // liveout bits, because they are needed by the following coalesce pass.
1513 IndexSet liveout(_live->live(b));
1514
1515 for( uint j = b->end_idx() + 1; j > 1; j-- ) {
1516 Node *n = b->_nodes[j-1];
1517
1518 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1519 // like to see in the same register. Compare uses the loop-phi and so
1520 // extends its live range BUT cannot be part of the cycle. If this
1521 // extended live range overlaps with the update of the loop-phi value
1522 // we need both alive at the same time -- which requires at least 1
1523 // copy. But because Intel has only 2-address registers we end up with
1524 // at least 2 copies, one before the loop-phi update instruction and
1525 // one after. Instead we split the input to the compare just after the
1526 // phi.
1527 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1528 Node *phi = n->in(1);
1529 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1530 Block *phi_block = _cfg._bbs[phi->_idx];
1531 if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) {
1532 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1533 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1534 insert_proj( phi_block, 1, spill, maxlrg++ );
1535 n->set_req(1,spill);
1536 must_recompute_live = true;
1537 }
1538 }
1539 }
1540
1541 // Get value being defined
1542 uint lidx = n2lidx(n);
1543 if( lidx && lidx < _maxlrg /* Ignore the occasional brand-new live range */) {
1544 // Remove from live-out set
1545 liveout.remove(lidx);
1546
1547 // Copies do not define a new value and so do not interfere.
1548 // Remove the copies source from the liveout set before interfering.
1549 uint idx = n->is_Copy();
1550 if( idx ) liveout.remove( n2lidx(n->in(idx)) );
1551 }
1552
1553 // Found a safepoint?
1554 JVMState *jvms = n->jvms();
1555 if( jvms ) {
1556 // Now scan for a live derived pointer
1557 IndexSetIterator elements(&liveout);
1558 uint neighbor;
1559 while ((neighbor = elements.next()) != 0) {
1560 // Find reaching DEF for base and derived values
1561 // This works because we are still in SSA during this call.
1562 Node *derived = lrgs(neighbor)._def;
1563 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1564 // If its an OOP with a non-zero offset, then it is derived.
1565 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1566 Node *base = find_base_for_derived( derived_base_map, derived, maxlrg );
1567 assert( base->_idx < _names.Size(), "" );
1568 // Add reaching DEFs of derived pointer and base pointer as a
1569 // pair of inputs
1570 n->add_req( derived );
1571 n->add_req( base );
1572
1573 // See if the base pointer is already live to this point.
1574 // Since I'm working on the SSA form, live-ness amounts to
1575 // reaching def's. So if I find the base's live range then
1576 // I know the base's def reaches here.
1577 if( (n2lidx(base) >= _maxlrg ||// (Brand new base (hence not live) or
1578 !liveout.member( n2lidx(base) ) ) && // not live) AND
1579 (n2lidx(base) > 0) && // not a constant
1580 _cfg._bbs[base->_idx] != b ) { // base not def'd in blk)
1581 // Base pointer is not currently live. Since I stretched
1582 // the base pointer to here and it crosses basic-block
1583 // boundaries, the global live info is now incorrect.
1584 // Recompute live.
1585 must_recompute_live = true;
1586 } // End of if base pointer is not live to debug info
1587 }
1588 } // End of scan all live data for derived ptrs crossing GC point
1589 } // End of if found a GC point
1590
1591 // Make all inputs live
1592 if( !n->is_Phi() ) { // Phi function uses come from prior block
1593 for( uint k = 1; k < n->req(); k++ ) {
1594 uint lidx = n2lidx(n->in(k));
1595 if( lidx < _maxlrg )
1596 liveout.insert( lidx );
1597 }
1598 }
1599
1600 } // End of forall instructions in block
1601 liveout.clear(); // Free the memory used by liveout.
1602
1603 } // End of forall blocks
1604 _maxlrg = maxlrg;
1605
1606 // If I created a new live range I need to recompute live
1607 if( maxlrg != _ifg->_maxlrg )
1608 must_recompute_live = true;
1609
1610 return must_recompute_live != 0;
1611 }
1612
1613
1614 //------------------------------add_reference----------------------------------
1615 // Extend the node to LRG mapping
1616 void PhaseChaitin::add_reference( const Node *node, const Node *old_node ) {
1617 _names.extend( node->_idx, n2lidx(old_node) );
1618 }
1619
1620 //------------------------------dump-------------------------------------------
1621 #ifndef PRODUCT
1622 void PhaseChaitin::dump( const Node *n ) const {
1623 uint r = (n->_idx < _names.Size() ) ? Find_const(n) : 0;
1624 tty->print("L%d",r);
1625 if( r && n->Opcode() != Op_Phi ) {
1626 if( _node_regs ) { // Got a post-allocation copy of allocation?
1627 tty->print("[");
1628 OptoReg::Name second = get_reg_second(n);
1629 if( OptoReg::is_valid(second) ) {
1630 if( OptoReg::is_reg(second) )
1631 tty->print("%s:",Matcher::regName[second]);
1632 else
1633 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1634 }
1635 OptoReg::Name first = get_reg_first(n);
1636 if( OptoReg::is_reg(first) )
1637 tty->print("%s]",Matcher::regName[first]);
1638 else
1639 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1640 } else
1641 n->out_RegMask().dump();
1642 }
1643 tty->print("/N%d\t",n->_idx);
1644 tty->print("%s === ", n->Name());
1645 uint k;
1646 for( k = 0; k < n->req(); k++) {
1647 Node *m = n->in(k);
1648 if( !m ) tty->print("_ ");
1649 else {
1650 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0;
1651 tty->print("L%d",r);
1652 // Data MultiNode's can have projections with no real registers.
1653 // Don't die while dumping them.
1654 int op = n->Opcode();
1655 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1656 if( _node_regs ) {
1657 tty->print("[");
1658 OptoReg::Name second = get_reg_second(n->in(k));
1659 if( OptoReg::is_valid(second) ) {
1660 if( OptoReg::is_reg(second) )
1661 tty->print("%s:",Matcher::regName[second]);
1662 else
1663 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
1664 reg2offset_unchecked(second));
1665 }
1666 OptoReg::Name first = get_reg_first(n->in(k));
1667 if( OptoReg::is_reg(first) )
1668 tty->print("%s]",Matcher::regName[first]);
1669 else
1670 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
1671 reg2offset_unchecked(first));
1672 } else
1673 n->in_RegMask(k).dump();
1674 }
1675 tty->print("/N%d ",m->_idx);
1676 }
1677 }
1678 if( k < n->len() && n->in(k) ) tty->print("| ");
1679 for( ; k < n->len(); k++ ) {
1680 Node *m = n->in(k);
1681 if( !m ) break;
1682 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0;
1683 tty->print("L%d",r);
1684 tty->print("/N%d ",m->_idx);
1685 }
1686 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1687 else n->dump_spec(tty);
1688 if( _spilled_once.test(n->_idx ) ) {
1689 tty->print(" Spill_1");
1690 if( _spilled_twice.test(n->_idx ) )
1691 tty->print(" Spill_2");
1692 }
1693 tty->print("\n");
1694 }
1695
1696 void PhaseChaitin::dump( const Block * b ) const {
1697 b->dump_head( &_cfg._bbs );
1698
1699 // For all instructions
1700 for( uint j = 0; j < b->_nodes.size(); j++ )
1701 dump(b->_nodes[j]);
1702 // Print live-out info at end of block
1703 if( _live ) {
1704 tty->print("Liveout: ");
1705 IndexSet *live = _live->live(b);
1706 IndexSetIterator elements(live);
1707 tty->print("{");
1708 uint i;
1709 while ((i = elements.next()) != 0) {
1710 tty->print("L%d ", Find_const(i));
1711 }
1712 tty->print_cr("}");
1713 }
1714 tty->print("\n");
1715 }
1716
1717 void PhaseChaitin::dump() const {
1718 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n",
1719 _matcher._new_SP, _framesize );
1720
1721 // For all blocks
1722 for( uint i = 0; i < _cfg._num_blocks; i++ )
1723 dump(_cfg._blocks[i]);
1724 // End of per-block dump
1725 tty->print("\n");
1726
1727 if (!_ifg) {
1728 tty->print("(No IFG.)\n");
1729 return;
1730 }
1731
1732 // Dump LRG array
1733 tty->print("--- Live RanGe Array ---\n");
1734 for(uint i2 = 1; i2 < _maxlrg; i2++ ) {
1735 tty->print("L%d: ",i2);
1736 if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( );
1737 else tty->print("new LRG");
1738 }
1739 tty->print_cr("");
1740
1741 // Dump lo-degree list
1742 tty->print("Lo degree: ");
1743 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
1744 tty->print("L%d ",i3);
1745 tty->print_cr("");
1746
1747 // Dump lo-stk-degree list
1748 tty->print("Lo stk degree: ");
1749 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
1750 tty->print("L%d ",i4);
1751 tty->print_cr("");
1752
1753 // Dump lo-degree list
1754 tty->print("Hi degree: ");
1755 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
1756 tty->print("L%d ",i5);
1757 tty->print_cr("");
1758 }
1759
1760 //------------------------------dump_degree_lists------------------------------
1761 void PhaseChaitin::dump_degree_lists() const {
1762 // Dump lo-degree list
1763 tty->print("Lo degree: ");
1764 for( uint i = _lo_degree; i; i = lrgs(i)._next )
1765 tty->print("L%d ",i);
1766 tty->print_cr("");
1767
1768 // Dump lo-stk-degree list
1769 tty->print("Lo stk degree: ");
1770 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
1771 tty->print("L%d ",i2);
1772 tty->print_cr("");
1773
1774 // Dump lo-degree list
1775 tty->print("Hi degree: ");
1776 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
1777 tty->print("L%d ",i3);
1778 tty->print_cr("");
1779 }
1780
1781 //------------------------------dump_simplified--------------------------------
1782 void PhaseChaitin::dump_simplified() const {
1783 tty->print("Simplified: ");
1784 for( uint i = _simplified; i; i = lrgs(i)._next )
1785 tty->print("L%d ",i);
1786 tty->print_cr("");
1787 }
1788
1789 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
1790 if ((int)reg < 0)
1791 sprintf(buf, "<OptoReg::%d>", (int)reg);
1792 else if (OptoReg::is_reg(reg))
1793 strcpy(buf, Matcher::regName[reg]);
1794 else
1795 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
1796 pc->reg2offset(reg));
1797 return buf+strlen(buf);
1798 }
1799
1800 //------------------------------dump_register----------------------------------
1801 // Dump a register name into a buffer. Be intelligent if we get called
1802 // before allocation is complete.
1803 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
1804 if( !this ) { // Not got anything?
1805 sprintf(buf,"N%d",n->_idx); // Then use Node index
1806 } else if( _node_regs ) {
1807 // Post allocation, use direct mappings, no LRG info available
1808 print_reg( get_reg_first(n), this, buf );
1809 } else {
1810 uint lidx = Find_const(n); // Grab LRG number
1811 if( !_ifg ) {
1812 sprintf(buf,"L%d",lidx); // No register binding yet
1813 } else if( !lidx ) { // Special, not allocated value
1814 strcpy(buf,"Special");
1815 } else if( (lrgs(lidx).num_regs() == 1)
1816 ? !lrgs(lidx).mask().is_bound1()
1817 : !lrgs(lidx).mask().is_bound2() ) {
1818 sprintf(buf,"L%d",lidx); // No register binding yet
1819 } else { // Hah! We have a bound machine register
1820 print_reg( lrgs(lidx).reg(), this, buf );
1821 }
1822 }
1823 return buf+strlen(buf);
1824 }
1825
1826 //----------------------dump_for_spill_split_recycle--------------------------
1827 void PhaseChaitin::dump_for_spill_split_recycle() const {
1828 if( WizardMode && (PrintCompilation || PrintOpto) ) {
1829 // Display which live ranges need to be split and the allocator's state
1830 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
1831 for( uint bidx = 1; bidx < _maxlrg; bidx++ ) {
1832 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
1833 tty->print("L%d: ", bidx);
1834 lrgs(bidx).dump();
1835 }
1836 }
1837 tty->cr();
1838 dump();
1839 }
1840 }
1841
1842 //------------------------------dump_frame------------------------------------
1843 void PhaseChaitin::dump_frame() const {
1844 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
1845 const TypeTuple *domain = C->tf()->domain();
1846 const int argcnt = domain->cnt() - TypeFunc::Parms;
1847
1848 // Incoming arguments in registers dump
1849 for( int k = 0; k < argcnt; k++ ) {
1850 OptoReg::Name parmreg = _matcher._parm_regs[k].first();
1851 if( OptoReg::is_reg(parmreg)) {
1852 const char *reg_name = OptoReg::regname(parmreg);
1853 tty->print("#r%3.3d %s", parmreg, reg_name);
1854 parmreg = _matcher._parm_regs[k].second();
1855 if( OptoReg::is_reg(parmreg)) {
1856 tty->print(":%s", OptoReg::regname(parmreg));
1857 }
1858 tty->print(" : parm %d: ", k);
1859 domain->field_at(k + TypeFunc::Parms)->dump();
1860 tty->print_cr("");
1861 }
1862 }
1863
1864 // Check for un-owned padding above incoming args
1865 OptoReg::Name reg = _matcher._new_SP;
1866 if( reg > _matcher._in_arg_limit ) {
1867 reg = OptoReg::add(reg, -1);
1868 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
1869 }
1870
1871 // Incoming argument area dump
1872 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
1873 while( reg > begin_in_arg ) {
1874 reg = OptoReg::add(reg, -1);
1875 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
1876 int j;
1877 for( j = 0; j < argcnt; j++) {
1878 if( _matcher._parm_regs[j].first() == reg ||
1879 _matcher._parm_regs[j].second() == reg ) {
1880 tty->print("parm %d: ",j);
1881 domain->field_at(j + TypeFunc::Parms)->dump();
1882 tty->print_cr("");
1883 break;
1884 }
1885 }
1886 if( j >= argcnt )
1887 tty->print_cr("HOLE, owned by SELF");
1888 }
1889
1890 // Old outgoing preserve area
1891 while( reg > _matcher._old_SP ) {
1892 reg = OptoReg::add(reg, -1);
1893 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
1894 }
1895
1896 // Old SP
1897 tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
1898 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
1899
1900 // Preserve area dump
1901 reg = OptoReg::add(reg, -1);
1902 while( OptoReg::is_stack(reg)) {
1903 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
1904 if( _matcher.return_addr() == reg )
1905 tty->print_cr("return address");
1906 else if( _matcher.return_addr() == OptoReg::add(reg,1) &&
1907 VerifyStackAtCalls )
1908 tty->print_cr("0xBADB100D +VerifyStackAtCalls");
1909 else if ((int)OptoReg::reg2stack(reg) < C->fixed_slots())
1910 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
1911 else
1912 tty->print_cr("pad2, in_preserve");
1913 reg = OptoReg::add(reg, -1);
1914 }
1915
1916 // Spill area dump
1917 reg = OptoReg::add(_matcher._new_SP, _framesize );
1918 while( reg > _matcher._out_arg_limit ) {
1919 reg = OptoReg::add(reg, -1);
1920 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
1921 }
1922
1923 // Outgoing argument area dump
1924 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
1925 reg = OptoReg::add(reg, -1);
1926 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
1927 }
1928
1929 // Outgoing new preserve area
1930 while( reg > _matcher._new_SP ) {
1931 reg = OptoReg::add(reg, -1);
1932 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
1933 }
1934 tty->print_cr("#");
1935 }
1936
1937 //------------------------------dump_bb----------------------------------------
1938 void PhaseChaitin::dump_bb( uint pre_order ) const {
1939 tty->print_cr("---dump of B%d---",pre_order);
1940 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1941 Block *b = _cfg._blocks[i];
1942 if( b->_pre_order == pre_order )
1943 dump(b);
1944 }
1945 }
1946
1947 //------------------------------dump_lrg---------------------------------------
1948 void PhaseChaitin::dump_lrg( uint lidx ) const {
1949 tty->print_cr("---dump of L%d---",lidx);
1950
1951 if( _ifg ) {
1952 if( lidx >= _maxlrg ) {
1953 tty->print("Attempt to print live range index beyond max live range.\n");
1954 return;
1955 }
1956 tty->print("L%d: ",lidx);
1957 lrgs(lidx).dump( );
1958 }
1959 if( _ifg ) { tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
1960 _ifg->neighbors(lidx)->dump();
1961 tty->cr();
1962 }
1963 // For all blocks
1964 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1965 Block *b = _cfg._blocks[i];
1966 int dump_once = 0;
1967
1968 // For all instructions
1969 for( uint j = 0; j < b->_nodes.size(); j++ ) {
1970 Node *n = b->_nodes[j];
1971 if( Find_const(n) == lidx ) {
1972 if( !dump_once++ ) {
1973 tty->cr();
1974 b->dump_head( &_cfg._bbs );
1975 }
1976 dump(n);
1977 continue;
1978 }
1979 uint cnt = n->req();
1980 for( uint k = 1; k < cnt; k++ ) {
1981 Node *m = n->in(k);
1982 if (!m) continue; // be robust in the dumper
1983 if( Find_const(m) == lidx ) {
1984 if( !dump_once++ ) {
1985 tty->cr();
1986 b->dump_head( &_cfg._bbs );
1987 }
1988 dump(n);
1989 }
1990 }
1991 }
1992 } // End of per-block dump
1993 tty->cr();
1994 }
1995 #endif // not PRODUCT
1996
1997 //------------------------------print_chaitin_statistics-------------------------------
1998 int PhaseChaitin::_final_loads = 0;
1999 int PhaseChaitin::_final_stores = 0;
2000 int PhaseChaitin::_final_memoves= 0;
2001 int PhaseChaitin::_final_copies = 0;
2002 double PhaseChaitin::_final_load_cost = 0;
2003 double PhaseChaitin::_final_store_cost = 0;
2004 double PhaseChaitin::_final_memove_cost= 0;
2005 double PhaseChaitin::_final_copy_cost = 0;
2006 int PhaseChaitin::_conserv_coalesce = 0;
2007 int PhaseChaitin::_conserv_coalesce_pair = 0;
2008 int PhaseChaitin::_conserv_coalesce_trie = 0;
2009 int PhaseChaitin::_conserv_coalesce_quad = 0;
2010 int PhaseChaitin::_post_alloc = 0;
2011 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2012 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2013 int PhaseChaitin::_used_cisc_instructions = 0;
2014 int PhaseChaitin::_unused_cisc_instructions = 0;
2015 int PhaseChaitin::_allocator_attempts = 0;
2016 int PhaseChaitin::_allocator_successes = 0;
2017
2018 #ifndef PRODUCT
2019 uint PhaseChaitin::_high_pressure = 0;
2020 uint PhaseChaitin::_low_pressure = 0;
2021
2022 void PhaseChaitin::print_chaitin_statistics() {
2023 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2024 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2025 tty->print_cr("Adjusted spill cost = %7.0f.",
2026 _final_load_cost*4.0 + _final_store_cost * 2.0 +
2027 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2028 tty->print("Conservatively coalesced %d copies, %d pairs",
2029 _conserv_coalesce, _conserv_coalesce_pair);
2030 if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2031 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2032 tty->print_cr(", %d post alloc.", _post_alloc);
2033 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2034 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2035 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2036 if( _used_cisc_instructions || _unused_cisc_instructions )
2037 tty->print_cr("Used cisc instruction %d, remained in register %d",
2038 _used_cisc_instructions, _unused_cisc_instructions);
2039 if( _allocator_successes != 0 )
2040 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2041 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2042 }
2043 #endif // not PRODUCT