1 /*
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class Compile;
26 class Node;
27 class MachNode;
28 class MachTypeNode;
29 class MachOper;
30
31 //---------------------------Matcher-------------------------------------------
32 class Matcher : public PhaseTransform {
33 friend class VMStructs;
34 // Private arena of State objects
35 ResourceArea _states_arena;
36
37 VectorSet _visited; // Visit bits
38
39 // Used to control the Label pass
40 VectorSet _shared; // Shared Ideal Node
41 VectorSet _dontcare; // Nothing the matcher cares about
42
43 // Private methods which perform the actual matching and reduction
44 // Walks the label tree, generating machine nodes
45 MachNode *ReduceInst( State *s, int rule, Node *&mem);
46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
49
50 // If this node already matched using "rule", return the MachNode for it.
51 MachNode* find_shared_node(Node* n, uint rule);
52
53 // Convert a dense opcode number to an expanded rule number
54 const int *_reduceOp;
55 const int *_leftOp;
56 const int *_rightOp;
57
58 // Map dense opcode number to info on when rule is swallowed constant.
59 const bool *_swallowed;
60
61 // Map dense rule number to determine if this is an instruction chain rule
62 const uint _begin_inst_chain_rule;
63 const uint _end_inst_chain_rule;
64
65 // We want to clone constants and possible CmpI-variants.
66 // If we do not clone CmpI, then we can have many instances of
67 // condition codes alive at once. This is OK on some chips and
68 // bad on others. Hence the machine-dependent table lookup.
69 const char *_must_clone;
70
71 // Find shared Nodes, or Nodes that otherwise are Matcher roots
72 void find_shared( Node *n );
73
74 // Debug and profile information for nodes in old space:
75 GrowableArray<Node_Notes*>* _old_node_note_array;
76
77 // Node labeling iterator for instruction selection
78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
79
80 Node *transform( Node *dummy );
81
82 Node_List &_proj_list; // For Machine nodes killing many values
83
84 Node_Array _shared_nodes;
85
86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
87 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal
88
89 // Accessors for the inherited field PhaseTransform::_nodes:
90 void grow_new_node_array(uint idx_limit) {
91 _nodes.map(idx_limit-1, NULL);
92 }
93 bool has_new_node(const Node* n) const {
94 return _nodes.at(n->_idx) != NULL;
95 }
96 Node* new_node(const Node* n) const {
97 assert(has_new_node(n), "set before get");
98 return _nodes.at(n->_idx);
99 }
100 void set_new_node(const Node* n, Node *nn) {
101 assert(!has_new_node(n), "set only once");
102 _nodes.map(n->_idx, nn);
103 }
104
105 #ifdef ASSERT
106 // Make sure only new nodes are reachable from this node
107 void verify_new_nodes_only(Node* root);
108 #endif
109
110 public:
111 int LabelRootDepth;
112 static const int base2reg[]; // Map Types to machine register types
113 // Convert ideal machine register to a register mask for spill-loads
114 static const RegMask *idealreg2regmask[];
115 RegMask *idealreg2spillmask[_last_machine_leaf];
116 RegMask *idealreg2debugmask[_last_machine_leaf];
117 void init_spill_mask( Node *ret );
118 // Convert machine register number to register mask
119 static uint mreg2regmask_max;
120 static RegMask mreg2regmask[];
121 static RegMask STACK_ONLY_mask;
122
123 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
124 void set_shared( Node *n ) { _shared.set(n->_idx); }
125 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
126 void set_visited( Node *n ) { _visited.set(n->_idx); }
127 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
128 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
129
130 // Mode bit to tell DFA and expand rules whether we are running after
131 // (or during) register selection. Usually, the matcher runs before,
132 // but it will also get called to generate post-allocation spill code.
133 // In this situation, it is a deadly error to attempt to allocate more
134 // temporary registers.
135 bool _allocation_started;
136
137 // Machine register names
138 static const char *regName[];
139 // Machine register encodings
140 static const unsigned char _regEncode[];
141 // Machine Node names
142 const char **_ruleName;
143 // Rules that are cheaper to rematerialize than to spill
144 static const uint _begin_rematerialize;
145 static const uint _end_rematerialize;
146
147 // An array of chars, from 0 to _last_Mach_Reg.
148 // No Save = 'N' (for register windows)
149 // Save on Entry = 'E'
150 // Save on Call = 'C'
151 // Always Save = 'A' (same as SOE + SOC)
152 const char *_register_save_policy;
153 const char *_c_reg_save_policy;
154 // Convert a machine register to a machine register type, so-as to
155 // properly match spill code.
156 const int *_register_save_type;
157 // Maps from machine register to boolean; true if machine register can
158 // be holding a call argument in some signature.
159 static bool can_be_java_arg( int reg );
160 // Maps from machine register to boolean; true if machine register holds
161 // a spillable argument.
162 static bool is_spillable_arg( int reg );
163
164 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
165 // List is valid in the post-matching space.
166 Node_List _null_check_tests;
167 void collect_null_checks( Node *proj );
168 void validate_null_checks( );
169
170 Matcher( Node_List &proj_list );
171
172 // Select instructions for entire method
173 void match( );
174 // Helper for match
175 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
176
177 // Transform, then walk. Does implicit DCE while walking.
178 // Name changed from "transform" to avoid it being virtual.
179 Node *xform( Node *old_space_node, int Nodes );
180
181 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
182 MachNode *match_tree( const Node *n );
183 MachNode *match_sfpt( SafePointNode *sfpt );
184 // Helper for match_sfpt
185 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
186
187 // Initialize first stack mask and related masks.
188 void init_first_stack_mask();
189
190 // If we should save-on-entry this register
191 bool is_save_on_entry( int reg );
192
193 // Fixup the save-on-entry registers
194 void Fixup_Save_On_Entry( );
195
196 // --- Frame handling ---
197
198 // Register number of the stack slot corresponding to the incoming SP.
199 // Per the Big Picture in the AD file, it is:
200 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
201 OptoReg::Name _old_SP;
202
203 // Register number of the stack slot corresponding to the highest incoming
204 // argument on the stack. Per the Big Picture in the AD file, it is:
205 // _old_SP + out_preserve_stack_slots + incoming argument size.
206 OptoReg::Name _in_arg_limit;
207
208 // Register number of the stack slot corresponding to the new SP.
209 // Per the Big Picture in the AD file, it is:
210 // _in_arg_limit + pad0
211 OptoReg::Name _new_SP;
212
213 // Register number of the stack slot corresponding to the highest outgoing
214 // argument on the stack. Per the Big Picture in the AD file, it is:
215 // _new_SP + max outgoing arguments of all calls
216 OptoReg::Name _out_arg_limit;
217
218 OptoRegPair *_parm_regs; // Array of machine registers per argument
219 RegMask *_calling_convention_mask; // Array of RegMasks per argument
220
221 // Does matcher support this ideal node?
222 static const bool has_match_rule(int opcode);
223 static const bool _hasMatchRule[_last_opcode];
224
225 // Used to determine if we have fast l2f conversion
226 // USII has it, USIII doesn't
227 static const bool convL2FSupported(void);
228
229 // Vector width in bytes
230 static const uint vector_width_in_bytes(void);
231
232 // Vector ideal reg
233 static const uint vector_ideal_reg(void);
234
235 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
236 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
237 // Depends on the details of 64-bit constant generation on the CPU.
238 static const bool isSimpleConstant64(jlong con);
239
240 // These calls are all generated by the ADLC
241
242 // TRUE - grows up, FALSE - grows down (Intel)
243 virtual bool stack_direction() const;
244
245 // Java-Java calling convention
246 // (what you use when Java calls Java)
247
248 // Alignment of stack in bytes, standard Intel word alignment is 4.
249 // Sparc probably wants at least double-word (8).
250 static uint stack_alignment_in_bytes();
251 // Alignment of stack, measured in stack slots.
252 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
253 static uint stack_alignment_in_slots() {
254 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
255 }
256
257 // Array mapping arguments to registers. Argument 0 is usually the 'this'
258 // pointer. Registers can include stack-slots and regular registers.
259 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
260
261 // Convert a sig into a calling convention register layout
262 // and find interesting things about it.
263 static OptoReg::Name find_receiver( bool is_outgoing );
264 // Return address register. On Intel it is a stack-slot. On PowerPC
265 // it is the Link register. On Sparc it is r31?
266 virtual OptoReg::Name return_addr() const;
267 RegMask _return_addr_mask;
268 // Return value register. On Intel it is EAX. On Sparc i0/o0.
269 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
270 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
271 RegMask _return_value_mask;
272 // Inline Cache Register
273 static OptoReg::Name inline_cache_reg();
274 static const RegMask &inline_cache_reg_mask();
275 static int inline_cache_reg_encode();
276
277 // Register for DIVI projection of divmodI
278 static RegMask divI_proj_mask();
279 // Register for MODI projection of divmodI
280 static RegMask modI_proj_mask();
281
282 // Register for DIVL projection of divmodL
283 static RegMask divL_proj_mask();
284 // Register for MODL projection of divmodL
285 static RegMask modL_proj_mask();
286
287 // Java-Interpreter calling convention
288 // (what you use when calling between compiled-Java and Interpreted-Java
289
290 // Number of callee-save + always-save registers
291 // Ignores frame pointer and "special" registers
292 static int number_of_saved_registers();
293
294 // The Method-klass-holder may be passed in the inline_cache_reg
295 // and then expanded into the inline_cache_reg and a method_oop register
296
297 static OptoReg::Name interpreter_method_oop_reg();
298 static const RegMask &interpreter_method_oop_reg_mask();
299 static int interpreter_method_oop_reg_encode();
300
301 static OptoReg::Name compiler_method_oop_reg();
302 static const RegMask &compiler_method_oop_reg_mask();
303 static int compiler_method_oop_reg_encode();
304
305 // Interpreter's Frame Pointer Register
306 static OptoReg::Name interpreter_frame_pointer_reg();
307 static const RegMask &interpreter_frame_pointer_reg_mask();
308
309 // Java-Native calling convention
310 // (what you use when intercalling between Java and C++ code)
311
312 // Array mapping arguments to registers. Argument 0 is usually the 'this'
313 // pointer. Registers can include stack-slots and regular registers.
314 static void c_calling_convention( BasicType*, VMRegPair *, uint );
315 // Frame pointer. The frame pointer is kept at the base of the stack
316 // and so is probably the stack pointer for most machines. On Intel
317 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
318 OptoReg::Name c_frame_pointer() const;
319 static RegMask c_frame_ptr_mask;
320
321 // !!!!! Special stuff for building ScopeDescs
322 virtual int regnum_to_fpu_offset(int regnum);
323
324 // Is this branch offset small enough to be addressed by a short branch?
325 bool is_short_branch_offset(int offset);
326
327 // Optional scaling for the parameter to the ClearArray/CopyArray node.
328 static const bool init_array_count_is_in_bytes;
329
330 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
331 // Anything this size or smaller may get converted to discrete scalar stores.
332 static const int init_array_short_size;
333
334 // Should the Matcher clone shifts on addressing modes, expecting them to
335 // be subsumed into complex addressing expressions or compute them into
336 // registers? True for Intel but false for most RISCs
337 static const bool clone_shift_expressions;
338
339 // Is it better to copy float constants, or load them directly from memory?
340 // Intel can load a float constant from a direct address, requiring no
341 // extra registers. Most RISCs will have to materialize an address into a
342 // register first, so they may as well materialize the constant immediately.
343 static const bool rematerialize_float_constants;
344
345 // If CPU can load and store mis-aligned doubles directly then no fixup is
346 // needed. Else we split the double into 2 integer pieces and move it
347 // piece-by-piece. Only happens when passing doubles into C code or when
348 // calling i2c adapters as the Java calling convention forces doubles to be
349 // aligned.
350 static const bool misaligned_doubles_ok;
351
352 // Perform a platform dependent implicit null fixup. This is needed
353 // on windows95 to take care of some unusual register constraints.
354 void pd_implicit_null_fixup(MachNode *load, uint idx);
355
356 // Advertise here if the CPU requires explicit rounding operations
357 // to implement the UseStrictFP mode.
358 static const bool strict_fp_requires_explicit_rounding;
359
360 // Do floats take an entire double register or just half?
361 static const bool float_in_double;
362 // Do ints take an entire long register or just half?
363 static const bool int_in_long;
364
365 // This routine is run whenever a graph fails to match.
366 // If it returns, the compiler should bailout to interpreter without error.
367 // In non-product mode, SoftMatchFailure is false to detect non-canonical
368 // graphs. Print a message and exit.
369 static void soft_match_failure() {
370 if( SoftMatchFailure ) return;
371 else { fatal("SoftMatchFailure is not allowed except in product"); }
372 }
373
374 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
375 // acting as an Acquire and thus we don't need an Acquire here. We
376 // retain the Node to act as a compiler ordering barrier.
377 static bool prior_fast_lock( const Node *acq );
378
379 // Used by the DFA in dfa_sparc.cpp. Check for a following
380 // FastUnLock acting as a Release and thus we don't need a Release
381 // here. We retain the Node to act as a compiler ordering barrier.
382 static bool post_fast_unlock( const Node *rel );
383
384 // Check for a following volatile memory barrier without an
385 // intervening load and thus we don't need a barrier here. We
386 // retain the Node to act as a compiler ordering barrier.
387 static bool post_store_load_barrier(const Node* mb);
388
389
390 #ifdef ASSERT
391 void dump_old2new_map(); // machine-independent to machine-dependent
392
393 Node* find_old_node(Node* new_node) {
394 return _new2old_map[new_node->_idx];
395 }
396 #endif
397 };