1 /*
2 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_reg_split.cpp.incl"
27
28 //------------------------------Split--------------------------------------
29 // Walk the graph in RPO and for each lrg which spills, propogate reaching
30 // definitions. During propogation, split the live range around regions of
31 // High Register Pressure (HRP). If a Def is in a region of Low Register
32 // Pressure (LRP), it will not get spilled until we encounter a region of
33 // HRP between it and one of its uses. We will spill at the transition
34 // point between LRP and HRP. Uses in the HRP region will use the spilled
35 // Def. The first Use outside the HRP region will generate a SpillCopy to
36 // hoist the live range back up into a register, and all subsequent uses
37 // will use that new Def until another HRP region is encountered. Defs in
38 // HRP regions will get trailing SpillCopies to push the LRG down into the
39 // stack immediately.
40 //
41 // As a side effect, unlink from (hence make dead) coalesced copies.
42 //
43
44 static const char out_of_nodes[] = "out of nodes during split";
45
46 //------------------------------get_spillcopy_wide-----------------------------
47 // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the
48 // wide ideal-register spill-mask if possible. If the 'wide-mask' does
49 // not cover the input (or output), use the input (or output) mask instead.
50 Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) {
51 // If ideal reg doesn't exist we've got a bad schedule happening
52 // that is forcing us to spill something that isn't spillable.
53 // Bail rather than abort
54 int ireg = def->ideal_reg();
55 if( ireg == 0 || ireg == Op_RegFlags ) {
56 assert(false, "attempted to spill a non-spillable item");
57 C->record_method_not_compilable("attempted to spill a non-spillable item");
58 return NULL;
59 }
60 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
61 return NULL;
62 }
63 const RegMask *i_mask = &def->out_RegMask();
64 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
65 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
66 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
67 const RegMask *w_o_mask;
68
69 if( w_mask->overlap( *o_mask ) && // Overlap AND
70 ((ireg != Op_RegL && ireg != Op_RegD // Single use or aligned
71 #ifdef _LP64
72 && ireg != Op_RegP
73 #endif
74 ) || o_mask->is_aligned_Pairs()) ) {
75 // Don't come here for mis-aligned doubles
76 w_o_mask = w_mask;
77 } else { // wide ideal mask does not overlap with o_mask
78 // Mis-aligned doubles come here and XMM->FPR moves on x86.
79 w_o_mask = o_mask; // Must target desired registers
80 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use
81 // a reg-reg move or do I need a trip across register classes
82 // (and thus through memory)?
83 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
84 // Here we assume a trip through memory is required.
85 w_i_mask = &C->FIRST_STACK_mask();
86 }
87 return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask );
88 }
89
90 //------------------------------insert_proj------------------------------------
91 // Insert the spill at chosen location. Skip over any interveneing Proj's or
92 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block
93 // instead. Update high-pressure indices. Create a new live range.
94 void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) {
95 // Skip intervening ProjNodes. Do not insert between a ProjNode and
96 // its definer.
97 while( i < b->_nodes.size() &&
98 (b->_nodes[i]->is_Proj() ||
99 b->_nodes[i]->is_Phi() ||
100 (b->_nodes[i]->is_Mach() &&
101 b->_nodes[i]->as_Mach()->ideal_Opcode() == Op_CreateEx)) )
102 i++;
103
104 // Do not insert between a call and his Catch
105 if( b->_nodes[i]->is_Catch() ) {
106 // Put the instruction at the top of the fall-thru block.
107 // Find the fall-thru projection
108 while( 1 ) {
109 const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj();
110 if( cp->_con == CatchProjNode::fall_through_index )
111 break;
112 }
113 int sidx = i - b->end_idx()-1;
114 b = b->_succs[sidx]; // Switch to successor block
115 i = 1; // Right at start of block
116 }
117
118 b->_nodes.insert(i,spill); // Insert node in block
119 _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect
120 // Adjust the point where we go hi-pressure
121 if( i <= b->_ihrp_index ) b->_ihrp_index++;
122 if( i <= b->_fhrp_index ) b->_fhrp_index++;
123
124 // Assign a new Live Range Number to the SpillCopy and grow
125 // the node->live range mapping.
126 new_lrg(spill,maxlrg);
127 }
128
129 //------------------------------split_DEF--------------------------------------
130 // There are four catagories of Split; UP/DOWN x DEF/USE
131 // Only three of these really occur as DOWN/USE will always color
132 // Any Split with a DEF cannot CISC-Spill now. Thus we need
133 // two helper routines, one for Split DEFS (insert after instruction),
134 // one for Split USES (insert before instruction). DEF insertion
135 // happens inside Split, where the Leaveblock array is updated.
136 uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) {
137 #ifdef ASSERT
138 // Increment the counter for this lrg
139 splits.at_put(slidx, splits.at(slidx)+1);
140 #endif
141 // If we are spilling the memory op for an implicit null check, at the
142 // null check location (ie - null check is in HRP block) we need to do
143 // the null-check first, then spill-down in the following block.
144 // (The implicit_null_check function ensures the use is also dominated
145 // by the branch-not-taken block.)
146 Node *be = b->end();
147 if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) {
148 // Spill goes in the branch-not-taken block
149 b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue];
150 loc = 0; // Just past the Region
151 }
152 assert( loc >= 0, "must insert past block head" );
153
154 // Get a def-side SpillCopy
155 Node *spill = get_spillcopy_wide(def,NULL,0);
156 // Did we fail to split?, then bail
157 if (!spill) {
158 return 0;
159 }
160
161 // Insert the spill at chosen location
162 insert_proj( b, loc+1, spill, maxlrg++);
163
164 // Insert new node into Reaches array
165 Reachblock[slidx] = spill;
166 // Update debug list of reaching down definitions by adding this one
167 debug_defs[slidx] = spill;
168
169 // return updated count of live ranges
170 return maxlrg;
171 }
172
173 //------------------------------split_USE--------------------------------------
174 // Splits at uses can involve redeffing the LRG, so no CISC Spilling there.
175 // Debug uses want to know if def is already stack enabled.
176 uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) {
177 #ifdef ASSERT
178 // Increment the counter for this lrg
179 splits.at_put(slidx, splits.at(slidx)+1);
180 #endif
181
182 // Some setup stuff for handling debug node uses
183 JVMState* jvms = use->jvms();
184 uint debug_start = jvms ? jvms->debug_start() : 999999;
185 uint debug_end = jvms ? jvms->debug_end() : 999999;
186
187 //-------------------------------------------
188 // Check for use of debug info
189 if (useidx >= debug_start && useidx < debug_end) {
190 // Actually it's perfectly legal for constant debug info to appear
191 // just unlikely. In this case the optimizer left a ConI of a 4
192 // as both inputs to a Phi with only a debug use. It's a single-def
193 // live range of a rematerializable value. The live range spills,
194 // rematerializes and now the ConI directly feeds into the debug info.
195 // assert(!def->is_Con(), "constant debug info already constructed directly");
196
197 // Special split handling for Debug Info
198 // If DEF is DOWN, just hook the edge and return
199 // If DEF is UP, Split it DOWN for this USE.
200 if( def->is_Mach() ) {
201 if( def_down ) {
202 // DEF is DOWN, so connect USE directly to the DEF
203 use->set_req(useidx, def);
204 } else {
205 // Block and index where the use occurs.
206 Block *b = _cfg._bbs[use->_idx];
207 // Put the clone just prior to use
208 int bindex = b->find_node(use);
209 // DEF is UP, so must copy it DOWN and hook in USE
210 // Insert SpillCopy before the USE, which uses DEF as its input,
211 // and defs a new live range, which is used by this node.
212 Node *spill = get_spillcopy_wide(def,use,useidx);
213 // did we fail to split?
214 if (!spill) {
215 // Bail
216 return 0;
217 }
218 // insert into basic block
219 insert_proj( b, bindex, spill, maxlrg++ );
220 // Use the new split
221 use->set_req(useidx,spill);
222 }
223 // No further split handling needed for this use
224 return maxlrg;
225 } // End special splitting for debug info live range
226 } // If debug info
227
228 // CISC-SPILLING
229 // Finally, check to see if USE is CISC-Spillable, and if so,
230 // gather_lrg_masks will add the flags bit to its mask, and
231 // no use side copy is needed. This frees up the live range
232 // register choices without causing copy coalescing, etc.
233 if( UseCISCSpill && cisc_sp ) {
234 int inp = use->cisc_operand();
235 if( inp != AdlcVMDeps::Not_cisc_spillable )
236 // Convert operand number to edge index number
237 inp = use->as_Mach()->operand_index(inp);
238 if( inp == (int)useidx ) {
239 use->set_req(useidx, def);
240 #ifndef PRODUCT
241 if( TraceCISCSpill ) {
242 tty->print(" set_split: ");
243 use->dump();
244 }
245 #endif
246 return maxlrg;
247 }
248 }
249
250 //-------------------------------------------
251 // Insert a Copy before the use
252
253 // Block and index where the use occurs.
254 int bindex;
255 // Phi input spill-copys belong at the end of the prior block
256 if( use->is_Phi() ) {
257 b = _cfg._bbs[b->pred(useidx)->_idx];
258 bindex = b->end_idx();
259 } else {
260 // Put the clone just prior to use
261 bindex = b->find_node(use);
262 }
263
264 Node *spill = get_spillcopy_wide( def, use, useidx );
265 if( !spill ) return 0; // Bailed out
266 // Insert SpillCopy before the USE, which uses the reaching DEF as
267 // its input, and defs a new live range, which is used by this node.
268 insert_proj( b, bindex, spill, maxlrg++ );
269 // Use the spill/clone
270 use->set_req(useidx,spill);
271
272 // return updated live range count
273 return maxlrg;
274 }
275
276 //------------------------------split_Rematerialize----------------------------
277 // Clone a local copy of the def.
278 Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) {
279 // The input live ranges will be stretched to the site of the new
280 // instruction. They might be stretched past a def and will thus
281 // have the old and new values of the same live range alive at the
282 // same time - a definite no-no. Split out private copies of
283 // the inputs.
284 if( def->req() > 1 ) {
285 for( uint i = 1; i < def->req(); i++ ) {
286 Node *in = def->in(i);
287 // Check for single-def (LRG cannot redefined)
288 uint lidx = n2lidx(in);
289 if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy
290 if (lrgs(lidx).is_singledef()) continue;
291
292 Block *b_def = _cfg._bbs[def->_idx];
293 int idx_def = b_def->find_node(def);
294 Node *in_spill = get_spillcopy_wide( in, def, i );
295 if( !in_spill ) return 0; // Bailed out
296 insert_proj(b_def,idx_def,in_spill,maxlrg++);
297 if( b_def == b )
298 insidx++;
299 def->set_req(i,in_spill);
300 }
301 }
302
303 Node *spill = def->clone();
304 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
305 // Check when generating nodes
306 return 0;
307 }
308
309 // See if any inputs are currently being spilled, and take the
310 // latest copy of spilled inputs.
311 if( spill->req() > 1 ) {
312 for( uint i = 1; i < spill->req(); i++ ) {
313 Node *in = spill->in(i);
314 uint lidx = Find_id(in);
315
316 // Walk backwards thru spill copy node intermediates
317 if (walkThru) {
318 while ( in->is_SpillCopy() && lidx >= _maxlrg ) {
319 in = in->in(1);
320 lidx = Find_id(in);
321 }
322
323 if (lidx < _maxlrg && lrgs(lidx).is_multidef()) {
324 // walkThru found a multidef LRG, which is unsafe to use, so
325 // just keep the original def used in the clone.
326 in = spill->in(i);
327 lidx = Find_id(in);
328 }
329 }
330
331 if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) {
332 Node *rdef = Reachblock[lrg2reach[lidx]];
333 if( rdef ) spill->set_req(i,rdef);
334 }
335 }
336 }
337
338
339 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" );
340 // Rematerialized op is def->spilled+1
341 set_was_spilled(spill);
342 if( _spilled_once.test(def->_idx) )
343 set_was_spilled(spill);
344
345 insert_proj( b, insidx, spill, maxlrg++ );
346 #ifdef ASSERT
347 // Increment the counter for this lrg
348 splits.at_put(slidx, splits.at(slidx)+1);
349 #endif
350 // See if the cloned def kills any flags, and copy those kills as well
351 uint i = insidx+1;
352 if( clone_projs( b, i, def, spill, maxlrg ) ) {
353 // Adjust the point where we go hi-pressure
354 if( i <= b->_ihrp_index ) b->_ihrp_index++;
355 if( i <= b->_fhrp_index ) b->_fhrp_index++;
356 }
357
358 return spill;
359 }
360
361 //------------------------------is_high_pressure-------------------------------
362 // Function to compute whether or not this live range is "high pressure"
363 // in this block - whether it spills eagerly or not.
364 bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) {
365 if( lrg->_was_spilled1 ) return true;
366 // Forced spilling due to conflict? Then split only at binding uses
367 // or defs, not for supposed capacity problems.
368 // CNC - Turned off 7/8/99, causes too much spilling
369 // if( lrg->_is_bound ) return false;
370
371 // Not yet reached the high-pressure cutoff point, so low pressure
372 uint hrp_idx = lrg->_is_float ? b->_fhrp_index : b->_ihrp_index;
373 if( insidx < hrp_idx ) return false;
374 // Register pressure for the block as a whole depends on reg class
375 int block_pres = lrg->_is_float ? b->_freg_pressure : b->_reg_pressure;
376 // Bound live ranges will split at the binding points first;
377 // Intermediate splits should assume the live range's register set
378 // got "freed up" and that num_regs will become INT_PRESSURE.
379 int bound_pres = lrg->_is_float ? FLOATPRESSURE : INTPRESSURE;
380 // Effective register pressure limit.
381 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
382 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
383 // High pressure if block pressure requires more register freedom
384 // than live range has.
385 return block_pres >= lrg_pres;
386 }
387
388
389 //------------------------------prompt_use---------------------------------
390 // True if lidx is used before any real register is def'd in the block
391 bool PhaseChaitin::prompt_use( Block *b, uint lidx ) {
392 if( lrgs(lidx)._was_spilled2 ) return false;
393
394 // Scan block for 1st use.
395 for( uint i = 1; i <= b->end_idx(); i++ ) {
396 Node *n = b->_nodes[i];
397 // Ignore PHI use, these can be up or down
398 if( n->is_Phi() ) continue;
399 for( uint j = 1; j < n->req(); j++ )
400 if( Find_id(n->in(j)) == lidx )
401 return true; // Found 1st use!
402 if( n->out_RegMask().is_NotEmpty() ) return false;
403 }
404 return false;
405 }
406
407 //------------------------------Split--------------------------------------
408 //----------Split Routine----------
409 // ***** NEW SPLITTING HEURISTIC *****
410 // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there.
411 // Else, no split unless there is a HRP block between a DEF and
412 // one of its uses, and then split at the HRP block.
413 //
414 // USES: If USE is in HRP, split at use to leave main LRG on stack.
415 // Else, hoist LRG back up to register only (ie - split is also DEF)
416 // We will compute a new maxlrg as we go
417 uint PhaseChaitin::Split( uint maxlrg ) {
418 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); )
419
420 uint bidx, pidx, slidx, insidx, inpidx, twoidx;
421 uint non_phi = 1, spill_cnt = 0;
422 Node **Reachblock;
423 Node *n1, *n2, *n3;
424 Node_List *defs,*phis;
425 bool *UPblock;
426 bool u1, u2, u3;
427 Block *b, *pred;
428 PhiNode *phi;
429 GrowableArray<uint> lidxs;
430
431 // Array of counters to count splits per live range
432 GrowableArray<uint> splits;
433
434 //----------Setup Code----------
435 // Create a convenient mapping from lrg numbers to reaches/leaves indices
436 uint *lrg2reach = NEW_RESOURCE_ARRAY( uint, _maxlrg );
437 // Keep track of DEFS & Phis for later passes
438 defs = new Node_List();
439 phis = new Node_List();
440 // Gather info on which LRG's are spilling, and build maps
441 for( bidx = 1; bidx < _maxlrg; bidx++ ) {
442 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
443 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color");
444 lrg2reach[bidx] = spill_cnt;
445 spill_cnt++;
446 lidxs.append(bidx);
447 #ifdef ASSERT
448 // Initialize the split counts to zero
449 splits.append(0);
450 #endif
451 #ifndef PRODUCT
452 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 )
453 tty->print_cr("Warning, 2nd spill of L%d",bidx);
454 #endif
455 }
456 }
457
458 // Create side arrays for propagating reaching defs info.
459 // Each block needs a node pointer for each spilling live range for the
460 // Def which is live into the block. Phi nodes handle multiple input
461 // Defs by querying the output of their predecessor blocks and resolving
462 // them to a single Def at the phi. The pointer is updated for each
463 // Def in the block, and then becomes the output for the block when
464 // processing of the block is complete. We also need to track whether
465 // a Def is UP or DOWN. UP means that it should get a register (ie -
466 // it is always in LRP regions), and DOWN means that it is probably
467 // on the stack (ie - it crosses HRP regions).
468 Node ***Reaches = NEW_RESOURCE_ARRAY( Node**, _cfg._num_blocks+1 );
469 bool **UP = NEW_RESOURCE_ARRAY( bool*, _cfg._num_blocks+1 );
470 Node **debug_defs = NEW_RESOURCE_ARRAY( Node*, spill_cnt );
471 VectorSet **UP_entry= NEW_RESOURCE_ARRAY( VectorSet*, spill_cnt );
472
473 // Initialize Reaches & UP
474 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) {
475 Reaches[bidx] = NEW_RESOURCE_ARRAY( Node*, spill_cnt );
476 UP[bidx] = NEW_RESOURCE_ARRAY( bool, spill_cnt );
477 Node **Reachblock = Reaches[bidx];
478 bool *UPblock = UP[bidx];
479 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
480 UPblock[slidx] = true; // Assume they start in registers
481 Reachblock[slidx] = NULL; // Assume that no def is present
482 }
483 }
484
485 // Initialize to array of empty vectorsets
486 for( slidx = 0; slidx < spill_cnt; slidx++ )
487 UP_entry[slidx] = new VectorSet(Thread::current()->resource_area());
488
489 //----------PASS 1----------
490 //----------Propagation & Node Insertion Code----------
491 // Walk the Blocks in RPO for DEF & USE info
492 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
493
494 if (C->check_node_count(spill_cnt, out_of_nodes)) {
495 return 0;
496 }
497
498 b = _cfg._blocks[bidx];
499 // Reaches & UP arrays for this block
500 Reachblock = Reaches[b->_pre_order];
501 UPblock = UP[b->_pre_order];
502 // Reset counter of start of non-Phi nodes in block
503 non_phi = 1;
504 //----------Block Entry Handling----------
505 // Check for need to insert a new phi
506 // Cycle through this block's predecessors, collecting Reaches
507 // info for each spilled LRG. If they are identical, no phi is
508 // needed. If they differ, check for a phi, and insert if missing,
509 // or update edges if present. Set current block's Reaches set to
510 // be either the phi's or the reaching def, as appropriate.
511 // If no Phi is needed, check if the LRG needs to spill on entry
512 // to the block due to HRP.
513 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
514 // Grab the live range number
515 uint lidx = lidxs.at(slidx);
516 // Do not bother splitting or putting in Phis for single-def
517 // rematerialized live ranges. This happens alot to constants
518 // with long live ranges.
519 if( lrgs(lidx).is_singledef() &&
520 lrgs(lidx)._def->rematerialize() ) {
521 // reset the Reaches & UP entries
522 Reachblock[slidx] = lrgs(lidx)._def;
523 UPblock[slidx] = true;
524 // Record following instruction in case 'n' rematerializes and
525 // kills flags
526 Block *pred1 = _cfg._bbs[b->pred(1)->_idx];
527 continue;
528 }
529
530 // Initialize needs_phi and needs_split
531 bool needs_phi = false;
532 bool needs_split = false;
533 bool has_phi = false;
534 // Walk the predecessor blocks to check inputs for that live range
535 // Grab predecessor block header
536 n1 = b->pred(1);
537 // Grab the appropriate reaching def info for inpidx
538 pred = _cfg._bbs[n1->_idx];
539 pidx = pred->_pre_order;
540 Node **Ltmp = Reaches[pidx];
541 bool *Utmp = UP[pidx];
542 n1 = Ltmp[slidx];
543 u1 = Utmp[slidx];
544 // Initialize node for saving type info
545 n3 = n1;
546 u3 = u1;
547
548 // Compare inputs to see if a Phi is needed
549 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) {
550 // Grab predecessor block headers
551 n2 = b->pred(inpidx);
552 // Grab the appropriate reaching def info for inpidx
553 pred = _cfg._bbs[n2->_idx];
554 pidx = pred->_pre_order;
555 Ltmp = Reaches[pidx];
556 Utmp = UP[pidx];
557 n2 = Ltmp[slidx];
558 u2 = Utmp[slidx];
559 // For each LRG, decide if a phi is necessary
560 if( n1 != n2 ) {
561 needs_phi = true;
562 }
563 // See if the phi has mismatched inputs, UP vs. DOWN
564 if( n1 && n2 && (u1 != u2) ) {
565 needs_split = true;
566 }
567 // Move n2/u2 to n1/u1 for next iteration
568 n1 = n2;
569 u1 = u2;
570 // Preserve a non-NULL predecessor for later type referencing
571 if( (n3 == NULL) && (n2 != NULL) ){
572 n3 = n2;
573 u3 = u2;
574 }
575 } // End for all potential Phi inputs
576
577 // check block for appropriate phinode & update edges
578 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
579 n1 = b->_nodes[insidx];
580 // bail if this is not a phi
581 phi = n1->is_Phi() ? n1->as_Phi() : NULL;
582 if( phi == NULL ) {
583 // Keep track of index of first non-PhiNode instruction in block
584 non_phi = insidx;
585 // break out of the for loop as we have handled all phi nodes
586 break;
587 }
588 // must be looking at a phi
589 if( Find_id(n1) == lidxs.at(slidx) ) {
590 // found the necessary phi
591 needs_phi = false;
592 has_phi = true;
593 // initialize the Reaches entry for this LRG
594 Reachblock[slidx] = phi;
595 break;
596 } // end if found correct phi
597 } // end for all phi's
598
599 // If a phi is needed or exist, check for it
600 if( needs_phi || has_phi ) {
601 // add new phinode if one not already found
602 if( needs_phi ) {
603 // create a new phi node and insert it into the block
604 // type is taken from left over pointer to a predecessor
605 assert(n3,"No non-NULL reaching DEF for a Phi");
606 phi = new (C, b->num_preds()) PhiNode(b->head(), n3->bottom_type());
607 // initialize the Reaches entry for this LRG
608 Reachblock[slidx] = phi;
609
610 // add node to block & node_to_block mapping
611 insert_proj( b, insidx++, phi, maxlrg++ );
612 non_phi++;
613 // Reset new phi's mapping to be the spilling live range
614 _names.map(phi->_idx, lidx);
615 assert(Find_id(phi) == lidx,"Bad update on Union-Find mapping");
616 } // end if not found correct phi
617 // Here you have either found or created the Phi, so record it
618 assert(phi != NULL,"Must have a Phi Node here");
619 phis->push(phi);
620 // PhiNodes should either force the LRG UP or DOWN depending
621 // on its inputs and the register pressure in the Phi's block.
622 UPblock[slidx] = true; // Assume new DEF is UP
623 // If entering a high-pressure area with no immediate use,
624 // assume Phi is DOWN
625 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) )
626 UPblock[slidx] = false;
627 // If we are not split up/down and all inputs are down, then we
628 // are down
629 if( !needs_split && !u3 )
630 UPblock[slidx] = false;
631 } // end if phi is needed
632
633 // Do not need a phi, so grab the reaching DEF
634 else {
635 // Grab predecessor block header
636 n1 = b->pred(1);
637 // Grab the appropriate reaching def info for k
638 pred = _cfg._bbs[n1->_idx];
639 pidx = pred->_pre_order;
640 Node **Ltmp = Reaches[pidx];
641 bool *Utmp = UP[pidx];
642 // reset the Reaches & UP entries
643 Reachblock[slidx] = Ltmp[slidx];
644 UPblock[slidx] = Utmp[slidx];
645 } // end else no Phi is needed
646 } // end for all spilling live ranges
647 // DEBUG
648 #ifndef PRODUCT
649 if(trace_spilling()) {
650 tty->print("/`\nBlock %d: ", b->_pre_order);
651 tty->print("Reaching Definitions after Phi handling\n");
652 for( uint x = 0; x < spill_cnt; x++ ) {
653 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]);
654 if( Reachblock[x] )
655 Reachblock[x]->dump();
656 else
657 tty->print("Undefined\n");
658 }
659 }
660 #endif
661
662 //----------Non-Phi Node Splitting----------
663 // Since phi-nodes have now been handled, the Reachblock array for this
664 // block is initialized with the correct starting value for the defs which
665 // reach non-phi instructions in this block. Thus, process non-phi
666 // instructions normally, inserting SpillCopy nodes for all spill
667 // locations.
668
669 // Memoize any DOWN reaching definitions for use as DEBUG info
670 for( insidx = 0; insidx < spill_cnt; insidx++ ) {
671 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx];
672 if( UPblock[insidx] ) // Memoize UP decision at block start
673 UP_entry[insidx]->set( b->_pre_order );
674 }
675
676 //----------Walk Instructions in the Block and Split----------
677 // For all non-phi instructions in the block
678 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
679 Node *n = b->_nodes[insidx];
680 // Find the defining Node's live range index
681 uint defidx = Find_id(n);
682 uint cnt = n->req();
683
684 if( n->is_Phi() ) {
685 // Skip phi nodes after removing dead copies.
686 if( defidx < _maxlrg ) {
687 // Check for useless Phis. These appear if we spill, then
688 // coalesce away copies. Dont touch Phis in spilling live
689 // ranges; they are busy getting modifed in this pass.
690 if( lrgs(defidx).reg() < LRG::SPILL_REG ) {
691 uint i;
692 Node *u = NULL;
693 // Look for the Phi merging 2 unique inputs
694 for( i = 1; i < cnt; i++ ) {
695 // Ignore repeats and self
696 if( n->in(i) != u && n->in(i) != n ) {
697 // Found a unique input
698 if( u != NULL ) // If it's the 2nd, bail out
699 break;
700 u = n->in(i); // Else record it
701 }
702 }
703 assert( u, "at least 1 valid input expected" );
704 if( i >= cnt ) { // Found one unique input
705 assert(Find_id(n) == Find_id(u), "should be the same lrg");
706 n->replace_by(u); // Then replace with unique input
707 n->disconnect_inputs(NULL);
708 b->_nodes.remove(insidx);
709 insidx--;
710 b->_ihrp_index--;
711 b->_fhrp_index--;
712 }
713 }
714 }
715 continue;
716 }
717 assert( insidx > b->_ihrp_index ||
718 (b->_reg_pressure < (uint)INTPRESSURE) ||
719 b->_ihrp_index > 4000000 ||
720 b->_ihrp_index >= b->end_idx() ||
721 !b->_nodes[b->_ihrp_index]->is_Proj(), "" );
722 assert( insidx > b->_fhrp_index ||
723 (b->_freg_pressure < (uint)FLOATPRESSURE) ||
724 b->_fhrp_index > 4000000 ||
725 b->_fhrp_index >= b->end_idx() ||
726 !b->_nodes[b->_fhrp_index]->is_Proj(), "" );
727
728 // ********** Handle Crossing HRP Boundry **********
729 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) {
730 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
731 // Check for need to split at HRP boundry - split if UP
732 n1 = Reachblock[slidx];
733 // bail out if no reaching DEF
734 if( n1 == NULL ) continue;
735 // bail out if live range is 'isolated' around inner loop
736 uint lidx = lidxs.at(slidx);
737 // If live range is currently UP
738 if( UPblock[slidx] ) {
739 // set location to insert spills at
740 // SPLIT DOWN HERE - NO CISC SPILL
741 if( is_high_pressure( b, &lrgs(lidx), insidx ) &&
742 !n1->rematerialize() ) {
743 // If there is already a valid stack definition available, use it
744 if( debug_defs[slidx] != NULL ) {
745 Reachblock[slidx] = debug_defs[slidx];
746 }
747 else {
748 // Insert point is just past last use or def in the block
749 int insert_point = insidx-1;
750 while( insert_point > 0 ) {
751 Node *n = b->_nodes[insert_point];
752 // Hit top of block? Quit going backwards
753 if( n->is_Phi() ) break;
754 // Found a def? Better split after it.
755 if( n2lidx(n) == lidx ) break;
756 // Look for a use
757 uint i;
758 for( i = 1; i < n->req(); i++ )
759 if( n2lidx(n->in(i)) == lidx )
760 break;
761 // Found a use? Better split after it.
762 if( i < n->req() ) break;
763 insert_point--;
764 }
765 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
766 // If it wasn't split bail
767 if (!maxlrg) {
768 return 0;
769 }
770 insidx++;
771 }
772 // This is a new DEF, so update UP
773 UPblock[slidx] = false;
774 #ifndef PRODUCT
775 // DEBUG
776 if( trace_spilling() ) {
777 tty->print("\nNew Split DOWN DEF of Spill Idx ");
778 tty->print("%d, UP %d:\n",slidx,false);
779 n1->dump();
780 }
781 #endif
782 }
783 } // end if LRG is UP
784 } // end for all spilling live ranges
785 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" );
786 } // end if crossing HRP Boundry
787
788 // If the LRG index is oob, then this is a new spillcopy, skip it.
789 if( defidx >= _maxlrg ) {
790 continue;
791 }
792 LRG &deflrg = lrgs(defidx);
793 uint copyidx = n->is_Copy();
794 // Remove coalesced copy from CFG
795 if( copyidx && defidx == n2lidx(n->in(copyidx)) ) {
796 n->replace_by( n->in(copyidx) );
797 n->set_req( copyidx, NULL );
798 b->_nodes.remove(insidx--);
799 b->_ihrp_index--; // Adjust the point where we go hi-pressure
800 b->_fhrp_index--;
801 continue;
802 }
803
804 #define DERIVED 0
805
806 // ********** Handle USES **********
807 bool nullcheck = false;
808 // Implicit null checks never use the spilled value
809 if( n->is_MachNullCheck() )
810 nullcheck = true;
811 if( !nullcheck ) {
812 // Search all inputs for a Spill-USE
813 JVMState* jvms = n->jvms();
814 uint oopoff = jvms ? jvms->oopoff() : cnt;
815 uint old_last = cnt - 1;
816 for( inpidx = 1; inpidx < cnt; inpidx++ ) {
817 // Derived/base pairs may be added to our inputs during this loop.
818 // If inpidx > old_last, then one of these new inputs is being
819 // handled. Skip the derived part of the pair, but process
820 // the base like any other input.
821 if( inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED ) {
822 continue; // skip derived_debug added below
823 }
824 // Get lidx of input
825 uint useidx = Find_id(n->in(inpidx));
826 // Not a brand-new split, and it is a spill use
827 if( useidx < _maxlrg && lrgs(useidx).reg() >= LRG::SPILL_REG ) {
828 // Check for valid reaching DEF
829 slidx = lrg2reach[useidx];
830 Node *def = Reachblock[slidx];
831 assert( def != NULL, "Using Undefined Value in Split()\n");
832
833 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp
834 // monitor references do not care where they live, so just hook
835 if ( jvms && jvms->is_monitor_use(inpidx) ) {
836 // The effect of this clone is to drop the node out of the block,
837 // so that the allocator does not see it anymore, and therefore
838 // does not attempt to assign it a register.
839 def = def->clone();
840 _names.extend(def->_idx,0);
841 _cfg._bbs.map(def->_idx,b);
842 n->set_req(inpidx, def);
843 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
844 return 0;
845 }
846 continue;
847 }
848
849 // Rematerializable? Then clone def at use site instead
850 // of store/load
851 if( def->rematerialize() ) {
852 int old_size = b->_nodes.size();
853 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true );
854 if( !def ) return 0; // Bail out
855 insidx += b->_nodes.size()-old_size;
856 }
857
858 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL;
859 // Base pointers and oopmap references do not care where they live.
860 if ((inpidx >= oopoff) ||
861 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) {
862 if (def->rematerialize() && lrgs(useidx)._was_spilled2) {
863 // This def has been rematerialized a couple of times without
864 // progress. It doesn't care if it lives UP or DOWN, so
865 // spill it down now.
866 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx);
867 // If it wasn't split bail
868 if (!maxlrg) {
869 return 0;
870 }
871 insidx++; // Reset iterator to skip USE side split
872 } else {
873 // Just hook the def edge
874 n->set_req(inpidx, def);
875 }
876
877 if (inpidx >= oopoff) {
878 // After oopoff, we have derived/base pairs. We must mention all
879 // derived pointers here as derived/base pairs for GC. If the
880 // derived value is spilling and we have a copy both in Reachblock
881 // (called here 'def') and debug_defs[slidx] we need to mention
882 // both in derived/base pairs or kill one.
883 Node *derived_debug = debug_defs[slidx];
884 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base?
885 mach && mach->ideal_Opcode() != Op_Halt &&
886 derived_debug != NULL &&
887 derived_debug != def ) { // Actual 2nd value appears
888 // We have already set 'def' as a derived value.
889 // Also set debug_defs[slidx] as a derived value.
890 uint k;
891 for( k = oopoff; k < cnt; k += 2 )
892 if( n->in(k) == derived_debug )
893 break; // Found an instance of debug derived
894 if( k == cnt ) {// No instance of debug_defs[slidx]
895 // Add a derived/base pair to cover the debug info.
896 // We have to process the added base later since it is not
897 // handled yet at this point but skip derived part.
898 assert(((n->req() - oopoff) & 1) == DERIVED,
899 "must match skip condition above");
900 n->add_req( derived_debug ); // this will be skipped above
901 n->add_req( n->in(inpidx+1) ); // this will be processed
902 // Increment cnt to handle added input edges on
903 // subsequent iterations.
904 cnt += 2;
905 }
906 }
907 }
908 continue;
909 }
910 // Special logic for DEBUG info
911 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) {
912 uint debug_start = jvms->debug_start();
913 // If this is debug info use & there is a reaching DOWN def
914 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) {
915 assert(inpidx < oopoff, "handle only debug info here");
916 // Just hook it in & move on
917 n->set_req(inpidx, debug_defs[slidx]);
918 // (Note that this can make two sides of a split live at the
919 // same time: The debug def on stack, and another def in a
920 // register. The GC needs to know about both of them, but any
921 // derived pointers after oopoff will refer to only one of the
922 // two defs and the GC would therefore miss the other. Thus
923 // this hack is only allowed for debug info which is Java state
924 // and therefore never a derived pointer.)
925 continue;
926 }
927 }
928 // Grab register mask info
929 const RegMask &dmask = def->out_RegMask();
930 const RegMask &umask = n->in_RegMask(inpidx);
931
932 assert(inpidx < oopoff, "cannot use-split oop map info");
933
934 bool dup = UPblock[slidx];
935 bool uup = umask.is_UP();
936
937 // Need special logic to handle bound USES. Insert a split at this
938 // bound use if we can't rematerialize the def, or if we need the
939 // split to form a misaligned pair.
940 if( !umask.is_AllStack() &&
941 (int)umask.Size() <= lrgs(useidx).num_regs() &&
942 (!def->rematerialize() ||
943 umask.is_misaligned_Pair())) {
944 // These need a Split regardless of overlap or pressure
945 // SPLIT - NO DEF - NO CISC SPILL
946 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
947 // If it wasn't split bail
948 if (!maxlrg) {
949 return 0;
950 }
951 insidx++; // Reset iterator to skip USE side split
952 continue;
953 }
954 // Here is the logic chart which describes USE Splitting:
955 // 0 = false or DOWN, 1 = true or UP
956 //
957 // Overlap | DEF | USE | Action
958 //-------------------------------------------------------
959 // 0 | 0 | 0 | Copy - mem -> mem
960 // 0 | 0 | 1 | Split-UP - Check HRP
961 // 0 | 1 | 0 | Split-DOWN - Debug Info?
962 // 0 | 1 | 1 | Copy - reg -> reg
963 // 1 | 0 | 0 | Reset Input Edge (no Split)
964 // 1 | 0 | 1 | Split-UP - Check HRP
965 // 1 | 1 | 0 | Split-DOWN - Debug Info?
966 // 1 | 1 | 1 | Reset Input Edge (no Split)
967 //
968 // So, if (dup == uup), then overlap test determines action,
969 // with true being no split, and false being copy. Else,
970 // if DEF is DOWN, Split-UP, and check HRP to decide on
971 // resetting DEF. Finally if DEF is UP, Split-DOWN, with
972 // special handling for Debug Info.
973 if( dup == uup ) {
974 if( dmask.overlap(umask) ) {
975 // Both are either up or down, and there is overlap, No Split
976 n->set_req(inpidx, def);
977 }
978 else { // Both are either up or down, and there is no overlap
979 if( dup ) { // If UP, reg->reg copy
980 // COPY ACROSS HERE - NO DEF - NO CISC SPILL
981 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
982 // If it wasn't split bail
983 if (!maxlrg) {
984 return 0;
985 }
986 insidx++; // Reset iterator to skip USE side split
987 }
988 else { // DOWN, mem->mem copy
989 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL
990 // First Split-UP to move value into Register
991 uint def_ideal = def->ideal_reg();
992 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal];
993 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm);
994 insert_proj( b, insidx, spill, maxlrg );
995 // Then Split-DOWN as if previous Split was DEF
996 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx);
997 // If it wasn't split bail
998 if (!maxlrg) {
999 return 0;
1000 }
1001 insidx += 2; // Reset iterator to skip USE side splits
1002 }
1003 } // End else no overlap
1004 } // End if dup == uup
1005 // dup != uup, so check dup for direction of Split
1006 else {
1007 if( dup ) { // If UP, Split-DOWN and check Debug Info
1008 // If this node is already a SpillCopy, just patch the edge
1009 // except the case of spilling to stack.
1010 if( n->is_SpillCopy() ) {
1011 RegMask tmp_rm(umask);
1012 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask);
1013 if( dmask.overlap(tmp_rm) ) {
1014 if( def != n->in(inpidx) ) {
1015 n->set_req(inpidx, def);
1016 }
1017 continue;
1018 }
1019 }
1020 // COPY DOWN HERE - NO DEF - NO CISC SPILL
1021 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1022 // If it wasn't split bail
1023 if (!maxlrg) {
1024 return 0;
1025 }
1026 insidx++; // Reset iterator to skip USE side split
1027 // Check for debug-info split. Capture it for later
1028 // debug splits of the same value
1029 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff)
1030 debug_defs[slidx] = n->in(inpidx);
1031
1032 }
1033 else { // DOWN, Split-UP and check register pressure
1034 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) {
1035 // COPY UP HERE - NO DEF - CISC SPILL
1036 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx);
1037 // If it wasn't split bail
1038 if (!maxlrg) {
1039 return 0;
1040 }
1041 insidx++; // Reset iterator to skip USE side split
1042 } else { // LRP
1043 // COPY UP HERE - WITH DEF - NO CISC SPILL
1044 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx);
1045 // If it wasn't split bail
1046 if (!maxlrg) {
1047 return 0;
1048 }
1049 // Flag this lift-up in a low-pressure block as
1050 // already-spilled, so if it spills again it will
1051 // spill hard (instead of not spilling hard and
1052 // coalescing away).
1053 set_was_spilled(n->in(inpidx));
1054 // Since this is a new DEF, update Reachblock & UP
1055 Reachblock[slidx] = n->in(inpidx);
1056 UPblock[slidx] = true;
1057 insidx++; // Reset iterator to skip USE side split
1058 }
1059 } // End else DOWN
1060 } // End dup != uup
1061 } // End if Spill USE
1062 } // End For All Inputs
1063 } // End If not nullcheck
1064
1065 // ********** Handle DEFS **********
1066 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1067 // just reset the Reaches info in LRP regions. DEFS must always update
1068 // UP info.
1069 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1070 uint slidx = lrg2reach[defidx];
1071 // Add to defs list for later assignment of new live range number
1072 defs->push(n);
1073 // Set a flag on the Node indicating it has already spilled.
1074 // Only do it for capacity spills not conflict spills.
1075 if( !deflrg._direct_conflict )
1076 set_was_spilled(n);
1077 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1078 // Grab UP info for DEF
1079 const RegMask &dmask = n->out_RegMask();
1080 bool defup = dmask.is_UP();
1081 // Only split at Def if this is a HRP block or bound (and spilled once)
1082 if( !n->rematerialize() &&
1083 (((dmask.is_bound1() || dmask.is_bound2() || dmask.is_misaligned_Pair()) &&
1084 (deflrg._direct_conflict || deflrg._must_spill)) ||
1085 // Check for LRG being up in a register and we are inside a high
1086 // pressure area. Spill it down immediately.
1087 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1088 assert( !n->rematerialize(), "" );
1089 assert( !n->is_SpillCopy(), "" );
1090 // Do a split at the def site.
1091 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1092 // If it wasn't split bail
1093 if (!maxlrg) {
1094 return 0;
1095 }
1096 // Split DEF's Down
1097 UPblock[slidx] = 0;
1098 #ifndef PRODUCT
1099 // DEBUG
1100 if( trace_spilling() ) {
1101 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1102 tty->print("%d, UP %d:\n",slidx,false);
1103 n->dump();
1104 }
1105 #endif
1106 }
1107 else { // Neither bound nor HRP, must be LRP
1108 // otherwise, just record the def
1109 Reachblock[slidx] = n;
1110 // UP should come from the outRegmask() of the DEF
1111 UPblock[slidx] = defup;
1112 // Update debug list of reaching down definitions, kill if DEF is UP
1113 debug_defs[slidx] = defup ? NULL : n;
1114 #ifndef PRODUCT
1115 // DEBUG
1116 if( trace_spilling() ) {
1117 tty->print("\nNew DEF of Spill Idx ");
1118 tty->print("%d, UP %d:\n",slidx,defup);
1119 n->dump();
1120 }
1121 #endif
1122 } // End else LRP
1123 } // End if spill def
1124
1125 // ********** Split Left Over Mem-Mem Moves **********
1126 // Check for mem-mem copies and split them now. Do not do this
1127 // to copies about to be spilled; they will be Split shortly.
1128 if( copyidx ) {
1129 Node *use = n->in(copyidx);
1130 uint useidx = Find_id(use);
1131 if( useidx < _maxlrg && // This is not a new split
1132 OptoReg::is_stack(deflrg.reg()) &&
1133 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack
1134 LRG &uselrg = lrgs(useidx);
1135 if( OptoReg::is_stack(uselrg.reg()) &&
1136 uselrg.reg() < LRG::SPILL_REG && // USE is from stack
1137 deflrg.reg() != uselrg.reg() ) { // Not trivially removed
1138 uint def_ideal_reg = Matcher::base2reg[n->bottom_type()->base()];
1139 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg];
1140 const RegMask &use_rm = n->in_RegMask(copyidx);
1141 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL
1142 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes
1143 return 0;
1144 }
1145 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm);
1146 n->set_req(copyidx,spill);
1147 n->as_MachSpillCopy()->set_in_RegMask(def_rm);
1148 // Put the spill just before the copy
1149 insert_proj( b, insidx++, spill, maxlrg++ );
1150 }
1151 }
1152 }
1153 }
1154 } // End For All Instructions in Block - Non-PHI Pass
1155
1156 // Check if each LRG is live out of this block so as not to propagate
1157 // beyond the last use of a LRG.
1158 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1159 uint defidx = lidxs.at(slidx);
1160 IndexSet *liveout = _live->live(b);
1161 if( !liveout->member(defidx) ) {
1162 #ifdef ASSERT
1163 // The index defidx is not live. Check the liveout array to ensure that
1164 // it contains no members which compress to defidx. Finding such an
1165 // instance may be a case to add liveout adjustment in compress_uf_map().
1166 // See 5063219.
1167 uint member;
1168 IndexSetIterator isi(liveout);
1169 while ((member = isi.next()) != 0) {
1170 assert(defidx != Find_const(member), "Live out member has not been compressed");
1171 }
1172 #endif
1173 Reachblock[slidx] = NULL;
1174 } else {
1175 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value");
1176 }
1177 }
1178 #ifndef PRODUCT
1179 if( trace_spilling() )
1180 b->dump();
1181 #endif
1182 } // End For All Blocks
1183
1184 //----------PASS 2----------
1185 // Reset all DEF live range numbers here
1186 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1187 // Grab the def
1188 n1 = defs->at(insidx);
1189 // Set new lidx for DEF
1190 new_lrg(n1, maxlrg++);
1191 }
1192 //----------Phi Node Splitting----------
1193 // Clean up a phi here, and assign a new live range number
1194 // Cycle through this block's predecessors, collecting Reaches
1195 // info for each spilled LRG and update edges.
1196 // Walk the phis list to patch inputs, split phis, and name phis
1197 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1198 Node *phi = phis->at(insidx);
1199 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1200 Block *b = _cfg._bbs[phi->_idx];
1201 // Grab the live range number
1202 uint lidx = Find_id(phi);
1203 uint slidx = lrg2reach[lidx];
1204 // Update node to lidx map
1205 new_lrg(phi, maxlrg++);
1206 // Get PASS1's up/down decision for the block.
1207 int phi_up = !!UP_entry[slidx]->test(b->_pre_order);
1208
1209 // Force down if double-spilling live range
1210 if( lrgs(lidx)._was_spilled1 )
1211 phi_up = false;
1212
1213 // When splitting a Phi we an split it normal or "inverted".
1214 // An inverted split makes the splits target the Phi's UP/DOWN
1215 // sense inverted; then the Phi is followed by a final def-side
1216 // split to invert back. It changes which blocks the spill code
1217 // goes in.
1218
1219 // Walk the predecessor blocks and assign the reaching def to the Phi.
1220 // Split Phi nodes by placing USE side splits wherever the reaching
1221 // DEF has the wrong UP/DOWN value.
1222 for( uint i = 1; i < b->num_preds(); i++ ) {
1223 // Get predecessor block pre-order number
1224 Block *pred = _cfg._bbs[b->pred(i)->_idx];
1225 pidx = pred->_pre_order;
1226 // Grab reaching def
1227 Node *def = Reaches[pidx][slidx];
1228 assert( def, "must have reaching def" );
1229 // If input up/down sense and reg-pressure DISagree
1230 if( def->rematerialize() ) {
1231 def = split_Rematerialize( def, pred, pred->end_idx(), maxlrg, splits, slidx, lrg2reach, Reachblock, false );
1232 if( !def ) return 0; // Bail out
1233 }
1234 // Update the Phi's input edge array
1235 phi->set_req(i,def);
1236 // Grab the UP/DOWN sense for the input
1237 u1 = UP[pidx][slidx];
1238 if( u1 != (phi_up != 0)) {
1239 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx);
1240 // If it wasn't split bail
1241 if (!maxlrg) {
1242 return 0;
1243 }
1244 }
1245 } // End for all inputs to the Phi
1246 } // End for all Phi Nodes
1247 // Update _maxlrg to save Union asserts
1248 _maxlrg = maxlrg;
1249
1250
1251 //----------PASS 3----------
1252 // Pass over all Phi's to union the live ranges
1253 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1254 Node *phi = phis->at(insidx);
1255 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1256 // Walk all inputs to Phi and Union input live range with Phi live range
1257 for( uint i = 1; i < phi->req(); i++ ) {
1258 // Grab the input node
1259 Node *n = phi->in(i);
1260 assert( n, "" );
1261 uint lidx = Find(n);
1262 uint pidx = Find(phi);
1263 if( lidx < pidx )
1264 Union(n, phi);
1265 else if( lidx > pidx )
1266 Union(phi, n);
1267 } // End for all inputs to the Phi Node
1268 } // End for all Phi Nodes
1269 // Now union all two address instructions
1270 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1271 // Grab the def
1272 n1 = defs->at(insidx);
1273 // Set new lidx for DEF & handle 2-addr instructions
1274 if( n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0) ) {
1275 assert( Find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index");
1276 // Union the input and output live ranges
1277 uint lr1 = Find(n1);
1278 uint lr2 = Find(n1->in(twoidx));
1279 if( lr1 < lr2 )
1280 Union(n1, n1->in(twoidx));
1281 else if( lr1 > lr2 )
1282 Union(n1->in(twoidx), n1);
1283 } // End if two address
1284 } // End for all defs
1285 // DEBUG
1286 #ifdef ASSERT
1287 // Validate all live range index assignments
1288 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
1289 b = _cfg._blocks[bidx];
1290 for( insidx = 0; insidx <= b->end_idx(); insidx++ ) {
1291 Node *n = b->_nodes[insidx];
1292 uint defidx = Find(n);
1293 assert(defidx < _maxlrg,"Bad live range index in Split");
1294 assert(defidx < maxlrg,"Bad live range index in Split");
1295 }
1296 }
1297 // Issue a warning if splitting made no progress
1298 int noprogress = 0;
1299 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1300 if( PrintOpto && WizardMode && splits.at(slidx) == 0 ) {
1301 tty->print_cr("Failed to split live range %d", lidxs.at(slidx));
1302 //BREAKPOINT;
1303 }
1304 else {
1305 noprogress++;
1306 }
1307 }
1308 if(!noprogress) {
1309 tty->print_cr("Failed to make progress in Split");
1310 //BREAKPOINT;
1311 }
1312 #endif
1313 // Return updated count of live ranges
1314 return maxlrg;
1315 }