1 /*
2 * Copyright 2000-2006 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_reg_split.cpp.incl"
27
28 //------------------------------Split--------------------------------------
29 // Walk the graph in RPO and for each lrg which spills, propogate reaching
30 // definitions. During propogation, split the live range around regions of
31 // High Register Pressure (HRP). If a Def is in a region of Low Register
32 // Pressure (LRP), it will not get spilled until we encounter a region of
33 // HRP between it and one of its uses. We will spill at the transition
34 // point between LRP and HRP. Uses in the HRP region will use the spilled
35 // Def. The first Use outside the HRP region will generate a SpillCopy to
36 // hoist the live range back up into a register, and all subsequent uses
37 // will use that new Def until another HRP region is encountered. Defs in
38 // HRP regions will get trailing SpillCopies to push the LRG down into the
39 // stack immediately.
40 //
41 // As a side effect, unlink from (hence make dead) coalesced copies.
42 //
43
44 static const char out_of_nodes[] = "out of nodes during split";
45
46 //------------------------------get_spillcopy_wide-----------------------------
47 // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the
48 // wide ideal-register spill-mask if possible. If the 'wide-mask' does
49 // not cover the input (or output), use the input (or output) mask instead.
50 Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) {
51 // If ideal reg doesn't exist we've got a bad schedule happening
52 // that is forcing us to spill something that isn't spillable.
53 // Bail rather than abort
54 int ireg = def->ideal_reg();
55 if( ireg == 0 || ireg == Op_RegFlags ) {
56 C->record_method_not_compilable("attempted to spill a non-spillable item");
57 return NULL;
58 }
59 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
60 return NULL;
61 }
62 const RegMask *i_mask = &def->out_RegMask();
63 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg];
64 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask;
65 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask;
66 const RegMask *w_o_mask;
67
68 if( w_mask->overlap( *o_mask ) && // Overlap AND
69 ((ireg != Op_RegL && ireg != Op_RegD // Single use or aligned
70 #ifdef _LP64
71 && ireg != Op_RegP
72 #endif
73 ) || o_mask->is_aligned_Pairs()) ) {
74 // Don't come here for mis-aligned doubles
75 w_o_mask = w_mask;
76 } else { // wide ideal mask does not overlap with o_mask
77 // Mis-aligned doubles come here and XMM->FPR moves on x86.
78 w_o_mask = o_mask; // Must target desired registers
79 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use
80 // a reg-reg move or do I need a trip across register classes
81 // (and thus through memory)?
82 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() )
83 // Here we assume a trip through memory is required.
84 w_i_mask = &C->FIRST_STACK_mask();
85 }
86 return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask );
87 }
88
89 //------------------------------insert_proj------------------------------------
90 // Insert the spill at chosen location. Skip over any interveneing Proj's or
91 // Phis. Skip over a CatchNode and projs, inserting in the fall-through block
92 // instead. Update high-pressure indices. Create a new live range.
93 void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) {
94 // Skip intervening ProjNodes. Do not insert between a ProjNode and
95 // its definer.
96 while( i < b->_nodes.size() &&
97 (b->_nodes[i]->is_Proj() ||
98 b->_nodes[i]->is_Phi() ) )
99 i++;
100
101 // Do not insert between a call and his Catch
102 if( b->_nodes[i]->is_Catch() ) {
103 // Put the instruction at the top of the fall-thru block.
104 // Find the fall-thru projection
105 while( 1 ) {
106 const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj();
107 if( cp->_con == CatchProjNode::fall_through_index )
108 break;
109 }
110 int sidx = i - b->end_idx()-1;
111 b = b->_succs[sidx]; // Switch to successor block
112 i = 1; // Right at start of block
113 }
114
115 b->_nodes.insert(i,spill); // Insert node in block
116 _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect
117 // Adjust the point where we go hi-pressure
118 if( i <= b->_ihrp_index ) b->_ihrp_index++;
119 if( i <= b->_fhrp_index ) b->_fhrp_index++;
120
121 // Assign a new Live Range Number to the SpillCopy and grow
122 // the node->live range mapping.
123 new_lrg(spill,maxlrg);
124 }
125
126 //------------------------------split_DEF--------------------------------------
127 // There are four catagories of Split; UP/DOWN x DEF/USE
128 // Only three of these really occur as DOWN/USE will always color
129 // Any Split with a DEF cannot CISC-Spill now. Thus we need
130 // two helper routines, one for Split DEFS (insert after instruction),
131 // one for Split USES (insert before instruction). DEF insertion
132 // happens inside Split, where the Leaveblock array is updated.
133 uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) {
134 #ifdef ASSERT
135 // Increment the counter for this lrg
136 splits.at_put(slidx, splits.at(slidx)+1);
137 #endif
138 // If we are spilling the memory op for an implicit null check, at the
139 // null check location (ie - null check is in HRP block) we need to do
140 // the null-check first, then spill-down in the following block.
141 // (The implicit_null_check function ensures the use is also dominated
142 // by the branch-not-taken block.)
143 Node *be = b->end();
144 if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) {
145 // Spill goes in the branch-not-taken block
146 b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue];
147 loc = 0; // Just past the Region
148 }
149 assert( loc >= 0, "must insert past block head" );
150
151 // Get a def-side SpillCopy
152 Node *spill = get_spillcopy_wide(def,NULL,0);
153 // Did we fail to split?, then bail
154 if (!spill) {
155 return 0;
156 }
157
158 // Insert the spill at chosen location
159 insert_proj( b, loc+1, spill, maxlrg++);
160
161 // Insert new node into Reaches array
162 Reachblock[slidx] = spill;
163 // Update debug list of reaching down definitions by adding this one
164 debug_defs[slidx] = spill;
165
166 // return updated count of live ranges
167 return maxlrg;
168 }
169
170 //------------------------------split_USE--------------------------------------
171 // Splits at uses can involve redeffing the LRG, so no CISC Spilling there.
172 // Debug uses want to know if def is already stack enabled.
173 uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) {
174 #ifdef ASSERT
175 // Increment the counter for this lrg
176 splits.at_put(slidx, splits.at(slidx)+1);
177 #endif
178
179 // Some setup stuff for handling debug node uses
180 JVMState* jvms = use->jvms();
181 uint debug_start = jvms ? jvms->debug_start() : 999999;
182 uint debug_end = jvms ? jvms->debug_end() : 999999;
183
184 //-------------------------------------------
185 // Check for use of debug info
186 if (useidx >= debug_start && useidx < debug_end) {
187 // Actually it's perfectly legal for constant debug info to appear
188 // just unlikely. In this case the optimizer left a ConI of a 4
189 // as both inputs to a Phi with only a debug use. It's a single-def
190 // live range of a rematerializable value. The live range spills,
191 // rematerializes and now the ConI directly feeds into the debug info.
192 // assert(!def->is_Con(), "constant debug info already constructed directly");
193
194 // Special split handling for Debug Info
195 // If DEF is DOWN, just hook the edge and return
196 // If DEF is UP, Split it DOWN for this USE.
197 if( def->is_Mach() ) {
198 if( def_down ) {
199 // DEF is DOWN, so connect USE directly to the DEF
200 use->set_req(useidx, def);
201 } else {
202 // Block and index where the use occurs.
203 Block *b = _cfg._bbs[use->_idx];
204 // Put the clone just prior to use
205 int bindex = b->find_node(use);
206 // DEF is UP, so must copy it DOWN and hook in USE
207 // Insert SpillCopy before the USE, which uses DEF as its input,
208 // and defs a new live range, which is used by this node.
209 Node *spill = get_spillcopy_wide(def,use,useidx);
210 // did we fail to split?
211 if (!spill) {
212 // Bail
213 return 0;
214 }
215 // insert into basic block
216 insert_proj( b, bindex, spill, maxlrg++ );
217 // Use the new split
218 use->set_req(useidx,spill);
219 }
220 // No further split handling needed for this use
221 return maxlrg;
222 } // End special splitting for debug info live range
223 } // If debug info
224
225 // CISC-SPILLING
226 // Finally, check to see if USE is CISC-Spillable, and if so,
227 // gather_lrg_masks will add the flags bit to its mask, and
228 // no use side copy is needed. This frees up the live range
229 // register choices without causing copy coalescing, etc.
230 if( UseCISCSpill && cisc_sp ) {
231 int inp = use->cisc_operand();
232 if( inp != AdlcVMDeps::Not_cisc_spillable )
233 // Convert operand number to edge index number
234 inp = use->as_Mach()->operand_index(inp);
235 if( inp == (int)useidx ) {
236 use->set_req(useidx, def);
237 #ifndef PRODUCT
238 if( TraceCISCSpill ) {
239 tty->print(" set_split: ");
240 use->dump();
241 }
242 #endif
243 return maxlrg;
244 }
245 }
246
247 //-------------------------------------------
248 // Insert a Copy before the use
249
250 // Block and index where the use occurs.
251 int bindex;
252 // Phi input spill-copys belong at the end of the prior block
253 if( use->is_Phi() ) {
254 b = _cfg._bbs[b->pred(useidx)->_idx];
255 bindex = b->end_idx();
256 } else {
257 // Put the clone just prior to use
258 bindex = b->find_node(use);
259 }
260
261 Node *spill = get_spillcopy_wide( def, use, useidx );
262 if( !spill ) return 0; // Bailed out
263 // Insert SpillCopy before the USE, which uses the reaching DEF as
264 // its input, and defs a new live range, which is used by this node.
265 insert_proj( b, bindex, spill, maxlrg++ );
266 // Use the spill/clone
267 use->set_req(useidx,spill);
268
269 // return updated live range count
270 return maxlrg;
271 }
272
273 //------------------------------split_Rematerialize----------------------------
274 // Clone a local copy of the def.
275 Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) {
276 // The input live ranges will be stretched to the site of the new
277 // instruction. They might be stretched past a def and will thus
278 // have the old and new values of the same live range alive at the
279 // same time - a definite no-no. Split out private copies of
280 // the inputs.
281 if( def->req() > 1 ) {
282 for( uint i = 1; i < def->req(); i++ ) {
283 Node *in = def->in(i);
284 // Check for single-def (LRG cannot redefined)
285 uint lidx = n2lidx(in);
286 if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy
287 if (lrgs(lidx).is_singledef()) continue;
288
289 Block *b_def = _cfg._bbs[def->_idx];
290 int idx_def = b_def->find_node(def);
291 Node *in_spill = get_spillcopy_wide( in, def, i );
292 if( !in_spill ) return 0; // Bailed out
293 insert_proj(b_def,idx_def,in_spill,maxlrg++);
294 if( b_def == b )
295 insidx++;
296 def->set_req(i,in_spill);
297 }
298 }
299
300 Node *spill = def->clone();
301 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
302 // Check when generating nodes
303 return 0;
304 }
305
306 // See if any inputs are currently being spilled, and take the
307 // latest copy of spilled inputs.
308 if( spill->req() > 1 ) {
309 for( uint i = 1; i < spill->req(); i++ ) {
310 Node *in = spill->in(i);
311 uint lidx = Find_id(in);
312
313 // Walk backwards thru spill copy node intermediates
314 if (walkThru) {
315 while ( in->is_SpillCopy() && lidx >= _maxlrg ) {
316 in = in->in(1);
317 lidx = Find_id(in);
318 }
319
320 if (lidx < _maxlrg && lrgs(lidx).is_multidef()) {
321 // walkThru found a multidef LRG, which is unsafe to use, so
322 // just keep the original def used in the clone.
323 in = spill->in(i);
324 lidx = Find_id(in);
325 }
326 }
327
328 if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) {
329 Node *rdef = Reachblock[lrg2reach[lidx]];
330 if( rdef ) spill->set_req(i,rdef);
331 }
332 }
333 }
334
335
336 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" );
337 // Rematerialized op is def->spilled+1
338 set_was_spilled(spill);
339 if( _spilled_once.test(def->_idx) )
340 set_was_spilled(spill);
341
342 insert_proj( b, insidx, spill, maxlrg++ );
343 #ifdef ASSERT
344 // Increment the counter for this lrg
345 splits.at_put(slidx, splits.at(slidx)+1);
346 #endif
347 // See if the cloned def kills any flags, and copy those kills as well
348 uint i = insidx+1;
349 if( clone_projs( b, i, def, spill, maxlrg ) ) {
350 // Adjust the point where we go hi-pressure
351 if( i <= b->_ihrp_index ) b->_ihrp_index++;
352 if( i <= b->_fhrp_index ) b->_fhrp_index++;
353 }
354
355 return spill;
356 }
357
358 //------------------------------is_high_pressure-------------------------------
359 // Function to compute whether or not this live range is "high pressure"
360 // in this block - whether it spills eagerly or not.
361 bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) {
362 if( lrg->_was_spilled1 ) return true;
363 // Forced spilling due to conflict? Then split only at binding uses
364 // or defs, not for supposed capacity problems.
365 // CNC - Turned off 7/8/99, causes too much spilling
366 // if( lrg->_is_bound ) return false;
367
368 // Not yet reached the high-pressure cutoff point, so low pressure
369 uint hrp_idx = lrg->_is_float ? b->_fhrp_index : b->_ihrp_index;
370 if( insidx < hrp_idx ) return false;
371 // Register pressure for the block as a whole depends on reg class
372 int block_pres = lrg->_is_float ? b->_freg_pressure : b->_reg_pressure;
373 // Bound live ranges will split at the binding points first;
374 // Intermediate splits should assume the live range's register set
375 // got "freed up" and that num_regs will become INT_PRESSURE.
376 int bound_pres = lrg->_is_float ? FLOATPRESSURE : INTPRESSURE;
377 // Effective register pressure limit.
378 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs())
379 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres;
380 // High pressure if block pressure requires more register freedom
381 // than live range has.
382 return block_pres >= lrg_pres;
383 }
384
385
386 //------------------------------prompt_use---------------------------------
387 // True if lidx is used before any real register is def'd in the block
388 bool PhaseChaitin::prompt_use( Block *b, uint lidx ) {
389 if( lrgs(lidx)._was_spilled2 ) return false;
390
391 // Scan block for 1st use.
392 for( uint i = 1; i <= b->end_idx(); i++ ) {
393 Node *n = b->_nodes[i];
394 // Ignore PHI use, these can be up or down
395 if( n->is_Phi() ) continue;
396 for( uint j = 1; j < n->req(); j++ )
397 if( Find_id(n->in(j)) == lidx )
398 return true; // Found 1st use!
399 if( n->out_RegMask().is_NotEmpty() ) return false;
400 }
401 return false;
402 }
403
404 //------------------------------Split--------------------------------------
405 //----------Split Routine----------
406 // ***** NEW SPLITTING HEURISTIC *****
407 // DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there.
408 // Else, no split unless there is a HRP block between a DEF and
409 // one of its uses, and then split at the HRP block.
410 //
411 // USES: If USE is in HRP, split at use to leave main LRG on stack.
412 // Else, hoist LRG back up to register only (ie - split is also DEF)
413 // We will compute a new maxlrg as we go
414 uint PhaseChaitin::Split( uint maxlrg ) {
415 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); )
416
417 uint bidx, pidx, slidx, insidx, inpidx, twoidx;
418 uint non_phi = 1, spill_cnt = 0;
419 Node **Reachblock;
420 Node *n1, *n2, *n3;
421 Node_List *defs,*phis;
422 bool *UPblock;
423 bool u1, u2, u3;
424 Block *b, *pred;
425 PhiNode *phi;
426 GrowableArray<uint> lidxs;
427
428 // Array of counters to count splits per live range
429 GrowableArray<uint> splits;
430
431 //----------Setup Code----------
432 // Create a convenient mapping from lrg numbers to reaches/leaves indices
433 uint *lrg2reach = NEW_RESOURCE_ARRAY( uint, _maxlrg );
434 // Keep track of DEFS & Phis for later passes
435 defs = new Node_List();
436 phis = new Node_List();
437 // Gather info on which LRG's are spilling, and build maps
438 for( bidx = 1; bidx < _maxlrg; bidx++ ) {
439 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
440 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color");
441 lrg2reach[bidx] = spill_cnt;
442 spill_cnt++;
443 lidxs.append(bidx);
444 #ifdef ASSERT
445 // Initialize the split counts to zero
446 splits.append(0);
447 #endif
448 #ifndef PRODUCT
449 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 )
450 tty->print_cr("Warning, 2nd spill of L%d",bidx);
451 #endif
452 }
453 }
454
455 // Create side arrays for propagating reaching defs info.
456 // Each block needs a node pointer for each spilling live range for the
457 // Def which is live into the block. Phi nodes handle multiple input
458 // Defs by querying the output of their predecessor blocks and resolving
459 // them to a single Def at the phi. The pointer is updated for each
460 // Def in the block, and then becomes the output for the block when
461 // processing of the block is complete. We also need to track whether
462 // a Def is UP or DOWN. UP means that it should get a register (ie -
463 // it is always in LRP regions), and DOWN means that it is probably
464 // on the stack (ie - it crosses HRP regions).
465 Node ***Reaches = NEW_RESOURCE_ARRAY( Node**, _cfg._num_blocks+1 );
466 bool **UP = NEW_RESOURCE_ARRAY( bool*, _cfg._num_blocks+1 );
467 Node **debug_defs = NEW_RESOURCE_ARRAY( Node*, spill_cnt );
468 VectorSet **UP_entry= NEW_RESOURCE_ARRAY( VectorSet*, spill_cnt );
469
470 // Initialize Reaches & UP
471 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) {
472 Reaches[bidx] = NEW_RESOURCE_ARRAY( Node*, spill_cnt );
473 UP[bidx] = NEW_RESOURCE_ARRAY( bool, spill_cnt );
474 Node **Reachblock = Reaches[bidx];
475 bool *UPblock = UP[bidx];
476 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
477 UPblock[slidx] = true; // Assume they start in registers
478 Reachblock[slidx] = NULL; // Assume that no def is present
479 }
480 }
481
482 // Initialize to array of empty vectorsets
483 for( slidx = 0; slidx < spill_cnt; slidx++ )
484 UP_entry[slidx] = new VectorSet(Thread::current()->resource_area());
485
486 //----------PASS 1----------
487 //----------Propagation & Node Insertion Code----------
488 // Walk the Blocks in RPO for DEF & USE info
489 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
490
491 if (C->check_node_count(spill_cnt, out_of_nodes)) {
492 return 0;
493 }
494
495 b = _cfg._blocks[bidx];
496 // Reaches & UP arrays for this block
497 Reachblock = Reaches[b->_pre_order];
498 UPblock = UP[b->_pre_order];
499 // Reset counter of start of non-Phi nodes in block
500 non_phi = 1;
501 //----------Block Entry Handling----------
502 // Check for need to insert a new phi
503 // Cycle through this block's predecessors, collecting Reaches
504 // info for each spilled LRG. If they are identical, no phi is
505 // needed. If they differ, check for a phi, and insert if missing,
506 // or update edges if present. Set current block's Reaches set to
507 // be either the phi's or the reaching def, as appropriate.
508 // If no Phi is needed, check if the LRG needs to spill on entry
509 // to the block due to HRP.
510 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
511 // Grab the live range number
512 uint lidx = lidxs.at(slidx);
513 // Do not bother splitting or putting in Phis for single-def
514 // rematerialized live ranges. This happens alot to constants
515 // with long live ranges.
516 if( lrgs(lidx).is_singledef() &&
517 lrgs(lidx)._def->rematerialize() ) {
518 // reset the Reaches & UP entries
519 Reachblock[slidx] = lrgs(lidx)._def;
520 UPblock[slidx] = true;
521 // Record following instruction in case 'n' rematerializes and
522 // kills flags
523 Block *pred1 = _cfg._bbs[b->pred(1)->_idx];
524 continue;
525 }
526
527 // Initialize needs_phi and needs_split
528 bool needs_phi = false;
529 bool needs_split = false;
530 bool has_phi = false;
531 // Walk the predecessor blocks to check inputs for that live range
532 // Grab predecessor block header
533 n1 = b->pred(1);
534 // Grab the appropriate reaching def info for inpidx
535 pred = _cfg._bbs[n1->_idx];
536 pidx = pred->_pre_order;
537 Node **Ltmp = Reaches[pidx];
538 bool *Utmp = UP[pidx];
539 n1 = Ltmp[slidx];
540 u1 = Utmp[slidx];
541 // Initialize node for saving type info
542 n3 = n1;
543 u3 = u1;
544
545 // Compare inputs to see if a Phi is needed
546 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) {
547 // Grab predecessor block headers
548 n2 = b->pred(inpidx);
549 // Grab the appropriate reaching def info for inpidx
550 pred = _cfg._bbs[n2->_idx];
551 pidx = pred->_pre_order;
552 Ltmp = Reaches[pidx];
553 Utmp = UP[pidx];
554 n2 = Ltmp[slidx];
555 u2 = Utmp[slidx];
556 // For each LRG, decide if a phi is necessary
557 if( n1 != n2 ) {
558 needs_phi = true;
559 }
560 // See if the phi has mismatched inputs, UP vs. DOWN
561 if( n1 && n2 && (u1 != u2) ) {
562 needs_split = true;
563 }
564 // Move n2/u2 to n1/u1 for next iteration
565 n1 = n2;
566 u1 = u2;
567 // Preserve a non-NULL predecessor for later type referencing
568 if( (n3 == NULL) && (n2 != NULL) ){
569 n3 = n2;
570 u3 = u2;
571 }
572 } // End for all potential Phi inputs
573
574 // check block for appropriate phinode & update edges
575 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
576 n1 = b->_nodes[insidx];
577 // bail if this is not a phi
578 phi = n1->is_Phi() ? n1->as_Phi() : NULL;
579 if( phi == NULL ) {
580 // Keep track of index of first non-PhiNode instruction in block
581 non_phi = insidx;
582 // break out of the for loop as we have handled all phi nodes
583 break;
584 }
585 // must be looking at a phi
586 if( Find_id(n1) == lidxs.at(slidx) ) {
587 // found the necessary phi
588 needs_phi = false;
589 has_phi = true;
590 // initialize the Reaches entry for this LRG
591 Reachblock[slidx] = phi;
592 break;
593 } // end if found correct phi
594 } // end for all phi's
595
596 // If a phi is needed or exist, check for it
597 if( needs_phi || has_phi ) {
598 // add new phinode if one not already found
599 if( needs_phi ) {
600 // create a new phi node and insert it into the block
601 // type is taken from left over pointer to a predecessor
602 assert(n3,"No non-NULL reaching DEF for a Phi");
603 phi = new (C, b->num_preds()) PhiNode(b->head(), n3->bottom_type());
604 // initialize the Reaches entry for this LRG
605 Reachblock[slidx] = phi;
606
607 // add node to block & node_to_block mapping
608 insert_proj( b, insidx++, phi, maxlrg++ );
609 non_phi++;
610 // Reset new phi's mapping to be the spilling live range
611 _names.map(phi->_idx, lidx);
612 assert(Find_id(phi) == lidx,"Bad update on Union-Find mapping");
613 } // end if not found correct phi
614 // Here you have either found or created the Phi, so record it
615 assert(phi != NULL,"Must have a Phi Node here");
616 phis->push(phi);
617 // PhiNodes should either force the LRG UP or DOWN depending
618 // on its inputs and the register pressure in the Phi's block.
619 UPblock[slidx] = true; // Assume new DEF is UP
620 // If entering a high-pressure area with no immediate use,
621 // assume Phi is DOWN
622 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) )
623 UPblock[slidx] = false;
624 // If we are not split up/down and all inputs are down, then we
625 // are down
626 if( !needs_split && !u3 )
627 UPblock[slidx] = false;
628 } // end if phi is needed
629
630 // Do not need a phi, so grab the reaching DEF
631 else {
632 // Grab predecessor block header
633 n1 = b->pred(1);
634 // Grab the appropriate reaching def info for k
635 pred = _cfg._bbs[n1->_idx];
636 pidx = pred->_pre_order;
637 Node **Ltmp = Reaches[pidx];
638 bool *Utmp = UP[pidx];
639 // reset the Reaches & UP entries
640 Reachblock[slidx] = Ltmp[slidx];
641 UPblock[slidx] = Utmp[slidx];
642 } // end else no Phi is needed
643 } // end for all spilling live ranges
644 // DEBUG
645 #ifndef PRODUCT
646 if(trace_spilling()) {
647 tty->print("/`\nBlock %d: ", b->_pre_order);
648 tty->print("Reaching Definitions after Phi handling\n");
649 for( uint x = 0; x < spill_cnt; x++ ) {
650 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]);
651 if( Reachblock[x] )
652 Reachblock[x]->dump();
653 else
654 tty->print("Undefined\n");
655 }
656 }
657 #endif
658
659 //----------Non-Phi Node Splitting----------
660 // Since phi-nodes have now been handled, the Reachblock array for this
661 // block is initialized with the correct starting value for the defs which
662 // reach non-phi instructions in this block. Thus, process non-phi
663 // instructions normally, inserting SpillCopy nodes for all spill
664 // locations.
665
666 // Memoize any DOWN reaching definitions for use as DEBUG info
667 for( insidx = 0; insidx < spill_cnt; insidx++ ) {
668 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx];
669 if( UPblock[insidx] ) // Memorize UP decision at block start
670 UP_entry[insidx]->set( b->_pre_order );
671 }
672
673 //----------Walk Instructions in the Block and Split----------
674 // For all non-phi instructions in the block
675 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) {
676 Node *n = b->_nodes[insidx];
677 // Find the defining Node's live range index
678 uint defidx = Find_id(n);
679 uint cnt = n->req();
680
681 if( n->is_Phi() ) {
682 // Skip phi nodes after removing dead copies.
683 if( defidx < _maxlrg ) {
684 // Check for useless Phis. These appear if we spill, then
685 // coalesce away copies. Dont touch Phis in spilling live
686 // ranges; they are busy getting modifed in this pass.
687 if( lrgs(defidx).reg() < LRG::SPILL_REG ) {
688 uint i;
689 Node *u = NULL;
690 // Look for the Phi merging 2 unique inputs
691 for( i = 1; i < cnt; i++ ) {
692 // Ignore repeats and self
693 if( n->in(i) != u && n->in(i) != n ) {
694 // Found a unique input
695 if( u != NULL ) // If it's the 2nd, bail out
696 break;
697 u = n->in(i); // Else record it
698 }
699 }
700 assert( u, "at least 1 valid input expected" );
701 if( i >= cnt ) { // Found one unique input
702 assert(Find_id(n) == Find_id(u), "should be the same lrg");
703 n->replace_by(u); // Then replace with unique input
704 n->disconnect_inputs(NULL);
705 b->_nodes.remove(insidx);
706 insidx--;
707 b->_ihrp_index--;
708 b->_fhrp_index--;
709 }
710 }
711 }
712 continue;
713 }
714 assert( insidx > b->_ihrp_index ||
715 (b->_reg_pressure < (uint)INTPRESSURE) ||
716 b->_ihrp_index > 4000000 ||
717 b->_ihrp_index >= b->end_idx() ||
718 !b->_nodes[b->_ihrp_index]->is_Proj(), "" );
719 assert( insidx > b->_fhrp_index ||
720 (b->_freg_pressure < (uint)FLOATPRESSURE) ||
721 b->_fhrp_index > 4000000 ||
722 b->_fhrp_index >= b->end_idx() ||
723 !b->_nodes[b->_fhrp_index]->is_Proj(), "" );
724
725 // ********** Handle Crossing HRP Boundry **********
726 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) {
727 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
728 // Check for need to split at HRP boundry - split if UP
729 n1 = Reachblock[slidx];
730 // bail out if no reaching DEF
731 if( n1 == NULL ) continue;
732 // bail out if live range is 'isolated' around inner loop
733 uint lidx = lidxs.at(slidx);
734 // If live range is currently UP
735 if( UPblock[slidx] ) {
736 // set location to insert spills at
737 // SPLIT DOWN HERE - NO CISC SPILL
738 if( is_high_pressure( b, &lrgs(lidx), insidx ) &&
739 !n1->rematerialize() ) {
740 // If there is already a valid stack definition available, use it
741 if( debug_defs[slidx] != NULL ) {
742 Reachblock[slidx] = debug_defs[slidx];
743 }
744 else {
745 // Insert point is just past last use or def in the block
746 int insert_point = insidx-1;
747 while( insert_point > 0 ) {
748 Node *n = b->_nodes[insert_point];
749 // Hit top of block? Quit going backwards
750 if( n->is_Phi() ) break;
751 // Found a def? Better split after it.
752 if( n2lidx(n) == lidx ) break;
753 // Look for a use
754 uint i;
755 for( i = 1; i < n->req(); i++ )
756 if( n2lidx(n->in(i)) == lidx )
757 break;
758 // Found a use? Better split after it.
759 if( i < n->req() ) break;
760 insert_point--;
761 }
762 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx);
763 // If it wasn't split bail
764 if (!maxlrg) {
765 return 0;
766 }
767 insidx++;
768 }
769 // This is a new DEF, so update UP
770 UPblock[slidx] = false;
771 #ifndef PRODUCT
772 // DEBUG
773 if( trace_spilling() ) {
774 tty->print("\nNew Split DOWN DEF of Spill Idx ");
775 tty->print("%d, UP %d:\n",slidx,false);
776 n1->dump();
777 }
778 #endif
779 }
780 } // end if LRG is UP
781 } // end for all spilling live ranges
782 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" );
783 } // end if crossing HRP Boundry
784
785 // If the LRG index is oob, then this is a new spillcopy, skip it.
786 if( defidx >= _maxlrg ) {
787 continue;
788 }
789 LRG &deflrg = lrgs(defidx);
790 uint copyidx = n->is_Copy();
791 // Remove coalesced copy from CFG
792 if( copyidx && defidx == n2lidx(n->in(copyidx)) ) {
793 n->replace_by( n->in(copyidx) );
794 n->set_req( copyidx, NULL );
795 b->_nodes.remove(insidx--);
796 b->_ihrp_index--; // Adjust the point where we go hi-pressure
797 b->_fhrp_index--;
798 continue;
799 }
800
801 #define DERIVED 0
802
803 // ********** Handle USES **********
804 bool nullcheck = false;
805 // Implicit null checks never use the spilled value
806 if( n->is_MachNullCheck() )
807 nullcheck = true;
808 if( !nullcheck ) {
809 // Search all inputs for a Spill-USE
810 JVMState* jvms = n->jvms();
811 uint oopoff = jvms ? jvms->oopoff() : cnt;
812 uint old_last = cnt - 1;
813 for( inpidx = 1; inpidx < cnt; inpidx++ ) {
814 // Derived/base pairs may be added to our inputs during this loop.
815 // If inpidx > old_last, then one of these new inputs is being
816 // handled. Skip the derived part of the pair, but process
817 // the base like any other input.
818 if( inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED ) {
819 continue; // skip derived_debug added below
820 }
821 // Get lidx of input
822 uint useidx = Find_id(n->in(inpidx));
823 // Not a brand-new split, and it is a spill use
824 if( useidx < _maxlrg && lrgs(useidx).reg() >= LRG::SPILL_REG ) {
825 // Check for valid reaching DEF
826 slidx = lrg2reach[useidx];
827 Node *def = Reachblock[slidx];
828 assert( def != NULL, "Using Undefined Value in Split()\n");
829
830 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp
831 // monitor references do not care where they live, so just hook
832 if ( jvms && jvms->is_monitor_use(inpidx) ) {
833 // The effect of this clone is to drop the node out of the block,
834 // so that the allocator does not see it anymore, and therefore
835 // does not attempt to assign it a register.
836 def = def->clone();
837 _names.extend(def->_idx,0);
838 _cfg._bbs.map(def->_idx,b);
839 n->set_req(inpidx, def);
840 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) {
841 return 0;
842 }
843 continue;
844 }
845
846 // Rematerializable? Then clone def at use site instead
847 // of store/load
848 if( def->rematerialize() ) {
849 int old_size = b->_nodes.size();
850 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true );
851 if( !def ) return 0; // Bail out
852 insidx += b->_nodes.size()-old_size;
853 }
854
855 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL;
856 // Base pointers and oopmap references do not care where they live.
857 if ((inpidx >= oopoff) ||
858 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) {
859 if (def->rematerialize() && lrgs(useidx)._was_spilled2) {
860 // This def has been rematerialized a couple of times without
861 // progress. It doesn't care if it lives UP or DOWN, so
862 // spill it down now.
863 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx);
864 // If it wasn't split bail
865 if (!maxlrg) {
866 return 0;
867 }
868 insidx++; // Reset iterator to skip USE side split
869 } else {
870 // Just hook the def edge
871 n->set_req(inpidx, def);
872 }
873
874 if (inpidx >= oopoff) {
875 // After oopoff, we have derived/base pairs. We must mention all
876 // derived pointers here as derived/base pairs for GC. If the
877 // derived value is spilling and we have a copy both in Reachblock
878 // (called here 'def') and debug_defs[slidx] we need to mention
879 // both in derived/base pairs or kill one.
880 Node *derived_debug = debug_defs[slidx];
881 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base?
882 mach && mach->ideal_Opcode() != Op_Halt &&
883 derived_debug != NULL &&
884 derived_debug != def ) { // Actual 2nd value appears
885 // We have already set 'def' as a derived value.
886 // Also set debug_defs[slidx] as a derived value.
887 uint k;
888 for( k = oopoff; k < cnt; k += 2 )
889 if( n->in(k) == derived_debug )
890 break; // Found an instance of debug derived
891 if( k == cnt ) {// No instance of debug_defs[slidx]
892 // Add a derived/base pair to cover the debug info.
893 // We have to process the added base later since it is not
894 // handled yet at this point but skip derived part.
895 assert(((n->req() - oopoff) & 1) == DERIVED,
896 "must match skip condition above");
897 n->add_req( derived_debug ); // this will be skipped above
898 n->add_req( n->in(inpidx+1) ); // this will be processed
899 // Increment cnt to handle added input edges on
900 // subsequent iterations.
901 cnt += 2;
902 }
903 }
904 }
905 continue;
906 }
907 // Special logic for DEBUG info
908 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) {
909 uint debug_start = jvms->debug_start();
910 // If this is debug info use & there is a reaching DOWN def
911 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) {
912 assert(inpidx < oopoff, "handle only debug info here");
913 // Just hook it in & move on
914 n->set_req(inpidx, debug_defs[slidx]);
915 // (Note that this can make two sides of a split live at the
916 // same time: The debug def on stack, and another def in a
917 // register. The GC needs to know about both of them, but any
918 // derived pointers after oopoff will refer to only one of the
919 // two defs and the GC would therefore miss the other. Thus
920 // this hack is only allowed for debug info which is Java state
921 // and therefore never a derived pointer.)
922 continue;
923 }
924 }
925 // Grab register mask info
926 const RegMask &dmask = def->out_RegMask();
927 const RegMask &umask = n->in_RegMask(inpidx);
928
929 assert(inpidx < oopoff, "cannot use-split oop map info");
930
931 bool dup = UPblock[slidx];
932 bool uup = umask.is_UP();
933
934 // Need special logic to handle bound USES. Insert a split at this
935 // bound use if we can't rematerialize the def, or if we need the
936 // split to form a misaligned pair.
937 if( !umask.is_AllStack() &&
938 (int)umask.Size() <= lrgs(useidx).num_regs() &&
939 (!def->rematerialize() ||
940 umask.is_misaligned_Pair())) {
941 // These need a Split regardless of overlap or pressure
942 // SPLIT - NO DEF - NO CISC SPILL
943 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx);
944 // If it wasn't split bail
945 if (!maxlrg) {
946 return 0;
947 }
948 insidx++; // Reset iterator to skip USE side split
949 continue;
950 }
951 // Here is the logic chart which describes USE Splitting:
952 // 0 = false or DOWN, 1 = true or UP
953 //
954 // Overlap | DEF | USE | Action
955 //-------------------------------------------------------
956 // 0 | 0 | 0 | Copy - mem -> mem
957 // 0 | 0 | 1 | Split-UP - Check HRP
958 // 0 | 1 | 0 | Split-DOWN - Debug Info?
959 // 0 | 1 | 1 | Copy - reg -> reg
960 // 1 | 0 | 0 | Reset Input Edge (no Split)
961 // 1 | 0 | 1 | Split-UP - Check HRP
962 // 1 | 1 | 0 | Split-DOWN - Debug Info?
963 // 1 | 1 | 1 | Reset Input Edge (no Split)
964 //
965 // So, if (dup == uup), then overlap test determines action,
966 // with true being no split, and false being copy. Else,
967 // if DEF is DOWN, Split-UP, and check HRP to decide on
968 // resetting DEF. Finally if DEF is UP, Split-DOWN, with
969 // special handling for Debug Info.
970 if( dup == uup ) {
971 if( dmask.overlap(umask) ) {
972 // Both are either up or down, and there is overlap, No Split
973 n->set_req(inpidx, def);
974 }
975 else { // Both are either up or down, and there is no overlap
976 if( dup ) { // If UP, reg->reg copy
977 // COPY ACROSS HERE - NO DEF - NO CISC SPILL
978 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
979 // If it wasn't split bail
980 if (!maxlrg) {
981 return 0;
982 }
983 insidx++; // Reset iterator to skip USE side split
984 }
985 else { // DOWN, mem->mem copy
986 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL
987 // First Split-UP to move value into Register
988 uint def_ideal = def->ideal_reg();
989 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal];
990 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm);
991 insert_proj( b, insidx, spill, maxlrg );
992 // Then Split-DOWN as if previous Split was DEF
993 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx);
994 // If it wasn't split bail
995 if (!maxlrg) {
996 return 0;
997 }
998 insidx += 2; // Reset iterator to skip USE side splits
999 }
1000 } // End else no overlap
1001 } // End if dup == uup
1002 // dup != uup, so check dup for direction of Split
1003 else {
1004 if( dup ) { // If UP, Split-DOWN and check Debug Info
1005 // If this node is already a SpillCopy, just patch the edge
1006 // except the case of spilling to stack.
1007 if( n->is_SpillCopy() ) {
1008 RegMask tmp_rm(umask);
1009 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask);
1010 if( dmask.overlap(tmp_rm) ) {
1011 if( def != n->in(inpidx) ) {
1012 n->set_req(inpidx, def);
1013 }
1014 continue;
1015 }
1016 }
1017 // COPY DOWN HERE - NO DEF - NO CISC SPILL
1018 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx);
1019 // If it wasn't split bail
1020 if (!maxlrg) {
1021 return 0;
1022 }
1023 insidx++; // Reset iterator to skip USE side split
1024 // Check for debug-info split. Capture it for later
1025 // debug splits of the same value
1026 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff)
1027 debug_defs[slidx] = n->in(inpidx);
1028
1029 }
1030 else { // DOWN, Split-UP and check register pressure
1031 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) {
1032 // COPY UP HERE - NO DEF - CISC SPILL
1033 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx);
1034 // If it wasn't split bail
1035 if (!maxlrg) {
1036 return 0;
1037 }
1038 insidx++; // Reset iterator to skip USE side split
1039 } else { // LRP
1040 // COPY UP HERE - WITH DEF - NO CISC SPILL
1041 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx);
1042 // If it wasn't split bail
1043 if (!maxlrg) {
1044 return 0;
1045 }
1046 // Flag this lift-up in a low-pressure block as
1047 // already-spilled, so if it spills again it will
1048 // spill hard (instead of not spilling hard and
1049 // coalescing away).
1050 set_was_spilled(n->in(inpidx));
1051 // Since this is a new DEF, update Reachblock & UP
1052 Reachblock[slidx] = n->in(inpidx);
1053 UPblock[slidx] = true;
1054 insidx++; // Reset iterator to skip USE side split
1055 }
1056 } // End else DOWN
1057 } // End dup != uup
1058 } // End if Spill USE
1059 } // End For All Inputs
1060 } // End If not nullcheck
1061
1062 // ********** Handle DEFS **********
1063 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or
1064 // just reset the Reaches info in LRP regions. DEFS must always update
1065 // UP info.
1066 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled?
1067 uint slidx = lrg2reach[defidx];
1068 // Add to defs list for later assignment of new live range number
1069 defs->push(n);
1070 // Set a flag on the Node indicating it has already spilled.
1071 // Only do it for capacity spills not conflict spills.
1072 if( !deflrg._direct_conflict )
1073 set_was_spilled(n);
1074 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list");
1075 // Grab UP info for DEF
1076 const RegMask &dmask = n->out_RegMask();
1077 bool defup = dmask.is_UP();
1078 // Only split at Def if this is a HRP block or bound (and spilled once)
1079 if( !n->rematerialize() &&
1080 (((dmask.is_bound1() || dmask.is_bound2() || dmask.is_misaligned_Pair()) &&
1081 (deflrg._direct_conflict || deflrg._must_spill)) ||
1082 // Check for LRG being up in a register and we are inside a high
1083 // pressure area. Spill it down immediately.
1084 (defup && is_high_pressure(b,&deflrg,insidx))) ) {
1085 assert( !n->rematerialize(), "" );
1086 assert( !n->is_SpillCopy(), "" );
1087 // Do a split at the def site.
1088 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx );
1089 // If it wasn't split bail
1090 if (!maxlrg) {
1091 return 0;
1092 }
1093 // Split DEF's Down
1094 UPblock[slidx] = 0;
1095 #ifndef PRODUCT
1096 // DEBUG
1097 if( trace_spilling() ) {
1098 tty->print("\nNew Split DOWN DEF of Spill Idx ");
1099 tty->print("%d, UP %d:\n",slidx,false);
1100 n->dump();
1101 }
1102 #endif
1103 }
1104 else { // Neither bound nor HRP, must be LRP
1105 // otherwise, just record the def
1106 Reachblock[slidx] = n;
1107 // UP should come from the outRegmask() of the DEF
1108 UPblock[slidx] = defup;
1109 // Update debug list of reaching down definitions, kill if DEF is UP
1110 debug_defs[slidx] = defup ? NULL : n;
1111 #ifndef PRODUCT
1112 // DEBUG
1113 if( trace_spilling() ) {
1114 tty->print("\nNew DEF of Spill Idx ");
1115 tty->print("%d, UP %d:\n",slidx,defup);
1116 n->dump();
1117 }
1118 #endif
1119 } // End else LRP
1120 } // End if spill def
1121
1122 // ********** Split Left Over Mem-Mem Moves **********
1123 // Check for mem-mem copies and split them now. Do not do this
1124 // to copies about to be spilled; they will be Split shortly.
1125 if( copyidx ) {
1126 Node *use = n->in(copyidx);
1127 uint useidx = Find_id(use);
1128 if( useidx < _maxlrg && // This is not a new split
1129 OptoReg::is_stack(deflrg.reg()) &&
1130 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack
1131 LRG &uselrg = lrgs(useidx);
1132 if( OptoReg::is_stack(uselrg.reg()) &&
1133 uselrg.reg() < LRG::SPILL_REG && // USE is from stack
1134 deflrg.reg() != uselrg.reg() ) { // Not trivially removed
1135 uint def_ideal_reg = Matcher::base2reg[n->bottom_type()->base()];
1136 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg];
1137 const RegMask &use_rm = n->in_RegMask(copyidx);
1138 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL
1139 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes
1140 return 0;
1141 }
1142 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm);
1143 n->set_req(copyidx,spill);
1144 n->as_MachSpillCopy()->set_in_RegMask(def_rm);
1145 // Put the spill just before the copy
1146 insert_proj( b, insidx++, spill, maxlrg++ );
1147 }
1148 }
1149 }
1150 }
1151 } // End For All Instructions in Block - Non-PHI Pass
1152
1153 // Check if each LRG is live out of this block so as not to propagate
1154 // beyond the last use of a LRG.
1155 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1156 uint defidx = lidxs.at(slidx);
1157 IndexSet *liveout = _live->live(b);
1158 if( !liveout->member(defidx) ) {
1159 #ifdef ASSERT
1160 // The index defidx is not live. Check the liveout array to ensure that
1161 // it contains no members which compress to defidx. Finding such an
1162 // instance may be a case to add liveout adjustment in compress_uf_map().
1163 // See 5063219.
1164 uint member;
1165 IndexSetIterator isi(liveout);
1166 while ((member = isi.next()) != 0) {
1167 assert(defidx != Find_const(member), "Live out member has not been compressed");
1168 }
1169 #endif
1170 Reachblock[slidx] = NULL;
1171 } else {
1172 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value");
1173 }
1174 }
1175 #ifndef PRODUCT
1176 if( trace_spilling() )
1177 b->dump();
1178 #endif
1179 } // End For All Blocks
1180
1181 //----------PASS 2----------
1182 // Reset all DEF live range numbers here
1183 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1184 // Grab the def
1185 n1 = defs->at(insidx);
1186 // Set new lidx for DEF
1187 new_lrg(n1, maxlrg++);
1188 }
1189 //----------Phi Node Splitting----------
1190 // Clean up a phi here, and assign a new live range number
1191 // Cycle through this block's predecessors, collecting Reaches
1192 // info for each spilled LRG and update edges.
1193 // Walk the phis list to patch inputs, split phis, and name phis
1194 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1195 Node *phi = phis->at(insidx);
1196 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1197 Block *b = _cfg._bbs[phi->_idx];
1198 // Grab the live range number
1199 uint lidx = Find_id(phi);
1200 uint slidx = lrg2reach[lidx];
1201 // Update node to lidx map
1202 new_lrg(phi, maxlrg++);
1203 // Get PASS1's up/down decision for the block.
1204 int phi_up = !!UP_entry[slidx]->test(b->_pre_order);
1205
1206 // Force down if double-spilling live range
1207 if( lrgs(lidx)._was_spilled1 )
1208 phi_up = false;
1209
1210 // When splitting a Phi we an split it normal or "inverted".
1211 // An inverted split makes the splits target the Phi's UP/DOWN
1212 // sense inverted; then the Phi is followed by a final def-side
1213 // split to invert back. It changes which blocks the spill code
1214 // goes in.
1215
1216 // Walk the predecessor blocks and assign the reaching def to the Phi.
1217 // Split Phi nodes by placing USE side splits wherever the reaching
1218 // DEF has the wrong UP/DOWN value.
1219 for( uint i = 1; i < b->num_preds(); i++ ) {
1220 // Get predecessor block pre-order number
1221 Block *pred = _cfg._bbs[b->pred(i)->_idx];
1222 pidx = pred->_pre_order;
1223 // Grab reaching def
1224 Node *def = Reaches[pidx][slidx];
1225 assert( def, "must have reaching def" );
1226 // If input up/down sense and reg-pressure DISagree
1227 if( def->rematerialize() ) {
1228 def = split_Rematerialize( def, pred, pred->end_idx(), maxlrg, splits, slidx, lrg2reach, Reachblock, false );
1229 if( !def ) return 0; // Bail out
1230 }
1231 // Update the Phi's input edge array
1232 phi->set_req(i,def);
1233 // Grab the UP/DOWN sense for the input
1234 u1 = UP[pidx][slidx];
1235 if( u1 != (phi_up != 0)) {
1236 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx);
1237 // If it wasn't split bail
1238 if (!maxlrg) {
1239 return 0;
1240 }
1241 }
1242 } // End for all inputs to the Phi
1243 } // End for all Phi Nodes
1244 // Update _maxlrg to save Union asserts
1245 _maxlrg = maxlrg;
1246
1247
1248 //----------PASS 3----------
1249 // Pass over all Phi's to union the live ranges
1250 for( insidx = 0; insidx < phis->size(); insidx++ ) {
1251 Node *phi = phis->at(insidx);
1252 assert(phi->is_Phi(),"This list must only contain Phi Nodes");
1253 // Walk all inputs to Phi and Union input live range with Phi live range
1254 for( uint i = 1; i < phi->req(); i++ ) {
1255 // Grab the input node
1256 Node *n = phi->in(i);
1257 assert( n, "" );
1258 uint lidx = Find(n);
1259 uint pidx = Find(phi);
1260 if( lidx < pidx )
1261 Union(n, phi);
1262 else if( lidx > pidx )
1263 Union(phi, n);
1264 } // End for all inputs to the Phi Node
1265 } // End for all Phi Nodes
1266 // Now union all two address instructions
1267 for( insidx = 0; insidx < defs->size(); insidx++ ) {
1268 // Grab the def
1269 n1 = defs->at(insidx);
1270 // Set new lidx for DEF & handle 2-addr instructions
1271 if( n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0) ) {
1272 assert( Find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index");
1273 // Union the input and output live ranges
1274 uint lr1 = Find(n1);
1275 uint lr2 = Find(n1->in(twoidx));
1276 if( lr1 < lr2 )
1277 Union(n1, n1->in(twoidx));
1278 else if( lr1 > lr2 )
1279 Union(n1->in(twoidx), n1);
1280 } // End if two address
1281 } // End for all defs
1282 // DEBUG
1283 #ifdef ASSERT
1284 // Validate all live range index assignments
1285 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) {
1286 b = _cfg._blocks[bidx];
1287 for( insidx = 0; insidx <= b->end_idx(); insidx++ ) {
1288 Node *n = b->_nodes[insidx];
1289 uint defidx = Find(n);
1290 assert(defidx < _maxlrg,"Bad live range index in Split");
1291 assert(defidx < maxlrg,"Bad live range index in Split");
1292 }
1293 }
1294 // Issue a warning if splitting made no progress
1295 int noprogress = 0;
1296 for( slidx = 0; slidx < spill_cnt; slidx++ ) {
1297 if( PrintOpto && WizardMode && splits.at(slidx) == 0 ) {
1298 tty->print_cr("Failed to split live range %d", lidxs.at(slidx));
1299 //BREAKPOINT;
1300 }
1301 else {
1302 noprogress++;
1303 }
1304 }
1305 if(!noprogress) {
1306 tty->print_cr("Failed to make progress in Split");
1307 //BREAKPOINT;
1308 }
1309 #endif
1310 // Return updated count of live ranges
1311 return maxlrg;
1312 }