65 _allocation_started(false),
66 _states_arena(Chunk::medium_size),
67 _visited(&_states_arena),
68 _shared(&_states_arena),
69 _dontcare(&_states_arena) {
70 C->set_matcher(this);
71
72 idealreg2spillmask[Op_RegI] = NULL;
73 idealreg2spillmask[Op_RegN] = NULL;
74 idealreg2spillmask[Op_RegL] = NULL;
75 idealreg2spillmask[Op_RegF] = NULL;
76 idealreg2spillmask[Op_RegD] = NULL;
77 idealreg2spillmask[Op_RegP] = NULL;
78
79 idealreg2debugmask[Op_RegI] = NULL;
80 idealreg2debugmask[Op_RegN] = NULL;
81 idealreg2debugmask[Op_RegL] = NULL;
82 idealreg2debugmask[Op_RegF] = NULL;
83 idealreg2debugmask[Op_RegD] = NULL;
84 idealreg2debugmask[Op_RegP] = NULL;
85 }
86
87 //------------------------------warp_incoming_stk_arg------------------------
88 // This warps a VMReg into an OptoReg::Name
89 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
90 OptoReg::Name warped;
91 if( reg->is_stack() ) { // Stack slot argument?
92 warped = OptoReg::add(_old_SP, reg->reg2stack() );
93 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
94 if( warped >= _in_arg_limit )
95 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
96 if (!RegMask::can_represent(warped)) {
97 // the compiler cannot represent this method's calling sequence
98 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
99 return OptoReg::Bad;
100 }
101 return warped;
102 }
103 return OptoReg::as_OptoReg(reg);
104 }
1136 return msfpt;
1137 }
1138
1139 //---------------------------match_tree----------------------------------------
1140 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1141 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1142 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1143 // a Load's result RegMask for memoization in idealreg2regmask[]
1144 MachNode *Matcher::match_tree( const Node *n ) {
1145 assert( n->Opcode() != Op_Phi, "cannot match" );
1146 assert( !n->is_block_start(), "cannot match" );
1147 // Set the mark for all locally allocated State objects.
1148 // When this call returns, the _states_arena arena will be reset
1149 // freeing all State objects.
1150 ResourceMark rm( &_states_arena );
1151
1152 LabelRootDepth = 0;
1153
1154 // StoreNodes require their Memory input to match any LoadNodes
1155 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1156
1157 // State object for root node of match tree
1158 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1159 State *s = new (&_states_arena) State;
1160 s->_kids[0] = NULL;
1161 s->_kids[1] = NULL;
1162 s->_leaf = (Node*)n;
1163 // Label the input tree, allocating labels from top-level arena
1164 Label_Root( n, s, n->in(0), mem );
1165 if (C->failing()) return NULL;
1166
1167 // The minimum cost match for the whole tree is found at the root State
1168 uint mincost = max_juint;
1169 uint cost = max_juint;
1170 uint i;
1171 for( i = 0; i < NUM_OPERANDS; i++ ) {
1172 if( s->valid(i) && // valid entry and
1173 s->_cost[i] < cost && // low cost and
1174 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1175 cost = s->_cost[mincost=i];
1176 }
1188 _old2new_map.map(n->_idx, m);
1189 #endif
1190
1191 // Add any Matcher-ignored edges
1192 uint cnt = n->req();
1193 uint start = 1;
1194 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1195 if( n->is_AddP() ) {
1196 assert( mem == (Node*)1, "" );
1197 start = AddPNode::Base+1;
1198 }
1199 for( i = start; i < cnt; i++ ) {
1200 if( !n->match_edge(i) ) {
1201 if( i < m->req() )
1202 m->ins_req( i, n->in(i) );
1203 else
1204 m->add_req( n->in(i) );
1205 }
1206 }
1207
1208 return m;
1209 }
1210
1211
1212 //------------------------------match_into_reg---------------------------------
1213 // Choose to either match this Node in a register or part of the current
1214 // match tree. Return true for requiring a register and false for matching
1215 // as part of the current match tree.
1216 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1217
1218 const Type *t = m->bottom_type();
1219
1220 if( t->singleton() ) {
1221 // Never force constants into registers. Allow them to match as
1222 // constants or registers. Copies of the same value will share
1223 // the same register. See find_shared_node.
1224 return false;
1225 } else { // Not a constant
1226 // Stop recursion if they have different Controls.
1227 // Slot 0 of constants is not really a Control.
1428 }
1429
1430 // Build the object to represent this state & prepare for recursive calls
1431 MachNode *mach = s->MachNodeGenerator( rule, C );
1432 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1433 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1434 Node *leaf = s->_leaf;
1435 // Check for instruction or instruction chain rule
1436 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1437 // Instruction
1438 mach->add_req( leaf->in(0) ); // Set initial control
1439 // Reduce interior of complex instruction
1440 ReduceInst_Interior( s, rule, mem, mach, 1 );
1441 } else {
1442 // Instruction chain rules are data-dependent on their inputs
1443 mach->add_req(0); // Set initial control to none
1444 ReduceInst_Chain_Rule( s, rule, mem, mach );
1445 }
1446
1447 // If a Memory was used, insert a Memory edge
1448 if( mem != (Node*)1 )
1449 mach->ins_req(MemNode::Memory,mem);
1450
1451 // If the _leaf is an AddP, insert the base edge
1452 if( leaf->is_AddP() )
1453 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1454
1455 uint num_proj = _proj_list.size();
1456
1457 // Perform any 1-to-many expansions required
1458 MachNode *ex = mach->Expand(s,_proj_list);
1459 if( ex != mach ) {
1460 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1461 if( ex->in(1)->is_Con() )
1462 ex->in(1)->set_req(0, C->root());
1463 // Remove old node from the graph
1464 for( uint i=0; i<mach->req(); i++ ) {
1465 mach->set_req(i,NULL);
1466 }
1467 }
1468
1469 // PhaseChaitin::fixup_spills will sometimes generate spill code
1493 int opnd_class_instance = s->_rule[op];
1494 // Choose between operand class or not.
1495 // This is what I will recieve.
1496 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1497 // New rule for child. Chase operand classes to get the actual rule.
1498 int newrule = s->_rule[catch_op];
1499
1500 if( newrule < NUM_OPERANDS ) {
1501 // Chain from operand or operand class, may be output of shared node
1502 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1503 "Bad AD file: Instruction chain rule must chain from operand");
1504 // Insert operand into array of operands for this instruction
1505 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1506
1507 ReduceOper( s, newrule, mem, mach );
1508 } else {
1509 // Chain from the result of an instruction
1510 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1511 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1512 Node *mem1 = (Node*)1;
1513 mach->add_req( ReduceInst(s, newrule, mem1) );
1514 }
1515 return;
1516 }
1517
1518
1519 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1520 if( s->_leaf->is_Load() ) {
1521 Node *mem2 = s->_leaf->in(MemNode::Memory);
1522 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1523 mem = mem2;
1524 }
1525 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1526 if( mach->in(0) == NULL )
1527 mach->set_req(0, s->_leaf->in(0));
1528 }
1529
1530 // Now recursively walk the state tree & add operand list.
1531 for( uint i=0; i<2; i++ ) { // binary tree
1532 State *newstate = s->_kids[i];
1533 if( newstate == NULL ) break; // Might only have 1 child
1534 // 'op' is what I am expecting to receive
1535 int op;
1536 if( i == 0 ) {
1537 op = _leftOp[rule];
1538 } else {
1539 op = _rightOp[rule];
1540 }
1541 // Operand type to catch childs result
1542 // This is what my child will give me.
1546 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1547 // New rule for child. Chase operand classes to get the actual rule.
1548 int newrule = newstate->_rule[catch_op];
1549
1550 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1551 // Operand/operandClass
1552 // Insert operand into array of operands for this instruction
1553 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1554 ReduceOper( newstate, newrule, mem, mach );
1555
1556 } else { // Child is internal operand or new instruction
1557 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1558 // internal operand --> call ReduceInst_Interior
1559 // Interior of complex instruction. Do nothing but recurse.
1560 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1561 } else {
1562 // instruction --> call build operand( ) to catch result
1563 // --> ReduceInst( newrule )
1564 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1565 Node *mem1 = (Node*)1;
1566 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1567 }
1568 }
1569 assert( mach->_opnds[num_opnds-1], "" );
1570 }
1571 return num_opnds;
1572 }
1573
1574 // This routine walks the interior of possible complex operands.
1575 // At each point we check our children in the match tree:
1576 // (1) No children -
1577 // We are a leaf; add _leaf field as an input to the MachNode
1578 // (2) Child is an internal operand -
1579 // Skip over it ( do nothing )
1580 // (3) Child is an instruction -
1581 // Call ReduceInst recursively and
1582 // and instruction as an input to the MachNode
1583 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1584 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1585 State *kid = s->_kids[0];
1586 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1587
1588 // Leaf? And not subsumed?
1589 if( kid == NULL && !_swallowed[rule] ) {
1590 mach->add_req( s->_leaf ); // Add leaf pointer
1591 return; // Bail out
1592 }
1593
1594 if( s->_leaf->is_Load() ) {
1595 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1596 mem = s->_leaf->in(MemNode::Memory);
1597 }
1598 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1599 if( !mach->in(0) )
1600 mach->set_req(0,s->_leaf->in(0));
1601 else {
1602 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1603 }
1604 }
1605
1606 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1607 int newrule;
1608 if( i == 0 )
1609 newrule = kid->_rule[_leftOp[rule]];
1610 else
1611 newrule = kid->_rule[_rightOp[rule]];
1612
1613 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1614 // Internal operand; recurse but do nothing else
1615 ReduceOper( kid, newrule, mem, mach );
1616
1617 } else { // Child is a new instruction
1618 // Reduce the instruction, and add a direct pointer from this
1619 // machine instruction to the newly reduced one.
1620 Node *mem1 = (Node*)1;
1621 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1622 }
1623 }
1624 }
1625
1626
1627 // -------------------------------------------------------------------------
1628 // Java-Java calling convention
1629 // (what you use when Java calls Java)
1630
1631 //------------------------------find_receiver----------------------------------
1632 // For a given signature, return the OptoReg for parameter 0.
1633 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1634 VMRegPair regs;
1635 BasicType sig_bt = T_OBJECT;
1636 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1637 // Return argument 0 register. In the LP64 build pointers
1638 // take 2 registers, but the VM wants only the 'main' name.
1639 return OptoReg::as_OptoReg(regs.first());
1640 }
1641
|
65 _allocation_started(false),
66 _states_arena(Chunk::medium_size),
67 _visited(&_states_arena),
68 _shared(&_states_arena),
69 _dontcare(&_states_arena) {
70 C->set_matcher(this);
71
72 idealreg2spillmask[Op_RegI] = NULL;
73 idealreg2spillmask[Op_RegN] = NULL;
74 idealreg2spillmask[Op_RegL] = NULL;
75 idealreg2spillmask[Op_RegF] = NULL;
76 idealreg2spillmask[Op_RegD] = NULL;
77 idealreg2spillmask[Op_RegP] = NULL;
78
79 idealreg2debugmask[Op_RegI] = NULL;
80 idealreg2debugmask[Op_RegN] = NULL;
81 idealreg2debugmask[Op_RegL] = NULL;
82 idealreg2debugmask[Op_RegF] = NULL;
83 idealreg2debugmask[Op_RegD] = NULL;
84 idealreg2debugmask[Op_RegP] = NULL;
85 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
86 }
87
88 //------------------------------warp_incoming_stk_arg------------------------
89 // This warps a VMReg into an OptoReg::Name
90 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
91 OptoReg::Name warped;
92 if( reg->is_stack() ) { // Stack slot argument?
93 warped = OptoReg::add(_old_SP, reg->reg2stack() );
94 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
95 if( warped >= _in_arg_limit )
96 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
97 if (!RegMask::can_represent(warped)) {
98 // the compiler cannot represent this method's calling sequence
99 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
100 return OptoReg::Bad;
101 }
102 return warped;
103 }
104 return OptoReg::as_OptoReg(reg);
105 }
1137 return msfpt;
1138 }
1139
1140 //---------------------------match_tree----------------------------------------
1141 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1142 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1143 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1144 // a Load's result RegMask for memoization in idealreg2regmask[]
1145 MachNode *Matcher::match_tree( const Node *n ) {
1146 assert( n->Opcode() != Op_Phi, "cannot match" );
1147 assert( !n->is_block_start(), "cannot match" );
1148 // Set the mark for all locally allocated State objects.
1149 // When this call returns, the _states_arena arena will be reset
1150 // freeing all State objects.
1151 ResourceMark rm( &_states_arena );
1152
1153 LabelRootDepth = 0;
1154
1155 // StoreNodes require their Memory input to match any LoadNodes
1156 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1157 #ifdef ASSERT
1158 Node* save_mem_node = _mem_node;
1159 _mem_node = n->is_Store() ? (Node*)n : NULL;
1160 #endif
1161 // State object for root node of match tree
1162 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1163 State *s = new (&_states_arena) State;
1164 s->_kids[0] = NULL;
1165 s->_kids[1] = NULL;
1166 s->_leaf = (Node*)n;
1167 // Label the input tree, allocating labels from top-level arena
1168 Label_Root( n, s, n->in(0), mem );
1169 if (C->failing()) return NULL;
1170
1171 // The minimum cost match for the whole tree is found at the root State
1172 uint mincost = max_juint;
1173 uint cost = max_juint;
1174 uint i;
1175 for( i = 0; i < NUM_OPERANDS; i++ ) {
1176 if( s->valid(i) && // valid entry and
1177 s->_cost[i] < cost && // low cost and
1178 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1179 cost = s->_cost[mincost=i];
1180 }
1192 _old2new_map.map(n->_idx, m);
1193 #endif
1194
1195 // Add any Matcher-ignored edges
1196 uint cnt = n->req();
1197 uint start = 1;
1198 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1199 if( n->is_AddP() ) {
1200 assert( mem == (Node*)1, "" );
1201 start = AddPNode::Base+1;
1202 }
1203 for( i = start; i < cnt; i++ ) {
1204 if( !n->match_edge(i) ) {
1205 if( i < m->req() )
1206 m->ins_req( i, n->in(i) );
1207 else
1208 m->add_req( n->in(i) );
1209 }
1210 }
1211
1212 debug_only( _mem_node = save_mem_node; )
1213 return m;
1214 }
1215
1216
1217 //------------------------------match_into_reg---------------------------------
1218 // Choose to either match this Node in a register or part of the current
1219 // match tree. Return true for requiring a register and false for matching
1220 // as part of the current match tree.
1221 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1222
1223 const Type *t = m->bottom_type();
1224
1225 if( t->singleton() ) {
1226 // Never force constants into registers. Allow them to match as
1227 // constants or registers. Copies of the same value will share
1228 // the same register. See find_shared_node.
1229 return false;
1230 } else { // Not a constant
1231 // Stop recursion if they have different Controls.
1232 // Slot 0 of constants is not really a Control.
1433 }
1434
1435 // Build the object to represent this state & prepare for recursive calls
1436 MachNode *mach = s->MachNodeGenerator( rule, C );
1437 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1438 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1439 Node *leaf = s->_leaf;
1440 // Check for instruction or instruction chain rule
1441 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1442 // Instruction
1443 mach->add_req( leaf->in(0) ); // Set initial control
1444 // Reduce interior of complex instruction
1445 ReduceInst_Interior( s, rule, mem, mach, 1 );
1446 } else {
1447 // Instruction chain rules are data-dependent on their inputs
1448 mach->add_req(0); // Set initial control to none
1449 ReduceInst_Chain_Rule( s, rule, mem, mach );
1450 }
1451
1452 // If a Memory was used, insert a Memory edge
1453 if( mem != (Node*)1 ) {
1454 mach->ins_req(MemNode::Memory,mem);
1455 #ifdef ASSERT
1456 // Verify adr type after matching memory operation
1457 const MachOper* oper = mach->memory_operand();
1458 if (oper != NULL && oper != (MachOper*)-1 &&
1459 mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode
1460 // It has a unique memory operand. Find corresponding ideal mem node.
1461 Node* m = NULL;
1462 if (leaf->is_Mem()) {
1463 m = leaf;
1464 } else {
1465 m = _mem_node;
1466 assert(m != NULL && m->is_Mem(), "expecting memory node");
1467 }
1468 if (m->adr_type() != mach->adr_type()) {
1469 m->dump();
1470 tty->print_cr("mach:");
1471 mach->dump(1);
1472 }
1473 assert(m->adr_type() == mach->adr_type(), "matcher should not change adr type");
1474 }
1475 #endif
1476 }
1477
1478 // If the _leaf is an AddP, insert the base edge
1479 if( leaf->is_AddP() )
1480 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1481
1482 uint num_proj = _proj_list.size();
1483
1484 // Perform any 1-to-many expansions required
1485 MachNode *ex = mach->Expand(s,_proj_list);
1486 if( ex != mach ) {
1487 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1488 if( ex->in(1)->is_Con() )
1489 ex->in(1)->set_req(0, C->root());
1490 // Remove old node from the graph
1491 for( uint i=0; i<mach->req(); i++ ) {
1492 mach->set_req(i,NULL);
1493 }
1494 }
1495
1496 // PhaseChaitin::fixup_spills will sometimes generate spill code
1520 int opnd_class_instance = s->_rule[op];
1521 // Choose between operand class or not.
1522 // This is what I will recieve.
1523 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1524 // New rule for child. Chase operand classes to get the actual rule.
1525 int newrule = s->_rule[catch_op];
1526
1527 if( newrule < NUM_OPERANDS ) {
1528 // Chain from operand or operand class, may be output of shared node
1529 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1530 "Bad AD file: Instruction chain rule must chain from operand");
1531 // Insert operand into array of operands for this instruction
1532 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1533
1534 ReduceOper( s, newrule, mem, mach );
1535 } else {
1536 // Chain from the result of an instruction
1537 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1538 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1539 Node *mem1 = (Node*)1;
1540 debug_only(Node *save_mem_node = _mem_node;)
1541 mach->add_req( ReduceInst(s, newrule, mem1) );
1542 debug_only(_mem_node = save_mem_node;)
1543 }
1544 return;
1545 }
1546
1547
1548 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1549 if( s->_leaf->is_Load() ) {
1550 Node *mem2 = s->_leaf->in(MemNode::Memory);
1551 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1552 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1553 mem = mem2;
1554 }
1555 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1556 if( mach->in(0) == NULL )
1557 mach->set_req(0, s->_leaf->in(0));
1558 }
1559
1560 // Now recursively walk the state tree & add operand list.
1561 for( uint i=0; i<2; i++ ) { // binary tree
1562 State *newstate = s->_kids[i];
1563 if( newstate == NULL ) break; // Might only have 1 child
1564 // 'op' is what I am expecting to receive
1565 int op;
1566 if( i == 0 ) {
1567 op = _leftOp[rule];
1568 } else {
1569 op = _rightOp[rule];
1570 }
1571 // Operand type to catch childs result
1572 // This is what my child will give me.
1576 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1577 // New rule for child. Chase operand classes to get the actual rule.
1578 int newrule = newstate->_rule[catch_op];
1579
1580 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1581 // Operand/operandClass
1582 // Insert operand into array of operands for this instruction
1583 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1584 ReduceOper( newstate, newrule, mem, mach );
1585
1586 } else { // Child is internal operand or new instruction
1587 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1588 // internal operand --> call ReduceInst_Interior
1589 // Interior of complex instruction. Do nothing but recurse.
1590 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1591 } else {
1592 // instruction --> call build operand( ) to catch result
1593 // --> ReduceInst( newrule )
1594 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1595 Node *mem1 = (Node*)1;
1596 debug_only(Node *save_mem_node = _mem_node;)
1597 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1598 debug_only(_mem_node = save_mem_node;)
1599 }
1600 }
1601 assert( mach->_opnds[num_opnds-1], "" );
1602 }
1603 return num_opnds;
1604 }
1605
1606 // This routine walks the interior of possible complex operands.
1607 // At each point we check our children in the match tree:
1608 // (1) No children -
1609 // We are a leaf; add _leaf field as an input to the MachNode
1610 // (2) Child is an internal operand -
1611 // Skip over it ( do nothing )
1612 // (3) Child is an instruction -
1613 // Call ReduceInst recursively and
1614 // and instruction as an input to the MachNode
1615 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1616 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1617 State *kid = s->_kids[0];
1618 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1619
1620 // Leaf? And not subsumed?
1621 if( kid == NULL && !_swallowed[rule] ) {
1622 mach->add_req( s->_leaf ); // Add leaf pointer
1623 return; // Bail out
1624 }
1625
1626 if( s->_leaf->is_Load() ) {
1627 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1628 mem = s->_leaf->in(MemNode::Memory);
1629 debug_only(_mem_node = s->_leaf;)
1630 }
1631 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1632 if( !mach->in(0) )
1633 mach->set_req(0,s->_leaf->in(0));
1634 else {
1635 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1636 }
1637 }
1638
1639 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1640 int newrule;
1641 if( i == 0 )
1642 newrule = kid->_rule[_leftOp[rule]];
1643 else
1644 newrule = kid->_rule[_rightOp[rule]];
1645
1646 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1647 // Internal operand; recurse but do nothing else
1648 ReduceOper( kid, newrule, mem, mach );
1649
1650 } else { // Child is a new instruction
1651 // Reduce the instruction, and add a direct pointer from this
1652 // machine instruction to the newly reduced one.
1653 Node *mem1 = (Node*)1;
1654 debug_only(Node *save_mem_node = _mem_node;)
1655 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1656 debug_only(_mem_node = save_mem_node;)
1657 }
1658 }
1659 }
1660
1661
1662 // -------------------------------------------------------------------------
1663 // Java-Java calling convention
1664 // (what you use when Java calls Java)
1665
1666 //------------------------------find_receiver----------------------------------
1667 // For a given signature, return the OptoReg for parameter 0.
1668 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1669 VMRegPair regs;
1670 BasicType sig_bt = T_OBJECT;
1671 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1672 // Return argument 0 register. In the LP64 build pointers
1673 // take 2 registers, but the VM wants only the 'main' name.
1674 return OptoReg::as_OptoReg(regs.first());
1675 }
1676
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