src/share/vm/opto/matcher.cpp

*** 80,89 ****
--- 80,90 ----
    idealreg2debugmask[Op_RegN] = NULL;
    idealreg2debugmask[Op_RegL] = NULL;
    idealreg2debugmask[Op_RegF] = NULL;
    idealreg2debugmask[Op_RegD] = NULL;
    idealreg2debugmask[Op_RegP] = NULL;
+   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
  }
  
  //------------------------------warp_incoming_stk_arg------------------------
  // This warps a VMReg into an OptoReg::Name
  OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
*** 1151,1161 ****
  
    LabelRootDepth = 0;
  
    // StoreNodes require their Memory input to match any LoadNodes
    Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
! 
    // State object for root node of match tree
    // Allocate it on _states_arena - stack allocation can cause stack overflow.
    State *s = new (&_states_arena) State;
    s->_kids[0] = NULL;
    s->_kids[1] = NULL;
--- 1152,1165 ----
  
    LabelRootDepth = 0;
  
    // StoreNodes require their Memory input to match any LoadNodes
    Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
! #ifdef ASSERT
!   Node* save_mem_node = _mem_node;
!   _mem_node = n->is_Store() ? (Node*)n : NULL;
! #endif
    // State object for root node of match tree
    // Allocate it on _states_arena - stack allocation can cause stack overflow.
    State *s = new (&_states_arena) State;
    s->_kids[0] = NULL;
    s->_kids[1] = NULL;
*** 1203,1212 ****
--- 1207,1217 ----
        else
          m->add_req( n->in(i) );
      }
    }
  
+   debug_only( _mem_node = save_mem_node; )
    return m;
  }
  
  
  //------------------------------match_into_reg---------------------------------
*** 1443,1454 ****
      mach->add_req(0);             // Set initial control to none
      ReduceInst_Chain_Rule( s, rule, mem, mach );
    }
  
    // If a Memory was used, insert a Memory edge
!   if( mem != (Node*)1 )
      mach->ins_req(MemNode::Memory,mem);
  
    // If the _leaf is an AddP, insert the base edge
    if( leaf->is_AddP() )
      mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
  
--- 1448,1481 ----
      mach->add_req(0);             // Set initial control to none
      ReduceInst_Chain_Rule( s, rule, mem, mach );
    }
  
    // If a Memory was used, insert a Memory edge
!   if( mem != (Node*)1 ) {
      mach->ins_req(MemNode::Memory,mem);
+ #ifdef ASSERT
+     // Verify adr type after matching memory operation
+     const MachOper* oper = mach->memory_operand();
+     if (oper != NULL && oper != (MachOper*)-1 &&
+         mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode
+       // It has a unique memory operand.  Find corresponding ideal mem node.
+       Node* m = NULL;
+       if (leaf->is_Mem()) {
+         m = leaf;
+       } else {
+         m = _mem_node;
+         assert(m != NULL && m->is_Mem(), "expecting memory node");
+       }
+       if (m->adr_type() != mach->adr_type()) {
+         m->dump();
+         tty->print_cr("mach:");
+         mach->dump(1);
+       }
+       assert(m->adr_type() == mach->adr_type(), "matcher should not change adr type");
+     }
+ #endif
+   }
  
    // If the _leaf is an AddP, insert the base edge
    if( leaf->is_AddP() )
      mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
  
*** 1508,1527 ****
--- 1535,1557 ----
    } else {
      // Chain from the result of an instruction
      assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
      mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
      Node *mem1 = (Node*)1;
+     debug_only(Node *save_mem_node = _mem_node;)
      mach->add_req( ReduceInst(s, newrule, mem1) );
+     debug_only(_mem_node = save_mem_node;)
    }
    return;
  }
  
  
  uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
    if( s->_leaf->is_Load() ) {
      Node *mem2 = s->_leaf->in(MemNode::Memory);
      assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
+     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
      mem = mem2;
    }
    if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
      if( mach->in(0) == NULL )
        mach->set_req(0, s->_leaf->in(0));
*** 1561,1571 ****
--- 1591,1603 ----
        } else {
          // instruction --> call build operand(  ) to catch result
          //             --> ReduceInst( newrule )
          mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
          Node *mem1 = (Node*)1;
+         debug_only(Node *save_mem_node = _mem_node;)
          mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
+         debug_only(_mem_node = save_mem_node;)
        }
      }
      assert( mach->_opnds[num_opnds-1], "" );
    }
    return num_opnds;
*** 1592,1601 ****
--- 1624,1634 ----
    }
  
    if( s->_leaf->is_Load() ) {
      assert( mem == (Node*)1, "multiple Memories being matched at once?" );
      mem = s->_leaf->in(MemNode::Memory);
+     debug_only(_mem_node = s->_leaf;)
    }
    if( s->_leaf->in(0) && s->_leaf->req() > 1) {
      if( !mach->in(0) )
        mach->set_req(0,s->_leaf->in(0));
      else {
*** 1616,1626 ****
--- 1649,1661 ----
  
      } else {                    // Child is a new instruction
        // Reduce the instruction, and add a direct pointer from this
        // machine instruction to the newly reduced one.
        Node *mem1 = (Node*)1;
+       debug_only(Node *save_mem_node = _mem_node;)
        mach->add_req( ReduceInst( kid, newrule, mem1 ) );
+       debug_only(_mem_node = save_mem_node;)
      }
    }
  }