1 /*
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_matcher.cpp.incl"
27
28 OptoReg::Name OptoReg::c_frame_pointer;
29
30
31
32 const int Matcher::base2reg[Type::lastype] = {
33 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
34 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
35 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
36 0, 0/*abio*/,
37 Op_RegP /* Return address */, 0, /* the memories */
38 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
39 0 /*bottom*/
40 };
41
42 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
43 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
44 RegMask Matcher::STACK_ONLY_mask;
45 RegMask Matcher::c_frame_ptr_mask;
46 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
47 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
48
49 //---------------------------Matcher-------------------------------------------
50 Matcher::Matcher( Node_List &proj_list ) :
51 PhaseTransform( Phase::Ins_Select ),
52 #ifdef ASSERT
53 _old2new_map(C->comp_arena()),
54 #endif
55 _shared_nodes(C->comp_arena()),
56 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
57 _swallowed(swallowed),
58 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
59 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
60 _must_clone(must_clone), _proj_list(proj_list),
61 _register_save_policy(register_save_policy),
62 _c_reg_save_policy(c_reg_save_policy),
63 _register_save_type(register_save_type),
64 _ruleName(ruleName),
65 _allocation_started(false),
66 _states_arena(Chunk::medium_size),
67 _visited(&_states_arena),
68 _shared(&_states_arena),
69 _dontcare(&_states_arena) {
70 C->set_matcher(this);
71
72 idealreg2spillmask[Op_RegI] = NULL;
73 idealreg2spillmask[Op_RegN] = NULL;
74 idealreg2spillmask[Op_RegL] = NULL;
75 idealreg2spillmask[Op_RegF] = NULL;
76 idealreg2spillmask[Op_RegD] = NULL;
77 idealreg2spillmask[Op_RegP] = NULL;
78
79 idealreg2debugmask[Op_RegI] = NULL;
80 idealreg2debugmask[Op_RegN] = NULL;
81 idealreg2debugmask[Op_RegL] = NULL;
82 idealreg2debugmask[Op_RegF] = NULL;
83 idealreg2debugmask[Op_RegD] = NULL;
84 idealreg2debugmask[Op_RegP] = NULL;
85 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
86 }
87
88 //------------------------------warp_incoming_stk_arg------------------------
89 // This warps a VMReg into an OptoReg::Name
90 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
91 OptoReg::Name warped;
92 if( reg->is_stack() ) { // Stack slot argument?
93 warped = OptoReg::add(_old_SP, reg->reg2stack() );
94 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
95 if( warped >= _in_arg_limit )
96 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
97 if (!RegMask::can_represent(warped)) {
98 // the compiler cannot represent this method's calling sequence
99 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
100 return OptoReg::Bad;
101 }
102 return warped;
103 }
104 return OptoReg::as_OptoReg(reg);
105 }
106
107 //---------------------------compute_old_SP------------------------------------
108 OptoReg::Name Compile::compute_old_SP() {
109 int fixed = fixed_slots();
110 int preserve = in_preserve_stack_slots();
111 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
112 }
113
114
115
116 #ifdef ASSERT
117 void Matcher::verify_new_nodes_only(Node* xroot) {
118 // Make sure that the new graph only references new nodes
119 ResourceMark rm;
120 Unique_Node_List worklist;
121 VectorSet visited(Thread::current()->resource_area());
122 worklist.push(xroot);
123 while (worklist.size() > 0) {
124 Node* n = worklist.pop();
125 visited <<= n->_idx;
126 assert(C->node_arena()->contains(n), "dead node");
127 for (uint j = 0; j < n->req(); j++) {
128 Node* in = n->in(j);
129 if (in != NULL) {
130 assert(C->node_arena()->contains(in), "dead node");
131 if (!visited.test(in->_idx)) {
132 worklist.push(in);
133 }
134 }
135 }
136 }
137 }
138 #endif
139
140
141 //---------------------------match---------------------------------------------
142 void Matcher::match( ) {
143 // One-time initialization of some register masks.
144 init_spill_mask( C->root()->in(1) );
145 _return_addr_mask = return_addr();
146 #ifdef _LP64
147 // Pointers take 2 slots in 64-bit land
148 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
149 #endif
150
151 // Map a Java-signature return type into return register-value
152 // machine registers for 0, 1 and 2 returned values.
153 const TypeTuple *range = C->tf()->range();
154 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
155 // Get ideal-register return type
156 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
157 // Get machine return register
158 uint sop = C->start()->Opcode();
159 OptoRegPair regs = return_value(ireg, false);
160
161 // And mask for same
162 _return_value_mask = RegMask(regs.first());
163 if( OptoReg::is_valid(regs.second()) )
164 _return_value_mask.Insert(regs.second());
165 }
166
167 // ---------------
168 // Frame Layout
169
170 // Need the method signature to determine the incoming argument types,
171 // because the types determine which registers the incoming arguments are
172 // in, and this affects the matched code.
173 const TypeTuple *domain = C->tf()->domain();
174 uint argcnt = domain->cnt() - TypeFunc::Parms;
175 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
176 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
177 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
178 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
179 uint i;
180 for( i = 0; i<argcnt; i++ ) {
181 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
182 }
183
184 // Pass array of ideal registers and length to USER code (from the AD file)
185 // that will convert this to an array of register numbers.
186 const StartNode *start = C->start();
187 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
188 #ifdef ASSERT
189 // Sanity check users' calling convention. Real handy while trying to
190 // get the initial port correct.
191 { for (uint i = 0; i<argcnt; i++) {
192 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
193 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
194 _parm_regs[i].set_bad();
195 continue;
196 }
197 VMReg parm_reg = vm_parm_regs[i].first();
198 assert(parm_reg->is_valid(), "invalid arg?");
199 if (parm_reg->is_reg()) {
200 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
201 assert(can_be_java_arg(opto_parm_reg) ||
202 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
203 opto_parm_reg == inline_cache_reg(),
204 "parameters in register must be preserved by runtime stubs");
205 }
206 for (uint j = 0; j < i; j++) {
207 assert(parm_reg != vm_parm_regs[j].first(),
208 "calling conv. must produce distinct regs");
209 }
210 }
211 }
212 #endif
213
214 // Do some initial frame layout.
215
216 // Compute the old incoming SP (may be called FP) as
217 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
218 _old_SP = C->compute_old_SP();
219 assert( is_even(_old_SP), "must be even" );
220
221 // Compute highest incoming stack argument as
222 // _old_SP + out_preserve_stack_slots + incoming argument size.
223 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
224 assert( is_even(_in_arg_limit), "out_preserve must be even" );
225 for( i = 0; i < argcnt; i++ ) {
226 // Permit args to have no register
227 _calling_convention_mask[i].Clear();
228 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
229 continue;
230 }
231 // calling_convention returns stack arguments as a count of
232 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
233 // the allocators point of view, taking into account all the
234 // preserve area, locks & pad2.
235
236 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
237 if( OptoReg::is_valid(reg1))
238 _calling_convention_mask[i].Insert(reg1);
239
240 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
241 if( OptoReg::is_valid(reg2))
242 _calling_convention_mask[i].Insert(reg2);
243
244 // Saved biased stack-slot register number
245 _parm_regs[i].set_pair(reg2, reg1);
246 }
247
248 // Finally, make sure the incoming arguments take up an even number of
249 // words, in case the arguments or locals need to contain doubleword stack
250 // slots. The rest of the system assumes that stack slot pairs (in
251 // particular, in the spill area) which look aligned will in fact be
252 // aligned relative to the stack pointer in the target machine. Double
253 // stack slots will always be allocated aligned.
254 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
255
256 // Compute highest outgoing stack argument as
257 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
258 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
259 assert( is_even(_out_arg_limit), "out_preserve must be even" );
260
261 if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) {
262 // the compiler cannot represent this method's calling sequence
263 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
264 }
265
266 if (C->failing()) return; // bailed out on incoming arg failure
267
268 // ---------------
269 // Collect roots of matcher trees. Every node for which
270 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
271 // can be a valid interior of some tree.
272 find_shared( C->root() );
273 find_shared( C->top() );
274
275 C->print_method("Before Matching", 2);
276
277 // Swap out to old-space; emptying new-space
278 Arena *old = C->node_arena()->move_contents(C->old_arena());
279
280 // Save debug and profile information for nodes in old space:
281 _old_node_note_array = C->node_note_array();
282 if (_old_node_note_array != NULL) {
283 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
284 (C->comp_arena(), _old_node_note_array->length(),
285 0, NULL));
286 }
287
288 // Pre-size the new_node table to avoid the need for range checks.
289 grow_new_node_array(C->unique());
290
291 // Reset node counter so MachNodes start with _idx at 0
292 int nodes = C->unique(); // save value
293 C->set_unique(0);
294
295 // Recursively match trees from old space into new space.
296 // Correct leaves of new-space Nodes; they point to old-space.
297 _visited.Clear(); // Clear visit bits for xform call
298 C->set_cached_top_node(xform( C->top(), nodes ));
299 if (!C->failing()) {
300 Node* xroot = xform( C->root(), 1 );
301 if (xroot == NULL) {
302 Matcher::soft_match_failure(); // recursive matching process failed
303 C->record_method_not_compilable("instruction match failed");
304 } else {
305 // During matching shared constants were attached to C->root()
306 // because xroot wasn't available yet, so transfer the uses to
307 // the xroot.
308 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
309 Node* n = C->root()->fast_out(j);
310 if (C->node_arena()->contains(n)) {
311 assert(n->in(0) == C->root(), "should be control user");
312 n->set_req(0, xroot);
313 --j;
314 --jmax;
315 }
316 }
317
318 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
319 #ifdef ASSERT
320 verify_new_nodes_only(xroot);
321 #endif
322 }
323 }
324 if (C->top() == NULL || C->root() == NULL) {
325 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
326 }
327 if (C->failing()) {
328 // delete old;
329 old->destruct_contents();
330 return;
331 }
332 assert( C->top(), "" );
333 assert( C->root(), "" );
334 validate_null_checks();
335
336 // Now smoke old-space
337 NOT_DEBUG( old->destruct_contents() );
338
339 // ------------------------
340 // Set up save-on-entry registers
341 Fixup_Save_On_Entry( );
342 }
343
344
345 //------------------------------Fixup_Save_On_Entry----------------------------
346 // The stated purpose of this routine is to take care of save-on-entry
347 // registers. However, the overall goal of the Match phase is to convert into
348 // machine-specific instructions which have RegMasks to guide allocation.
349 // So what this procedure really does is put a valid RegMask on each input
350 // to the machine-specific variations of all Return, TailCall and Halt
351 // instructions. It also adds edgs to define the save-on-entry values (and of
352 // course gives them a mask).
353
354 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
355 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
356 // Do all the pre-defined register masks
357 rms[TypeFunc::Control ] = RegMask::Empty;
358 rms[TypeFunc::I_O ] = RegMask::Empty;
359 rms[TypeFunc::Memory ] = RegMask::Empty;
360 rms[TypeFunc::ReturnAdr] = ret_adr;
361 rms[TypeFunc::FramePtr ] = fp;
362 return rms;
363 }
364
365 //---------------------------init_first_stack_mask-----------------------------
366 // Create the initial stack mask used by values spilling to the stack.
367 // Disallow any debug info in outgoing argument areas by setting the
368 // initial mask accordingly.
369 void Matcher::init_first_stack_mask() {
370
371 // Allocate storage for spill masks as masks for the appropriate load type.
372 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask)*12);
373 idealreg2spillmask[Op_RegN] = &rms[0];
374 idealreg2spillmask[Op_RegI] = &rms[1];
375 idealreg2spillmask[Op_RegL] = &rms[2];
376 idealreg2spillmask[Op_RegF] = &rms[3];
377 idealreg2spillmask[Op_RegD] = &rms[4];
378 idealreg2spillmask[Op_RegP] = &rms[5];
379 idealreg2debugmask[Op_RegN] = &rms[6];
380 idealreg2debugmask[Op_RegI] = &rms[7];
381 idealreg2debugmask[Op_RegL] = &rms[8];
382 idealreg2debugmask[Op_RegF] = &rms[9];
383 idealreg2debugmask[Op_RegD] = &rms[10];
384 idealreg2debugmask[Op_RegP] = &rms[11];
385
386 OptoReg::Name i;
387
388 // At first, start with the empty mask
389 C->FIRST_STACK_mask().Clear();
390
391 // Add in the incoming argument area
392 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
393 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
394 C->FIRST_STACK_mask().Insert(i);
395
396 // Add in all bits past the outgoing argument area
397 guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)),
398 "must be able to represent all call arguments in reg mask");
399 init = _out_arg_limit;
400 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
401 C->FIRST_STACK_mask().Insert(i);
402
403 // Finally, set the "infinite stack" bit.
404 C->FIRST_STACK_mask().set_AllStack();
405
406 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
407 #ifdef _LP64
408 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
409 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
410 #endif
411 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
412 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
413 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
414 idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask());
415 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
416 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
417 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
418 idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask());
419 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
420 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
421
422 // Make up debug masks. Any spill slot plus callee-save registers.
423 // Caller-save registers are assumed to be trashable by the various
424 // inline-cache fixup routines.
425 *idealreg2debugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
426 *idealreg2debugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
427 *idealreg2debugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
428 *idealreg2debugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
429 *idealreg2debugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
430 *idealreg2debugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
431
432 // Prevent stub compilations from attempting to reference
433 // callee-saved registers from debug info
434 bool exclude_soe = !Compile::current()->is_method_compilation();
435
436 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
437 // registers the caller has to save do not work
438 if( _register_save_policy[i] == 'C' ||
439 _register_save_policy[i] == 'A' ||
440 (_register_save_policy[i] == 'E' && exclude_soe) ) {
441 idealreg2debugmask[Op_RegN]->Remove(i);
442 idealreg2debugmask[Op_RegI]->Remove(i); // Exclude save-on-call
443 idealreg2debugmask[Op_RegL]->Remove(i); // registers from debug
444 idealreg2debugmask[Op_RegF]->Remove(i); // masks
445 idealreg2debugmask[Op_RegD]->Remove(i);
446 idealreg2debugmask[Op_RegP]->Remove(i);
447 }
448 }
449 }
450
451 //---------------------------is_save_on_entry----------------------------------
452 bool Matcher::is_save_on_entry( int reg ) {
453 return
454 _register_save_policy[reg] == 'E' ||
455 _register_save_policy[reg] == 'A' || // Save-on-entry register?
456 // Also save argument registers in the trampolining stubs
457 (C->save_argument_registers() && is_spillable_arg(reg));
458 }
459
460 //---------------------------Fixup_Save_On_Entry-------------------------------
461 void Matcher::Fixup_Save_On_Entry( ) {
462 init_first_stack_mask();
463
464 Node *root = C->root(); // Short name for root
465 // Count number of save-on-entry registers.
466 uint soe_cnt = number_of_saved_registers();
467 uint i;
468
469 // Find the procedure Start Node
470 StartNode *start = C->start();
471 assert( start, "Expect a start node" );
472
473 // Save argument registers in the trampolining stubs
474 if( C->save_argument_registers() )
475 for( i = 0; i < _last_Mach_Reg; i++ )
476 if( is_spillable_arg(i) )
477 soe_cnt++;
478
479 // Input RegMask array shared by all Returns.
480 // The type for doubles and longs has a count of 2, but
481 // there is only 1 returned value
482 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
483 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
484 // Returns have 0 or 1 returned values depending on call signature.
485 // Return register is specified by return_value in the AD file.
486 if (ret_edge_cnt > TypeFunc::Parms)
487 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
488
489 // Input RegMask array shared by all Rethrows.
490 uint reth_edge_cnt = TypeFunc::Parms+1;
491 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
492 // Rethrow takes exception oop only, but in the argument 0 slot.
493 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
494 #ifdef _LP64
495 // Need two slots for ptrs in 64-bit land
496 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
497 #endif
498
499 // Input RegMask array shared by all TailCalls
500 uint tail_call_edge_cnt = TypeFunc::Parms+2;
501 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
502
503 // Input RegMask array shared by all TailJumps
504 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
505 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
506
507 // TailCalls have 2 returned values (target & moop), whose masks come
508 // from the usual MachNode/MachOper mechanism. Find a sample
509 // TailCall to extract these masks and put the correct masks into
510 // the tail_call_rms array.
511 for( i=1; i < root->req(); i++ ) {
512 MachReturnNode *m = root->in(i)->as_MachReturn();
513 if( m->ideal_Opcode() == Op_TailCall ) {
514 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
515 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
516 break;
517 }
518 }
519
520 // TailJumps have 2 returned values (target & ex_oop), whose masks come
521 // from the usual MachNode/MachOper mechanism. Find a sample
522 // TailJump to extract these masks and put the correct masks into
523 // the tail_jump_rms array.
524 for( i=1; i < root->req(); i++ ) {
525 MachReturnNode *m = root->in(i)->as_MachReturn();
526 if( m->ideal_Opcode() == Op_TailJump ) {
527 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
528 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
529 break;
530 }
531 }
532
533 // Input RegMask array shared by all Halts
534 uint halt_edge_cnt = TypeFunc::Parms;
535 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
536
537 // Capture the return input masks into each exit flavor
538 for( i=1; i < root->req(); i++ ) {
539 MachReturnNode *exit = root->in(i)->as_MachReturn();
540 switch( exit->ideal_Opcode() ) {
541 case Op_Return : exit->_in_rms = ret_rms; break;
542 case Op_Rethrow : exit->_in_rms = reth_rms; break;
543 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
544 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
545 case Op_Halt : exit->_in_rms = halt_rms; break;
546 default : ShouldNotReachHere();
547 }
548 }
549
550 // Next unused projection number from Start.
551 int proj_cnt = C->tf()->domain()->cnt();
552
553 // Do all the save-on-entry registers. Make projections from Start for
554 // them, and give them a use at the exit points. To the allocator, they
555 // look like incoming register arguments.
556 for( i = 0; i < _last_Mach_Reg; i++ ) {
557 if( is_save_on_entry(i) ) {
558
559 // Add the save-on-entry to the mask array
560 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
561 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
562 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
563 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
564 // Halts need the SOE registers, but only in the stack as debug info.
565 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
566 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
567
568 Node *mproj;
569
570 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
571 // into a single RegD.
572 if( (i&1) == 0 &&
573 _register_save_type[i ] == Op_RegF &&
574 _register_save_type[i+1] == Op_RegF &&
575 is_save_on_entry(i+1) ) {
576 // Add other bit for double
577 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
578 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
579 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
580 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
581 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
582 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
583 proj_cnt += 2; // Skip 2 for doubles
584 }
585 else if( (i&1) == 1 && // Else check for high half of double
586 _register_save_type[i-1] == Op_RegF &&
587 _register_save_type[i ] == Op_RegF &&
588 is_save_on_entry(i-1) ) {
589 ret_rms [ ret_edge_cnt] = RegMask::Empty;
590 reth_rms [ reth_edge_cnt] = RegMask::Empty;
591 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
592 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
593 halt_rms [ halt_edge_cnt] = RegMask::Empty;
594 mproj = C->top();
595 }
596 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
597 // into a single RegL.
598 else if( (i&1) == 0 &&
599 _register_save_type[i ] == Op_RegI &&
600 _register_save_type[i+1] == Op_RegI &&
601 is_save_on_entry(i+1) ) {
602 // Add other bit for long
603 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
604 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
605 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
606 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
607 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
608 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
609 proj_cnt += 2; // Skip 2 for longs
610 }
611 else if( (i&1) == 1 && // Else check for high half of long
612 _register_save_type[i-1] == Op_RegI &&
613 _register_save_type[i ] == Op_RegI &&
614 is_save_on_entry(i-1) ) {
615 ret_rms [ ret_edge_cnt] = RegMask::Empty;
616 reth_rms [ reth_edge_cnt] = RegMask::Empty;
617 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
618 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
619 halt_rms [ halt_edge_cnt] = RegMask::Empty;
620 mproj = C->top();
621 } else {
622 // Make a projection for it off the Start
623 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
624 }
625
626 ret_edge_cnt ++;
627 reth_edge_cnt ++;
628 tail_call_edge_cnt ++;
629 tail_jump_edge_cnt ++;
630 halt_edge_cnt ++;
631
632 // Add a use of the SOE register to all exit paths
633 for( uint j=1; j < root->req(); j++ )
634 root->in(j)->add_req(mproj);
635 } // End of if a save-on-entry register
636 } // End of for all machine registers
637 }
638
639 //------------------------------init_spill_mask--------------------------------
640 void Matcher::init_spill_mask( Node *ret ) {
641 if( idealreg2regmask[Op_RegI] ) return; // One time only init
642
643 OptoReg::c_frame_pointer = c_frame_pointer();
644 c_frame_ptr_mask = c_frame_pointer();
645 #ifdef _LP64
646 // pointers are twice as big
647 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
648 #endif
649
650 // Start at OptoReg::stack0()
651 STACK_ONLY_mask.Clear();
652 OptoReg::Name init = OptoReg::stack2reg(0);
653 // STACK_ONLY_mask is all stack bits
654 OptoReg::Name i;
655 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
656 STACK_ONLY_mask.Insert(i);
657 // Also set the "infinite stack" bit.
658 STACK_ONLY_mask.set_AllStack();
659
660 // Copy the register names over into the shared world
661 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
662 // SharedInfo::regName[i] = regName[i];
663 // Handy RegMasks per machine register
664 mreg2regmask[i].Insert(i);
665 }
666
667 // Grab the Frame Pointer
668 Node *fp = ret->in(TypeFunc::FramePtr);
669 Node *mem = ret->in(TypeFunc::Memory);
670 const TypePtr* atp = TypePtr::BOTTOM;
671 // Share frame pointer while making spill ops
672 set_shared(fp);
673
674 // Compute generic short-offset Loads
675 #ifdef _LP64
676 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
677 #endif
678 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
679 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
680 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
681 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
682 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
683 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
684 spillD != NULL && spillP != NULL, "");
685
686 // Get the ADLC notion of the right regmask, for each basic type.
687 #ifdef _LP64
688 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
689 #endif
690 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
691 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
692 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
693 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
694 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
695 }
696
697 #ifdef ASSERT
698 static void match_alias_type(Compile* C, Node* n, Node* m) {
699 if (!VerifyAliases) return; // do not go looking for trouble by default
700 const TypePtr* nat = n->adr_type();
701 const TypePtr* mat = m->adr_type();
702 int nidx = C->get_alias_index(nat);
703 int midx = C->get_alias_index(mat);
704 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
705 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
706 for (uint i = 1; i < n->req(); i++) {
707 Node* n1 = n->in(i);
708 const TypePtr* n1at = n1->adr_type();
709 if (n1at != NULL) {
710 nat = n1at;
711 nidx = C->get_alias_index(n1at);
712 }
713 }
714 }
715 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
716 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
717 switch (n->Opcode()) {
718 case Op_PrefetchRead:
719 case Op_PrefetchWrite:
720 nidx = Compile::AliasIdxRaw;
721 nat = TypeRawPtr::BOTTOM;
722 break;
723 }
724 }
725 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
726 switch (n->Opcode()) {
727 case Op_ClearArray:
728 midx = Compile::AliasIdxRaw;
729 mat = TypeRawPtr::BOTTOM;
730 break;
731 }
732 }
733 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
734 switch (n->Opcode()) {
735 case Op_Return:
736 case Op_Rethrow:
737 case Op_Halt:
738 case Op_TailCall:
739 case Op_TailJump:
740 nidx = Compile::AliasIdxBot;
741 nat = TypePtr::BOTTOM;
742 break;
743 }
744 }
745 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
746 switch (n->Opcode()) {
747 case Op_StrComp:
748 case Op_AryEq:
749 case Op_MemBarVolatile:
750 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
751 nidx = Compile::AliasIdxTop;
752 nat = NULL;
753 break;
754 }
755 }
756 if (nidx != midx) {
757 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
758 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
759 n->dump();
760 m->dump();
761 }
762 assert(C->subsume_loads() && C->must_alias(nat, midx),
763 "must not lose alias info when matching");
764 }
765 }
766 #endif
767
768
769 //------------------------------MStack-----------------------------------------
770 // State and MStack class used in xform() and find_shared() iterative methods.
771 enum Node_State { Pre_Visit, // node has to be pre-visited
772 Visit, // visit node
773 Post_Visit, // post-visit node
774 Alt_Post_Visit // alternative post-visit path
775 };
776
777 class MStack: public Node_Stack {
778 public:
779 MStack(int size) : Node_Stack(size) { }
780
781 void push(Node *n, Node_State ns) {
782 Node_Stack::push(n, (uint)ns);
783 }
784 void push(Node *n, Node_State ns, Node *parent, int indx) {
785 ++_inode_top;
786 if ((_inode_top + 1) >= _inode_max) grow();
787 _inode_top->node = parent;
788 _inode_top->indx = (uint)indx;
789 ++_inode_top;
790 _inode_top->node = n;
791 _inode_top->indx = (uint)ns;
792 }
793 Node *parent() {
794 pop();
795 return node();
796 }
797 Node_State state() const {
798 return (Node_State)index();
799 }
800 void set_state(Node_State ns) {
801 set_index((uint)ns);
802 }
803 };
804
805
806 //------------------------------xform------------------------------------------
807 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
808 // Node in new-space. Given a new-space Node, recursively walk his children.
809 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
810 Node *Matcher::xform( Node *n, int max_stack ) {
811 // Use one stack to keep both: child's node/state and parent's node/index
812 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
813 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
814
815 while (mstack.is_nonempty()) {
816 n = mstack.node(); // Leave node on stack
817 Node_State nstate = mstack.state();
818 if (nstate == Visit) {
819 mstack.set_state(Post_Visit);
820 Node *oldn = n;
821 // Old-space or new-space check
822 if (!C->node_arena()->contains(n)) {
823 // Old space!
824 Node* m;
825 if (has_new_node(n)) { // Not yet Label/Reduced
826 m = new_node(n);
827 } else {
828 if (!is_dontcare(n)) { // Matcher can match this guy
829 // Calls match special. They match alone with no children.
830 // Their children, the incoming arguments, match normally.
831 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
832 if (C->failing()) return NULL;
833 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
834 } else { // Nothing the matcher cares about
835 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
836 // Convert to machine-dependent projection
837 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
838 if (m->in(0) != NULL) // m might be top
839 collect_null_checks(m);
840 } else { // Else just a regular 'ol guy
841 m = n->clone(); // So just clone into new-space
842 // Def-Use edges will be added incrementally as Uses
843 // of this node are matched.
844 assert(m->outcnt() == 0, "no Uses of this clone yet");
845 }
846 }
847
848 set_new_node(n, m); // Map old to new
849 if (_old_node_note_array != NULL) {
850 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
851 n->_idx);
852 C->set_node_notes_at(m->_idx, nn);
853 }
854 debug_only(match_alias_type(C, n, m));
855 }
856 n = m; // n is now a new-space node
857 mstack.set_node(n);
858 }
859
860 // New space!
861 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
862
863 int i;
864 // Put precedence edges on stack first (match them last).
865 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
866 Node *m = oldn->in(i);
867 if (m == NULL) break;
868 // set -1 to call add_prec() instead of set_req() during Step1
869 mstack.push(m, Visit, n, -1);
870 }
871
872 // For constant debug info, I'd rather have unmatched constants.
873 int cnt = n->req();
874 JVMState* jvms = n->jvms();
875 int debug_cnt = jvms ? jvms->debug_start() : cnt;
876
877 // Now do only debug info. Clone constants rather than matching.
878 // Constants are represented directly in the debug info without
879 // the need for executable machine instructions.
880 // Monitor boxes are also represented directly.
881 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
882 Node *m = n->in(i); // Get input
883 int op = m->Opcode();
884 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
885 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
886 op == Op_ConF || op == Op_ConD || op == Op_ConL
887 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
888 ) {
889 m = m->clone();
890 mstack.push(m, Post_Visit, n, i); // Don't neet to visit
891 mstack.push(m->in(0), Visit, m, 0);
892 } else {
893 mstack.push(m, Visit, n, i);
894 }
895 }
896
897 // And now walk his children, and convert his inputs to new-space.
898 for( ; i >= 0; --i ) { // For all normal inputs do
899 Node *m = n->in(i); // Get input
900 if(m != NULL)
901 mstack.push(m, Visit, n, i);
902 }
903
904 }
905 else if (nstate == Post_Visit) {
906 // Set xformed input
907 Node *p = mstack.parent();
908 if (p != NULL) { // root doesn't have parent
909 int i = (int)mstack.index();
910 if (i >= 0)
911 p->set_req(i, n); // required input
912 else if (i == -1)
913 p->add_prec(n); // precedence input
914 else
915 ShouldNotReachHere();
916 }
917 mstack.pop(); // remove processed node from stack
918 }
919 else {
920 ShouldNotReachHere();
921 }
922 } // while (mstack.is_nonempty())
923 return n; // Return new-space Node
924 }
925
926 //------------------------------warp_outgoing_stk_arg------------------------
927 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
928 // Convert outgoing argument location to a pre-biased stack offset
929 if (reg->is_stack()) {
930 OptoReg::Name warped = reg->reg2stack();
931 // Adjust the stack slot offset to be the register number used
932 // by the allocator.
933 warped = OptoReg::add(begin_out_arg_area, warped);
934 // Keep track of the largest numbered stack slot used for an arg.
935 // Largest used slot per call-site indicates the amount of stack
936 // that is killed by the call.
937 if( warped >= out_arg_limit_per_call )
938 out_arg_limit_per_call = OptoReg::add(warped,1);
939 if (!RegMask::can_represent(warped)) {
940 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
941 return OptoReg::Bad;
942 }
943 return warped;
944 }
945 return OptoReg::as_OptoReg(reg);
946 }
947
948
949 //------------------------------match_sfpt-------------------------------------
950 // Helper function to match call instructions. Calls match special.
951 // They match alone with no children. Their children, the incoming
952 // arguments, match normally.
953 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
954 MachSafePointNode *msfpt = NULL;
955 MachCallNode *mcall = NULL;
956 uint cnt;
957 // Split out case for SafePoint vs Call
958 CallNode *call;
959 const TypeTuple *domain;
960 ciMethod* method = NULL;
961 if( sfpt->is_Call() ) {
962 call = sfpt->as_Call();
963 domain = call->tf()->domain();
964 cnt = domain->cnt();
965
966 // Match just the call, nothing else
967 MachNode *m = match_tree(call);
968 if (C->failing()) return NULL;
969 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
970
971 // Copy data from the Ideal SafePoint to the machine version
972 mcall = m->as_MachCall();
973
974 mcall->set_tf( call->tf());
975 mcall->set_entry_point(call->entry_point());
976 mcall->set_cnt( call->cnt());
977
978 if( mcall->is_MachCallJava() ) {
979 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
980 const CallJavaNode *call_java = call->as_CallJava();
981 method = call_java->method();
982 mcall_java->_method = method;
983 mcall_java->_bci = call_java->_bci;
984 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
985 if( mcall_java->is_MachCallStaticJava() )
986 mcall_java->as_MachCallStaticJava()->_name =
987 call_java->as_CallStaticJava()->_name;
988 if( mcall_java->is_MachCallDynamicJava() )
989 mcall_java->as_MachCallDynamicJava()->_vtable_index =
990 call_java->as_CallDynamicJava()->_vtable_index;
991 }
992 else if( mcall->is_MachCallRuntime() ) {
993 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
994 }
995 msfpt = mcall;
996 }
997 // This is a non-call safepoint
998 else {
999 call = NULL;
1000 domain = NULL;
1001 MachNode *mn = match_tree(sfpt);
1002 if (C->failing()) return NULL;
1003 msfpt = mn->as_MachSafePoint();
1004 cnt = TypeFunc::Parms;
1005 }
1006
1007 // Advertise the correct memory effects (for anti-dependence computation).
1008 msfpt->set_adr_type(sfpt->adr_type());
1009
1010 // Allocate a private array of RegMasks. These RegMasks are not shared.
1011 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1012 // Empty them all.
1013 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1014
1015 // Do all the pre-defined non-Empty register masks
1016 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1017 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1018
1019 // Place first outgoing argument can possibly be put.
1020 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1021 assert( is_even(begin_out_arg_area), "" );
1022 // Compute max outgoing register number per call site.
1023 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1024 // Calls to C may hammer extra stack slots above and beyond any arguments.
1025 // These are usually backing store for register arguments for varargs.
1026 if( call != NULL && call->is_CallRuntime() )
1027 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1028
1029
1030 // Do the normal argument list (parameters) register masks
1031 int argcnt = cnt - TypeFunc::Parms;
1032 if( argcnt > 0 ) { // Skip it all if we have no args
1033 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1034 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1035 int i;
1036 for( i = 0; i < argcnt; i++ ) {
1037 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1038 }
1039 // V-call to pick proper calling convention
1040 call->calling_convention( sig_bt, parm_regs, argcnt );
1041
1042 #ifdef ASSERT
1043 // Sanity check users' calling convention. Really handy during
1044 // the initial porting effort. Fairly expensive otherwise.
1045 { for (int i = 0; i<argcnt; i++) {
1046 if( !parm_regs[i].first()->is_valid() &&
1047 !parm_regs[i].second()->is_valid() ) continue;
1048 VMReg reg1 = parm_regs[i].first();
1049 VMReg reg2 = parm_regs[i].second();
1050 for (int j = 0; j < i; j++) {
1051 if( !parm_regs[j].first()->is_valid() &&
1052 !parm_regs[j].second()->is_valid() ) continue;
1053 VMReg reg3 = parm_regs[j].first();
1054 VMReg reg4 = parm_regs[j].second();
1055 if( !reg1->is_valid() ) {
1056 assert( !reg2->is_valid(), "valid halvsies" );
1057 } else if( !reg3->is_valid() ) {
1058 assert( !reg4->is_valid(), "valid halvsies" );
1059 } else {
1060 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1061 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1062 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1063 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1064 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1065 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1066 }
1067 }
1068 }
1069 }
1070 #endif
1071
1072 // Visit each argument. Compute its outgoing register mask.
1073 // Return results now can have 2 bits returned.
1074 // Compute max over all outgoing arguments both per call-site
1075 // and over the entire method.
1076 for( i = 0; i < argcnt; i++ ) {
1077 // Address of incoming argument mask to fill in
1078 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1079 if( !parm_regs[i].first()->is_valid() &&
1080 !parm_regs[i].second()->is_valid() ) {
1081 continue; // Avoid Halves
1082 }
1083 // Grab first register, adjust stack slots and insert in mask.
1084 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1085 if (OptoReg::is_valid(reg1))
1086 rm->Insert( reg1 );
1087 // Grab second register (if any), adjust stack slots and insert in mask.
1088 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1089 if (OptoReg::is_valid(reg2))
1090 rm->Insert( reg2 );
1091 } // End of for all arguments
1092
1093 // Compute number of stack slots needed to restore stack in case of
1094 // Pascal-style argument popping.
1095 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1096 }
1097
1098 // Compute the max stack slot killed by any call. These will not be
1099 // available for debug info, and will be used to adjust FIRST_STACK_mask
1100 // after all call sites have been visited.
1101 if( _out_arg_limit < out_arg_limit_per_call)
1102 _out_arg_limit = out_arg_limit_per_call;
1103
1104 if (mcall) {
1105 // Kill the outgoing argument area, including any non-argument holes and
1106 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1107 // Since the max-per-method covers the max-per-call-site and debug info
1108 // is excluded on the max-per-method basis, debug info cannot land in
1109 // this killed area.
1110 uint r_cnt = mcall->tf()->range()->cnt();
1111 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1112 if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) {
1113 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1114 } else {
1115 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1116 proj->_rout.Insert(OptoReg::Name(i));
1117 }
1118 if( proj->_rout.is_NotEmpty() )
1119 _proj_list.push(proj);
1120 }
1121 // Transfer the safepoint information from the call to the mcall
1122 // Move the JVMState list
1123 msfpt->set_jvms(sfpt->jvms());
1124 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1125 jvms->set_map(sfpt);
1126 }
1127
1128 // Debug inputs begin just after the last incoming parameter
1129 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1130 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1131
1132 // Move the OopMap
1133 msfpt->_oop_map = sfpt->_oop_map;
1134
1135 // Registers killed by the call are set in the local scheduling pass
1136 // of Global Code Motion.
1137 return msfpt;
1138 }
1139
1140 //---------------------------match_tree----------------------------------------
1141 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1142 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1143 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1144 // a Load's result RegMask for memoization in idealreg2regmask[]
1145 MachNode *Matcher::match_tree( const Node *n ) {
1146 assert( n->Opcode() != Op_Phi, "cannot match" );
1147 assert( !n->is_block_start(), "cannot match" );
1148 // Set the mark for all locally allocated State objects.
1149 // When this call returns, the _states_arena arena will be reset
1150 // freeing all State objects.
1151 ResourceMark rm( &_states_arena );
1152
1153 LabelRootDepth = 0;
1154
1155 // StoreNodes require their Memory input to match any LoadNodes
1156 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1157 #ifdef ASSERT
1158 Node* save_mem_node = _mem_node;
1159 _mem_node = n->is_Store() ? (Node*)n : NULL;
1160 #endif
1161 // State object for root node of match tree
1162 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1163 State *s = new (&_states_arena) State;
1164 s->_kids[0] = NULL;
1165 s->_kids[1] = NULL;
1166 s->_leaf = (Node*)n;
1167 // Label the input tree, allocating labels from top-level arena
1168 Label_Root( n, s, n->in(0), mem );
1169 if (C->failing()) return NULL;
1170
1171 // The minimum cost match for the whole tree is found at the root State
1172 uint mincost = max_juint;
1173 uint cost = max_juint;
1174 uint i;
1175 for( i = 0; i < NUM_OPERANDS; i++ ) {
1176 if( s->valid(i) && // valid entry and
1177 s->_cost[i] < cost && // low cost and
1178 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1179 cost = s->_cost[mincost=i];
1180 }
1181 if (mincost == max_juint) {
1182 #ifndef PRODUCT
1183 tty->print("No matching rule for:");
1184 s->dump();
1185 #endif
1186 Matcher::soft_match_failure();
1187 return NULL;
1188 }
1189 // Reduce input tree based upon the state labels to machine Nodes
1190 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1191 #ifdef ASSERT
1192 _old2new_map.map(n->_idx, m);
1193 #endif
1194
1195 // Add any Matcher-ignored edges
1196 uint cnt = n->req();
1197 uint start = 1;
1198 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1199 if( n->is_AddP() ) {
1200 assert( mem == (Node*)1, "" );
1201 start = AddPNode::Base+1;
1202 }
1203 for( i = start; i < cnt; i++ ) {
1204 if( !n->match_edge(i) ) {
1205 if( i < m->req() )
1206 m->ins_req( i, n->in(i) );
1207 else
1208 m->add_req( n->in(i) );
1209 }
1210 }
1211
1212 debug_only( _mem_node = save_mem_node; )
1213 return m;
1214 }
1215
1216
1217 //------------------------------match_into_reg---------------------------------
1218 // Choose to either match this Node in a register or part of the current
1219 // match tree. Return true for requiring a register and false for matching
1220 // as part of the current match tree.
1221 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1222
1223 const Type *t = m->bottom_type();
1224
1225 if( t->singleton() ) {
1226 // Never force constants into registers. Allow them to match as
1227 // constants or registers. Copies of the same value will share
1228 // the same register. See find_shared_node.
1229 return false;
1230 } else { // Not a constant
1231 // Stop recursion if they have different Controls.
1232 // Slot 0 of constants is not really a Control.
1233 if( control && m->in(0) && control != m->in(0) ) {
1234
1235 // Actually, we can live with the most conservative control we
1236 // find, if it post-dominates the others. This allows us to
1237 // pick up load/op/store trees where the load can float a little
1238 // above the store.
1239 Node *x = control;
1240 const uint max_scan = 6; // Arbitrary scan cutoff
1241 uint j;
1242 for( j=0; j<max_scan; j++ ) {
1243 if( x->is_Region() ) // Bail out at merge points
1244 return true;
1245 x = x->in(0);
1246 if( x == m->in(0) ) // Does 'control' post-dominate
1247 break; // m->in(0)? If so, we can use it
1248 }
1249 if( j == max_scan ) // No post-domination before scan end?
1250 return true; // Then break the match tree up
1251 }
1252 if (m->is_DecodeN() && Matcher::clone_shift_expressions) {
1253 // These are commonly used in address expressions and can
1254 // efficiently fold into them on X64 in some cases.
1255 return false;
1256 }
1257 }
1258
1259 // Not forceably cloning. If shared, put it into a register.
1260 return shared;
1261 }
1262
1263
1264 //------------------------------Instruction Selection--------------------------
1265 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1266 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1267 // things the Matcher does not match (e.g., Memory), and things with different
1268 // Controls (hence forced into different blocks). We pass in the Control
1269 // selected for this entire State tree.
1270
1271 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1272 // Store and the Load must have identical Memories (as well as identical
1273 // pointers). Since the Matcher does not have anything for Memory (and
1274 // does not handle DAGs), I have to match the Memory input myself. If the
1275 // Tree root is a Store, I require all Loads to have the identical memory.
1276 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1277 // Since Label_Root is a recursive function, its possible that we might run
1278 // out of stack space. See bugs 6272980 & 6227033 for more info.
1279 LabelRootDepth++;
1280 if (LabelRootDepth > MaxLabelRootDepth) {
1281 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1282 return NULL;
1283 }
1284 uint care = 0; // Edges matcher cares about
1285 uint cnt = n->req();
1286 uint i = 0;
1287
1288 // Examine children for memory state
1289 // Can only subsume a child into your match-tree if that child's memory state
1290 // is not modified along the path to another input.
1291 // It is unsafe even if the other inputs are separate roots.
1292 Node *input_mem = NULL;
1293 for( i = 1; i < cnt; i++ ) {
1294 if( !n->match_edge(i) ) continue;
1295 Node *m = n->in(i); // Get ith input
1296 assert( m, "expect non-null children" );
1297 if( m->is_Load() ) {
1298 if( input_mem == NULL ) {
1299 input_mem = m->in(MemNode::Memory);
1300 } else if( input_mem != m->in(MemNode::Memory) ) {
1301 input_mem = NodeSentinel;
1302 }
1303 }
1304 }
1305
1306 for( i = 1; i < cnt; i++ ){// For my children
1307 if( !n->match_edge(i) ) continue;
1308 Node *m = n->in(i); // Get ith input
1309 // Allocate states out of a private arena
1310 State *s = new (&_states_arena) State;
1311 svec->_kids[care++] = s;
1312 assert( care <= 2, "binary only for now" );
1313
1314 // Recursively label the State tree.
1315 s->_kids[0] = NULL;
1316 s->_kids[1] = NULL;
1317 s->_leaf = m;
1318
1319 // Check for leaves of the State Tree; things that cannot be a part of
1320 // the current tree. If it finds any, that value is matched as a
1321 // register operand. If not, then the normal matching is used.
1322 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1323 //
1324 // Stop recursion if this is LoadNode and the root of this tree is a
1325 // StoreNode and the load & store have different memories.
1326 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1327 // Can NOT include the match of a subtree when its memory state
1328 // is used by any of the other subtrees
1329 (input_mem == NodeSentinel) ) {
1330 #ifndef PRODUCT
1331 // Print when we exclude matching due to different memory states at input-loads
1332 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1333 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1334 tty->print_cr("invalid input_mem");
1335 }
1336 #endif
1337 // Switch to a register-only opcode; this value must be in a register
1338 // and cannot be subsumed as part of a larger instruction.
1339 s->DFA( m->ideal_reg(), m );
1340
1341 } else {
1342 // If match tree has no control and we do, adopt it for entire tree
1343 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1344 control = m->in(0); // Pick up control
1345 // Else match as a normal part of the match tree.
1346 control = Label_Root(m,s,control,mem);
1347 if (C->failing()) return NULL;
1348 }
1349 }
1350
1351
1352 // Call DFA to match this node, and return
1353 svec->DFA( n->Opcode(), n );
1354
1355 #ifdef ASSERT
1356 uint x;
1357 for( x = 0; x < _LAST_MACH_OPER; x++ )
1358 if( svec->valid(x) )
1359 break;
1360
1361 if (x >= _LAST_MACH_OPER) {
1362 n->dump();
1363 svec->dump();
1364 assert( false, "bad AD file" );
1365 }
1366 #endif
1367 return control;
1368 }
1369
1370
1371 // Con nodes reduced using the same rule can share their MachNode
1372 // which reduces the number of copies of a constant in the final
1373 // program. The register allocator is free to split uses later to
1374 // split live ranges.
1375 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1376 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1377
1378 // See if this Con has already been reduced using this rule.
1379 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1380 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1381 if (last != NULL && rule == last->rule()) {
1382 // Don't expect control change for DecodeN
1383 if (leaf->is_DecodeN())
1384 return last;
1385 // Get the new space root.
1386 Node* xroot = new_node(C->root());
1387 if (xroot == NULL) {
1388 // This shouldn't happen give the order of matching.
1389 return NULL;
1390 }
1391
1392 // Shared constants need to have their control be root so they
1393 // can be scheduled properly.
1394 Node* control = last->in(0);
1395 if (control != xroot) {
1396 if (control == NULL || control == C->root()) {
1397 last->set_req(0, xroot);
1398 } else {
1399 assert(false, "unexpected control");
1400 return NULL;
1401 }
1402 }
1403 return last;
1404 }
1405 return NULL;
1406 }
1407
1408
1409 //------------------------------ReduceInst-------------------------------------
1410 // Reduce a State tree (with given Control) into a tree of MachNodes.
1411 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1412 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1413 // Each MachNode has a number of complicated MachOper operands; each
1414 // MachOper also covers a further tree of Ideal Nodes.
1415
1416 // The root of the Ideal match tree is always an instruction, so we enter
1417 // the recursion here. After building the MachNode, we need to recurse
1418 // the tree checking for these cases:
1419 // (1) Child is an instruction -
1420 // Build the instruction (recursively), add it as an edge.
1421 // Build a simple operand (register) to hold the result of the instruction.
1422 // (2) Child is an interior part of an instruction -
1423 // Skip over it (do nothing)
1424 // (3) Child is the start of a operand -
1425 // Build the operand, place it inside the instruction
1426 // Call ReduceOper.
1427 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1428 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1429
1430 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1431 if (shared_node != NULL) {
1432 return shared_node;
1433 }
1434
1435 // Build the object to represent this state & prepare for recursive calls
1436 MachNode *mach = s->MachNodeGenerator( rule, C );
1437 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1438 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1439 Node *leaf = s->_leaf;
1440 // Check for instruction or instruction chain rule
1441 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1442 // Instruction
1443 mach->add_req( leaf->in(0) ); // Set initial control
1444 // Reduce interior of complex instruction
1445 ReduceInst_Interior( s, rule, mem, mach, 1 );
1446 } else {
1447 // Instruction chain rules are data-dependent on their inputs
1448 mach->add_req(0); // Set initial control to none
1449 ReduceInst_Chain_Rule( s, rule, mem, mach );
1450 }
1451
1452 // If a Memory was used, insert a Memory edge
1453 if( mem != (Node*)1 ) {
1454 mach->ins_req(MemNode::Memory,mem);
1455 #ifdef ASSERT
1456 // Verify adr type after matching memory operation
1457 const MachOper* oper = mach->memory_operand();
1458 if (oper != NULL && oper != (MachOper*)-1 &&
1459 mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode
1460 // It has a unique memory operand. Find corresponding ideal mem node.
1461 Node* m = NULL;
1462 if (leaf->is_Mem()) {
1463 m = leaf;
1464 } else {
1465 m = _mem_node;
1466 assert(m != NULL && m->is_Mem(), "expecting memory node");
1467 }
1468 if (m->adr_type() != mach->adr_type()) {
1469 m->dump();
1470 tty->print_cr("mach:");
1471 mach->dump(1);
1472 }
1473 assert(m->adr_type() == mach->adr_type(), "matcher should not change adr type");
1474 }
1475 #endif
1476 }
1477
1478 // If the _leaf is an AddP, insert the base edge
1479 if( leaf->is_AddP() )
1480 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1481
1482 uint num_proj = _proj_list.size();
1483
1484 // Perform any 1-to-many expansions required
1485 MachNode *ex = mach->Expand(s,_proj_list);
1486 if( ex != mach ) {
1487 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1488 if( ex->in(1)->is_Con() )
1489 ex->in(1)->set_req(0, C->root());
1490 // Remove old node from the graph
1491 for( uint i=0; i<mach->req(); i++ ) {
1492 mach->set_req(i,NULL);
1493 }
1494 }
1495
1496 // PhaseChaitin::fixup_spills will sometimes generate spill code
1497 // via the matcher. By the time, nodes have been wired into the CFG,
1498 // and any further nodes generated by expand rules will be left hanging
1499 // in space, and will not get emitted as output code. Catch this.
1500 // Also, catch any new register allocation constraints ("projections")
1501 // generated belatedly during spill code generation.
1502 if (_allocation_started) {
1503 guarantee(ex == mach, "no expand rules during spill generation");
1504 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1505 }
1506
1507 if (leaf->is_Con() || leaf->is_DecodeN()) {
1508 // Record the con for sharing
1509 _shared_nodes.map(leaf->_idx, ex);
1510 }
1511
1512 return ex;
1513 }
1514
1515 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1516 // 'op' is what I am expecting to receive
1517 int op = _leftOp[rule];
1518 // Operand type to catch childs result
1519 // This is what my child will give me.
1520 int opnd_class_instance = s->_rule[op];
1521 // Choose between operand class or not.
1522 // This is what I will recieve.
1523 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1524 // New rule for child. Chase operand classes to get the actual rule.
1525 int newrule = s->_rule[catch_op];
1526
1527 if( newrule < NUM_OPERANDS ) {
1528 // Chain from operand or operand class, may be output of shared node
1529 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1530 "Bad AD file: Instruction chain rule must chain from operand");
1531 // Insert operand into array of operands for this instruction
1532 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1533
1534 ReduceOper( s, newrule, mem, mach );
1535 } else {
1536 // Chain from the result of an instruction
1537 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1538 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1539 Node *mem1 = (Node*)1;
1540 debug_only(Node *save_mem_node = _mem_node;)
1541 mach->add_req( ReduceInst(s, newrule, mem1) );
1542 debug_only(_mem_node = save_mem_node;)
1543 }
1544 return;
1545 }
1546
1547
1548 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1549 if( s->_leaf->is_Load() ) {
1550 Node *mem2 = s->_leaf->in(MemNode::Memory);
1551 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1552 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1553 mem = mem2;
1554 }
1555 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1556 if( mach->in(0) == NULL )
1557 mach->set_req(0, s->_leaf->in(0));
1558 }
1559
1560 // Now recursively walk the state tree & add operand list.
1561 for( uint i=0; i<2; i++ ) { // binary tree
1562 State *newstate = s->_kids[i];
1563 if( newstate == NULL ) break; // Might only have 1 child
1564 // 'op' is what I am expecting to receive
1565 int op;
1566 if( i == 0 ) {
1567 op = _leftOp[rule];
1568 } else {
1569 op = _rightOp[rule];
1570 }
1571 // Operand type to catch childs result
1572 // This is what my child will give me.
1573 int opnd_class_instance = newstate->_rule[op];
1574 // Choose between operand class or not.
1575 // This is what I will receive.
1576 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1577 // New rule for child. Chase operand classes to get the actual rule.
1578 int newrule = newstate->_rule[catch_op];
1579
1580 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1581 // Operand/operandClass
1582 // Insert operand into array of operands for this instruction
1583 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1584 ReduceOper( newstate, newrule, mem, mach );
1585
1586 } else { // Child is internal operand or new instruction
1587 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1588 // internal operand --> call ReduceInst_Interior
1589 // Interior of complex instruction. Do nothing but recurse.
1590 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1591 } else {
1592 // instruction --> call build operand( ) to catch result
1593 // --> ReduceInst( newrule )
1594 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1595 Node *mem1 = (Node*)1;
1596 debug_only(Node *save_mem_node = _mem_node;)
1597 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1598 debug_only(_mem_node = save_mem_node;)
1599 }
1600 }
1601 assert( mach->_opnds[num_opnds-1], "" );
1602 }
1603 return num_opnds;
1604 }
1605
1606 // This routine walks the interior of possible complex operands.
1607 // At each point we check our children in the match tree:
1608 // (1) No children -
1609 // We are a leaf; add _leaf field as an input to the MachNode
1610 // (2) Child is an internal operand -
1611 // Skip over it ( do nothing )
1612 // (3) Child is an instruction -
1613 // Call ReduceInst recursively and
1614 // and instruction as an input to the MachNode
1615 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1616 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1617 State *kid = s->_kids[0];
1618 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1619
1620 // Leaf? And not subsumed?
1621 if( kid == NULL && !_swallowed[rule] ) {
1622 mach->add_req( s->_leaf ); // Add leaf pointer
1623 return; // Bail out
1624 }
1625
1626 if( s->_leaf->is_Load() ) {
1627 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1628 mem = s->_leaf->in(MemNode::Memory);
1629 debug_only(_mem_node = s->_leaf;)
1630 }
1631 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1632 if( !mach->in(0) )
1633 mach->set_req(0,s->_leaf->in(0));
1634 else {
1635 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1636 }
1637 }
1638
1639 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1640 int newrule;
1641 if( i == 0 )
1642 newrule = kid->_rule[_leftOp[rule]];
1643 else
1644 newrule = kid->_rule[_rightOp[rule]];
1645
1646 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1647 // Internal operand; recurse but do nothing else
1648 ReduceOper( kid, newrule, mem, mach );
1649
1650 } else { // Child is a new instruction
1651 // Reduce the instruction, and add a direct pointer from this
1652 // machine instruction to the newly reduced one.
1653 Node *mem1 = (Node*)1;
1654 debug_only(Node *save_mem_node = _mem_node;)
1655 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1656 debug_only(_mem_node = save_mem_node;)
1657 }
1658 }
1659 }
1660
1661
1662 // -------------------------------------------------------------------------
1663 // Java-Java calling convention
1664 // (what you use when Java calls Java)
1665
1666 //------------------------------find_receiver----------------------------------
1667 // For a given signature, return the OptoReg for parameter 0.
1668 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1669 VMRegPair regs;
1670 BasicType sig_bt = T_OBJECT;
1671 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1672 // Return argument 0 register. In the LP64 build pointers
1673 // take 2 registers, but the VM wants only the 'main' name.
1674 return OptoReg::as_OptoReg(regs.first());
1675 }
1676
1677 // A method-klass-holder may be passed in the inline_cache_reg
1678 // and then expanded into the inline_cache_reg and a method_oop register
1679 // defined in ad_<arch>.cpp
1680
1681
1682 //------------------------------find_shared------------------------------------
1683 // Set bits if Node is shared or otherwise a root
1684 void Matcher::find_shared( Node *n ) {
1685 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1686 MStack mstack(C->unique() * 2);
1687 mstack.push(n, Visit); // Don't need to pre-visit root node
1688 while (mstack.is_nonempty()) {
1689 n = mstack.node(); // Leave node on stack
1690 Node_State nstate = mstack.state();
1691 if (nstate == Pre_Visit) {
1692 if (is_visited(n)) { // Visited already?
1693 // Node is shared and has no reason to clone. Flag it as shared.
1694 // This causes it to match into a register for the sharing.
1695 set_shared(n); // Flag as shared and
1696 mstack.pop(); // remove node from stack
1697 continue;
1698 }
1699 nstate = Visit; // Not already visited; so visit now
1700 }
1701 if (nstate == Visit) {
1702 mstack.set_state(Post_Visit);
1703 set_visited(n); // Flag as visited now
1704 bool mem_op = false;
1705
1706 switch( n->Opcode() ) { // Handle some opcodes special
1707 case Op_Phi: // Treat Phis as shared roots
1708 case Op_Parm:
1709 case Op_Proj: // All handled specially during matching
1710 case Op_SafePointScalarObject:
1711 set_shared(n);
1712 set_dontcare(n);
1713 break;
1714 case Op_If:
1715 case Op_CountedLoopEnd:
1716 mstack.set_state(Alt_Post_Visit); // Alternative way
1717 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1718 // with matching cmp/branch in 1 instruction. The Matcher needs the
1719 // Bool and CmpX side-by-side, because it can only get at constants
1720 // that are at the leaves of Match trees, and the Bool's condition acts
1721 // as a constant here.
1722 mstack.push(n->in(1), Visit); // Clone the Bool
1723 mstack.push(n->in(0), Pre_Visit); // Visit control input
1724 continue; // while (mstack.is_nonempty())
1725 case Op_ConvI2D: // These forms efficiently match with a prior
1726 case Op_ConvI2F: // Load but not a following Store
1727 if( n->in(1)->is_Load() && // Prior load
1728 n->outcnt() == 1 && // Not already shared
1729 n->unique_out()->is_Store() ) // Following store
1730 set_shared(n); // Force it to be a root
1731 break;
1732 case Op_ReverseBytesI:
1733 case Op_ReverseBytesL:
1734 if( n->in(1)->is_Load() && // Prior load
1735 n->outcnt() == 1 ) // Not already shared
1736 set_shared(n); // Force it to be a root
1737 break;
1738 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1739 case Op_IfFalse:
1740 case Op_IfTrue:
1741 case Op_MachProj:
1742 case Op_MergeMem:
1743 case Op_Catch:
1744 case Op_CatchProj:
1745 case Op_CProj:
1746 case Op_JumpProj:
1747 case Op_JProj:
1748 case Op_NeverBranch:
1749 set_dontcare(n);
1750 break;
1751 case Op_Jump:
1752 mstack.push(n->in(1), Visit); // Switch Value
1753 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1754 continue; // while (mstack.is_nonempty())
1755 case Op_StrComp:
1756 case Op_AryEq:
1757 set_shared(n); // Force result into register (it will be anyways)
1758 break;
1759 case Op_ConP: { // Convert pointers above the centerline to NUL
1760 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1761 const TypePtr* tp = tn->type()->is_ptr();
1762 if (tp->_ptr == TypePtr::AnyNull) {
1763 tn->set_type(TypePtr::NULL_PTR);
1764 }
1765 break;
1766 }
1767 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1768 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1769 const TypePtr* tp = tn->type()->is_narrowoop()->make_oopptr();
1770 if (tp->_ptr == TypePtr::AnyNull) {
1771 tn->set_type(TypeNarrowOop::NULL_PTR);
1772 }
1773 break;
1774 }
1775 case Op_Binary: // These are introduced in the Post_Visit state.
1776 ShouldNotReachHere();
1777 break;
1778 case Op_StoreB: // Do match these, despite no ideal reg
1779 case Op_StoreC:
1780 case Op_StoreCM:
1781 case Op_StoreD:
1782 case Op_StoreF:
1783 case Op_StoreI:
1784 case Op_StoreL:
1785 case Op_StoreP:
1786 case Op_StoreN:
1787 case Op_Store16B:
1788 case Op_Store8B:
1789 case Op_Store4B:
1790 case Op_Store8C:
1791 case Op_Store4C:
1792 case Op_Store2C:
1793 case Op_Store4I:
1794 case Op_Store2I:
1795 case Op_Store2L:
1796 case Op_Store4F:
1797 case Op_Store2F:
1798 case Op_Store2D:
1799 case Op_ClearArray:
1800 case Op_SafePoint:
1801 mem_op = true;
1802 break;
1803 case Op_LoadB:
1804 case Op_LoadC:
1805 case Op_LoadD:
1806 case Op_LoadF:
1807 case Op_LoadI:
1808 case Op_LoadKlass:
1809 case Op_LoadNKlass:
1810 case Op_LoadL:
1811 case Op_LoadS:
1812 case Op_LoadP:
1813 case Op_LoadN:
1814 case Op_LoadRange:
1815 case Op_LoadD_unaligned:
1816 case Op_LoadL_unaligned:
1817 case Op_Load16B:
1818 case Op_Load8B:
1819 case Op_Load4B:
1820 case Op_Load4C:
1821 case Op_Load2C:
1822 case Op_Load8C:
1823 case Op_Load8S:
1824 case Op_Load4S:
1825 case Op_Load2S:
1826 case Op_Load4I:
1827 case Op_Load2I:
1828 case Op_Load2L:
1829 case Op_Load4F:
1830 case Op_Load2F:
1831 case Op_Load2D:
1832 mem_op = true;
1833 // Must be root of match tree due to prior load conflict
1834 if( C->subsume_loads() == false ) {
1835 set_shared(n);
1836 }
1837 // Fall into default case
1838 default:
1839 if( !n->ideal_reg() )
1840 set_dontcare(n); // Unmatchable Nodes
1841 } // end_switch
1842
1843 for(int i = n->req() - 1; i >= 0; --i) { // For my children
1844 Node *m = n->in(i); // Get ith input
1845 if (m == NULL) continue; // Ignore NULLs
1846 uint mop = m->Opcode();
1847
1848 // Must clone all producers of flags, or we will not match correctly.
1849 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
1850 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
1851 // are also there, so we may match a float-branch to int-flags and
1852 // expect the allocator to haul the flags from the int-side to the
1853 // fp-side. No can do.
1854 if( _must_clone[mop] ) {
1855 mstack.push(m, Visit);
1856 continue; // for(int i = ...)
1857 }
1858
1859 // Clone addressing expressions as they are "free" in most instructions
1860 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
1861 Node *off = m->in(AddPNode::Offset);
1862 if( off->is_Con() ) {
1863 set_visited(m); // Flag as visited now
1864 Node *adr = m->in(AddPNode::Address);
1865
1866 // Intel, ARM and friends can handle 2 adds in addressing mode
1867 if( clone_shift_expressions && adr->is_AddP() &&
1868 // AtomicAdd is not an addressing expression.
1869 // Cheap to find it by looking for screwy base.
1870 !adr->in(AddPNode::Base)->is_top() ) {
1871 set_visited(adr); // Flag as visited now
1872 Node *shift = adr->in(AddPNode::Offset);
1873 // Check for shift by small constant as well
1874 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
1875 shift->in(2)->get_int() <= 3 ) {
1876 set_visited(shift); // Flag as visited now
1877 mstack.push(shift->in(2), Visit);
1878 #ifdef _LP64
1879 // Allow Matcher to match the rule which bypass
1880 // ConvI2L operation for an array index on LP64
1881 // if the index value is positive.
1882 if( shift->in(1)->Opcode() == Op_ConvI2L &&
1883 shift->in(1)->as_Type()->type()->is_long()->_lo >= 0 ) {
1884 set_visited(shift->in(1)); // Flag as visited now
1885 mstack.push(shift->in(1)->in(1), Pre_Visit);
1886 } else
1887 #endif
1888 mstack.push(shift->in(1), Pre_Visit);
1889 } else {
1890 mstack.push(shift, Pre_Visit);
1891 }
1892 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
1893 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
1894 } else { // Sparc, Alpha, PPC and friends
1895 mstack.push(adr, Pre_Visit);
1896 }
1897
1898 // Clone X+offset as it also folds into most addressing expressions
1899 mstack.push(off, Visit);
1900 mstack.push(m->in(AddPNode::Base), Pre_Visit);
1901 continue; // for(int i = ...)
1902 } // if( off->is_Con() )
1903 } // if( mem_op &&
1904 mstack.push(m, Pre_Visit);
1905 } // for(int i = ...)
1906 }
1907 else if (nstate == Alt_Post_Visit) {
1908 mstack.pop(); // Remove node from stack
1909 // We cannot remove the Cmp input from the Bool here, as the Bool may be
1910 // shared and all users of the Bool need to move the Cmp in parallel.
1911 // This leaves both the Bool and the If pointing at the Cmp. To
1912 // prevent the Matcher from trying to Match the Cmp along both paths
1913 // BoolNode::match_edge always returns a zero.
1914
1915 // We reorder the Op_If in a pre-order manner, so we can visit without
1916 // accidently sharing the Cmp (the Bool and the If make 2 users).
1917 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
1918 }
1919 else if (nstate == Post_Visit) {
1920 mstack.pop(); // Remove node from stack
1921
1922 // Now hack a few special opcodes
1923 switch( n->Opcode() ) { // Handle some opcodes special
1924 case Op_StorePConditional:
1925 case Op_StoreLConditional:
1926 case Op_CompareAndSwapI:
1927 case Op_CompareAndSwapL:
1928 case Op_CompareAndSwapP:
1929 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
1930 Node *newval = n->in(MemNode::ValueIn );
1931 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
1932 Node *pair = new (C, 3) BinaryNode( oldval, newval );
1933 n->set_req(MemNode::ValueIn,pair);
1934 n->del_req(LoadStoreNode::ExpectedIn);
1935 break;
1936 }
1937 case Op_CMoveD: // Convert trinary to binary-tree
1938 case Op_CMoveF:
1939 case Op_CMoveI:
1940 case Op_CMoveL:
1941 case Op_CMoveN:
1942 case Op_CMoveP: {
1943 // Restructure into a binary tree for Matching. It's possible that
1944 // we could move this code up next to the graph reshaping for IfNodes
1945 // or vice-versa, but I do not want to debug this for Ladybird.
1946 // 10/2/2000 CNC.
1947 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
1948 n->set_req(1,pair1);
1949 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
1950 n->set_req(2,pair2);
1951 n->del_req(3);
1952 break;
1953 }
1954 default:
1955 break;
1956 }
1957 }
1958 else {
1959 ShouldNotReachHere();
1960 }
1961 } // end of while (mstack.is_nonempty())
1962 }
1963
1964 #ifdef ASSERT
1965 // machine-independent root to machine-dependent root
1966 void Matcher::dump_old2new_map() {
1967 _old2new_map.dump();
1968 }
1969 #endif
1970
1971 //---------------------------collect_null_checks-------------------------------
1972 // Find null checks in the ideal graph; write a machine-specific node for
1973 // it. Used by later implicit-null-check handling. Actually collects
1974 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
1975 // value being tested.
1976 void Matcher::collect_null_checks( Node *proj ) {
1977 Node *iff = proj->in(0);
1978 if( iff->Opcode() == Op_If ) {
1979 // During matching If's have Bool & Cmp side-by-side
1980 BoolNode *b = iff->in(1)->as_Bool();
1981 Node *cmp = iff->in(2);
1982 int opc = cmp->Opcode();
1983 if (opc != Op_CmpP && opc != Op_CmpN) return;
1984
1985 const Type* ct = cmp->in(2)->bottom_type();
1986 if (ct == TypePtr::NULL_PTR ||
1987 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
1988
1989 if( proj->Opcode() == Op_IfTrue ) {
1990 extern int all_null_checks_found;
1991 all_null_checks_found++;
1992 if( b->_test._test == BoolTest::ne ) {
1993 _null_check_tests.push(proj);
1994 _null_check_tests.push(cmp->in(1));
1995 }
1996 } else {
1997 assert( proj->Opcode() == Op_IfFalse, "" );
1998 if( b->_test._test == BoolTest::eq ) {
1999 _null_check_tests.push(proj);
2000 _null_check_tests.push(cmp->in(1));
2001 }
2002 }
2003 }
2004 }
2005 }
2006
2007 //---------------------------validate_null_checks------------------------------
2008 // Its possible that the value being NULL checked is not the root of a match
2009 // tree. If so, I cannot use the value in an implicit null check.
2010 void Matcher::validate_null_checks( ) {
2011 uint cnt = _null_check_tests.size();
2012 for( uint i=0; i < cnt; i+=2 ) {
2013 Node *test = _null_check_tests[i];
2014 Node *val = _null_check_tests[i+1];
2015 if (has_new_node(val)) {
2016 // Is a match-tree root, so replace with the matched value
2017 _null_check_tests.map(i+1, new_node(val));
2018 } else {
2019 // Yank from candidate list
2020 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2021 _null_check_tests.map(i,_null_check_tests[--cnt]);
2022 _null_check_tests.pop();
2023 _null_check_tests.pop();
2024 i-=2;
2025 }
2026 }
2027 }
2028
2029
2030 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
2031 // acting as an Acquire and thus we don't need an Acquire here. We
2032 // retain the Node to act as a compiler ordering barrier.
2033 bool Matcher::prior_fast_lock( const Node *acq ) {
2034 Node *r = acq->in(0);
2035 if( !r->is_Region() || r->req() <= 1 ) return false;
2036 Node *proj = r->in(1);
2037 if( !proj->is_Proj() ) return false;
2038 Node *call = proj->in(0);
2039 if( !call->is_Call() || call->as_Call()->entry_point() != OptoRuntime::complete_monitor_locking_Java() )
2040 return false;
2041
2042 return true;
2043 }
2044
2045 // Used by the DFA in dfa_sparc.cpp. Check for a following FastUnLock
2046 // acting as a Release and thus we don't need a Release here. We
2047 // retain the Node to act as a compiler ordering barrier.
2048 bool Matcher::post_fast_unlock( const Node *rel ) {
2049 Compile *C = Compile::current();
2050 assert( rel->Opcode() == Op_MemBarRelease, "" );
2051 const MemBarReleaseNode *mem = (const MemBarReleaseNode*)rel;
2052 DUIterator_Fast imax, i = mem->fast_outs(imax);
2053 Node *ctrl = NULL;
2054 while( true ) {
2055 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2056 assert( ctrl->is_Proj(), "only projections here" );
2057 ProjNode *proj = (ProjNode*)ctrl;
2058 if( proj->_con == TypeFunc::Control &&
2059 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2060 break;
2061 i++;
2062 }
2063 Node *iff = NULL;
2064 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2065 Node *x = ctrl->fast_out(j);
2066 if( x->is_If() && x->req() > 1 &&
2067 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2068 iff = x;
2069 break;
2070 }
2071 }
2072 if( !iff ) return false;
2073 Node *bol = iff->in(1);
2074 // The iff might be some random subclass of If or bol might be Con-Top
2075 if (!bol->is_Bool()) return false;
2076 assert( bol->req() > 1, "" );
2077 return (bol->in(1)->Opcode() == Op_FastUnlock);
2078 }
2079
2080 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2081 // atomic instruction acting as a store_load barrier without any
2082 // intervening volatile load, and thus we don't need a barrier here.
2083 // We retain the Node to act as a compiler ordering barrier.
2084 bool Matcher::post_store_load_barrier(const Node *vmb) {
2085 Compile *C = Compile::current();
2086 assert( vmb->is_MemBar(), "" );
2087 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2088 const MemBarNode *mem = (const MemBarNode*)vmb;
2089
2090 // Get the Proj node, ctrl, that can be used to iterate forward
2091 Node *ctrl = NULL;
2092 DUIterator_Fast imax, i = mem->fast_outs(imax);
2093 while( true ) {
2094 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2095 assert( ctrl->is_Proj(), "only projections here" );
2096 ProjNode *proj = (ProjNode*)ctrl;
2097 if( proj->_con == TypeFunc::Control &&
2098 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2099 break;
2100 i++;
2101 }
2102
2103 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2104 Node *x = ctrl->fast_out(j);
2105 int xop = x->Opcode();
2106
2107 // We don't need current barrier if we see another or a lock
2108 // before seeing volatile load.
2109 //
2110 // Op_Fastunlock previously appeared in the Op_* list below.
2111 // With the advent of 1-0 lock operations we're no longer guaranteed
2112 // that a monitor exit operation contains a serializing instruction.
2113
2114 if (xop == Op_MemBarVolatile ||
2115 xop == Op_FastLock ||
2116 xop == Op_CompareAndSwapL ||
2117 xop == Op_CompareAndSwapP ||
2118 xop == Op_CompareAndSwapN ||
2119 xop == Op_CompareAndSwapI)
2120 return true;
2121
2122 if (x->is_MemBar()) {
2123 // We must retain this membar if there is an upcoming volatile
2124 // load, which will be preceded by acquire membar.
2125 if (xop == Op_MemBarAcquire)
2126 return false;
2127 // For other kinds of barriers, check by pretending we
2128 // are them, and seeing if we can be removed.
2129 else
2130 return post_store_load_barrier((const MemBarNode*)x);
2131 }
2132
2133 // Delicate code to detect case of an upcoming fastlock block
2134 if( x->is_If() && x->req() > 1 &&
2135 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2136 Node *iff = x;
2137 Node *bol = iff->in(1);
2138 // The iff might be some random subclass of If or bol might be Con-Top
2139 if (!bol->is_Bool()) return false;
2140 assert( bol->req() > 1, "" );
2141 return (bol->in(1)->Opcode() == Op_FastUnlock);
2142 }
2143 // probably not necessary to check for these
2144 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2145 return false;
2146 }
2147 return false;
2148 }
2149
2150 //=============================================================================
2151 //---------------------------State---------------------------------------------
2152 State::State(void) {
2153 #ifdef ASSERT
2154 _id = 0;
2155 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2156 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2157 //memset(_cost, -1, sizeof(_cost));
2158 //memset(_rule, -1, sizeof(_rule));
2159 #endif
2160 memset(_valid, 0, sizeof(_valid));
2161 }
2162
2163 #ifdef ASSERT
2164 State::~State() {
2165 _id = 99;
2166 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2167 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2168 memset(_cost, -3, sizeof(_cost));
2169 memset(_rule, -3, sizeof(_rule));
2170 }
2171 #endif
2172
2173 #ifndef PRODUCT
2174 //---------------------------dump----------------------------------------------
2175 void State::dump() {
2176 tty->print("\n");
2177 dump(0);
2178 }
2179
2180 void State::dump(int depth) {
2181 for( int j = 0; j < depth; j++ )
2182 tty->print(" ");
2183 tty->print("--N: ");
2184 _leaf->dump();
2185 uint i;
2186 for( i = 0; i < _LAST_MACH_OPER; i++ )
2187 // Check for valid entry
2188 if( valid(i) ) {
2189 for( int j = 0; j < depth; j++ )
2190 tty->print(" ");
2191 assert(_cost[i] != max_juint, "cost must be a valid value");
2192 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2193 tty->print_cr("%s %d %s",
2194 ruleName[i], _cost[i], ruleName[_rule[i]] );
2195 }
2196 tty->print_cr("");
2197
2198 for( i=0; i<2; i++ )
2199 if( _kids[i] )
2200 _kids[i]->dump(depth+1);
2201 }
2202 #endif