*** old/src/cpu/x86/vm/x86_64.ad	Wed Jun  4 12:01:45 2008
--- new/src/cpu/x86/vm/x86_64.ad	Wed Jun  4 12:01:45 2008

*** 1838,1859 ****
--- 1838,1856 ----
  //=============================================================================
  #ifndef PRODUCT
  void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
  {
    if (UseCompressedOops) {
!     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
!     st->print_cr("leaq    rscratch1, [r12_heapbase, r, Address::times_8, 0]");
!     st->print_cr("cmpq    rax, rscratch1\t # Inline cache check");
!     st->print("subq    rax, r12_heapbase\t # encode_heap_oop_not_null(rax)\n\t");
!     st->print("shrq    rax, %d\n\t", LogMinObjAlignmentInBytes);
!     st->print_cr("cmpl    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
+                  "# Inline cache check", oopDesc::klass_offset_in_bytes());
    } else {
      st->print_cr("cmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
                   "# Inline cache check", oopDesc::klass_offset_in_bytes());
    }
    st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
    st->print_cr("\tnop");
    if (!OptoBreakpoint) {
      st->print_cr("\tnop");
    }
  }
  #endif
  
  void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
  {

*** 1860,1901 ****
--- 1857,1887 ----
    MacroAssembler masm(&cbuf);
  #ifdef ASSERT
    uint code_size = cbuf.code_size();
  #endif
    if (UseCompressedOops) {
!     masm.load_klass(rscratch1, j_rarg0);
!     masm.cmpq(rax, rscratch1);
!     // masm.encode_heap_oop_not_null(rax);
!     masm.subq(rax, r12_heapbase);
+     masm.shrq(rax, LogMinObjAlignmentInBytes);
+     masm.cmpl(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
    } else {
      masm.cmpq(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
    }
  
    masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
  
    /* WARNING these NOPs are critical so that verified entry point is properly
!      aligned (4 bytes) for patching by NativeJump::patch_verified_entry() */
    int nops_cnt = 1;
    if (!OptoBreakpoint) {
      // Leave space for int3
       nops_cnt += 1;
    }
    if (UseCompressedOops) {
      // ??? divisible by 4 is aligned?
      nops_cnt += 1;
    }
    masm.nop(nops_cnt);
  
    assert(cbuf.code_size() - code_size == size(ra_),
!          "checking code size of inline cache node");
+   // C2 aligns Start block (verified entry point) to InteriorEntryAlignment
!   assert((InteriorEntryAlignment & 0x3) == 0, "verified entry point should be aligned to 4 bytes");
  }
  
  uint MachUEPNode::size(PhaseRegAlloc* ra_) const
  {
    if (UseCompressedOops) {
      return OptoBreakpoint ? 19 : 20;
    } else {
      return OptoBreakpoint ? 11 : 12;
    }
+   return MachNode::size(ra_); // too many variables; just compute it
+                               // the hard way
  }
  
  
  //=============================================================================
  uint size_exception_handler()

*** 6147,6157 ****
--- 6133,6143 ----
  instruct loadNKlass(rRegN dst, memory mem)
  %{
    match(Set dst (LoadNKlass mem));
  
    ins_cost(125); // XXX
-   format %{ "movl    $dst, $mem\t# compressed klass ptr\n\t" %}
    ins_encode %{
      Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
      Register dst = as_Register($dst$$reg);
      __ movl(dst, addr);
    %}