*** old/src/cpu/x86/vm/x86_32.ad	Wed Jun  4 12:01:43 2008
--- new/src/cpu/x86/vm/x86_32.ad	Wed Jun  4 12:01:43 2008

*** 1167,1203 ****
--- 1167,1194 ----
  //=============================================================================
  #ifndef PRODUCT
  void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
    st->print_cr(  "CMP    EAX,[ECX+4]\t# Inline cache check");
    st->print_cr("\tJNE    SharedRuntime::handle_ic_miss_stub");
    st->print_cr("\tNOP");
    st->print_cr("\tNOP");
    if( !OptoBreakpoint )
      st->print_cr("\tNOP");
  }
  #endif
  
  void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
    MacroAssembler masm(&cbuf);
  #ifdef ASSERT
    uint code_size = cbuf.code_size();
  #endif
    masm.cmpl(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
    masm.jump_cc(Assembler::notEqual,
                 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
    /* WARNING these NOPs are critical so that verified entry point is properly
!      aligned (4 bytes) for patching by NativeJump::patch_verified_entry() */
    int nops_cnt = 2;
    if( !OptoBreakpoint ) // Leave space for int3
       nops_cnt += 1;
    masm.nop(nops_cnt);
  
    assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
+   // C2 aligns Start block (verified entry point) to InteriorEntryAlignment
+   assert((InteriorEntryAlignment & 0x3) == 0, "verified entry point should be aligned to 4 bytes");
  }
  
  uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
!   return OptoBreakpoint ? 11 : 12;
!   return MachNode::size(ra_); // too many variables; just compute it
+                               // the hard way
  }
  
  
  //=============================================================================
  uint size_exception_handler() {