1 /*
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for x86 assembly code generation.
28
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
48
49
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
53
54 #ifdef _WIN64
55
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
60
61 REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
65
66 #else
67
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
74
75 REGISTER_DECLARATION(FloatRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(FloatRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(FloatRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(FloatRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(FloatRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(FloatRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(FloatRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(FloatRegister, c_farg7, xmm7);
83
84 #endif // _WIN64
85
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
101
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
114
115 REGISTER_DECLARATION(FloatRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(FloatRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(FloatRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(FloatRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(FloatRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(FloatRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(FloatRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(FloatRegister, j_farg7, xmm7);
123
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
126
127 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
128
129 #endif // _LP64
130
131 // Address is an abstraction used to represent a memory location
132 // using any of the amd64 addressing modes with one object.
133 //
134 // Note: A register location is represented via a Register, not
135 // via an address for efficiency & simplicity reasons.
136
137 class ArrayAddress;
138
139 class Address VALUE_OBJ_CLASS_SPEC {
140 public:
141 enum ScaleFactor {
142 no_scale = -1,
143 times_1 = 0,
144 times_2 = 1,
145 times_4 = 2,
146 times_8 = 3
147 };
148
149 private:
150 Register _base;
151 Register _index;
152 ScaleFactor _scale;
153 int _disp;
154 RelocationHolder _rspec;
155
156 // Easily misused constructor make them private
157 #ifndef _LP64
158 Address(address loc, RelocationHolder spec);
159 #endif // _LP64
160
161 public:
162 // creation
163 Address()
164 : _base(noreg),
165 _index(noreg),
166 _scale(no_scale),
167 _disp(0) {
168 }
169
170 // No default displacement otherwise Register can be implicitly
171 // converted to 0(Register) which is quite a different animal.
172
173 Address(Register base, int disp)
174 : _base(base),
175 _index(noreg),
176 _scale(no_scale),
177 _disp(disp) {
178 }
179
180 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
181 : _base (base),
182 _index(index),
183 _scale(scale),
184 _disp (disp) {
185 assert(!index->is_valid() == (scale == Address::no_scale),
186 "inconsistent address");
187 }
188
189 // The following two overloads are used in connection with the
190 // ByteSize type (see sizes.hpp). They simplify the use of
191 // ByteSize'd arguments in assembly code. Note that their equivalent
192 // for the optimized build are the member functions with int disp
193 // argument since ByteSize is mapped to an int type in that case.
194 //
195 // Note: DO NOT introduce similar overloaded functions for WordSize
196 // arguments as in the optimized mode, both ByteSize and WordSize
197 // are mapped to the same type and thus the compiler cannot make a
198 // distinction anymore (=> compiler errors).
199
200 #ifdef ASSERT
201 Address(Register base, ByteSize disp)
202 : _base(base),
203 _index(noreg),
204 _scale(no_scale),
205 _disp(in_bytes(disp)) {
206 }
207
208 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
209 : _base(base),
210 _index(index),
211 _scale(scale),
212 _disp(in_bytes(disp)) {
213 assert(!index->is_valid() == (scale == Address::no_scale),
214 "inconsistent address");
215 }
216 #endif // ASSERT
217
218 // accessors
219 bool uses(Register reg) const {
220 return _base == reg || _index == reg;
221 }
222
223 // Convert the raw encoding form into the form expected by the constructor for
224 // Address. An index of 4 (rsp) corresponds to having no index, so convert
225 // that to noreg for the Address constructor.
226 static Address make_raw(int base, int index, int scale, int disp);
227
228 static Address make_array(ArrayAddress);
229
230
231 private:
232 bool base_needs_rex() const {
233 return _base != noreg && _base->encoding() >= 8;
234 }
235
236 bool index_needs_rex() const {
237 return _index != noreg &&_index->encoding() >= 8;
238 }
239
240 relocInfo::relocType reloc() const { return _rspec.type(); }
241
242 friend class Assembler;
243 friend class MacroAssembler;
244 friend class LIR_Assembler; // base/index/scale/disp
245 };
246
247 //
248 // AddressLiteral has been split out from Address because operands of this type
249 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
250 // the few instructions that need to deal with address literals are unique and the
251 // MacroAssembler does not have to implement every instruction in the Assembler
252 // in order to search for address literals that may need special handling depending
253 // on the instruction and the platform. As small step on the way to merging i486/amd64
254 // directories.
255 //
256 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
257 friend class ArrayAddress;
258 RelocationHolder _rspec;
259 // Typically we use AddressLiterals we want to use their rval
260 // However in some situations we want the lval (effect address) of the item.
261 // We provide a special factory for making those lvals.
262 bool _is_lval;
263
264 // If the target is far we'll need to load the ea of this to
265 // a register to reach it. Otherwise if near we can do rip
266 // relative addressing.
267
268 address _target;
269
270 protected:
271 // creation
272 AddressLiteral()
273 : _is_lval(false),
274 _target(NULL)
275 {}
276
277 public:
278
279
280 AddressLiteral(address target, relocInfo::relocType rtype);
281
282 AddressLiteral(address target, RelocationHolder const& rspec)
283 : _rspec(rspec),
284 _is_lval(false),
285 _target(target)
286 {}
287
288 AddressLiteral addr() {
289 AddressLiteral ret = *this;
290 ret._is_lval = true;
291 return ret;
292 }
293
294
295 private:
296
297 address target() { return _target; }
298 bool is_lval() { return _is_lval; }
299
300 relocInfo::relocType reloc() const { return _rspec.type(); }
301 const RelocationHolder& rspec() const { return _rspec; }
302
303 friend class Assembler;
304 friend class MacroAssembler;
305 friend class Address;
306 friend class LIR_Assembler;
307 };
308
309 // Convience classes
310 class RuntimeAddress: public AddressLiteral {
311
312 public:
313
314 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
315
316 };
317
318 class OopAddress: public AddressLiteral {
319
320 public:
321
322 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
323
324 };
325
326 class ExternalAddress: public AddressLiteral {
327
328 public:
329
330 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
331
332 };
333
334 class InternalAddress: public AddressLiteral {
335
336 public:
337
338 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
339
340 };
341
342 // x86 can do array addressing as a single operation since disp can be an absolute
343 // address amd64 can't. We create a class that expresses the concept but does extra
344 // magic on amd64 to get the final result
345
346 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
347 private:
348
349 AddressLiteral _base;
350 Address _index;
351
352 public:
353
354 ArrayAddress() {};
355 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
356 AddressLiteral base() { return _base; }
357 Address index() { return _index; }
358
359 };
360
361 #ifndef _LP64
362 const int FPUStateSizeInWords = 27;
363 #else
364 const int FPUStateSizeInWords = 512 / wordSize;
365 #endif // _LP64
366
367 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
368 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
369 // is what you get. The Assembler is generating code into a CodeBuffer.
370
371 class Assembler : public AbstractAssembler {
372 friend class AbstractAssembler; // for the non-virtual hack
373 friend class LIR_Assembler; // as_Address()
374
375 protected:
376 #ifdef ASSERT
377 void check_relocation(RelocationHolder const& rspec, int format);
378 #endif
379
380 inline void emit_long64(jlong x);
381
382 void emit_data(jint data, relocInfo::relocType rtype, int format /* = 0 */);
383 void emit_data(jint data, RelocationHolder const& rspec, int format /* = 0 */);
384 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
385 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
386
387 // Helper functions for groups of instructions
388 void emit_arith_b(int op1, int op2, Register dst, int imm8);
389
390 void emit_arith(int op1, int op2, Register dst, int imm32);
391 // only x86??
392 void emit_arith(int op1, int op2, Register dst, jobject obj);
393 void emit_arith(int op1, int op2, Register dst, Register src);
394
395 void emit_operand(Register reg,
396 Register base, Register index, Address::ScaleFactor scale,
397 int disp,
398 RelocationHolder const& rspec);
399 void emit_operand(Register reg, Address adr);
400
401 // Immediate-to-memory forms
402 void emit_arith_operand(int op1, Register rm, Address adr, int imm32);
403
404 void emit_farith(int b1, int b2, int i);
405
406 // macroassembler?? QQQ
407 bool reachable(AddressLiteral adr) { return true; }
408
409 // These are all easily abused and hence protected
410
411 // Make these disappear in 64bit mode since they would never be correct
412 #ifndef _LP64
413 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);
414 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);
415
416 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);
417 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);
418
419 void push_literal32(int32_t imm32, RelocationHolder const& rspec);
420 #endif // _LP64
421
422 // These are unique in that we are ensured by the caller that the 32bit
423 // relative in these instructions will always be able to reach the potentially
424 // 64bit address described by entry. Since they can take a 64bit address they
425 // don't have the 32 suffix like the other instructions in this class.
426
427 void call_literal(address entry, RelocationHolder const& rspec);
428 void jmp_literal(address entry, RelocationHolder const& rspec);
429
430
431 public:
432 enum Condition { // The x86 condition codes used for conditional jumps/moves.
433 zero = 0x4,
434 notZero = 0x5,
435 equal = 0x4,
436 notEqual = 0x5,
437 less = 0xc,
438 lessEqual = 0xe,
439 greater = 0xf,
440 greaterEqual = 0xd,
441 below = 0x2,
442 belowEqual = 0x6,
443 above = 0x7,
444 aboveEqual = 0x3,
445 overflow = 0x0,
446 noOverflow = 0x1,
447 carrySet = 0x2,
448 carryClear = 0x3,
449 negative = 0x8,
450 positive = 0x9,
451 parity = 0xa,
452 noParity = 0xb
453 };
454
455 enum Prefix {
456 // segment overrides
457 CS_segment = 0x2e,
458 SS_segment = 0x36,
459 DS_segment = 0x3e,
460 ES_segment = 0x26,
461 FS_segment = 0x64,
462 GS_segment = 0x65,
463
464 REX = 0x40,
465
466 REX_B = 0x41,
467 REX_X = 0x42,
468 REX_XB = 0x43,
469 REX_R = 0x44,
470 REX_RB = 0x45,
471 REX_RX = 0x46,
472 REX_RXB = 0x47,
473
474 REX_W = 0x48,
475
476 REX_WB = 0x49,
477 REX_WX = 0x4A,
478 REX_WXB = 0x4B,
479 REX_WR = 0x4C,
480 REX_WRB = 0x4D,
481 REX_WRX = 0x4E,
482 REX_WRXB = 0x4F
483 };
484
485 enum WhichOperand {
486 // input to locate_operand, and format code for relocations
487 imm32_operand = 0, // embedded 32-bit immediate operand
488 disp32_operand = 1, // embedded 32-bit displacement or address
489 call32_operand = 2, // embedded 32-bit self-relative displacement
490 _WhichOperand_limit = 3
491 };
492
493 public:
494
495 // Creation
496 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
497
498 // Decoding
499 static address locate_operand(address inst, WhichOperand which);
500 static address locate_next_instruction(address inst);
501
502 // Stack
503 void pushad();
504 void popad();
505
506 void pushfd();
507 void popfd();
508
509 void pushl(int imm32);
510 void pushoop(jobject obj);
511
512 void pushl(Register src);
513 void pushl(Address src);
514 // void pushl(Label& L, relocInfo::relocType rtype); ? needed?
515
516 // dummy to prevent NULL being converted to Register
517 void pushl(void* dummy);
518
519 void popl(Register dst);
520 void popl(Address dst);
521
522 // Instruction prefixes
523 void prefix(Prefix p);
524
525 // Moves
526 void movb(Register dst, Address src);
527 void movb(Address dst, int imm8);
528 void movb(Address dst, Register src);
529
530 void movw(Address dst, int imm16);
531 void movw(Register dst, Address src);
532 void movw(Address dst, Register src);
533
534 // these are dummies used to catch attempting to convert NULL to Register
535 void movl(Register dst, void* junk);
536 void movl(Address dst, void* junk);
537
538 void movl(Register dst, int imm32);
539 void movl(Address dst, int imm32);
540 void movl(Register dst, Register src);
541 void movl(Register dst, Address src);
542 void movl(Address dst, Register src);
543
544 void movsxb(Register dst, Address src);
545 void movsxb(Register dst, Register src);
546
547 void movsxw(Register dst, Address src);
548 void movsxw(Register dst, Register src);
549
550 void movzxb(Register dst, Address src);
551 void movzxb(Register dst, Register src);
552
553 void movzxw(Register dst, Address src);
554 void movzxw(Register dst, Register src);
555
556 // Conditional moves (P6 only)
557 void cmovl(Condition cc, Register dst, Register src);
558 void cmovl(Condition cc, Register dst, Address src);
559
560 // Prefetches (SSE, SSE2, 3DNOW only)
561 void prefetcht0(Address src);
562 void prefetcht1(Address src);
563 void prefetcht2(Address src);
564 void prefetchnta(Address src);
565 void prefetchw(Address src);
566 void prefetchr(Address src);
567
568 // Arithmetics
569 void adcl(Register dst, int imm32);
570 void adcl(Register dst, Address src);
571 void adcl(Register dst, Register src);
572
573 void addl(Address dst, int imm32);
574 void addl(Address dst, Register src);
575 void addl(Register dst, int imm32);
576 void addl(Register dst, Address src);
577 void addl(Register dst, Register src);
578
579 void andl(Register dst, int imm32);
580 void andl(Register dst, Address src);
581 void andl(Register dst, Register src);
582
583 void cmpb(Address dst, int imm8);
584 void cmpw(Address dst, int imm16);
585 void cmpl(Address dst, int imm32);
586 void cmpl(Register dst, int imm32);
587 void cmpl(Register dst, Register src);
588 void cmpl(Register dst, Address src);
589
590 // this is a dummy used to catch attempting to convert NULL to Register
591 void cmpl(Register dst, void* junk);
592
593 protected:
594 // Don't use next inc() and dec() methods directly. INC & DEC instructions
595 // could cause a partial flag stall since they don't set CF flag.
596 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
597 // which call inc() & dec() or add() & sub() in accordance with
598 // the product flag UseIncDec value.
599
600 void decl(Register dst);
601 void decl(Address dst);
602
603 void incl(Register dst);
604 void incl(Address dst);
605
606 public:
607 void idivl(Register src);
608 void cdql();
609
610 void imull(Register dst, Register src);
611 void imull(Register dst, Register src, int value);
612
613 void leal(Register dst, Address src);
614
615 void mull(Address src);
616 void mull(Register src);
617
618 void negl(Register dst);
619
620 void notl(Register dst);
621
622 void orl(Address dst, int imm32);
623 void orl(Register dst, int imm32);
624 void orl(Register dst, Address src);
625 void orl(Register dst, Register src);
626
627 void rcll(Register dst, int imm8);
628
629 void sarl(Register dst, int imm8);
630 void sarl(Register dst);
631
632 void sbbl(Address dst, int imm32);
633 void sbbl(Register dst, int imm32);
634 void sbbl(Register dst, Address src);
635 void sbbl(Register dst, Register src);
636
637 void shldl(Register dst, Register src);
638
639 void shll(Register dst, int imm8);
640 void shll(Register dst);
641
642 void shrdl(Register dst, Register src);
643
644 void shrl(Register dst, int imm8);
645 void shrl(Register dst);
646
647 void subl(Address dst, int imm32);
648 void subl(Address dst, Register src);
649 void subl(Register dst, int imm32);
650 void subl(Register dst, Address src);
651 void subl(Register dst, Register src);
652
653 void testb(Register dst, int imm8);
654 void testl(Register dst, int imm32);
655 void testl(Register dst, Address src);
656 void testl(Register dst, Register src);
657
658 void xaddl(Address dst, Register src);
659
660 void xorl(Register dst, int imm32);
661 void xorl(Register dst, Address src);
662 void xorl(Register dst, Register src);
663
664 // Miscellaneous
665 void bswap(Register reg);
666 void lock();
667
668 void xchg (Register reg, Address adr);
669 void xchgl(Register dst, Register src);
670
671 void cmpxchg (Register reg, Address adr);
672 void cmpxchg8 (Address adr);
673
674 void nop(int i = 1);
675 void addr_nop_4();
676 void addr_nop_5();
677 void addr_nop_7();
678 void addr_nop_8();
679
680 void hlt();
681 void ret(int imm16);
682 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
683 void smovl();
684 void rep_movl();
685 void rep_set();
686 void repne_scan();
687 void setb(Condition cc, Register dst);
688 void membar(); // Serializing memory-fence
689 void cpuid();
690 void cld();
691 void std();
692
693 void emit_raw (unsigned char);
694
695 // Calls
696 void call(Label& L, relocInfo::relocType rtype);
697 void call(Register reg); // push pc; pc <- reg
698 void call(Address adr); // push pc; pc <- adr
699
700 // Jumps
701 void jmp(Address entry); // pc <- entry
702 void jmp(Register entry); // pc <- entry
703
704 // Label operations & relative jumps (PPUM Appendix D)
705 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
706
707 // Force an 8-bit jump offset
708 // void jmpb(address entry);
709
710 // Unconditional 8-bit offset jump to L.
711 // WARNING: be very careful using this for forward jumps. If the label is
712 // not bound within an 8-bit offset of this instruction, a run-time error
713 // will occur.
714 void jmpb(Label& L);
715
716 // jcc is the generic conditional branch generator to run-
717 // time routines, jcc is used for branches to labels. jcc
718 // takes a branch opcode (cc) and a label (L) and generates
719 // either a backward branch or a forward branch and links it
720 // to the label fixup chain. Usage:
721 //
722 // Label L; // unbound label
723 // jcc(cc, L); // forward branch to unbound label
724 // bind(L); // bind label to the current pc
725 // jcc(cc, L); // backward branch to bound label
726 // bind(L); // illegal: a label may be bound only once
727 //
728 // Note: The same Label can be used for forward and backward branches
729 // but it may be bound only once.
730
731 void jcc(Condition cc, Label& L,
732 relocInfo::relocType rtype = relocInfo::none);
733
734 // Conditional jump to a 8-bit offset to L.
735 // WARNING: be very careful using this for forward jumps. If the label is
736 // not bound within an 8-bit offset of this instruction, a run-time error
737 // will occur.
738 void jccb(Condition cc, Label& L);
739
740 // Floating-point operations
741 void fld1();
742 void fldz();
743
744 void fld_s(Address adr);
745 void fld_s(int index);
746 void fld_d(Address adr);
747 void fld_x(Address adr); // extended-precision (80-bit) format
748
749 void fst_s(Address adr);
750 void fst_d(Address adr);
751
752 void fstp_s(Address adr);
753 void fstp_d(Address adr);
754 void fstp_d(int index);
755 void fstp_x(Address adr); // extended-precision (80-bit) format
756
757 void fild_s(Address adr);
758 void fild_d(Address adr);
759
760 void fist_s (Address adr);
761 void fistp_s(Address adr);
762 void fistp_d(Address adr);
763
764 void fabs();
765 void fchs();
766
767 void flog();
768 void flog10();
769
770 void fldln2();
771 void fyl2x();
772 void fldlg2();
773
774 void fcos();
775 void fsin();
776 void ftan();
777 void fsqrt();
778
779 // "Alternate" versions of instructions place result down in FPU
780 // stack instead of on TOS
781 void fadd_s(Address src);
782 void fadd_d(Address src);
783 void fadd(int i);
784 void fadda(int i); // "alternate" fadd
785
786 void fsub_s(Address src);
787 void fsub_d(Address src);
788 void fsubr_s(Address src);
789 void fsubr_d(Address src);
790
791 void fmul_s(Address src);
792 void fmul_d(Address src);
793 void fmul(int i);
794 void fmula(int i); // "alternate" fmul
795
796 void fdiv_s(Address src);
797 void fdiv_d(Address src);
798 void fdivr_s(Address src);
799 void fdivr_d(Address src);
800
801 void fsub(int i);
802 void fsuba(int i); // "alternate" fsub
803 void fsubr(int i);
804 void fsubra(int i); // "alternate" reversed fsub
805 void fdiv(int i);
806 void fdiva(int i); // "alternate" fdiv
807 void fdivr(int i);
808 void fdivra(int i); // "alternate" reversed fdiv
809
810 void faddp(int i = 1);
811 void fsubp(int i = 1);
812 void fsubrp(int i = 1);
813 void fmulp(int i = 1);
814 void fdivp(int i = 1);
815 void fdivrp(int i = 1);
816 void fprem();
817 void fprem1();
818
819 void fxch(int i = 1);
820 void fincstp();
821 void fdecstp();
822 void ffree(int i = 0);
823
824 void fcomp_s(Address src);
825 void fcomp_d(Address src);
826 void fcom(int i);
827 void fcomp(int i = 1);
828 void fcompp();
829
830 void fucomi(int i = 1);
831 void fucomip(int i = 1);
832
833 void ftst();
834 void fnstsw_ax();
835 void fwait();
836 void finit();
837 void fldcw(Address src);
838 void fnstcw(Address src);
839
840 void fnsave(Address dst);
841 void frstor(Address src);
842 void fldenv(Address src);
843
844 void sahf();
845
846 protected:
847 void emit_sse_operand(XMMRegister reg, Address adr);
848 void emit_sse_operand(Register reg, Address adr);
849 void emit_sse_operand(XMMRegister dst, XMMRegister src);
850 void emit_sse_operand(XMMRegister dst, Register src);
851 void emit_sse_operand(Register dst, XMMRegister src);
852
853 void emit_operand(MMXRegister reg, Address adr);
854
855 public:
856 // mmx operations
857 void movq( MMXRegister dst, Address src );
858 void movq( Address dst, MMXRegister src );
859 void emms();
860
861 // xmm operations
862 void addss(XMMRegister dst, Address src); // Add Scalar Single-Precision Floating-Point Values
863 void addss(XMMRegister dst, XMMRegister src);
864 void addsd(XMMRegister dst, Address src); // Add Scalar Double-Precision Floating-Point Values
865 void addsd(XMMRegister dst, XMMRegister src);
866
867 void subss(XMMRegister dst, Address src); // Subtract Scalar Single-Precision Floating-Point Values
868 void subss(XMMRegister dst, XMMRegister src);
869 void subsd(XMMRegister dst, Address src); // Subtract Scalar Double-Precision Floating-Point Values
870 void subsd(XMMRegister dst, XMMRegister src);
871
872 void mulss(XMMRegister dst, Address src); // Multiply Scalar Single-Precision Floating-Point Values
873 void mulss(XMMRegister dst, XMMRegister src);
874 void mulsd(XMMRegister dst, Address src); // Multiply Scalar Double-Precision Floating-Point Values
875 void mulsd(XMMRegister dst, XMMRegister src);
876
877 void divss(XMMRegister dst, Address src); // Divide Scalar Single-Precision Floating-Point Values
878 void divss(XMMRegister dst, XMMRegister src);
879 void divsd(XMMRegister dst, Address src); // Divide Scalar Double-Precision Floating-Point Values
880 void divsd(XMMRegister dst, XMMRegister src);
881
882 void sqrtss(XMMRegister dst, Address src); // Compute Square Root of Scalar Single-Precision Floating-Point Value
883 void sqrtss(XMMRegister dst, XMMRegister src);
884 void sqrtsd(XMMRegister dst, Address src); // Compute Square Root of Scalar Double-Precision Floating-Point Value
885 void sqrtsd(XMMRegister dst, XMMRegister src);
886
887 void pxor(XMMRegister dst, Address src); // Xor Packed Byte Integer Values
888 void pxor(XMMRegister dst, XMMRegister src); // Xor Packed Byte Integer Values
889
890 void comiss(XMMRegister dst, Address src); // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
891 void comiss(XMMRegister dst, XMMRegister src);
892 void comisd(XMMRegister dst, Address src); // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
893 void comisd(XMMRegister dst, XMMRegister src);
894
895 void ucomiss(XMMRegister dst, Address src); // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
896 void ucomiss(XMMRegister dst, XMMRegister src);
897 void ucomisd(XMMRegister dst, Address src); // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
898 void ucomisd(XMMRegister dst, XMMRegister src);
899
900 void cvtss2sd(XMMRegister dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
901 void cvtss2sd(XMMRegister dst, XMMRegister src);
902 void cvtsd2ss(XMMRegister dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
903 void cvtsd2ss(XMMRegister dst, XMMRegister src);
904 void cvtdq2pd(XMMRegister dst, XMMRegister src);
905 void cvtdq2ps(XMMRegister dst, XMMRegister src);
906
907 void cvtsi2ss(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
908 void cvtsi2ss(XMMRegister dst, Register src);
909 void cvtsi2sd(XMMRegister dst, Address src); // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
910 void cvtsi2sd(XMMRegister dst, Register src);
911
912 void cvtss2si(Register dst, Address src); // Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
913 void cvtss2si(Register dst, XMMRegister src);
914 void cvtsd2si(Register dst, Address src); // Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
915 void cvtsd2si(Register dst, XMMRegister src);
916
917 void cvttss2si(Register dst, Address src); // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
918 void cvttss2si(Register dst, XMMRegister src);
919 void cvttsd2si(Register dst, Address src); // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
920 void cvttsd2si(Register dst, XMMRegister src);
921
922 protected: // Avoid using the next instructions directly.
923 // New cpus require use of movsd and movss to avoid partial register stall
924 // when loading from memory. But for old Opteron use movlpd instead of movsd.
925 // The selection is done in MacroAssembler::movdbl() and movflt().
926 void movss(XMMRegister dst, Address src); // Move Scalar Single-Precision Floating-Point Values
927 void movss(XMMRegister dst, XMMRegister src);
928 void movss(Address dst, XMMRegister src);
929 void movsd(XMMRegister dst, Address src); // Move Scalar Double-Precision Floating-Point Values
930 void movsd(XMMRegister dst, XMMRegister src);
931 void movsd(Address dst, XMMRegister src);
932 void movlpd(XMMRegister dst, Address src);
933 // New cpus require use of movaps and movapd to avoid partial register stall
934 // when moving between registers.
935 void movaps(XMMRegister dst, XMMRegister src);
936 void movapd(XMMRegister dst, XMMRegister src);
937 public:
938
939 void andps(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
940 void andps(XMMRegister dst, XMMRegister src);
941 void andpd(XMMRegister dst, Address src); // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
942 void andpd(XMMRegister dst, XMMRegister src);
943
944 void andnps(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values
945 void andnps(XMMRegister dst, XMMRegister src);
946 void andnpd(XMMRegister dst, Address src); // Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values
947 void andnpd(XMMRegister dst, XMMRegister src);
948
949 void orps(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Single-Precision Floating-Point Values
950 void orps(XMMRegister dst, XMMRegister src);
951 void orpd(XMMRegister dst, Address src); // Bitwise Logical OR of Packed Double-Precision Floating-Point Values
952 void orpd(XMMRegister dst, XMMRegister src);
953
954 void xorps(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
955 void xorps(XMMRegister dst, XMMRegister src);
956 void xorpd(XMMRegister dst, Address src); // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
957 void xorpd(XMMRegister dst, XMMRegister src);
958
959 void movq(XMMRegister dst, Address src); // Move Quadword
960 void movq(XMMRegister dst, XMMRegister src);
961 void movq(Address dst, XMMRegister src);
962
963 void movd(XMMRegister dst, Address src); // Move Doubleword
964 void movd(XMMRegister dst, Register src);
965 void movd(Register dst, XMMRegister src);
966 void movd(Address dst, XMMRegister src);
967
968 void movdqa(XMMRegister dst, Address src); // Move Aligned Double Quadword
969 void movdqa(XMMRegister dst, XMMRegister src);
970 void movdqa(Address dst, XMMRegister src);
971
972 void pshufd(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Doublewords
973 void pshufd(XMMRegister dst, Address src, int mode);
974 void pshuflw(XMMRegister dst, XMMRegister src, int mode); // Shuffle Packed Low Words
975 void pshuflw(XMMRegister dst, Address src, int mode);
976
977 void psrlq(XMMRegister dst, int shift); // Shift Right Logical Quadword Immediate
978
979 void punpcklbw(XMMRegister dst, XMMRegister src); // Interleave Low Bytes
980 void punpcklbw(XMMRegister dst, Address src);
981
982 void ldmxcsr( Address src );
983 void stmxcsr( Address dst );
984 };
985
986
987 // MacroAssembler extends Assembler by frequently used macros.
988 //
989 // Instructions for which a 'better' code sequence exists depending
990 // on arguments should also go in here.
991
992 class MacroAssembler: public Assembler {
993 friend class LIR_Assembler;
994 protected:
995
996 Address as_Address(AddressLiteral adr);
997 Address as_Address(ArrayAddress adr);
998
999 // Support for VM calls
1000 //
1001 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1002 // may customize this version by overriding it for its purposes (e.g., to save/restore
1003 // additional registers when doing a VM call).
1004 #ifdef CC_INTERP
1005 // c++ interpreter never wants to use interp_masm version of call_VM
1006 #define VIRTUAL
1007 #else
1008 #define VIRTUAL virtual
1009 #endif
1010
1011 VIRTUAL void call_VM_leaf_base(
1012 address entry_point, // the entry point
1013 int number_of_arguments // the number of arguments to pop after the call
1014 );
1015
1016 // This is the base routine called by the different versions of call_VM. The interpreter
1017 // may customize this version by overriding it for its purposes (e.g., to save/restore
1018 // additional registers when doing a VM call).
1019 //
1020 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1021 // returns the register which contains the thread upon return. If a thread register has been
1022 // specified, the return value will correspond to that register. If no last_java_sp is specified
1023 // (noreg) than rsp will be used instead.
1024 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1025 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1026 Register java_thread, // the thread if computed before ; use noreg otherwise
1027 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1028 address entry_point, // the entry point
1029 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1030 bool check_exceptions // whether to check for pending exceptions after return
1031 );
1032
1033 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1034 // The implementation is only non-empty for the InterpreterMacroAssembler,
1035 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1036 virtual void check_and_handle_popframe(Register java_thread);
1037 virtual void check_and_handle_earlyret(Register java_thread);
1038
1039 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1040
1041 // helpers for FPU flag access
1042 // tmp is a temporary register, if none is available use noreg
1043 void save_rax (Register tmp);
1044 void restore_rax(Register tmp);
1045
1046 public:
1047 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1048
1049 // Support for NULL-checks
1050 //
1051 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1052 // If the accessed location is M[reg + offset] and the offset is known, provide the
1053 // offset. No explicit code generation is needed if the offset is within a certain
1054 // range (0 <= offset <= page_size).
1055
1056 void null_check(Register reg, int offset = -1);
1057 static bool needs_explicit_null_check(int offset);
1058
1059 // Required platform-specific helpers for Label::patch_instructions.
1060 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1061 void pd_patch_instruction(address branch, address target);
1062 #ifndef PRODUCT
1063 static void pd_print_patched_instruction(address branch);
1064 #endif
1065
1066 // The following 4 methods return the offset of the appropriate move instruction
1067
1068 // Support for fast byte/word loading with zero extension (depending on particular CPU)
1069 int load_unsigned_byte(Register dst, Address src);
1070 int load_unsigned_word(Register dst, Address src);
1071
1072 // Support for fast byte/word loading with sign extension (depending on particular CPU)
1073 int load_signed_byte(Register dst, Address src);
1074 int load_signed_word(Register dst, Address src);
1075
1076 // Support for sign-extension (hi:lo = extend_sign(lo))
1077 void extend_sign(Register hi, Register lo);
1078
1079 // Support for inc/dec with optimal instruction selection depending on value
1080 void increment(Register reg, int value = 1);
1081 void decrement(Register reg, int value = 1);
1082 void increment(Address dst, int value = 1);
1083 void decrement(Address dst, int value = 1);
1084
1085 // Support optimal SSE move instructions.
1086 void movflt(XMMRegister dst, XMMRegister src) {
1087 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1088 else { movss (dst, src); return; }
1089 }
1090 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1091 void movflt(XMMRegister dst, AddressLiteral src);
1092 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1093
1094 void movdbl(XMMRegister dst, XMMRegister src) {
1095 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1096 else { movsd (dst, src); return; }
1097 }
1098
1099 void movdbl(XMMRegister dst, AddressLiteral src);
1100
1101 void movdbl(XMMRegister dst, Address src) {
1102 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1103 else { movlpd(dst, src); return; }
1104 }
1105 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1106
1107 void increment(AddressLiteral dst);
1108 void increment(ArrayAddress dst);
1109
1110
1111 // Alignment
1112 void align(int modulus);
1113
1114 // Misc
1115 void fat_nop(); // 5 byte nop
1116
1117 // Stack frame creation/removal
1118 void enter();
1119 void leave();
1120
1121 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1122 // The pointer will be loaded into the thread register.
1123 void get_thread(Register thread);
1124
1125 // Support for VM calls
1126 //
1127 // It is imperative that all calls into the VM are handled via the call_VM macros.
1128 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1129 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1130
1131 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true);
1132 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
1133 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1134 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1135
1136 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
1137 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
1138 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
1139 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
1140
1141 void call_VM_leaf(address entry_point, int number_of_arguments = 0);
1142 void call_VM_leaf(address entry_point, Register arg_1);
1143 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
1144 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
1145
1146 // last Java Frame (fills frame anchor)
1147 void set_last_Java_frame(Register thread, Register last_java_sp, Register last_java_fp, address last_java_pc);
1148 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1149
1150 // Stores
1151 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1152 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1153
1154 // split store_check(Register obj) to enhance instruction interleaving
1155 void store_check_part_1(Register obj);
1156 void store_check_part_2(Register obj);
1157
1158 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1159 void c2bool(Register x);
1160
1161 // C++ bool manipulation
1162
1163 void movbool(Register dst, Address src);
1164 void movbool(Address dst, bool boolconst);
1165 void movbool(Address dst, Register src);
1166 void testbool(Register dst);
1167
1168 // Int division/reminder for Java
1169 // (as idivl, but checks for special case as described in JVM spec.)
1170 // returns idivl instruction offset for implicit exception handling
1171 int corrected_idivl(Register reg);
1172
1173 void int3();
1174
1175 // Long negation for Java
1176 void lneg(Register hi, Register lo);
1177
1178 // Long multiplication for Java
1179 // (destroys contents of rax, rbx, rcx and rdx)
1180 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1181
1182 // Long shifts for Java
1183 // (semantics as described in JVM spec.)
1184 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1185 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1186
1187 // Long compare for Java
1188 // (semantics as described in JVM spec.)
1189 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1190
1191 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1192 //
1193 // CF (corresponds to C0) if x < y
1194 // PF (corresponds to C2) if unordered
1195 // ZF (corresponds to C3) if x = y
1196 //
1197 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1198 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1199 void fcmp(Register tmp);
1200 // Variant of the above which allows y to be further down the stack
1201 // and which only pops x and y if specified. If pop_right is
1202 // specified then pop_left must also be specified.
1203 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1204
1205 // Floating-point comparison for Java
1206 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1207 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1208 // (semantics as described in JVM spec.)
1209 void fcmp2int(Register dst, bool unordered_is_less);
1210 // Variant of the above which allows y to be further down the stack
1211 // and which only pops x and y if specified. If pop_right is
1212 // specified then pop_left must also be specified.
1213 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1214
1215 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1216 // tmp is a temporary register, if none is available use noreg
1217 void fremr(Register tmp);
1218
1219
1220 // same as fcmp2int, but using SSE2
1221 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1222 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1223
1224 // Inlined sin/cos generator for Java; must not use CPU instruction
1225 // directly on Intel as it does not have high enough precision
1226 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1227 // number of FPU stack slots in use; all but the topmost will
1228 // require saving if a slow case is necessary. Assumes argument is
1229 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1230 // this code.
1231 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1232
1233 // branch to L if FPU flag C2 is set/not set
1234 // tmp is a temporary register, if none is available use noreg
1235 void jC2 (Register tmp, Label& L);
1236 void jnC2(Register tmp, Label& L);
1237
1238 // Pop ST (ffree & fincstp combined)
1239 void fpop();
1240
1241 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1242 void push_fTOS();
1243
1244 // pops double TOS element from CPU stack and pushes on FPU stack
1245 void pop_fTOS();
1246
1247 void empty_FPU_stack();
1248
1249 void push_IU_state();
1250 void pop_IU_state();
1251
1252 void push_FPU_state();
1253 void pop_FPU_state();
1254
1255 void push_CPU_state();
1256 void pop_CPU_state();
1257
1258 // Sign extension
1259 void sign_extend_short(Register reg);
1260 void sign_extend_byte(Register reg);
1261
1262 // Division by power of 2, rounding towards 0
1263 void division_with_shift(Register reg, int shift_value);
1264
1265 // Round up to a power of two
1266 void round_to(Register reg, int modulus);
1267
1268 // Callee saved registers handling
1269 void push_callee_saved_registers();
1270 void pop_callee_saved_registers();
1271
1272 // allocation
1273 void eden_allocate(
1274 Register obj, // result: pointer to object after successful allocation
1275 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1276 int con_size_in_bytes, // object size in bytes if known at compile time
1277 Register t1, // temp register
1278 Label& slow_case // continuation point if fast allocation fails
1279 );
1280 void tlab_allocate(
1281 Register obj, // result: pointer to object after successful allocation
1282 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1283 int con_size_in_bytes, // object size in bytes if known at compile time
1284 Register t1, // temp register
1285 Register t2, // temp register
1286 Label& slow_case // continuation point if fast allocation fails
1287 );
1288 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1289
1290 //----
1291 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1292
1293 // Debugging
1294 void verify_oop(Register reg, const char* s = "broken oop"); // only if +VerifyOops
1295 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1296
1297 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); // only if +VerifyFPU
1298 void stop(const char* msg); // prints msg, dumps registers and stops execution
1299 void warn(const char* msg); // prints msg and continues
1300 static void debug(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1301 void os_breakpoint();
1302 void untested() { stop("untested"); }
1303 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
1304 void should_not_reach_here() { stop("should not reach here"); }
1305 void print_CPU_state();
1306
1307 // Stack overflow checking
1308 void bang_stack_with_offset(int offset) {
1309 // stack grows down, caller passes positive offset
1310 assert(offset > 0, "must bang with negative offset");
1311 movl(Address(rsp, (-offset)), rax);
1312 }
1313
1314 // Writes to stack successive pages until offset reached to check for
1315 // stack overflow + shadow pages. Also, clobbers tmp
1316 void bang_stack_size(Register size, Register tmp);
1317
1318 // Support for serializing memory accesses between threads
1319 void serialize_memory(Register thread, Register tmp);
1320
1321 void verify_tlab();
1322
1323 // Biased locking support
1324 // lock_reg and obj_reg must be loaded up with the appropriate values.
1325 // swap_reg must be rax, and is killed.
1326 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1327 // be killed; if not supplied, push/pop will be used internally to
1328 // allocate a temporary (inefficient, avoid if possible).
1329 // Optional slow case is for implementations (interpreter and C1) which branch to
1330 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1331 // Returns offset of first potentially-faulting instruction for null
1332 // check info (currently consumed only by C1). If
1333 // swap_reg_contains_mark is true then returns -1 as it is assumed
1334 // the calling code has already passed any potential faults.
1335 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
1336 bool swap_reg_contains_mark,
1337 Label& done, Label* slow_case = NULL,
1338 BiasedLockingCounters* counters = NULL);
1339 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1340
1341
1342 Condition negate_condition(Condition cond);
1343
1344 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1345 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1346 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1347 // here in MacroAssembler. The major exception to this rule is call
1348
1349 // Arithmetics
1350
1351 void cmp8(AddressLiteral src1, int8_t imm);
1352
1353 // QQQ renamed to drag out the casting of address to int32_t/intptr_t
1354 void cmp32(Register src1, int32_t imm);
1355
1356 void cmp32(AddressLiteral src1, int32_t imm);
1357 // compare reg - mem, or reg - &mem
1358 void cmp32(Register src1, AddressLiteral src2);
1359
1360 void cmp32(Register src1, Address src2);
1361
1362 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1363 void cmpptr(Address src1, AddressLiteral src2);
1364
1365 void cmpptr(Register src1, AddressLiteral src2);
1366
1367 void cmpoop(Address dst, jobject obj);
1368 void cmpoop(Register dst, jobject obj);
1369
1370
1371 void cmpxchgptr(Register reg, AddressLiteral adr);
1372
1373 // Helper functions for statistics gathering.
1374 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1375 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1376 // Unconditional atomic increment.
1377 void atomic_incl(AddressLiteral counter_addr);
1378
1379 void lea(Register dst, AddressLiteral adr);
1380 void lea(Address dst, AddressLiteral adr);
1381
1382 void test32(Register dst, AddressLiteral src);
1383
1384 // Calls
1385
1386 void call(Label& L, relocInfo::relocType rtype);
1387 void call(Register entry);
1388
1389 // NOTE: this call tranfers to the effective address of entry NOT
1390 // the address contained by entry. This is because this is more natural
1391 // for jumps/calls.
1392 void call(AddressLiteral entry);
1393
1394 // Jumps
1395
1396 // NOTE: these jumps tranfer to the effective address of dst NOT
1397 // the address contained by dst. This is because this is more natural
1398 // for jumps/calls.
1399 void jump(AddressLiteral dst);
1400 void jump_cc(Condition cc, AddressLiteral dst);
1401
1402 // 32bit can do a case table jump in one instruction but we no longer allow the base
1403 // to be installed in the Address class. This jump will tranfers to the address
1404 // contained in the location described by entry (not the address of entry)
1405 void jump(ArrayAddress entry);
1406
1407 // Floating
1408
1409 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1410 void andpd(XMMRegister dst, AddressLiteral src);
1411
1412 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1413 void comiss(XMMRegister dst, AddressLiteral src);
1414
1415 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1416 void comisd(XMMRegister dst, AddressLiteral src);
1417
1418 void fldcw(Address src) { Assembler::fldcw(src); }
1419 void fldcw(AddressLiteral src);
1420
1421 void fld_s(int index) { Assembler::fld_s(index); }
1422 void fld_s(Address src) { Assembler::fld_s(src); }
1423 void fld_s(AddressLiteral src);
1424
1425 void fld_d(Address src) { Assembler::fld_d(src); }
1426 void fld_d(AddressLiteral src);
1427
1428 void fld_x(Address src) { Assembler::fld_x(src); }
1429 void fld_x(AddressLiteral src);
1430
1431 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1432 void ldmxcsr(AddressLiteral src);
1433
1434 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1435 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1436 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1437 void movss(XMMRegister dst, AddressLiteral src);
1438
1439 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1440 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1441 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1442 void movsd(XMMRegister dst, AddressLiteral src);
1443
1444 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1445 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1446 void ucomiss(XMMRegister dst, AddressLiteral src);
1447
1448 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1449 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1450 void ucomisd(XMMRegister dst, AddressLiteral src);
1451
1452 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1453 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1454 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1455 void xorpd(XMMRegister dst, AddressLiteral src);
1456
1457 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1458 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1459 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1460 void xorps(XMMRegister dst, AddressLiteral src);
1461
1462 // Data
1463
1464 void movoop(Register dst, jobject obj);
1465 void movoop(Address dst, jobject obj);
1466
1467 void movptr(ArrayAddress dst, Register src);
1468 // can this do an lea?
1469 void movptr(Register dst, ArrayAddress src);
1470
1471 void movptr(Register dst, AddressLiteral src);
1472
1473 // to avoid hiding movl
1474 void mov32(AddressLiteral dst, Register src);
1475 void mov32(Register dst, AddressLiteral src);
1476 // to avoid hiding movb
1477 void movbyte(ArrayAddress dst, int src);
1478
1479 // Can push value or effective address
1480 void pushptr(AddressLiteral src);
1481
1482 #undef VIRTUAL
1483
1484 };
1485
1486 /**
1487 * class SkipIfEqual:
1488 *
1489 * Instantiating this class will result in assembly code being output that will
1490 * jump around any code emitted between the creation of the instance and it's
1491 * automatic destruction at the end of a scope block, depending on the value of
1492 * the flag passed to the constructor, which will be checked at run-time.
1493 */
1494 class SkipIfEqual {
1495 private:
1496 MacroAssembler* _masm;
1497 Label _label;
1498
1499 public:
1500 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1501 ~SkipIfEqual();
1502 };
1503
1504 #ifdef ASSERT
1505 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
1506 #endif