*** old/src/cpu/sparc/vm/sparc.ad	Wed May 14 20:04:32 2008
--- new/src/cpu/sparc/vm/sparc.ad	Wed May 14 20:04:31 2008

*** 5469,5479 ****
--- 5469,5479 ----
  %}
  
  // Load Klass Pointer
  instruct loadKlass(iRegP dst, memory mem) %{
    match(Set dst (LoadKlass mem));
!   predicate(!n->in(MemNode::Address)->bottom_type()->is_narrow());
!   predicate(!n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
    ins_cost(MEMORY_REF_COST);
    size(4);
  
  #ifndef _LP64
    format %{ "LDUW   $mem,$dst\t! klass ptr" %}

*** 5484,5497 ****
--- 5484,5497 ----
  #endif
    ins_encode( form3_mem_reg( mem, dst ) );
    ins_pipe(iload_mem);
  %}
  
! // Load narrow Klass Pointer
! instruct loadKlassComp(iRegP dst, memory mem) %{
!   match(Set dst (LoadKlass mem));
!   predicate(n->in(MemNode::Address)->bottom_type()->is_narrow());
! instruct loadNKlass(iRegN dst, memory mem) %{
!   match(Set dst (LoadNKlass mem));
!   predicate(n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
    ins_cost(MEMORY_REF_COST);
  
    format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
  
    ins_encode %{

*** 5501,5513 ****
--- 5501,5510 ----
       if (index != G0) {
         __ lduw(base, index, dst);
       } else {
         __ lduw(base, $mem$$disp, dst);
       }
       // klass oop never null but this is generated for nonheader klass loads
       // too which can be null.
       __ decode_heap_oop(dst);
    %}
    ins_pipe(iload_mem);
  %}
  
  // Load Short (16bit signed)

*** 5607,5632 ****
--- 5604,5631 ----
      __ sethi(polling_page, false );
    %}
    ins_pipe(loadConP_poll);
  %}
  
+ instruct loadConN0(iRegN dst, immN0 src) %{
+   match(Set dst src);
+ 
+   size(4);
+   format %{ "CLR    $dst\t! compressed NULL ptr" %}
+   ins_encode( SetNull( dst ) );
+   ins_pipe(ialu_imm);
+ %}
+ 
  instruct loadConN(iRegN dst, immN src) %{
    match(Set dst src);
!   ins_cost(DEFAULT_COST * 3/2);
!   format %{ "SET    $src,$dst\t!ptr" %}
!   format %{ "SET    $src,$dst\t! compressed ptr" %}
    ins_encode %{
      address con = (address)$src$$constant;
      Register dst = $dst$$Register;
      if (con == NULL) {
        __ mov(G0, dst);
      } else {
        __ set_oop((jobject)$src$$constant, dst);
        __ encode_heap_oop(dst);
      }
+     __ load_narrow_oop_con((jobject)$src$$constant, dst);
    %}
!   ins_pipe(loadConP);
  
!   ins_pipe(ialu_hi_lo_reg);
  %}
  
  instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
    // %%% maybe this should work like loadConD
    match(Set dst src);

*** 6256,6265 ****
--- 6255,6292 ----
    format %{ "MOV$cmp $fcc,$src,$dst" %}
    ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
    ins_pipe(ialu_imm);
  %}
  
+ // Conditional move ofr RegN. Only cmov(reg,reg).
+ instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
+   match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
+   ins_cost(150);
+   format %{ "MOV$cmp $pcc,$src,$dst" %}
+   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
+   ins_pipe(ialu_reg);
+ %}
+ 
+ // This instruction works also for CmpN so we don't need cmovNN_reg.
+ instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
+   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
+   ins_cost(150);
+   size(4);
+   format %{ "MOV$cmp  $icc,$src,$dst" %}
+   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
+   ins_pipe(ialu_reg);
+ %}
+ 
+ instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
+   match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
+   ins_cost(150);
+   size(4);
+   format %{ "MOV$cmp $fcc,$src,$dst" %}
+   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
+   ins_pipe(ialu_reg);
+ %}
+ 
  // Conditional move
  instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
    match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
    ins_cost(150);
    format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}

*** 6415,6425 ****
--- 6442,6451 ----
    ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
    ins_pipe(ialu_reg);
  %}
  
  
  
  //----------OS and Locking Instructions----------------------------------------
  
  // This name is KNOWN by the ADLC and cannot be changed.
  // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
  // for this guy.

*** 8263,8272 ****
--- 8289,8319 ----
    opcode(Assembler::subcc_op3, Assembler::arith_op);
    ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
    ins_pipe(ialu_cconly_reg_imm);
  %}
  
+ // Compare Narrow oops
+ instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
+   match(Set icc (CmpN op1 op2));
+ 
+   size(4);
+   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
+   opcode(Assembler::subcc_op3, Assembler::arith_op);
+   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
+   ins_pipe(ialu_cconly_reg_reg);
+ %}
+ 
+ instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
+   match(Set icc (CmpN op1 op2));
+ 
+   size(4);
+   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
+   opcode(Assembler::subcc_op3, Assembler::arith_op);
+   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
+   ins_pipe(ialu_cconly_reg_imm);
+ %}
+ 
  //----------Max and Min--------------------------------------------------------
  // Min Instructions
  // Conditional move for min
  instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
    effect( USE_DEF op2, USE op1, USE icc );

*** 8593,8602 ****
--- 8640,8657 ----
    format %{ "MOV$cmp  $xcc,$src,$dst" %}
    ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
    ins_pipe(ialu_imm);
  %}
  
+ instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
+   match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
+   ins_cost(150);
+   format %{ "MOV$cmp  $xcc,$src,$dst" %}
+   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
+   ins_pipe(ialu_reg);
+ %}
+ 
  instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
    match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
    ins_cost(150);
    format %{ "MOV$cmp  $xcc,$src,$dst" %}
    ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );

*** 8824,8843 ****
--- 8879,8888 ----
    ins_encode( enc_PartialSubtypeCheck() );
    ins_pipe(partial_subtype_check_pipe);
  %}
  
  
  instruct compP_iRegN_immN0(flagsRegP pcc, iRegN op1, immN0 op2 ) %{
    match(Set pcc (CmpN op1 op2));
  
    size(4);
    format %{ "CMP    $op1,$op2\t! ptr" %}
    opcode(Assembler::subcc_op3, Assembler::arith_op);
    ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
    ins_pipe(ialu_cconly_reg_imm);
  %}
  
  // ============================================================================
  // inlined locking and unlocking
  
  instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
    match(Set pcc (FastLock object box));