5454 ins_cost(MEMORY_REF_COST);
5455 size(4);
5456
5457 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5458 ins_encode %{
5459 Register base = as_Register($mem$$base);
5460 Register index = as_Register($mem$$index);
5461 Register dst = $dst$$Register;
5462 if (index != G0) {
5463 __ lduw(base, index, dst);
5464 } else {
5465 __ lduw(base, $mem$$disp, dst);
5466 }
5467 %}
5468 ins_pipe(iload_mem);
5469 %}
5470
5471 // Load Klass Pointer
5472 instruct loadKlass(iRegP dst, memory mem) %{
5473 match(Set dst (LoadKlass mem));
5474 predicate(!n->in(MemNode::Address)->bottom_type()->is_narrow());
5475 ins_cost(MEMORY_REF_COST);
5476 size(4);
5477
5478 #ifndef _LP64
5479 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5480 opcode(Assembler::lduw_op3, 0, REGP_OP);
5481 #else
5482 format %{ "LDX $mem,$dst\t! klass ptr" %}
5483 opcode(Assembler::ldx_op3, 0, REGP_OP);
5484 #endif
5485 ins_encode( form3_mem_reg( mem, dst ) );
5486 ins_pipe(iload_mem);
5487 %}
5488
5489 // Load Klass Pointer
5490 instruct loadKlassComp(iRegP dst, memory mem) %{
5491 match(Set dst (LoadKlass mem));
5492 predicate(n->in(MemNode::Address)->bottom_type()->is_narrow());
5493 ins_cost(MEMORY_REF_COST);
5494
5495 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5496
5497 ins_encode %{
5498 Register base = as_Register($mem$$base);
5499 Register index = as_Register($mem$$index);
5500 Register dst = $dst$$Register;
5501 if (index != G0) {
5502 __ lduw(base, index, dst);
5503 } else {
5504 __ lduw(base, $mem$$disp, dst);
5505 }
5506 // klass oop never null but this is generated for nonheader klass loads
5507 // too which can be null.
5508 __ decode_heap_oop(dst);
5509 %}
5510 ins_pipe(iload_mem);
5511 %}
5512
5513 // Load Short (16bit signed)
5514 instruct loadS(iRegI dst, memory mem) %{
5515 match(Set dst (LoadS mem));
5516 ins_cost(MEMORY_REF_COST);
5517
5518 size(4);
5519 format %{ "LDSH $mem,$dst" %}
5520 opcode(Assembler::ldsh_op3);
5521 ins_encode( form3_mem_reg( mem, dst ) );
5522 ins_pipe(iload_mask_mem);
5523 %}
5524
5525 // Load Double
5526 instruct loadD(regD dst, memory mem) %{
5527 match(Set dst (LoadD mem));
5528 ins_cost(MEMORY_REF_COST);
5592 instruct loadConP0(iRegP dst, immP0 src) %{
5593 match(Set dst src);
5594
5595 size(4);
5596 format %{ "CLR $dst\t!ptr" %}
5597 ins_encode( SetNull( dst ) );
5598 ins_pipe(ialu_imm);
5599 %}
5600
5601 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5602 match(Set dst src);
5603 ins_cost(DEFAULT_COST);
5604 format %{ "SET $src,$dst\t!ptr" %}
5605 ins_encode %{
5606 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
5607 __ sethi(polling_page, false );
5608 %}
5609 ins_pipe(loadConP_poll);
5610 %}
5611
5612 instruct loadConN(iRegN dst, immN src) %{
5613 match(Set dst src);
5614 ins_cost(DEFAULT_COST * 2);
5615 format %{ "SET $src,$dst\t!ptr" %}
5616 ins_encode %{
5617 address con = (address)$src$$constant;
5618 Register dst = $dst$$Register;
5619 if (con == NULL) {
5620 __ mov(G0, dst);
5621 } else {
5622 __ set_oop((jobject)$src$$constant, dst);
5623 __ encode_heap_oop(dst);
5624 }
5625 %}
5626 ins_pipe(loadConP);
5627
5628 %}
5629
5630 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5631 // %%% maybe this should work like loadConD
5632 match(Set dst src);
5633 effect(KILL tmp);
5634 ins_cost(DEFAULT_COST * 4);
5635 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5636 ins_encode( LdImmL(src, dst, tmp) );
5637 ins_pipe(loadConL);
5638 %}
5639
5640 instruct loadConL0( iRegL dst, immL0 src ) %{
5641 match(Set dst src);
5642 ins_cost(DEFAULT_COST);
5643 size(4);
5644 format %{ "CLR $dst\t! long" %}
5645 ins_encode( Set13( src, dst ) );
5646 ins_pipe(ialu_imm);
5647 %}
6241 %}
6242
6243 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6244 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6245 ins_cost(150);
6246 size(4);
6247 format %{ "MOV$cmp $fcc,$src,$dst" %}
6248 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6249 ins_pipe(ialu_reg);
6250 %}
6251
6252 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6253 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6254 ins_cost(140);
6255 size(4);
6256 format %{ "MOV$cmp $fcc,$src,$dst" %}
6257 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6258 ins_pipe(ialu_imm);
6259 %}
6260
6261 // Conditional move
6262 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6263 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6264 ins_cost(150);
6265 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6266 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6267 ins_pipe(ialu_reg);
6268 %}
6269
6270 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6271 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6272 ins_cost(140);
6273 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6274 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6275 ins_pipe(ialu_imm);
6276 %}
6277
6278 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6279 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6280 ins_cost(150);
6400 ins_cost(150);
6401
6402 size(4);
6403 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6404 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6405 ins_pipe(ialu_reg);
6406 %}
6407
6408
6409 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6410 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6411 ins_cost(150);
6412
6413 size(4);
6414 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6415 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6416 ins_pipe(ialu_reg);
6417 %}
6418
6419
6420
6421 //----------OS and Locking Instructions----------------------------------------
6422
6423 // This name is KNOWN by the ADLC and cannot be changed.
6424 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6425 // for this guy.
6426 instruct tlsLoadP(g2RegP dst) %{
6427 match(Set dst (ThreadLocal));
6428
6429 size(0);
6430 ins_cost(0);
6431 format %{ "# TLS is in G2" %}
6432 ins_encode( /*empty encoding*/ );
6433 ins_pipe(ialu_none);
6434 %}
6435
6436 instruct checkCastPP( iRegP dst ) %{
6437 match(Set dst (CheckCastPP dst));
6438
6439 size(0);
6440 format %{ "# checkcastPP of $dst" %}
8248 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8249 match(Set pcc (CmpP op1 op2));
8250
8251 size(4);
8252 format %{ "CMP $op1,$op2\t! ptr" %}
8253 opcode(Assembler::subcc_op3, Assembler::arith_op);
8254 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8255 ins_pipe(ialu_cconly_reg_reg);
8256 %}
8257
8258 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8259 match(Set pcc (CmpP op1 op2));
8260
8261 size(4);
8262 format %{ "CMP $op1,$op2\t! ptr" %}
8263 opcode(Assembler::subcc_op3, Assembler::arith_op);
8264 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8265 ins_pipe(ialu_cconly_reg_imm);
8266 %}
8267
8268 //----------Max and Min--------------------------------------------------------
8269 // Min Instructions
8270 // Conditional move for min
8271 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8272 effect( USE_DEF op2, USE op1, USE icc );
8273
8274 size(4);
8275 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8276 opcode(Assembler::less);
8277 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8278 ins_pipe(ialu_reg_flags);
8279 %}
8280
8281 // Min Register with Register.
8282 instruct minI_eReg(iRegI op1, iRegI op2) %{
8283 match(Set op2 (MinI op1 op2));
8284 ins_cost(DEFAULT_COST*2);
8285 expand %{
8286 flagsReg icc;
8287 compI_iReg(icc,op1,op2);
8578 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8579 ins_pipe(ialu_imm);
8580 %}
8581
8582 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8583 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8584 ins_cost(150);
8585 format %{ "MOV$cmp $xcc,$src,$dst" %}
8586 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8587 ins_pipe(ialu_reg);
8588 %}
8589
8590 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8591 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8592 ins_cost(140);
8593 format %{ "MOV$cmp $xcc,$src,$dst" %}
8594 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8595 ins_pipe(ialu_imm);
8596 %}
8597
8598 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8599 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8600 ins_cost(150);
8601 format %{ "MOV$cmp $xcc,$src,$dst" %}
8602 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8603 ins_pipe(ialu_reg);
8604 %}
8605
8606 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8607 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8608 ins_cost(140);
8609 format %{ "MOV$cmp $xcc,$src,$dst" %}
8610 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8611 ins_pipe(ialu_imm);
8612 %}
8613
8614 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8615 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8616 ins_cost(150);
8617 opcode(0x101);
8809 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
8810 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
8811 match(Set index (PartialSubtypeCheck sub super));
8812 effect( KILL pcc, KILL o7 );
8813 ins_cost(DEFAULT_COST*10);
8814 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
8815 ins_encode( enc_PartialSubtypeCheck() );
8816 ins_pipe(partial_subtype_check_pipe);
8817 %}
8818
8819 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
8820 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
8821 effect( KILL idx, KILL o7 );
8822 ins_cost(DEFAULT_COST*10);
8823 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
8824 ins_encode( enc_PartialSubtypeCheck() );
8825 ins_pipe(partial_subtype_check_pipe);
8826 %}
8827
8828
8829 instruct compP_iRegN_immN0(flagsRegP pcc, iRegN op1, immN0 op2 ) %{
8830 match(Set pcc (CmpN op1 op2));
8831
8832 size(4);
8833 format %{ "CMP $op1,$op2\t! ptr" %}
8834 opcode(Assembler::subcc_op3, Assembler::arith_op);
8835 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8836 ins_pipe(ialu_cconly_reg_imm);
8837 %}
8838
8839 // ============================================================================
8840 // inlined locking and unlocking
8841
8842 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8843 match(Set pcc (FastLock object box));
8844
8845 effect(KILL scratch, TEMP scratch2);
8846 ins_cost(100);
8847
8848 size(4*112); // conservative overestimation ...
8849 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8850 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
8851 ins_pipe(long_memory_op);
8852 %}
8853
8854
8855 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8856 match(Set pcc (FastUnlock object box));
8857 effect(KILL scratch, TEMP scratch2);
8858 ins_cost(100);
|
5454 ins_cost(MEMORY_REF_COST);
5455 size(4);
5456
5457 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5458 ins_encode %{
5459 Register base = as_Register($mem$$base);
5460 Register index = as_Register($mem$$index);
5461 Register dst = $dst$$Register;
5462 if (index != G0) {
5463 __ lduw(base, index, dst);
5464 } else {
5465 __ lduw(base, $mem$$disp, dst);
5466 }
5467 %}
5468 ins_pipe(iload_mem);
5469 %}
5470
5471 // Load Klass Pointer
5472 instruct loadKlass(iRegP dst, memory mem) %{
5473 match(Set dst (LoadKlass mem));
5474 predicate(!n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
5475 ins_cost(MEMORY_REF_COST);
5476 size(4);
5477
5478 #ifndef _LP64
5479 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5480 opcode(Assembler::lduw_op3, 0, REGP_OP);
5481 #else
5482 format %{ "LDX $mem,$dst\t! klass ptr" %}
5483 opcode(Assembler::ldx_op3, 0, REGP_OP);
5484 #endif
5485 ins_encode( form3_mem_reg( mem, dst ) );
5486 ins_pipe(iload_mem);
5487 %}
5488
5489 // Load narrow Klass Pointer
5490 instruct loadNKlass(iRegN dst, memory mem) %{
5491 match(Set dst (LoadNKlass mem));
5492 predicate(n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
5493 ins_cost(MEMORY_REF_COST);
5494
5495 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5496
5497 ins_encode %{
5498 Register base = as_Register($mem$$base);
5499 Register index = as_Register($mem$$index);
5500 Register dst = $dst$$Register;
5501 if (index != G0) {
5502 __ lduw(base, index, dst);
5503 } else {
5504 __ lduw(base, $mem$$disp, dst);
5505 }
5506 %}
5507 ins_pipe(iload_mem);
5508 %}
5509
5510 // Load Short (16bit signed)
5511 instruct loadS(iRegI dst, memory mem) %{
5512 match(Set dst (LoadS mem));
5513 ins_cost(MEMORY_REF_COST);
5514
5515 size(4);
5516 format %{ "LDSH $mem,$dst" %}
5517 opcode(Assembler::ldsh_op3);
5518 ins_encode( form3_mem_reg( mem, dst ) );
5519 ins_pipe(iload_mask_mem);
5520 %}
5521
5522 // Load Double
5523 instruct loadD(regD dst, memory mem) %{
5524 match(Set dst (LoadD mem));
5525 ins_cost(MEMORY_REF_COST);
5589 instruct loadConP0(iRegP dst, immP0 src) %{
5590 match(Set dst src);
5591
5592 size(4);
5593 format %{ "CLR $dst\t!ptr" %}
5594 ins_encode( SetNull( dst ) );
5595 ins_pipe(ialu_imm);
5596 %}
5597
5598 instruct loadConP_poll(iRegP dst, immP_poll src) %{
5599 match(Set dst src);
5600 ins_cost(DEFAULT_COST);
5601 format %{ "SET $src,$dst\t!ptr" %}
5602 ins_encode %{
5603 Address polling_page(reg_to_register_object($dst$$reg), (address)os::get_polling_page());
5604 __ sethi(polling_page, false );
5605 %}
5606 ins_pipe(loadConP_poll);
5607 %}
5608
5609 instruct loadConN0(iRegN dst, immN0 src) %{
5610 match(Set dst src);
5611
5612 size(4);
5613 format %{ "CLR $dst\t! compressed NULL ptr" %}
5614 ins_encode( SetNull( dst ) );
5615 ins_pipe(ialu_imm);
5616 %}
5617
5618 instruct loadConN(iRegN dst, immN src) %{
5619 match(Set dst src);
5620 ins_cost(DEFAULT_COST * 3/2);
5621 format %{ "SET $src,$dst\t! compressed ptr" %}
5622 ins_encode %{
5623 Register dst = $dst$$Register;
5624 __ load_narrow_oop_con((jobject)$src$$constant, dst);
5625 %}
5626 ins_pipe(ialu_hi_lo_reg);
5627 %}
5628
5629 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
5630 // %%% maybe this should work like loadConD
5631 match(Set dst src);
5632 effect(KILL tmp);
5633 ins_cost(DEFAULT_COST * 4);
5634 format %{ "SET64 $src,$dst KILL $tmp\t! long" %}
5635 ins_encode( LdImmL(src, dst, tmp) );
5636 ins_pipe(loadConL);
5637 %}
5638
5639 instruct loadConL0( iRegL dst, immL0 src ) %{
5640 match(Set dst src);
5641 ins_cost(DEFAULT_COST);
5642 size(4);
5643 format %{ "CLR $dst\t! long" %}
5644 ins_encode( Set13( src, dst ) );
5645 ins_pipe(ialu_imm);
5646 %}
6240 %}
6241
6242 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6243 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6244 ins_cost(150);
6245 size(4);
6246 format %{ "MOV$cmp $fcc,$src,$dst" %}
6247 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6248 ins_pipe(ialu_reg);
6249 %}
6250
6251 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6252 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6253 ins_cost(140);
6254 size(4);
6255 format %{ "MOV$cmp $fcc,$src,$dst" %}
6256 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6257 ins_pipe(ialu_imm);
6258 %}
6259
6260 // Conditional move ofr RegN. Only cmov(reg,reg).
6261 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6262 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6263 ins_cost(150);
6264 format %{ "MOV$cmp $pcc,$src,$dst" %}
6265 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6266 ins_pipe(ialu_reg);
6267 %}
6268
6269 // This instruction works also for CmpN so we don't need cmovNN_reg.
6270 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6271 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6272 ins_cost(150);
6273 size(4);
6274 format %{ "MOV$cmp $icc,$src,$dst" %}
6275 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6276 ins_pipe(ialu_reg);
6277 %}
6278
6279 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6280 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6281 ins_cost(150);
6282 size(4);
6283 format %{ "MOV$cmp $fcc,$src,$dst" %}
6284 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6285 ins_pipe(ialu_reg);
6286 %}
6287
6288 // Conditional move
6289 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6290 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6291 ins_cost(150);
6292 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6293 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6294 ins_pipe(ialu_reg);
6295 %}
6296
6297 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6298 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6299 ins_cost(140);
6300 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6301 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6302 ins_pipe(ialu_imm);
6303 %}
6304
6305 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6306 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6307 ins_cost(150);
6427 ins_cost(150);
6428
6429 size(4);
6430 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6431 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6432 ins_pipe(ialu_reg);
6433 %}
6434
6435
6436 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6437 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6438 ins_cost(150);
6439
6440 size(4);
6441 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6442 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6443 ins_pipe(ialu_reg);
6444 %}
6445
6446
6447 //----------OS and Locking Instructions----------------------------------------
6448
6449 // This name is KNOWN by the ADLC and cannot be changed.
6450 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6451 // for this guy.
6452 instruct tlsLoadP(g2RegP dst) %{
6453 match(Set dst (ThreadLocal));
6454
6455 size(0);
6456 ins_cost(0);
6457 format %{ "# TLS is in G2" %}
6458 ins_encode( /*empty encoding*/ );
6459 ins_pipe(ialu_none);
6460 %}
6461
6462 instruct checkCastPP( iRegP dst ) %{
6463 match(Set dst (CheckCastPP dst));
6464
6465 size(0);
6466 format %{ "# checkcastPP of $dst" %}
8274 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8275 match(Set pcc (CmpP op1 op2));
8276
8277 size(4);
8278 format %{ "CMP $op1,$op2\t! ptr" %}
8279 opcode(Assembler::subcc_op3, Assembler::arith_op);
8280 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8281 ins_pipe(ialu_cconly_reg_reg);
8282 %}
8283
8284 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8285 match(Set pcc (CmpP op1 op2));
8286
8287 size(4);
8288 format %{ "CMP $op1,$op2\t! ptr" %}
8289 opcode(Assembler::subcc_op3, Assembler::arith_op);
8290 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8291 ins_pipe(ialu_cconly_reg_imm);
8292 %}
8293
8294 // Compare Narrow oops
8295 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8296 match(Set icc (CmpN op1 op2));
8297
8298 size(4);
8299 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8300 opcode(Assembler::subcc_op3, Assembler::arith_op);
8301 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8302 ins_pipe(ialu_cconly_reg_reg);
8303 %}
8304
8305 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8306 match(Set icc (CmpN op1 op2));
8307
8308 size(4);
8309 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8310 opcode(Assembler::subcc_op3, Assembler::arith_op);
8311 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8312 ins_pipe(ialu_cconly_reg_imm);
8313 %}
8314
8315 //----------Max and Min--------------------------------------------------------
8316 // Min Instructions
8317 // Conditional move for min
8318 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8319 effect( USE_DEF op2, USE op1, USE icc );
8320
8321 size(4);
8322 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8323 opcode(Assembler::less);
8324 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8325 ins_pipe(ialu_reg_flags);
8326 %}
8327
8328 // Min Register with Register.
8329 instruct minI_eReg(iRegI op1, iRegI op2) %{
8330 match(Set op2 (MinI op1 op2));
8331 ins_cost(DEFAULT_COST*2);
8332 expand %{
8333 flagsReg icc;
8334 compI_iReg(icc,op1,op2);
8625 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8626 ins_pipe(ialu_imm);
8627 %}
8628
8629 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
8630 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8631 ins_cost(150);
8632 format %{ "MOV$cmp $xcc,$src,$dst" %}
8633 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8634 ins_pipe(ialu_reg);
8635 %}
8636
8637 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
8638 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
8639 ins_cost(140);
8640 format %{ "MOV$cmp $xcc,$src,$dst" %}
8641 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8642 ins_pipe(ialu_imm);
8643 %}
8644
8645 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
8646 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
8647 ins_cost(150);
8648 format %{ "MOV$cmp $xcc,$src,$dst" %}
8649 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8650 ins_pipe(ialu_reg);
8651 %}
8652
8653 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
8654 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8655 ins_cost(150);
8656 format %{ "MOV$cmp $xcc,$src,$dst" %}
8657 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
8658 ins_pipe(ialu_reg);
8659 %}
8660
8661 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
8662 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
8663 ins_cost(140);
8664 format %{ "MOV$cmp $xcc,$src,$dst" %}
8665 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
8666 ins_pipe(ialu_imm);
8667 %}
8668
8669 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
8670 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
8671 ins_cost(150);
8672 opcode(0x101);
8864 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
8865 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
8866 match(Set index (PartialSubtypeCheck sub super));
8867 effect( KILL pcc, KILL o7 );
8868 ins_cost(DEFAULT_COST*10);
8869 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
8870 ins_encode( enc_PartialSubtypeCheck() );
8871 ins_pipe(partial_subtype_check_pipe);
8872 %}
8873
8874 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
8875 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
8876 effect( KILL idx, KILL o7 );
8877 ins_cost(DEFAULT_COST*10);
8878 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
8879 ins_encode( enc_PartialSubtypeCheck() );
8880 ins_pipe(partial_subtype_check_pipe);
8881 %}
8882
8883
8884 // ============================================================================
8885 // inlined locking and unlocking
8886
8887 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8888 match(Set pcc (FastLock object box));
8889
8890 effect(KILL scratch, TEMP scratch2);
8891 ins_cost(100);
8892
8893 size(4*112); // conservative overestimation ...
8894 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %}
8895 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
8896 ins_pipe(long_memory_op);
8897 %}
8898
8899
8900 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
8901 match(Set pcc (FastUnlock object box));
8902 effect(KILL scratch, TEMP scratch2);
8903 ins_cost(100);
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