6063 // Load Klass Pointer
6064 instruct loadKlass(rRegP dst, memory mem)
6065 %{
6066 match(Set dst (LoadKlass mem));
6067 predicate(!n->in(MemNode::Address)->bottom_type()->is_narrow());
6068
6069 ins_cost(125); // XXX
6070 format %{ "movq $dst, $mem\t# class" %}
6071 opcode(0x8B);
6072 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6073 ins_pipe(ialu_reg_mem); // XXX
6074 %}
6075
6076 // Load Klass Pointer
6077 instruct loadKlassComp(rRegP dst, memory mem)
6078 %{
6079 match(Set dst (LoadKlass mem));
6080 predicate(n->in(MemNode::Address)->bottom_type()->is_narrow());
6081
6082 ins_cost(125); // XXX
6083 format %{ "movl $dst, $mem\t# compressed class" %}
6084 ins_encode %{
6085 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6086 Register dst = as_Register($dst$$reg);
6087 __ movl(dst, addr);
6088 // klass is never null in the header but this is generated for all
6089 // klass loads not just the _klass field in the header.
6090 __ decode_heap_oop(dst);
6091 %}
6092 ins_pipe(ialu_reg_mem); // XXX
6093 %}
6094
6095 // Load Float
6096 instruct loadF(regF dst, memory mem)
6097 %{
6098 match(Set dst (LoadF mem));
6099
6100 ins_cost(145); // XXX
6101 format %{ "movss $dst, $mem\t# float" %}
6102 opcode(0xF3, 0x0F, 0x10);
6103 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6332
6333 ins_cost(60);
6334 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6335 ins_encode(load_immP31(dst, src));
6336 ins_pipe(ialu_reg);
6337 %}
6338
6339 instruct loadConF(regF dst, immF src)
6340 %{
6341 match(Set dst src);
6342 ins_cost(125);
6343
6344 format %{ "movss $dst, [$src]" %}
6345 ins_encode(load_conF(dst, src));
6346 ins_pipe(pipe_slow);
6347 %}
6348
6349 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6350 match(Set dst src);
6351 effect(KILL cr);
6352 format %{ "xorq $dst, $src\t# compressed ptr" %}
6353 ins_encode %{
6354 Register dst = $dst$$Register;
6355 __ xorq(dst, dst);
6356 %}
6357 ins_pipe(ialu_reg);
6358 %}
6359
6360 instruct loadConN(rRegN dst, immN src) %{
6361 match(Set dst src);
6362
6363 ins_cost(125);
6364 format %{ "movl $dst, $src\t# compressed ptr" %}
6365 ins_encode %{
6366 address con = (address)$src$$constant;
6367 Register dst = $dst$$Register;
6368 if (con == NULL) {
6369 ShouldNotReachHere();
6370 } else {
6371 __ movoop(dst, (jobject)$src$$constant);
6372 __ encode_heap_oop_not_null(dst);
6373 }
6374 %}
6375 ins_pipe(ialu_reg_fat); // XXX
6376 %}
6377
6378 instruct loadConF0(regF dst, immF0 src)
6379 %{
6380 match(Set dst src);
6381 ins_cost(100);
6382
6383 format %{ "xorps $dst, $dst\t# float 0.0" %}
6384 opcode(0x0F, 0x57);
6979 %{
6980 match(Set dst (CastX2P src));
6981
6982 format %{ "movq $dst, $src\t# long->ptr" %}
6983 ins_encode(enc_copy_wide(dst, src));
6984 ins_pipe(ialu_reg_reg); // XXX
6985 %}
6986
6987 instruct castP2X(rRegL dst, rRegP src)
6988 %{
6989 match(Set dst (CastP2X src));
6990
6991 format %{ "movq $dst, $src\t# ptr -> long" %}
6992 ins_encode(enc_copy_wide(dst, src));
6993 ins_pipe(ialu_reg_reg); // XXX
6994 %}
6995
6996
6997 // Convert oop pointer into compressed form
6998 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6999 match(Set dst (EncodeP src));
7000 effect(KILL cr);
7001 format %{ "encode_heap_oop $dst,$src" %}
7002 ins_encode %{
7003 Register s = $src$$Register;
7004 Register d = $dst$$Register;
7005 if (s != d) {
7006 __ movq(d, s);
7007 }
7008 __ encode_heap_oop(d);
7009 %}
7010 ins_pipe(ialu_reg_long);
7011 %}
7012
7013 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7014 match(Set dst (DecodeN src));
7015 effect(KILL cr);
7016 format %{ "decode_heap_oop $dst,$src" %}
7017 ins_encode %{
7018 Register s = $src$$Register;
7019 Register d = $dst$$Register;
7020 if (s != d) {
7021 __ movq(d, s);
7022 }
7023 __ decode_heap_oop(d);
7024 %}
7025 ins_pipe(ialu_reg_long);
7026 %}
7027
7028
7029 //----------Conditional Move---------------------------------------------------
7030 // Jump
7031 // dummy instruction for generating temp registers
7032 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7033 match(Jump (LShiftL switch_val shift));
7034 ins_cost(350);
7035 predicate(false);
7036 effect(TEMP dest);
7037
7038 format %{ "leaq $dest, table_base\n\t"
7039 "jmp [$dest + $switch_val << $shift]\n\t" %}
7040 ins_encode(jump_enc_offset(switch_val, shift, dest));
7041 ins_pipe(pipe_jmp);
7042 ins_pc_relative(1);
7043 %}
7044
7045 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
|
6063 // Load Klass Pointer
6064 instruct loadKlass(rRegP dst, memory mem)
6065 %{
6066 match(Set dst (LoadKlass mem));
6067 predicate(!n->in(MemNode::Address)->bottom_type()->is_narrow());
6068
6069 ins_cost(125); // XXX
6070 format %{ "movq $dst, $mem\t# class" %}
6071 opcode(0x8B);
6072 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6073 ins_pipe(ialu_reg_mem); // XXX
6074 %}
6075
6076 // Load Klass Pointer
6077 instruct loadKlassComp(rRegP dst, memory mem)
6078 %{
6079 match(Set dst (LoadKlass mem));
6080 predicate(n->in(MemNode::Address)->bottom_type()->is_narrow());
6081
6082 ins_cost(125); // XXX
6083 format %{ "movl $dst, $mem\t# compressed class\n\t"
6084 "decode_heap_oop $dst,$dst" %}
6085 ins_encode %{
6086 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6087 Register dst = as_Register($dst$$reg);
6088 __ movl(dst, addr);
6089 // klass is never null in the header but this is generated for all
6090 // klass loads not just the _klass field in the header.
6091 __ decode_heap_oop(dst);
6092 %}
6093 ins_pipe(ialu_reg_mem); // XXX
6094 %}
6095
6096 // Load Float
6097 instruct loadF(regF dst, memory mem)
6098 %{
6099 match(Set dst (LoadF mem));
6100
6101 ins_cost(145); // XXX
6102 format %{ "movss $dst, $mem\t# float" %}
6103 opcode(0xF3, 0x0F, 0x10);
6104 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6333
6334 ins_cost(60);
6335 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6336 ins_encode(load_immP31(dst, src));
6337 ins_pipe(ialu_reg);
6338 %}
6339
6340 instruct loadConF(regF dst, immF src)
6341 %{
6342 match(Set dst src);
6343 ins_cost(125);
6344
6345 format %{ "movss $dst, [$src]" %}
6346 ins_encode(load_conF(dst, src));
6347 ins_pipe(pipe_slow);
6348 %}
6349
6350 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6351 match(Set dst src);
6352 effect(KILL cr);
6353 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6354 ins_encode %{
6355 Register dst = $dst$$Register;
6356 __ xorq(dst, dst);
6357 %}
6358 ins_pipe(ialu_reg);
6359 %}
6360
6361 instruct loadConN(rRegN dst, immN src) %{
6362 match(Set dst src);
6363
6364 ins_cost(125);
6365 format %{ "movq $dst, $src\t# compressed ptr\n\t"
6366 "encode_heap_oop_not_null $dst,$dst" %}
6367 ins_encode %{
6368 address con = (address)$src$$constant;
6369 Register dst = $dst$$Register;
6370 if (con == NULL) {
6371 ShouldNotReachHere();
6372 } else {
6373 __ movoop(dst, (jobject)$src$$constant);
6374 __ encode_heap_oop_not_null(dst);
6375 }
6376 %}
6377 ins_pipe(ialu_reg_fat); // XXX
6378 %}
6379
6380 instruct loadConF0(regF dst, immF0 src)
6381 %{
6382 match(Set dst src);
6383 ins_cost(100);
6384
6385 format %{ "xorps $dst, $dst\t# float 0.0" %}
6386 opcode(0x0F, 0x57);
6981 %{
6982 match(Set dst (CastX2P src));
6983
6984 format %{ "movq $dst, $src\t# long->ptr" %}
6985 ins_encode(enc_copy_wide(dst, src));
6986 ins_pipe(ialu_reg_reg); // XXX
6987 %}
6988
6989 instruct castP2X(rRegL dst, rRegP src)
6990 %{
6991 match(Set dst (CastP2X src));
6992
6993 format %{ "movq $dst, $src\t# ptr -> long" %}
6994 ins_encode(enc_copy_wide(dst, src));
6995 ins_pipe(ialu_reg_reg); // XXX
6996 %}
6997
6998
6999 // Convert oop pointer into compressed form
7000 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7001 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() != TypePtr::NotNull);
7002 match(Set dst (EncodeP src));
7003 effect(KILL cr);
7004 format %{ "encode_heap_oop $dst,$src" %}
7005 ins_encode %{
7006 Register s = $src$$Register;
7007 Register d = $dst$$Register;
7008 if (s != d) {
7009 __ movq(d, s);
7010 }
7011 __ encode_heap_oop(d);
7012 %}
7013 ins_pipe(ialu_reg_long);
7014 %}
7015
7016 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7017 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() == TypePtr::NotNull);
7018 match(Set dst (EncodeP src));
7019 effect(KILL cr);
7020 format %{ "encode_heap_oop_not_null $dst,$src" %}
7021 ins_encode %{
7022 Register s = $src$$Register;
7023 Register d = $dst$$Register;
7024 __ encode_heap_oop_not_null(d, s);
7025 %}
7026 ins_pipe(ialu_reg_long);
7027 %}
7028
7029 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7030 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull);
7031 match(Set dst (DecodeN src));
7032 effect(KILL cr);
7033 format %{ "decode_heap_oop $dst,$src" %}
7034 ins_encode %{
7035 Register s = $src$$Register;
7036 Register d = $dst$$Register;
7037 if (s != d) {
7038 __ movq(d, s);
7039 }
7040 __ decode_heap_oop(d);
7041 %}
7042 ins_pipe(ialu_reg_long);
7043 %}
7044
7045 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{
7046 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull);
7047 match(Set dst (DecodeN src));
7048 format %{ "decode_heap_oop_not_null $dst,$src" %}
7049 ins_encode %{
7050 Register s = $src$$Register;
7051 Register d = $dst$$Register;
7052 __ decode_heap_oop_not_null(d, s);
7053 %}
7054 ins_pipe(ialu_reg_long);
7055 %}
7056
7057
7058 //----------Conditional Move---------------------------------------------------
7059 // Jump
7060 // dummy instruction for generating temp registers
7061 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7062 match(Jump (LShiftL switch_val shift));
7063 ins_cost(350);
7064 predicate(false);
7065 effect(TEMP dest);
7066
7067 format %{ "leaq $dest, table_base\n\t"
7068 "jmp [$dest + $switch_val << $shift]\n\t" %}
7069 ins_encode(jump_enc_offset(switch_val, shift, dest));
7070 ins_pipe(pipe_jmp);
7071 ins_pc_relative(1);
7072 %}
7073
7074 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
|