1 //
2 // Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
143
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
146
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
149
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
152
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
155
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
158
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
161
162 #ifdef _WIN64
163
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
166
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
169
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
172
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
175
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
178
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
181
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
184
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
187
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
190
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
193
194 #else
195
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
198
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
201
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
204
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
207
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
210
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
213
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
216
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
219
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
222
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
225
226 #endif // _WIN64
227
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
229
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
237
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
254
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
272
273 alloc_class chunk2(RFLAGS);
274
275
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
302
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
317
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R12, R12_H,
330 R13, R13_H,
331 R14, R14_H);
332
333 reg_class ptr_no_rbp_reg(RDX, RDX_H,
334 RAX, RAX_H,
335 RDI, RDI_H,
336 RSI, RSI_H,
337 RCX, RCX_H,
338 RBX, RBX_H,
339 R8, R8_H,
340 R9, R9_H,
341 R10, R10_H,
342 R11, R11_H,
343 R12, R12_H,
344 R13, R13_H,
345 R14, R14_H);
346
347 // Class for all pointer registers except RAX, RBX and RSP
348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
349 RBP, RBP_H,
350 RDI, RDI_H,
351 RSI, RSI_H,
352 RCX, RCX_H,
353 R8, R8_H,
354 R9, R9_H,
355 R10, R10_H,
356 R11, R11_H,
357 R12, R12_H,
358 R13, R13_H,
359 R14, R14_H);
360
361 // Singleton class for RAX pointer register
362 reg_class ptr_rax_reg(RAX, RAX_H);
363
364 // Singleton class for RBX pointer register
365 reg_class ptr_rbx_reg(RBX, RBX_H);
366
367 // Singleton class for RSI pointer register
368 reg_class ptr_rsi_reg(RSI, RSI_H);
369
370 // Singleton class for RDI pointer register
371 reg_class ptr_rdi_reg(RDI, RDI_H);
372
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
375
376 // Singleton class for stack pointer
377 reg_class ptr_rsp_reg(RSP, RSP_H);
378
379 // Singleton class for TLS pointer
380 reg_class ptr_r15_reg(R15, R15_H);
381
382 // Class for all long registers (except RSP)
383 reg_class long_reg(RAX, RAX_H,
384 RDX, RDX_H,
385 RBP, RBP_H,
386 RDI, RDI_H,
387 RSI, RSI_H,
388 RCX, RCX_H,
389 RBX, RBX_H,
390 R8, R8_H,
391 R9, R9_H,
392 R10, R10_H,
393 R11, R11_H,
394 R13, R13_H,
395 R14, R14_H);
396
397 // Class for all long registers except RAX, RDX (and RSP)
398 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
399 RDI, RDI_H,
400 RSI, RSI_H,
401 RCX, RCX_H,
402 RBX, RBX_H,
403 R8, R8_H,
404 R9, R9_H,
405 R10, R10_H,
406 R11, R11_H,
407 R13, R13_H,
408 R14, R14_H);
409
410 // Class for all long registers except RCX (and RSP)
411 reg_class long_no_rcx_reg(RBP, RBP_H,
412 RDI, RDI_H,
413 RSI, RSI_H,
414 RAX, RAX_H,
415 RDX, RDX_H,
416 RBX, RBX_H,
417 R8, R8_H,
418 R9, R9_H,
419 R10, R10_H,
420 R11, R11_H,
421 R13, R13_H,
422 R14, R14_H);
423
424 // Class for all long registers except RAX (and RSP)
425 reg_class long_no_rax_reg(RBP, RBP_H,
426 RDX, RDX_H,
427 RDI, RDI_H,
428 RSI, RSI_H,
429 RCX, RCX_H,
430 RBX, RBX_H,
431 R8, R8_H,
432 R9, R9_H,
433 R10, R10_H,
434 R11, R11_H,
435 R13, R13_H,
436 R14, R14_H);
437
438 // Singleton class for RAX long register
439 reg_class long_rax_reg(RAX, RAX_H);
440
441 // Singleton class for RCX long register
442 reg_class long_rcx_reg(RCX, RCX_H);
443
444 // Singleton class for RDX long register
445 reg_class long_rdx_reg(RDX, RDX_H);
446
447 // Singleton class for R12 long register
448 reg_class long_r12_reg(R12, R12_H);
449
450 // Class for all int registers (except RSP)
451 reg_class int_reg(RAX,
452 RDX,
453 RBP,
454 RDI,
455 RSI,
456 RCX,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers except RCX (and RSP)
466 reg_class int_no_rcx_reg(RAX,
467 RDX,
468 RBP,
469 RDI,
470 RSI,
471 RBX,
472 R8,
473 R9,
474 R10,
475 R11,
476 R13,
477 R14);
478
479 // Class for all int registers except RAX, RDX (and RSP)
480 reg_class int_no_rax_rdx_reg(RBP,
481 RDI
482 RSI,
483 RCX,
484 RBX,
485 R8,
486 R9,
487 R10,
488 R11,
489 R13,
490 R14);
491
492 // Singleton class for RAX int register
493 reg_class int_rax_reg(RAX);
494
495 // Singleton class for RBX int register
496 reg_class int_rbx_reg(RBX);
497
498 // Singleton class for RCX int register
499 reg_class int_rcx_reg(RCX);
500
501 // Singleton class for RCX int register
502 reg_class int_rdx_reg(RDX);
503
504 // Singleton class for RCX int register
505 reg_class int_rdi_reg(RDI);
506
507 // Singleton class for instruction pointer
508 // reg_class ip_reg(RIP);
509
510 // Singleton class for condition codes
511 reg_class int_flags(RFLAGS);
512
513 // Class for all float registers
514 reg_class float_reg(XMM0,
515 XMM1,
516 XMM2,
517 XMM3,
518 XMM4,
519 XMM5,
520 XMM6,
521 XMM7,
522 XMM8,
523 XMM9,
524 XMM10,
525 XMM11,
526 XMM12,
527 XMM13,
528 XMM14,
529 XMM15);
530
531 // Class for all double registers
532 reg_class double_reg(XMM0, XMM0_H,
533 XMM1, XMM1_H,
534 XMM2, XMM2_H,
535 XMM3, XMM3_H,
536 XMM4, XMM4_H,
537 XMM5, XMM5_H,
538 XMM6, XMM6_H,
539 XMM7, XMM7_H,
540 XMM8, XMM8_H,
541 XMM9, XMM9_H,
542 XMM10, XMM10_H,
543 XMM11, XMM11_H,
544 XMM12, XMM12_H,
545 XMM13, XMM13_H,
546 XMM14, XMM14_H,
547 XMM15, XMM15_H);
548 %}
549
550
551 //----------SOURCE BLOCK-------------------------------------------------------
552 // This is a block of C++ code which provides values, functions, and
553 // definitions necessary in the rest of the architecture description
554 source %{
555 #define RELOC_IMM64 Assembler::imm64_operand
556 #define RELOC_DISP32 Assembler::disp32_operand
557
558 #define __ _masm.
559
560 // !!!!! Special hack to get all types of calls to specify the byte offset
561 // from the start of the call to the point where the return address
562 // will point.
563 int MachCallStaticJavaNode::ret_addr_offset()
564 {
565 return 5; // 5 bytes from start of call to where return address points
566 }
567
568 int MachCallDynamicJavaNode::ret_addr_offset()
569 {
570 return 15; // 15 bytes from start of call to where return address points
571 }
572
573 // In os_cpu .ad file
574 // int MachCallRuntimeNode::ret_addr_offset()
575
576 // Indicate if the safepoint node needs the polling page as an input.
577 // Since amd64 does not have absolute addressing but RIP-relative
578 // addressing and the polling page is within 2G, it doesn't.
579 bool SafePointNode::needs_polling_address_input()
580 {
581 return false;
582 }
583
584 //
585 // Compute padding required for nodes which need alignment
586 //
587
588 // The address of the call instruction needs to be 4-byte aligned to
589 // ensure that it does not span a cache line so that it can be patched.
590 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
591 {
592 current_offset += 1; // skip call opcode byte
593 return round_to(current_offset, alignment_required()) - current_offset;
594 }
595
596 // The address of the call instruction needs to be 4-byte aligned to
597 // ensure that it does not span a cache line so that it can be patched.
598 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
599 {
600 current_offset += 11; // skip movq instruction + call opcode byte
601 return round_to(current_offset, alignment_required()) - current_offset;
602 }
603
604 #ifndef PRODUCT
605 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
606 {
607 st->print("INT3");
608 }
609 #endif
610
611 // EMIT_RM()
612 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3)
613 {
614 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
615 *(cbuf.code_end()) = c;
616 cbuf.set_code_end(cbuf.code_end() + 1);
617 }
618
619 // EMIT_CC()
620 void emit_cc(CodeBuffer &cbuf, int f1, int f2)
621 {
622 unsigned char c = (unsigned char) (f1 | f2);
623 *(cbuf.code_end()) = c;
624 cbuf.set_code_end(cbuf.code_end() + 1);
625 }
626
627 // EMIT_OPCODE()
628 void emit_opcode(CodeBuffer &cbuf, int code)
629 {
630 *(cbuf.code_end()) = (unsigned char) code;
631 cbuf.set_code_end(cbuf.code_end() + 1);
632 }
633
634 // EMIT_OPCODE() w/ relocation information
635 void emit_opcode(CodeBuffer &cbuf,
636 int code, relocInfo::relocType reloc, int offset, int format)
637 {
638 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format);
639 emit_opcode(cbuf, code);
640 }
641
642 // EMIT_D8()
643 void emit_d8(CodeBuffer &cbuf, int d8)
644 {
645 *(cbuf.code_end()) = (unsigned char) d8;
646 cbuf.set_code_end(cbuf.code_end() + 1);
647 }
648
649 // EMIT_D16()
650 void emit_d16(CodeBuffer &cbuf, int d16)
651 {
652 *((short *)(cbuf.code_end())) = d16;
653 cbuf.set_code_end(cbuf.code_end() + 2);
654 }
655
656 // EMIT_D32()
657 void emit_d32(CodeBuffer &cbuf, int d32)
658 {
659 *((int *)(cbuf.code_end())) = d32;
660 cbuf.set_code_end(cbuf.code_end() + 4);
661 }
662
663 // EMIT_D64()
664 void emit_d64(CodeBuffer &cbuf, int64_t d64)
665 {
666 *((int64_t*) (cbuf.code_end())) = d64;
667 cbuf.set_code_end(cbuf.code_end() + 8);
668 }
669
670 // emit 32 bit value and construct relocation entry from relocInfo::relocType
671 void emit_d32_reloc(CodeBuffer& cbuf,
672 int d32,
673 relocInfo::relocType reloc,
674 int format)
675 {
676 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
677 cbuf.relocate(cbuf.inst_mark(), reloc, format);
678
679 *((int*) (cbuf.code_end())) = d32;
680 cbuf.set_code_end(cbuf.code_end() + 4);
681 }
682
683 // emit 32 bit value and construct relocation entry from RelocationHolder
684 void emit_d32_reloc(CodeBuffer& cbuf,
685 int d32,
686 RelocationHolder const& rspec,
687 int format)
688 {
689 #ifdef ASSERT
690 if (rspec.reloc()->type() == relocInfo::oop_type &&
691 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
692 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code");
693 }
694 #endif
695 cbuf.relocate(cbuf.inst_mark(), rspec, format);
696
697 *((int* )(cbuf.code_end())) = d32;
698 cbuf.set_code_end(cbuf.code_end() + 4);
699 }
700
701 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
702 address next_ip = cbuf.code_end() + 4;
703 emit_d32_reloc(cbuf, (int) (addr - next_ip),
704 external_word_Relocation::spec(addr),
705 RELOC_DISP32);
706 }
707
708
709 // emit 64 bit value and construct relocation entry from relocInfo::relocType
710 void emit_d64_reloc(CodeBuffer& cbuf,
711 int64_t d64,
712 relocInfo::relocType reloc,
713 int format)
714 {
715 cbuf.relocate(cbuf.inst_mark(), reloc, format);
716
717 *((int64_t*) (cbuf.code_end())) = d64;
718 cbuf.set_code_end(cbuf.code_end() + 8);
719 }
720
721 // emit 64 bit value and construct relocation entry from RelocationHolder
722 void emit_d64_reloc(CodeBuffer& cbuf,
723 int64_t d64,
724 RelocationHolder const& rspec,
725 int format)
726 {
727 #ifdef ASSERT
728 if (rspec.reloc()->type() == relocInfo::oop_type &&
729 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
730 assert(oop(d64)->is_oop() && oop(d64)->is_perm(),
731 "cannot embed non-perm oops in code");
732 }
733 #endif
734 cbuf.relocate(cbuf.inst_mark(), rspec, format);
735
736 *((int64_t*) (cbuf.code_end())) = d64;
737 cbuf.set_code_end(cbuf.code_end() + 8);
738 }
739
740 // Access stack slot for load or store
741 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
742 {
743 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
744 if (-0x80 <= disp && disp < 0x80) {
745 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
746 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
747 emit_d8(cbuf, disp); // Displacement // R/M byte
748 } else {
749 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
750 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
751 emit_d32(cbuf, disp); // Displacement // R/M byte
752 }
753 }
754
755 // rRegI ereg, memory mem) %{ // emit_reg_mem
756 void encode_RegMem(CodeBuffer &cbuf,
757 int reg,
758 int base, int index, int scale, int disp, bool disp_is_oop)
759 {
760 assert(!disp_is_oop, "cannot have disp");
761 int regenc = reg & 7;
762 int baseenc = base & 7;
763 int indexenc = index & 7;
764
765 // There is no index & no scale, use form without SIB byte
766 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
767 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
768 if (disp == 0 && base != RBP_enc && base != R13_enc) {
769 emit_rm(cbuf, 0x0, regenc, baseenc); // *
770 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
771 // If 8-bit displacement, mode 0x1
772 emit_rm(cbuf, 0x1, regenc, baseenc); // *
773 emit_d8(cbuf, disp);
774 } else {
775 // If 32-bit displacement
776 if (base == -1) { // Special flag for absolute address
777 emit_rm(cbuf, 0x0, regenc, 0x5); // *
778 if (disp_is_oop) {
779 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
780 } else {
781 emit_d32(cbuf, disp);
782 }
783 } else {
784 // Normal base + offset
785 emit_rm(cbuf, 0x2, regenc, baseenc); // *
786 if (disp_is_oop) {
787 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
788 } else {
789 emit_d32(cbuf, disp);
790 }
791 }
792 }
793 } else {
794 // Else, encode with the SIB byte
795 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
796 if (disp == 0 && base != RBP_enc && base != R13_enc) {
797 // If no displacement
798 emit_rm(cbuf, 0x0, regenc, 0x4); // *
799 emit_rm(cbuf, scale, indexenc, baseenc);
800 } else {
801 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
802 // If 8-bit displacement, mode 0x1
803 emit_rm(cbuf, 0x1, regenc, 0x4); // *
804 emit_rm(cbuf, scale, indexenc, baseenc);
805 emit_d8(cbuf, disp);
806 } else {
807 // If 32-bit displacement
808 if (base == 0x04 ) {
809 emit_rm(cbuf, 0x2, regenc, 0x4);
810 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
811 } else {
812 emit_rm(cbuf, 0x2, regenc, 0x4);
813 emit_rm(cbuf, scale, indexenc, baseenc); // *
814 }
815 if (disp_is_oop) {
816 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
817 } else {
818 emit_d32(cbuf, disp);
819 }
820 }
821 }
822 }
823 }
824
825 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
826 {
827 if (dstenc != srcenc) {
828 if (dstenc < 8) {
829 if (srcenc >= 8) {
830 emit_opcode(cbuf, Assembler::REX_B);
831 srcenc -= 8;
832 }
833 } else {
834 if (srcenc < 8) {
835 emit_opcode(cbuf, Assembler::REX_R);
836 } else {
837 emit_opcode(cbuf, Assembler::REX_RB);
838 srcenc -= 8;
839 }
840 dstenc -= 8;
841 }
842
843 emit_opcode(cbuf, 0x8B);
844 emit_rm(cbuf, 0x3, dstenc, srcenc);
845 }
846 }
847
848 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
849 if( dst_encoding == src_encoding ) {
850 // reg-reg copy, use an empty encoding
851 } else {
852 MacroAssembler _masm(&cbuf);
853
854 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
855 }
856 }
857
858
859 //=============================================================================
860 #ifndef PRODUCT
861 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
862 {
863 Compile* C = ra_->C;
864
865 int framesize = C->frame_slots() << LogBytesPerInt;
866 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
867 // Remove wordSize for return adr already pushed
868 // and another for the RBP we are going to save
869 framesize -= 2*wordSize;
870 bool need_nop = true;
871
872 // Calls to C2R adapters often do not accept exceptional returns.
873 // We require that their callers must bang for them. But be
874 // careful, because some VM calls (such as call site linkage) can
875 // use several kilobytes of stack. But the stack safety zone should
876 // account for that. See bugs 4446381, 4468289, 4497237.
877 if (C->need_stack_bang(framesize)) {
878 st->print_cr("# stack bang"); st->print("\t");
879 need_nop = false;
880 }
881 st->print_cr("pushq rbp"); st->print("\t");
882
883 if (VerifyStackAtCalls) {
884 // Majik cookie to verify stack depth
885 st->print_cr("pushq 0xffffffffbadb100d"
886 "\t# Majik cookie for stack depth check");
887 st->print("\t");
888 framesize -= wordSize; // Remove 2 for cookie
889 need_nop = false;
890 }
891
892 if (framesize) {
893 st->print("subq rsp, #%d\t# Create frame", framesize);
894 if (framesize < 0x80 && need_nop) {
895 st->print("\n\tnop\t# nop for patch_verified_entry");
896 }
897 }
898 }
899 #endif
900
901 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
902 {
903 Compile* C = ra_->C;
904
905 // WARNING: Initial instruction MUST be 5 bytes or longer so that
906 // NativeJump::patch_verified_entry will be able to patch out the entry
907 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
908 // depth is ok at 5 bytes, the frame allocation can be either 3 or
909 // 6 bytes. So if we don't do the fldcw or the push then we must
910 // use the 6 byte frame allocation even if we have no frame. :-(
911 // If method sets FPU control word do it now
912
913 int framesize = C->frame_slots() << LogBytesPerInt;
914 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
915 // Remove wordSize for return adr already pushed
916 // and another for the RBP we are going to save
917 framesize -= 2*wordSize;
918 bool need_nop = true;
919
920 // Calls to C2R adapters often do not accept exceptional returns.
921 // We require that their callers must bang for them. But be
922 // careful, because some VM calls (such as call site linkage) can
923 // use several kilobytes of stack. But the stack safety zone should
924 // account for that. See bugs 4446381, 4468289, 4497237.
925 if (C->need_stack_bang(framesize)) {
926 MacroAssembler masm(&cbuf);
927 masm.generate_stack_overflow_check(framesize);
928 need_nop = false;
929 }
930
931 // We always push rbp so that on return to interpreter rbp will be
932 // restored correctly and we can correct the stack.
933 emit_opcode(cbuf, 0x50 | RBP_enc);
934
935 if (VerifyStackAtCalls) {
936 // Majik cookie to verify stack depth
937 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
938 emit_d32(cbuf, 0xbadb100d);
939 framesize -= wordSize; // Remove 2 for cookie
940 need_nop = false;
941 }
942
943 if (framesize) {
944 emit_opcode(cbuf, Assembler::REX_W);
945 if (framesize < 0x80) {
946 emit_opcode(cbuf, 0x83); // sub SP,#framesize
947 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
948 emit_d8(cbuf, framesize);
949 if (need_nop) {
950 emit_opcode(cbuf, 0x90); // nop
951 }
952 } else {
953 emit_opcode(cbuf, 0x81); // sub SP,#framesize
954 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
955 emit_d32(cbuf, framesize);
956 }
957 }
958
959 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
960
961 #ifdef ASSERT
962 if (VerifyStackAtCalls) {
963 Label L;
964 MacroAssembler masm(&cbuf);
965 masm.pushq(rax);
966 masm.movq(rax, rsp);
967 masm.andq(rax, StackAlignmentInBytes-1);
968 masm.cmpq(rax, StackAlignmentInBytes-wordSize);
969 masm.popq(rax);
970 masm.jcc(Assembler::equal, L);
971 masm.stop("Stack is not properly aligned!");
972 masm.bind(L);
973 }
974 #endif
975 }
976
977 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
978 {
979 return MachNode::size(ra_); // too many variables; just compute it
980 // the hard way
981 }
982
983 int MachPrologNode::reloc() const
984 {
985 return 0; // a large enough number
986 }
987
988 //=============================================================================
989 #ifndef PRODUCT
990 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
991 {
992 Compile* C = ra_->C;
993 int framesize = C->frame_slots() << LogBytesPerInt;
994 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
995 // Remove word for return adr already pushed
996 // and RBP
997 framesize -= 2*wordSize;
998
999 if (framesize) {
1000 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
1001 st->print("\t");
1002 }
1003
1004 st->print_cr("popq\trbp");
1005 if (do_polling() && C->is_method_compilation()) {
1006 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
1007 "# Safepoint: poll for GC");
1008 st->print("\t");
1009 }
1010 }
1011 #endif
1012
1013 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1014 {
1015 Compile* C = ra_->C;
1016 int framesize = C->frame_slots() << LogBytesPerInt;
1017 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1018 // Remove word for return adr already pushed
1019 // and RBP
1020 framesize -= 2*wordSize;
1021
1022 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1023
1024 if (framesize) {
1025 emit_opcode(cbuf, Assembler::REX_W);
1026 if (framesize < 0x80) {
1027 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1028 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1029 emit_d8(cbuf, framesize);
1030 } else {
1031 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1032 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1033 emit_d32(cbuf, framesize);
1034 }
1035 }
1036
1037 // popq rbp
1038 emit_opcode(cbuf, 0x58 | RBP_enc);
1039
1040 if (do_polling() && C->is_method_compilation()) {
1041 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
1042 // XXX reg_mem doesn't support RIP-relative addressing yet
1043 cbuf.set_inst_mark();
1044 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX
1045 emit_opcode(cbuf, 0x85); // testl
1046 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
1047 // cbuf.inst_mark() is beginning of instruction
1048 emit_d32_reloc(cbuf, os::get_polling_page());
1049 // relocInfo::poll_return_type,
1050 }
1051 }
1052
1053 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1054 {
1055 Compile* C = ra_->C;
1056 int framesize = C->frame_slots() << LogBytesPerInt;
1057 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1058 // Remove word for return adr already pushed
1059 // and RBP
1060 framesize -= 2*wordSize;
1061
1062 uint size = 0;
1063
1064 if (do_polling() && C->is_method_compilation()) {
1065 size += 6;
1066 }
1067
1068 // count popq rbp
1069 size++;
1070
1071 if (framesize) {
1072 if (framesize < 0x80) {
1073 size += 4;
1074 } else if (framesize) {
1075 size += 7;
1076 }
1077 }
1078
1079 return size;
1080 }
1081
1082 int MachEpilogNode::reloc() const
1083 {
1084 return 2; // a large enough number
1085 }
1086
1087 const Pipeline* MachEpilogNode::pipeline() const
1088 {
1089 return MachNode::pipeline_class();
1090 }
1091
1092 int MachEpilogNode::safepoint_offset() const
1093 {
1094 return 0;
1095 }
1096
1097 //=============================================================================
1098
1099 enum RC {
1100 rc_bad,
1101 rc_int,
1102 rc_float,
1103 rc_stack
1104 };
1105
1106 static enum RC rc_class(OptoReg::Name reg)
1107 {
1108 if( !OptoReg::is_valid(reg) ) return rc_bad;
1109
1110 if (OptoReg::is_stack(reg)) return rc_stack;
1111
1112 VMReg r = OptoReg::as_VMReg(reg);
1113
1114 if (r->is_Register()) return rc_int;
1115
1116 assert(r->is_XMMRegister(), "must be");
1117 return rc_float;
1118 }
1119
1120 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1121 PhaseRegAlloc* ra_,
1122 bool do_size,
1123 outputStream* st) const
1124 {
1125
1126 // Get registers to move
1127 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1128 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1129 OptoReg::Name dst_second = ra_->get_reg_second(this);
1130 OptoReg::Name dst_first = ra_->get_reg_first(this);
1131
1132 enum RC src_second_rc = rc_class(src_second);
1133 enum RC src_first_rc = rc_class(src_first);
1134 enum RC dst_second_rc = rc_class(dst_second);
1135 enum RC dst_first_rc = rc_class(dst_first);
1136
1137 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1138 "must move at least 1 register" );
1139
1140 if (src_first == dst_first && src_second == dst_second) {
1141 // Self copy, no move
1142 return 0;
1143 } else if (src_first_rc == rc_stack) {
1144 // mem ->
1145 if (dst_first_rc == rc_stack) {
1146 // mem -> mem
1147 assert(src_second != dst_first, "overlap");
1148 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1149 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1150 // 64-bit
1151 int src_offset = ra_->reg2offset(src_first);
1152 int dst_offset = ra_->reg2offset(dst_first);
1153 if (cbuf) {
1154 emit_opcode(*cbuf, 0xFF);
1155 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1156
1157 emit_opcode(*cbuf, 0x8F);
1158 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1159
1160 #ifndef PRODUCT
1161 } else if (!do_size) {
1162 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1163 "popq [rsp + #%d]",
1164 src_offset,
1165 dst_offset);
1166 #endif
1167 }
1168 return
1169 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1170 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1171 } else {
1172 // 32-bit
1173 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1174 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1175 // No pushl/popl, so:
1176 int src_offset = ra_->reg2offset(src_first);
1177 int dst_offset = ra_->reg2offset(dst_first);
1178 if (cbuf) {
1179 emit_opcode(*cbuf, Assembler::REX_W);
1180 emit_opcode(*cbuf, 0x89);
1181 emit_opcode(*cbuf, 0x44);
1182 emit_opcode(*cbuf, 0x24);
1183 emit_opcode(*cbuf, 0xF8);
1184
1185 emit_opcode(*cbuf, 0x8B);
1186 encode_RegMem(*cbuf,
1187 RAX_enc,
1188 RSP_enc, 0x4, 0, src_offset,
1189 false);
1190
1191 emit_opcode(*cbuf, 0x89);
1192 encode_RegMem(*cbuf,
1193 RAX_enc,
1194 RSP_enc, 0x4, 0, dst_offset,
1195 false);
1196
1197 emit_opcode(*cbuf, Assembler::REX_W);
1198 emit_opcode(*cbuf, 0x8B);
1199 emit_opcode(*cbuf, 0x44);
1200 emit_opcode(*cbuf, 0x24);
1201 emit_opcode(*cbuf, 0xF8);
1202
1203 #ifndef PRODUCT
1204 } else if (!do_size) {
1205 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1206 "movl rax, [rsp + #%d]\n\t"
1207 "movl [rsp + #%d], rax\n\t"
1208 "movq rax, [rsp - #8]",
1209 src_offset,
1210 dst_offset);
1211 #endif
1212 }
1213 return
1214 5 + // movq
1215 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1216 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1217 5; // movq
1218 }
1219 } else if (dst_first_rc == rc_int) {
1220 // mem -> gpr
1221 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1222 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1223 // 64-bit
1224 int offset = ra_->reg2offset(src_first);
1225 if (cbuf) {
1226 if (Matcher::_regEncode[dst_first] < 8) {
1227 emit_opcode(*cbuf, Assembler::REX_W);
1228 } else {
1229 emit_opcode(*cbuf, Assembler::REX_WR);
1230 }
1231 emit_opcode(*cbuf, 0x8B);
1232 encode_RegMem(*cbuf,
1233 Matcher::_regEncode[dst_first],
1234 RSP_enc, 0x4, 0, offset,
1235 false);
1236 #ifndef PRODUCT
1237 } else if (!do_size) {
1238 st->print("movq %s, [rsp + #%d]\t# spill",
1239 Matcher::regName[dst_first],
1240 offset);
1241 #endif
1242 }
1243 return
1244 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1245 } else {
1246 // 32-bit
1247 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1248 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1249 int offset = ra_->reg2offset(src_first);
1250 if (cbuf) {
1251 if (Matcher::_regEncode[dst_first] >= 8) {
1252 emit_opcode(*cbuf, Assembler::REX_R);
1253 }
1254 emit_opcode(*cbuf, 0x8B);
1255 encode_RegMem(*cbuf,
1256 Matcher::_regEncode[dst_first],
1257 RSP_enc, 0x4, 0, offset,
1258 false);
1259 #ifndef PRODUCT
1260 } else if (!do_size) {
1261 st->print("movl %s, [rsp + #%d]\t# spill",
1262 Matcher::regName[dst_first],
1263 offset);
1264 #endif
1265 }
1266 return
1267 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1268 ((Matcher::_regEncode[dst_first] < 8)
1269 ? 3
1270 : 4); // REX
1271 }
1272 } else if (dst_first_rc == rc_float) {
1273 // mem-> xmm
1274 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1275 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1276 // 64-bit
1277 int offset = ra_->reg2offset(src_first);
1278 if (cbuf) {
1279 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1280 if (Matcher::_regEncode[dst_first] >= 8) {
1281 emit_opcode(*cbuf, Assembler::REX_R);
1282 }
1283 emit_opcode(*cbuf, 0x0F);
1284 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1285 encode_RegMem(*cbuf,
1286 Matcher::_regEncode[dst_first],
1287 RSP_enc, 0x4, 0, offset,
1288 false);
1289 #ifndef PRODUCT
1290 } else if (!do_size) {
1291 st->print("%s %s, [rsp + #%d]\t# spill",
1292 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1293 Matcher::regName[dst_first],
1294 offset);
1295 #endif
1296 }
1297 return
1298 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1299 ((Matcher::_regEncode[dst_first] < 8)
1300 ? 5
1301 : 6); // REX
1302 } else {
1303 // 32-bit
1304 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1305 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1306 int offset = ra_->reg2offset(src_first);
1307 if (cbuf) {
1308 emit_opcode(*cbuf, 0xF3);
1309 if (Matcher::_regEncode[dst_first] >= 8) {
1310 emit_opcode(*cbuf, Assembler::REX_R);
1311 }
1312 emit_opcode(*cbuf, 0x0F);
1313 emit_opcode(*cbuf, 0x10);
1314 encode_RegMem(*cbuf,
1315 Matcher::_regEncode[dst_first],
1316 RSP_enc, 0x4, 0, offset,
1317 false);
1318 #ifndef PRODUCT
1319 } else if (!do_size) {
1320 st->print("movss %s, [rsp + #%d]\t# spill",
1321 Matcher::regName[dst_first],
1322 offset);
1323 #endif
1324 }
1325 return
1326 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1327 ((Matcher::_regEncode[dst_first] < 8)
1328 ? 5
1329 : 6); // REX
1330 }
1331 }
1332 } else if (src_first_rc == rc_int) {
1333 // gpr ->
1334 if (dst_first_rc == rc_stack) {
1335 // gpr -> mem
1336 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1337 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1338 // 64-bit
1339 int offset = ra_->reg2offset(dst_first);
1340 if (cbuf) {
1341 if (Matcher::_regEncode[src_first] < 8) {
1342 emit_opcode(*cbuf, Assembler::REX_W);
1343 } else {
1344 emit_opcode(*cbuf, Assembler::REX_WR);
1345 }
1346 emit_opcode(*cbuf, 0x89);
1347 encode_RegMem(*cbuf,
1348 Matcher::_regEncode[src_first],
1349 RSP_enc, 0x4, 0, offset,
1350 false);
1351 #ifndef PRODUCT
1352 } else if (!do_size) {
1353 st->print("movq [rsp + #%d], %s\t# spill",
1354 offset,
1355 Matcher::regName[src_first]);
1356 #endif
1357 }
1358 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1359 } else {
1360 // 32-bit
1361 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1362 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1363 int offset = ra_->reg2offset(dst_first);
1364 if (cbuf) {
1365 if (Matcher::_regEncode[src_first] >= 8) {
1366 emit_opcode(*cbuf, Assembler::REX_R);
1367 }
1368 emit_opcode(*cbuf, 0x89);
1369 encode_RegMem(*cbuf,
1370 Matcher::_regEncode[src_first],
1371 RSP_enc, 0x4, 0, offset,
1372 false);
1373 #ifndef PRODUCT
1374 } else if (!do_size) {
1375 st->print("movl [rsp + #%d], %s\t# spill",
1376 offset,
1377 Matcher::regName[src_first]);
1378 #endif
1379 }
1380 return
1381 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1382 ((Matcher::_regEncode[src_first] < 8)
1383 ? 3
1384 : 4); // REX
1385 }
1386 } else if (dst_first_rc == rc_int) {
1387 // gpr -> gpr
1388 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1389 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1390 // 64-bit
1391 if (cbuf) {
1392 if (Matcher::_regEncode[dst_first] < 8) {
1393 if (Matcher::_regEncode[src_first] < 8) {
1394 emit_opcode(*cbuf, Assembler::REX_W);
1395 } else {
1396 emit_opcode(*cbuf, Assembler::REX_WB);
1397 }
1398 } else {
1399 if (Matcher::_regEncode[src_first] < 8) {
1400 emit_opcode(*cbuf, Assembler::REX_WR);
1401 } else {
1402 emit_opcode(*cbuf, Assembler::REX_WRB);
1403 }
1404 }
1405 emit_opcode(*cbuf, 0x8B);
1406 emit_rm(*cbuf, 0x3,
1407 Matcher::_regEncode[dst_first] & 7,
1408 Matcher::_regEncode[src_first] & 7);
1409 #ifndef PRODUCT
1410 } else if (!do_size) {
1411 st->print("movq %s, %s\t# spill",
1412 Matcher::regName[dst_first],
1413 Matcher::regName[src_first]);
1414 #endif
1415 }
1416 return 3; // REX
1417 } else {
1418 // 32-bit
1419 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1420 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1421 if (cbuf) {
1422 if (Matcher::_regEncode[dst_first] < 8) {
1423 if (Matcher::_regEncode[src_first] >= 8) {
1424 emit_opcode(*cbuf, Assembler::REX_B);
1425 }
1426 } else {
1427 if (Matcher::_regEncode[src_first] < 8) {
1428 emit_opcode(*cbuf, Assembler::REX_R);
1429 } else {
1430 emit_opcode(*cbuf, Assembler::REX_RB);
1431 }
1432 }
1433 emit_opcode(*cbuf, 0x8B);
1434 emit_rm(*cbuf, 0x3,
1435 Matcher::_regEncode[dst_first] & 7,
1436 Matcher::_regEncode[src_first] & 7);
1437 #ifndef PRODUCT
1438 } else if (!do_size) {
1439 st->print("movl %s, %s\t# spill",
1440 Matcher::regName[dst_first],
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 return
1445 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1446 ? 2
1447 : 3; // REX
1448 }
1449 } else if (dst_first_rc == rc_float) {
1450 // gpr -> xmm
1451 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1452 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1453 // 64-bit
1454 if (cbuf) {
1455 emit_opcode(*cbuf, 0x66);
1456 if (Matcher::_regEncode[dst_first] < 8) {
1457 if (Matcher::_regEncode[src_first] < 8) {
1458 emit_opcode(*cbuf, Assembler::REX_W);
1459 } else {
1460 emit_opcode(*cbuf, Assembler::REX_WB);
1461 }
1462 } else {
1463 if (Matcher::_regEncode[src_first] < 8) {
1464 emit_opcode(*cbuf, Assembler::REX_WR);
1465 } else {
1466 emit_opcode(*cbuf, Assembler::REX_WRB);
1467 }
1468 }
1469 emit_opcode(*cbuf, 0x0F);
1470 emit_opcode(*cbuf, 0x6E);
1471 emit_rm(*cbuf, 0x3,
1472 Matcher::_regEncode[dst_first] & 7,
1473 Matcher::_regEncode[src_first] & 7);
1474 #ifndef PRODUCT
1475 } else if (!do_size) {
1476 st->print("movdq %s, %s\t# spill",
1477 Matcher::regName[dst_first],
1478 Matcher::regName[src_first]);
1479 #endif
1480 }
1481 return 5; // REX
1482 } else {
1483 // 32-bit
1484 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1485 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1486 if (cbuf) {
1487 emit_opcode(*cbuf, 0x66);
1488 if (Matcher::_regEncode[dst_first] < 8) {
1489 if (Matcher::_regEncode[src_first] >= 8) {
1490 emit_opcode(*cbuf, Assembler::REX_B);
1491 }
1492 } else {
1493 if (Matcher::_regEncode[src_first] < 8) {
1494 emit_opcode(*cbuf, Assembler::REX_R);
1495 } else {
1496 emit_opcode(*cbuf, Assembler::REX_RB);
1497 }
1498 }
1499 emit_opcode(*cbuf, 0x0F);
1500 emit_opcode(*cbuf, 0x6E);
1501 emit_rm(*cbuf, 0x3,
1502 Matcher::_regEncode[dst_first] & 7,
1503 Matcher::_regEncode[src_first] & 7);
1504 #ifndef PRODUCT
1505 } else if (!do_size) {
1506 st->print("movdl %s, %s\t# spill",
1507 Matcher::regName[dst_first],
1508 Matcher::regName[src_first]);
1509 #endif
1510 }
1511 return
1512 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1513 ? 4
1514 : 5; // REX
1515 }
1516 }
1517 } else if (src_first_rc == rc_float) {
1518 // xmm ->
1519 if (dst_first_rc == rc_stack) {
1520 // xmm -> mem
1521 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1522 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1523 // 64-bit
1524 int offset = ra_->reg2offset(dst_first);
1525 if (cbuf) {
1526 emit_opcode(*cbuf, 0xF2);
1527 if (Matcher::_regEncode[src_first] >= 8) {
1528 emit_opcode(*cbuf, Assembler::REX_R);
1529 }
1530 emit_opcode(*cbuf, 0x0F);
1531 emit_opcode(*cbuf, 0x11);
1532 encode_RegMem(*cbuf,
1533 Matcher::_regEncode[src_first],
1534 RSP_enc, 0x4, 0, offset,
1535 false);
1536 #ifndef PRODUCT
1537 } else if (!do_size) {
1538 st->print("movsd [rsp + #%d], %s\t# spill",
1539 offset,
1540 Matcher::regName[src_first]);
1541 #endif
1542 }
1543 return
1544 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1545 ((Matcher::_regEncode[src_first] < 8)
1546 ? 5
1547 : 6); // REX
1548 } else {
1549 // 32-bit
1550 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1551 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1552 int offset = ra_->reg2offset(dst_first);
1553 if (cbuf) {
1554 emit_opcode(*cbuf, 0xF3);
1555 if (Matcher::_regEncode[src_first] >= 8) {
1556 emit_opcode(*cbuf, Assembler::REX_R);
1557 }
1558 emit_opcode(*cbuf, 0x0F);
1559 emit_opcode(*cbuf, 0x11);
1560 encode_RegMem(*cbuf,
1561 Matcher::_regEncode[src_first],
1562 RSP_enc, 0x4, 0, offset,
1563 false);
1564 #ifndef PRODUCT
1565 } else if (!do_size) {
1566 st->print("movss [rsp + #%d], %s\t# spill",
1567 offset,
1568 Matcher::regName[src_first]);
1569 #endif
1570 }
1571 return
1572 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1573 ((Matcher::_regEncode[src_first] < 8)
1574 ? 5
1575 : 6); // REX
1576 }
1577 } else if (dst_first_rc == rc_int) {
1578 // xmm -> gpr
1579 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1580 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1581 // 64-bit
1582 if (cbuf) {
1583 emit_opcode(*cbuf, 0x66);
1584 if (Matcher::_regEncode[dst_first] < 8) {
1585 if (Matcher::_regEncode[src_first] < 8) {
1586 emit_opcode(*cbuf, Assembler::REX_W);
1587 } else {
1588 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
1589 }
1590 } else {
1591 if (Matcher::_regEncode[src_first] < 8) {
1592 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
1593 } else {
1594 emit_opcode(*cbuf, Assembler::REX_WRB);
1595 }
1596 }
1597 emit_opcode(*cbuf, 0x0F);
1598 emit_opcode(*cbuf, 0x7E);
1599 emit_rm(*cbuf, 0x3,
1600 Matcher::_regEncode[dst_first] & 7,
1601 Matcher::_regEncode[src_first] & 7);
1602 #ifndef PRODUCT
1603 } else if (!do_size) {
1604 st->print("movdq %s, %s\t# spill",
1605 Matcher::regName[dst_first],
1606 Matcher::regName[src_first]);
1607 #endif
1608 }
1609 return 5; // REX
1610 } else {
1611 // 32-bit
1612 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1613 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1614 if (cbuf) {
1615 emit_opcode(*cbuf, 0x66);
1616 if (Matcher::_regEncode[dst_first] < 8) {
1617 if (Matcher::_regEncode[src_first] >= 8) {
1618 emit_opcode(*cbuf, Assembler::REX_R); // attention!
1619 }
1620 } else {
1621 if (Matcher::_regEncode[src_first] < 8) {
1622 emit_opcode(*cbuf, Assembler::REX_B); // attention!
1623 } else {
1624 emit_opcode(*cbuf, Assembler::REX_RB);
1625 }
1626 }
1627 emit_opcode(*cbuf, 0x0F);
1628 emit_opcode(*cbuf, 0x7E);
1629 emit_rm(*cbuf, 0x3,
1630 Matcher::_regEncode[dst_first] & 7,
1631 Matcher::_regEncode[src_first] & 7);
1632 #ifndef PRODUCT
1633 } else if (!do_size) {
1634 st->print("movdl %s, %s\t# spill",
1635 Matcher::regName[dst_first],
1636 Matcher::regName[src_first]);
1637 #endif
1638 }
1639 return
1640 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1641 ? 4
1642 : 5; // REX
1643 }
1644 } else if (dst_first_rc == rc_float) {
1645 // xmm -> xmm
1646 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1647 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1648 // 64-bit
1649 if (cbuf) {
1650 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
1651 if (Matcher::_regEncode[dst_first] < 8) {
1652 if (Matcher::_regEncode[src_first] >= 8) {
1653 emit_opcode(*cbuf, Assembler::REX_B);
1654 }
1655 } else {
1656 if (Matcher::_regEncode[src_first] < 8) {
1657 emit_opcode(*cbuf, Assembler::REX_R);
1658 } else {
1659 emit_opcode(*cbuf, Assembler::REX_RB);
1660 }
1661 }
1662 emit_opcode(*cbuf, 0x0F);
1663 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1664 emit_rm(*cbuf, 0x3,
1665 Matcher::_regEncode[dst_first] & 7,
1666 Matcher::_regEncode[src_first] & 7);
1667 #ifndef PRODUCT
1668 } else if (!do_size) {
1669 st->print("%s %s, %s\t# spill",
1670 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1671 Matcher::regName[dst_first],
1672 Matcher::regName[src_first]);
1673 #endif
1674 }
1675 return
1676 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1677 ? 4
1678 : 5; // REX
1679 } else {
1680 // 32-bit
1681 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1682 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1683 if (cbuf) {
1684 if (!UseXmmRegToRegMoveAll)
1685 emit_opcode(*cbuf, 0xF3);
1686 if (Matcher::_regEncode[dst_first] < 8) {
1687 if (Matcher::_regEncode[src_first] >= 8) {
1688 emit_opcode(*cbuf, Assembler::REX_B);
1689 }
1690 } else {
1691 if (Matcher::_regEncode[src_first] < 8) {
1692 emit_opcode(*cbuf, Assembler::REX_R);
1693 } else {
1694 emit_opcode(*cbuf, Assembler::REX_RB);
1695 }
1696 }
1697 emit_opcode(*cbuf, 0x0F);
1698 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1699 emit_rm(*cbuf, 0x3,
1700 Matcher::_regEncode[dst_first] & 7,
1701 Matcher::_regEncode[src_first] & 7);
1702 #ifndef PRODUCT
1703 } else if (!do_size) {
1704 st->print("%s %s, %s\t# spill",
1705 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1706 Matcher::regName[dst_first],
1707 Matcher::regName[src_first]);
1708 #endif
1709 }
1710 return
1711 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1712 ? (UseXmmRegToRegMoveAll ? 3 : 4)
1713 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
1714 }
1715 }
1716 }
1717
1718 assert(0," foo ");
1719 Unimplemented();
1720
1721 return 0;
1722 }
1723
1724 #ifndef PRODUCT
1725 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1726 {
1727 implementation(NULL, ra_, false, st);
1728 }
1729 #endif
1730
1731 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1732 {
1733 implementation(&cbuf, ra_, false, NULL);
1734 }
1735
1736 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1737 {
1738 return implementation(NULL, ra_, true, NULL);
1739 }
1740
1741 //=============================================================================
1742 #ifndef PRODUCT
1743 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1744 {
1745 st->print("nop \t# %d bytes pad for loops and calls", _count);
1746 }
1747 #endif
1748
1749 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1750 {
1751 MacroAssembler _masm(&cbuf);
1752 __ nop(_count);
1753 }
1754
1755 uint MachNopNode::size(PhaseRegAlloc*) const
1756 {
1757 return _count;
1758 }
1759
1760
1761 //=============================================================================
1762 #ifndef PRODUCT
1763 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1764 {
1765 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1766 int reg = ra_->get_reg_first(this);
1767 st->print("leaq %s, [rsp + #%d]\t# box lock",
1768 Matcher::regName[reg], offset);
1769 }
1770 #endif
1771
1772 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1773 {
1774 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1775 int reg = ra_->get_encode(this);
1776 if (offset >= 0x80) {
1777 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1778 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1779 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1780 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1781 emit_d32(cbuf, offset);
1782 } else {
1783 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1784 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1785 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1786 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1787 emit_d8(cbuf, offset);
1788 }
1789 }
1790
1791 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1792 {
1793 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1794 return (offset < 0x80) ? 5 : 8; // REX
1795 }
1796
1797 //=============================================================================
1798
1799 // emit call stub, compiled java to interpreter
1800 void emit_java_to_interp(CodeBuffer& cbuf)
1801 {
1802 // Stub is fixed up when the corresponding call is converted from
1803 // calling compiled code to calling interpreted code.
1804 // movq rbx, 0
1805 // jmp -5 # to self
1806
1807 address mark = cbuf.inst_mark(); // get mark within main instrs section
1808
1809 // Note that the code buffer's inst_mark is always relative to insts.
1810 // That's why we must use the macroassembler to generate a stub.
1811 MacroAssembler _masm(&cbuf);
1812
1813 address base =
1814 __ start_a_stub(Compile::MAX_stubs_size);
1815 if (base == NULL) return; // CodeBuffer::expand failed
1816 // static stub relocation stores the instruction address of the call
1817 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1818 // static stub relocation also tags the methodOop in the code-stream.
1819 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1820 __ jump(RuntimeAddress(__ pc()));
1821
1822 // Update current stubs pointer and restore code_end.
1823 __ end_a_stub();
1824 }
1825
1826 // size of call stub, compiled java to interpretor
1827 uint size_java_to_interp()
1828 {
1829 return 15; // movq (1+1+8); jmp (1+4)
1830 }
1831
1832 // relocation entries for call stub, compiled java to interpretor
1833 uint reloc_java_to_interp()
1834 {
1835 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1836 }
1837
1838 //=============================================================================
1839 #ifndef PRODUCT
1840 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1841 {
1842 if (UseCompressedOops) {
1843 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
1844 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
1845 st->print_cr("cmpq rax, rscratch1\t # Inline cache check");
1846 } else {
1847 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
1848 "# Inline cache check", oopDesc::klass_offset_in_bytes());
1849 }
1850 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1851 st->print_cr("\tnop");
1852 if (!OptoBreakpoint) {
1853 st->print_cr("\tnop");
1854 }
1855 }
1856 #endif
1857
1858 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1859 {
1860 MacroAssembler masm(&cbuf);
1861 #ifdef ASSERT
1862 uint code_size = cbuf.code_size();
1863 #endif
1864 if (UseCompressedOops) {
1865 masm.load_klass(rscratch1, j_rarg0);
1866 masm.cmpq(rax, rscratch1);
1867 } else {
1868 masm.cmpq(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1869 }
1870
1871 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1872
1873 /* WARNING these NOPs are critical so that verified entry point is properly
1874 aligned for patching by NativeJump::patch_verified_entry() */
1875 int nops_cnt = 1;
1876 if (!OptoBreakpoint) {
1877 // Leave space for int3
1878 nops_cnt += 1;
1879 }
1880 if (UseCompressedOops) {
1881 // ??? divisible by 4 is aligned?
1882 nops_cnt += 1;
1883 }
1884 masm.nop(nops_cnt);
1885
1886 assert(cbuf.code_size() - code_size == size(ra_),
1887 "checking code size of inline cache node");
1888 }
1889
1890 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1891 {
1892 if (UseCompressedOops) {
1893 return OptoBreakpoint ? 19 : 20;
1894 } else {
1895 return OptoBreakpoint ? 11 : 12;
1896 }
1897 }
1898
1899
1900 //=============================================================================
1901 uint size_exception_handler()
1902 {
1903 // NativeCall instruction size is the same as NativeJump.
1904 // Note that this value is also credited (in output.cpp) to
1905 // the size of the code section.
1906 return NativeJump::instruction_size;
1907 }
1908
1909 // Emit exception handler code.
1910 int emit_exception_handler(CodeBuffer& cbuf)
1911 {
1912
1913 // Note that the code buffer's inst_mark is always relative to insts.
1914 // That's why we must use the macroassembler to generate a handler.
1915 MacroAssembler _masm(&cbuf);
1916 address base =
1917 __ start_a_stub(size_exception_handler());
1918 if (base == NULL) return 0; // CodeBuffer::expand failed
1919 int offset = __ offset();
1920 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1921 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1922 __ end_a_stub();
1923 return offset;
1924 }
1925
1926 uint size_deopt_handler()
1927 {
1928 // three 5 byte instructions
1929 return 15;
1930 }
1931
1932 // Emit deopt handler code.
1933 int emit_deopt_handler(CodeBuffer& cbuf)
1934 {
1935
1936 // Note that the code buffer's inst_mark is always relative to insts.
1937 // That's why we must use the macroassembler to generate a handler.
1938 MacroAssembler _masm(&cbuf);
1939 address base =
1940 __ start_a_stub(size_deopt_handler());
1941 if (base == NULL) return 0; // CodeBuffer::expand failed
1942 int offset = __ offset();
1943 address the_pc = (address) __ pc();
1944 Label next;
1945 // push a "the_pc" on the stack without destroying any registers
1946 // as they all may be live.
1947
1948 // push address of "next"
1949 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1950 __ bind(next);
1951 // adjust it so it matches "the_pc"
1952 __ subq(Address(rsp, 0), __ offset() - offset);
1953 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1954 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1955 __ end_a_stub();
1956 return offset;
1957 }
1958
1959 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1960 int mark = cbuf.insts()->mark_off();
1961 MacroAssembler _masm(&cbuf);
1962 address double_address = __ double_constant(x);
1963 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1964 emit_d32_reloc(cbuf,
1965 (int) (double_address - cbuf.code_end() - 4),
1966 internal_word_Relocation::spec(double_address),
1967 RELOC_DISP32);
1968 }
1969
1970 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1971 int mark = cbuf.insts()->mark_off();
1972 MacroAssembler _masm(&cbuf);
1973 address float_address = __ float_constant(x);
1974 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1975 emit_d32_reloc(cbuf,
1976 (int) (float_address - cbuf.code_end() - 4),
1977 internal_word_Relocation::spec(float_address),
1978 RELOC_DISP32);
1979 }
1980
1981
1982 int Matcher::regnum_to_fpu_offset(int regnum)
1983 {
1984 return regnum - 32; // The FP registers are in the second chunk
1985 }
1986
1987 // This is UltraSparc specific, true just means we have fast l2f conversion
1988 const bool Matcher::convL2FSupported(void) {
1989 return true;
1990 }
1991
1992 // Vector width in bytes
1993 const uint Matcher::vector_width_in_bytes(void) {
1994 return 8;
1995 }
1996
1997 // Vector ideal reg
1998 const uint Matcher::vector_ideal_reg(void) {
1999 return Op_RegD;
2000 }
2001
2002 // Is this branch offset short enough that a short branch can be used?
2003 //
2004 // NOTE: If the platform does not provide any short branch variants, then
2005 // this method should return false for offset 0.
2006 bool Matcher::is_short_branch_offset(int offset)
2007 {
2008 return -0x80 <= offset && offset < 0x80;
2009 }
2010
2011 const bool Matcher::isSimpleConstant64(jlong value) {
2012 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
2013 //return value == (int) value; // Cf. storeImmL and immL32.
2014
2015 // Probably always true, even if a temp register is required.
2016 return true;
2017 }
2018
2019 // The ecx parameter to rep stosq for the ClearArray node is in words.
2020 const bool Matcher::init_array_count_is_in_bytes = false;
2021
2022 // Threshold size for cleararray.
2023 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2024
2025 // Should the Matcher clone shifts on addressing modes, expecting them
2026 // to be subsumed into complex addressing expressions or compute them
2027 // into registers? True for Intel but false for most RISCs
2028 const bool Matcher::clone_shift_expressions = true;
2029
2030 // Is it better to copy float constants, or load them directly from
2031 // memory? Intel can load a float constant from a direct address,
2032 // requiring no extra registers. Most RISCs will have to materialize
2033 // an address into a register first, so they would do better to copy
2034 // the constant from stack.
2035 const bool Matcher::rematerialize_float_constants = true; // XXX
2036
2037 // If CPU can load and store mis-aligned doubles directly then no
2038 // fixup is needed. Else we split the double into 2 integer pieces
2039 // and move it piece-by-piece. Only happens when passing doubles into
2040 // C code as the Java calling convention forces doubles to be aligned.
2041 const bool Matcher::misaligned_doubles_ok = true;
2042
2043 // No-op on amd64
2044 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
2045
2046 // Advertise here if the CPU requires explicit rounding operations to
2047 // implement the UseStrictFP mode.
2048 const bool Matcher::strict_fp_requires_explicit_rounding = true;
2049
2050 // Do floats take an entire double register or just half?
2051 const bool Matcher::float_in_double = true;
2052 // Do ints take an entire long register or just half?
2053 const bool Matcher::int_in_long = true;
2054
2055 // Return whether or not this register is ever used as an argument.
2056 // This function is used on startup to build the trampoline stubs in
2057 // generateOptoStub. Registers not mentioned will be killed by the VM
2058 // call in the trampoline, and arguments in those registers not be
2059 // available to the callee.
2060 bool Matcher::can_be_java_arg(int reg)
2061 {
2062 return
2063 reg == RDI_num || reg == RDI_H_num ||
2064 reg == RSI_num || reg == RSI_H_num ||
2065 reg == RDX_num || reg == RDX_H_num ||
2066 reg == RCX_num || reg == RCX_H_num ||
2067 reg == R8_num || reg == R8_H_num ||
2068 reg == R9_num || reg == R9_H_num ||
2069 reg == R12_num || reg == R12_H_num ||
2070 reg == XMM0_num || reg == XMM0_H_num ||
2071 reg == XMM1_num || reg == XMM1_H_num ||
2072 reg == XMM2_num || reg == XMM2_H_num ||
2073 reg == XMM3_num || reg == XMM3_H_num ||
2074 reg == XMM4_num || reg == XMM4_H_num ||
2075 reg == XMM5_num || reg == XMM5_H_num ||
2076 reg == XMM6_num || reg == XMM6_H_num ||
2077 reg == XMM7_num || reg == XMM7_H_num;
2078 }
2079
2080 bool Matcher::is_spillable_arg(int reg)
2081 {
2082 return can_be_java_arg(reg);
2083 }
2084
2085 // Register for DIVI projection of divmodI
2086 RegMask Matcher::divI_proj_mask() {
2087 return INT_RAX_REG_mask;
2088 }
2089
2090 // Register for MODI projection of divmodI
2091 RegMask Matcher::modI_proj_mask() {
2092 return INT_RDX_REG_mask;
2093 }
2094
2095 // Register for DIVL projection of divmodL
2096 RegMask Matcher::divL_proj_mask() {
2097 return LONG_RAX_REG_mask;
2098 }
2099
2100 // Register for MODL projection of divmodL
2101 RegMask Matcher::modL_proj_mask() {
2102 return LONG_RDX_REG_mask;
2103 }
2104
2105 static Address build_address(int b, int i, int s, int d) {
2106 Register index = as_Register(i);
2107 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2108 if (index == rsp) {
2109 index = noreg;
2110 scale = Address::no_scale;
2111 }
2112 Address addr(as_Register(b), index, scale, d);
2113 return addr;
2114 }
2115
2116 %}
2117
2118 //----------ENCODING BLOCK-----------------------------------------------------
2119 // This block specifies the encoding classes used by the compiler to
2120 // output byte streams. Encoding classes are parameterized macros
2121 // used by Machine Instruction Nodes in order to generate the bit
2122 // encoding of the instruction. Operands specify their base encoding
2123 // interface with the interface keyword. There are currently
2124 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2125 // COND_INTER. REG_INTER causes an operand to generate a function
2126 // which returns its register number when queried. CONST_INTER causes
2127 // an operand to generate a function which returns the value of the
2128 // constant when queried. MEMORY_INTER causes an operand to generate
2129 // four functions which return the Base Register, the Index Register,
2130 // the Scale Value, and the Offset Value of the operand when queried.
2131 // COND_INTER causes an operand to generate six functions which return
2132 // the encoding code (ie - encoding bits for the instruction)
2133 // associated with each basic boolean condition for a conditional
2134 // instruction.
2135 //
2136 // Instructions specify two basic values for encoding. Again, a
2137 // function is available to check if the constant displacement is an
2138 // oop. They use the ins_encode keyword to specify their encoding
2139 // classes (which must be a sequence of enc_class names, and their
2140 // parameters, specified in the encoding block), and they use the
2141 // opcode keyword to specify, in order, their primary, secondary, and
2142 // tertiary opcode. Only the opcode sections which a particular
2143 // instruction needs for encoding need to be specified.
2144 encode %{
2145 // Build emit functions for each basic byte or larger field in the
2146 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2147 // from C++ code in the enc_class source block. Emit functions will
2148 // live in the main source block for now. In future, we can
2149 // generalize this by adding a syntax that specifies the sizes of
2150 // fields in an order, so that the adlc can build the emit functions
2151 // automagically
2152
2153 // Emit primary opcode
2154 enc_class OpcP
2155 %{
2156 emit_opcode(cbuf, $primary);
2157 %}
2158
2159 // Emit secondary opcode
2160 enc_class OpcS
2161 %{
2162 emit_opcode(cbuf, $secondary);
2163 %}
2164
2165 // Emit tertiary opcode
2166 enc_class OpcT
2167 %{
2168 emit_opcode(cbuf, $tertiary);
2169 %}
2170
2171 // Emit opcode directly
2172 enc_class Opcode(immI d8)
2173 %{
2174 emit_opcode(cbuf, $d8$$constant);
2175 %}
2176
2177 // Emit size prefix
2178 enc_class SizePrefix
2179 %{
2180 emit_opcode(cbuf, 0x66);
2181 %}
2182
2183 enc_class reg(rRegI reg)
2184 %{
2185 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
2186 %}
2187
2188 enc_class reg_reg(rRegI dst, rRegI src)
2189 %{
2190 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2191 %}
2192
2193 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
2194 %{
2195 emit_opcode(cbuf, $opcode$$constant);
2196 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2197 %}
2198
2199 enc_class cmpfp_fixup()
2200 %{
2201 // jnp,s exit
2202 emit_opcode(cbuf, 0x7B);
2203 emit_d8(cbuf, 0x0A);
2204
2205 // pushfq
2206 emit_opcode(cbuf, 0x9C);
2207
2208 // andq $0xffffff2b, (%rsp)
2209 emit_opcode(cbuf, Assembler::REX_W);
2210 emit_opcode(cbuf, 0x81);
2211 emit_opcode(cbuf, 0x24);
2212 emit_opcode(cbuf, 0x24);
2213 emit_d32(cbuf, 0xffffff2b);
2214
2215 // popfq
2216 emit_opcode(cbuf, 0x9D);
2217
2218 // nop (target for branch to avoid branch to branch)
2219 emit_opcode(cbuf, 0x90);
2220 %}
2221
2222 enc_class cmpfp3(rRegI dst)
2223 %{
2224 int dstenc = $dst$$reg;
2225
2226 // movl $dst, -1
2227 if (dstenc >= 8) {
2228 emit_opcode(cbuf, Assembler::REX_B);
2229 }
2230 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2231 emit_d32(cbuf, -1);
2232
2233 // jp,s done
2234 emit_opcode(cbuf, 0x7A);
2235 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
2236
2237 // jb,s done
2238 emit_opcode(cbuf, 0x72);
2239 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2240
2241 // setne $dst
2242 if (dstenc >= 4) {
2243 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2244 }
2245 emit_opcode(cbuf, 0x0F);
2246 emit_opcode(cbuf, 0x95);
2247 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2248
2249 // movzbl $dst, $dst
2250 if (dstenc >= 4) {
2251 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2252 }
2253 emit_opcode(cbuf, 0x0F);
2254 emit_opcode(cbuf, 0xB6);
2255 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2256 %}
2257
2258 enc_class cdql_enc(no_rax_rdx_RegI div)
2259 %{
2260 // Full implementation of Java idiv and irem; checks for
2261 // special case as described in JVM spec., p.243 & p.271.
2262 //
2263 // normal case special case
2264 //
2265 // input : rax: dividend min_int
2266 // reg: divisor -1
2267 //
2268 // output: rax: quotient (= rax idiv reg) min_int
2269 // rdx: remainder (= rax irem reg) 0
2270 //
2271 // Code sequnce:
2272 //
2273 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
2274 // 5: 75 07/08 jne e <normal>
2275 // 7: 33 d2 xor %edx,%edx
2276 // [div >= 8 -> offset + 1]
2277 // [REX_B]
2278 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2279 // c: 74 03/04 je 11 <done>
2280 // 000000000000000e <normal>:
2281 // e: 99 cltd
2282 // [div >= 8 -> offset + 1]
2283 // [REX_B]
2284 // f: f7 f9 idiv $div
2285 // 0000000000000011 <done>:
2286
2287 // cmp $0x80000000,%eax
2288 emit_opcode(cbuf, 0x3d);
2289 emit_d8(cbuf, 0x00);
2290 emit_d8(cbuf, 0x00);
2291 emit_d8(cbuf, 0x00);
2292 emit_d8(cbuf, 0x80);
2293
2294 // jne e <normal>
2295 emit_opcode(cbuf, 0x75);
2296 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2297
2298 // xor %edx,%edx
2299 emit_opcode(cbuf, 0x33);
2300 emit_d8(cbuf, 0xD2);
2301
2302 // cmp $0xffffffffffffffff,%ecx
2303 if ($div$$reg >= 8) {
2304 emit_opcode(cbuf, Assembler::REX_B);
2305 }
2306 emit_opcode(cbuf, 0x83);
2307 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2308 emit_d8(cbuf, 0xFF);
2309
2310 // je 11 <done>
2311 emit_opcode(cbuf, 0x74);
2312 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2313
2314 // <normal>
2315 // cltd
2316 emit_opcode(cbuf, 0x99);
2317
2318 // idivl (note: must be emitted by the user of this rule)
2319 // <done>
2320 %}
2321
2322 enc_class cdqq_enc(no_rax_rdx_RegL div)
2323 %{
2324 // Full implementation of Java ldiv and lrem; checks for
2325 // special case as described in JVM spec., p.243 & p.271.
2326 //
2327 // normal case special case
2328 //
2329 // input : rax: dividend min_long
2330 // reg: divisor -1
2331 //
2332 // output: rax: quotient (= rax idiv reg) min_long
2333 // rdx: remainder (= rax irem reg) 0
2334 //
2335 // Code sequnce:
2336 //
2337 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2338 // 7: 00 00 80
2339 // a: 48 39 d0 cmp %rdx,%rax
2340 // d: 75 08 jne 17 <normal>
2341 // f: 33 d2 xor %edx,%edx
2342 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2343 // 15: 74 05 je 1c <done>
2344 // 0000000000000017 <normal>:
2345 // 17: 48 99 cqto
2346 // 19: 48 f7 f9 idiv $div
2347 // 000000000000001c <done>:
2348
2349 // mov $0x8000000000000000,%rdx
2350 emit_opcode(cbuf, Assembler::REX_W);
2351 emit_opcode(cbuf, 0xBA);
2352 emit_d8(cbuf, 0x00);
2353 emit_d8(cbuf, 0x00);
2354 emit_d8(cbuf, 0x00);
2355 emit_d8(cbuf, 0x00);
2356 emit_d8(cbuf, 0x00);
2357 emit_d8(cbuf, 0x00);
2358 emit_d8(cbuf, 0x00);
2359 emit_d8(cbuf, 0x80);
2360
2361 // cmp %rdx,%rax
2362 emit_opcode(cbuf, Assembler::REX_W);
2363 emit_opcode(cbuf, 0x39);
2364 emit_d8(cbuf, 0xD0);
2365
2366 // jne 17 <normal>
2367 emit_opcode(cbuf, 0x75);
2368 emit_d8(cbuf, 0x08);
2369
2370 // xor %edx,%edx
2371 emit_opcode(cbuf, 0x33);
2372 emit_d8(cbuf, 0xD2);
2373
2374 // cmp $0xffffffffffffffff,$div
2375 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2376 emit_opcode(cbuf, 0x83);
2377 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2378 emit_d8(cbuf, 0xFF);
2379
2380 // je 1e <done>
2381 emit_opcode(cbuf, 0x74);
2382 emit_d8(cbuf, 0x05);
2383
2384 // <normal>
2385 // cqto
2386 emit_opcode(cbuf, Assembler::REX_W);
2387 emit_opcode(cbuf, 0x99);
2388
2389 // idivq (note: must be emitted by the user of this rule)
2390 // <done>
2391 %}
2392
2393 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2394 enc_class OpcSE(immI imm)
2395 %{
2396 // Emit primary opcode and set sign-extend bit
2397 // Check for 8-bit immediate, and set sign extend bit in opcode
2398 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2399 emit_opcode(cbuf, $primary | 0x02);
2400 } else {
2401 // 32-bit immediate
2402 emit_opcode(cbuf, $primary);
2403 }
2404 %}
2405
2406 enc_class OpcSErm(rRegI dst, immI imm)
2407 %{
2408 // OpcSEr/m
2409 int dstenc = $dst$$reg;
2410 if (dstenc >= 8) {
2411 emit_opcode(cbuf, Assembler::REX_B);
2412 dstenc -= 8;
2413 }
2414 // Emit primary opcode and set sign-extend bit
2415 // Check for 8-bit immediate, and set sign extend bit in opcode
2416 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2417 emit_opcode(cbuf, $primary | 0x02);
2418 } else {
2419 // 32-bit immediate
2420 emit_opcode(cbuf, $primary);
2421 }
2422 // Emit r/m byte with secondary opcode, after primary opcode.
2423 emit_rm(cbuf, 0x3, $secondary, dstenc);
2424 %}
2425
2426 enc_class OpcSErm_wide(rRegL dst, immI imm)
2427 %{
2428 // OpcSEr/m
2429 int dstenc = $dst$$reg;
2430 if (dstenc < 8) {
2431 emit_opcode(cbuf, Assembler::REX_W);
2432 } else {
2433 emit_opcode(cbuf, Assembler::REX_WB);
2434 dstenc -= 8;
2435 }
2436 // Emit primary opcode and set sign-extend bit
2437 // Check for 8-bit immediate, and set sign extend bit in opcode
2438 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2439 emit_opcode(cbuf, $primary | 0x02);
2440 } else {
2441 // 32-bit immediate
2442 emit_opcode(cbuf, $primary);
2443 }
2444 // Emit r/m byte with secondary opcode, after primary opcode.
2445 emit_rm(cbuf, 0x3, $secondary, dstenc);
2446 %}
2447
2448 enc_class Con8or32(immI imm)
2449 %{
2450 // Check for 8-bit immediate, and set sign extend bit in opcode
2451 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2452 $$$emit8$imm$$constant;
2453 } else {
2454 // 32-bit immediate
2455 $$$emit32$imm$$constant;
2456 }
2457 %}
2458
2459 enc_class Lbl(label labl)
2460 %{
2461 // JMP, CALL
2462 Label* l = $labl$$label;
2463 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2464 %}
2465
2466 enc_class LblShort(label labl)
2467 %{
2468 // JMP, CALL
2469 Label* l = $labl$$label;
2470 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2471 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2472 emit_d8(cbuf, disp);
2473 %}
2474
2475 enc_class opc2_reg(rRegI dst)
2476 %{
2477 // BSWAP
2478 emit_cc(cbuf, $secondary, $dst$$reg);
2479 %}
2480
2481 enc_class opc3_reg(rRegI dst)
2482 %{
2483 // BSWAP
2484 emit_cc(cbuf, $tertiary, $dst$$reg);
2485 %}
2486
2487 enc_class reg_opc(rRegI div)
2488 %{
2489 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2490 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2491 %}
2492
2493 enc_class Jcc(cmpOp cop, label labl)
2494 %{
2495 // JCC
2496 Label* l = $labl$$label;
2497 $$$emit8$primary;
2498 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2499 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2500 %}
2501
2502 enc_class JccShort (cmpOp cop, label labl)
2503 %{
2504 // JCC
2505 Label *l = $labl$$label;
2506 emit_cc(cbuf, $primary, $cop$$cmpcode);
2507 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2508 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2509 emit_d8(cbuf, disp);
2510 %}
2511
2512 enc_class enc_cmov(cmpOp cop)
2513 %{
2514 // CMOV
2515 $$$emit8$primary;
2516 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2517 %}
2518
2519 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
2520 %{
2521 // Invert sense of branch from sense of cmov
2522 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2523 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
2524 ? (UseXmmRegToRegMoveAll ? 3 : 4)
2525 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
2526 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
2527 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
2528 if ($dst$$reg < 8) {
2529 if ($src$$reg >= 8) {
2530 emit_opcode(cbuf, Assembler::REX_B);
2531 }
2532 } else {
2533 if ($src$$reg < 8) {
2534 emit_opcode(cbuf, Assembler::REX_R);
2535 } else {
2536 emit_opcode(cbuf, Assembler::REX_RB);
2537 }
2538 }
2539 emit_opcode(cbuf, 0x0F);
2540 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2541 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2542 %}
2543
2544 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
2545 %{
2546 // Invert sense of branch from sense of cmov
2547 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2548 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
2549
2550 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
2551 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
2552 if ($dst$$reg < 8) {
2553 if ($src$$reg >= 8) {
2554 emit_opcode(cbuf, Assembler::REX_B);
2555 }
2556 } else {
2557 if ($src$$reg < 8) {
2558 emit_opcode(cbuf, Assembler::REX_R);
2559 } else {
2560 emit_opcode(cbuf, Assembler::REX_RB);
2561 }
2562 }
2563 emit_opcode(cbuf, 0x0F);
2564 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2565 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2566 %}
2567
2568 enc_class enc_PartialSubtypeCheck()
2569 %{
2570 Register Rrdi = as_Register(RDI_enc); // result register
2571 Register Rrax = as_Register(RAX_enc); // super class
2572 Register Rrcx = as_Register(RCX_enc); // killed
2573 Register Rrsi = as_Register(RSI_enc); // sub class
2574 Label hit, miss, cmiss;
2575
2576 MacroAssembler _masm(&cbuf);
2577 // Compare super with sub directly, since super is not in its own SSA.
2578 // The compiler used to emit this test, but we fold it in here,
2579 // to allow platform-specific tweaking on sparc.
2580 __ cmpq(Rrax, Rrsi);
2581 __ jcc(Assembler::equal, hit);
2582 #ifndef PRODUCT
2583 __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
2584 __ incrementl(Address(Rrcx, 0));
2585 #endif //PRODUCT
2586 __ movq(Rrdi, Address(Rrsi,
2587 sizeof(oopDesc) +
2588 Klass::secondary_supers_offset_in_bytes()));
2589 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
2590 __ addq(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
2591 if (UseCompressedOops) {
2592 __ encode_heap_oop(Rrax);
2593 __ repne_scanl();
2594 __ jcc(Assembler::notEqual, cmiss);
2595 __ decode_heap_oop(Rrax);
2596 __ movq(Address(Rrsi,
2597 sizeof(oopDesc) +
2598 Klass::secondary_super_cache_offset_in_bytes()),
2599 Rrax);
2600 __ jmp(hit);
2601 __ bind(cmiss);
2602 __ decode_heap_oop(Rrax);
2603 __ jmp(miss);
2604 } else {
2605 __ repne_scanq();
2606 __ jcc(Assembler::notEqual, miss);
2607 __ movq(Address(Rrsi,
2608 sizeof(oopDesc) +
2609 Klass::secondary_super_cache_offset_in_bytes()),
2610 Rrax);
2611 }
2612 __ bind(hit);
2613 if ($primary) {
2614 __ xorq(Rrdi, Rrdi);
2615 }
2616 __ bind(miss);
2617 %}
2618
2619 enc_class Java_To_Interpreter(method meth)
2620 %{
2621 // CALL Java_To_Interpreter
2622 // This is the instruction starting address for relocation info.
2623 cbuf.set_inst_mark();
2624 $$$emit8$primary;
2625 // CALL directly to the runtime
2626 emit_d32_reloc(cbuf,
2627 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2628 runtime_call_Relocation::spec(),
2629 RELOC_DISP32);
2630 %}
2631
2632 enc_class Java_Static_Call(method meth)
2633 %{
2634 // JAVA STATIC CALL
2635 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2636 // determine who we intended to call.
2637 cbuf.set_inst_mark();
2638 $$$emit8$primary;
2639
2640 if (!_method) {
2641 emit_d32_reloc(cbuf,
2642 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2643 runtime_call_Relocation::spec(),
2644 RELOC_DISP32);
2645 } else if (_optimized_virtual) {
2646 emit_d32_reloc(cbuf,
2647 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2648 opt_virtual_call_Relocation::spec(),
2649 RELOC_DISP32);
2650 } else {
2651 emit_d32_reloc(cbuf,
2652 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2653 static_call_Relocation::spec(),
2654 RELOC_DISP32);
2655 }
2656 if (_method) {
2657 // Emit stub for static call
2658 emit_java_to_interp(cbuf);
2659 }
2660 %}
2661
2662 enc_class Java_Dynamic_Call(method meth)
2663 %{
2664 // JAVA DYNAMIC CALL
2665 // !!!!!
2666 // Generate "movq rax, -1", placeholder instruction to load oop-info
2667 // emit_call_dynamic_prologue( cbuf );
2668 cbuf.set_inst_mark();
2669
2670 // movq rax, -1
2671 emit_opcode(cbuf, Assembler::REX_W);
2672 emit_opcode(cbuf, 0xB8 | RAX_enc);
2673 emit_d64_reloc(cbuf,
2674 (int64_t) Universe::non_oop_word(),
2675 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2676 address virtual_call_oop_addr = cbuf.inst_mark();
2677 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2678 // who we intended to call.
2679 cbuf.set_inst_mark();
2680 $$$emit8$primary;
2681 emit_d32_reloc(cbuf,
2682 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2683 virtual_call_Relocation::spec(virtual_call_oop_addr),
2684 RELOC_DISP32);
2685 %}
2686
2687 enc_class Java_Compiled_Call(method meth)
2688 %{
2689 // JAVA COMPILED CALL
2690 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2691
2692 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2693 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2694
2695 // callq *disp(%rax)
2696 cbuf.set_inst_mark();
2697 $$$emit8$primary;
2698 if (disp < 0x80) {
2699 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2700 emit_d8(cbuf, disp); // Displacement
2701 } else {
2702 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2703 emit_d32(cbuf, disp); // Displacement
2704 }
2705 %}
2706
2707 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2708 %{
2709 // SAL, SAR, SHR
2710 int dstenc = $dst$$reg;
2711 if (dstenc >= 8) {
2712 emit_opcode(cbuf, Assembler::REX_B);
2713 dstenc -= 8;
2714 }
2715 $$$emit8$primary;
2716 emit_rm(cbuf, 0x3, $secondary, dstenc);
2717 $$$emit8$shift$$constant;
2718 %}
2719
2720 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2721 %{
2722 // SAL, SAR, SHR
2723 int dstenc = $dst$$reg;
2724 if (dstenc < 8) {
2725 emit_opcode(cbuf, Assembler::REX_W);
2726 } else {
2727 emit_opcode(cbuf, Assembler::REX_WB);
2728 dstenc -= 8;
2729 }
2730 $$$emit8$primary;
2731 emit_rm(cbuf, 0x3, $secondary, dstenc);
2732 $$$emit8$shift$$constant;
2733 %}
2734
2735 enc_class load_immI(rRegI dst, immI src)
2736 %{
2737 int dstenc = $dst$$reg;
2738 if (dstenc >= 8) {
2739 emit_opcode(cbuf, Assembler::REX_B);
2740 dstenc -= 8;
2741 }
2742 emit_opcode(cbuf, 0xB8 | dstenc);
2743 $$$emit32$src$$constant;
2744 %}
2745
2746 enc_class load_immL(rRegL dst, immL src)
2747 %{
2748 int dstenc = $dst$$reg;
2749 if (dstenc < 8) {
2750 emit_opcode(cbuf, Assembler::REX_W);
2751 } else {
2752 emit_opcode(cbuf, Assembler::REX_WB);
2753 dstenc -= 8;
2754 }
2755 emit_opcode(cbuf, 0xB8 | dstenc);
2756 emit_d64(cbuf, $src$$constant);
2757 %}
2758
2759 enc_class load_immUL32(rRegL dst, immUL32 src)
2760 %{
2761 // same as load_immI, but this time we care about zeroes in the high word
2762 int dstenc = $dst$$reg;
2763 if (dstenc >= 8) {
2764 emit_opcode(cbuf, Assembler::REX_B);
2765 dstenc -= 8;
2766 }
2767 emit_opcode(cbuf, 0xB8 | dstenc);
2768 $$$emit32$src$$constant;
2769 %}
2770
2771 enc_class load_immL32(rRegL dst, immL32 src)
2772 %{
2773 int dstenc = $dst$$reg;
2774 if (dstenc < 8) {
2775 emit_opcode(cbuf, Assembler::REX_W);
2776 } else {
2777 emit_opcode(cbuf, Assembler::REX_WB);
2778 dstenc -= 8;
2779 }
2780 emit_opcode(cbuf, 0xC7);
2781 emit_rm(cbuf, 0x03, 0x00, dstenc);
2782 $$$emit32$src$$constant;
2783 %}
2784
2785 enc_class load_immP31(rRegP dst, immP32 src)
2786 %{
2787 // same as load_immI, but this time we care about zeroes in the high word
2788 int dstenc = $dst$$reg;
2789 if (dstenc >= 8) {
2790 emit_opcode(cbuf, Assembler::REX_B);
2791 dstenc -= 8;
2792 }
2793 emit_opcode(cbuf, 0xB8 | dstenc);
2794 $$$emit32$src$$constant;
2795 %}
2796
2797 enc_class load_immP(rRegP dst, immP src)
2798 %{
2799 int dstenc = $dst$$reg;
2800 if (dstenc < 8) {
2801 emit_opcode(cbuf, Assembler::REX_W);
2802 } else {
2803 emit_opcode(cbuf, Assembler::REX_WB);
2804 dstenc -= 8;
2805 }
2806 emit_opcode(cbuf, 0xB8 | dstenc);
2807 // This next line should be generated from ADLC
2808 if ($src->constant_is_oop()) {
2809 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2810 } else {
2811 emit_d64(cbuf, $src$$constant);
2812 }
2813 %}
2814
2815 enc_class load_immF(regF dst, immF con)
2816 %{
2817 // XXX reg_mem doesn't support RIP-relative addressing yet
2818 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2819 emit_float_constant(cbuf, $con$$constant);
2820 %}
2821
2822 enc_class load_immD(regD dst, immD con)
2823 %{
2824 // XXX reg_mem doesn't support RIP-relative addressing yet
2825 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2826 emit_double_constant(cbuf, $con$$constant);
2827 %}
2828
2829 enc_class load_conF (regF dst, immF con) %{ // Load float constant
2830 emit_opcode(cbuf, 0xF3);
2831 if ($dst$$reg >= 8) {
2832 emit_opcode(cbuf, Assembler::REX_R);
2833 }
2834 emit_opcode(cbuf, 0x0F);
2835 emit_opcode(cbuf, 0x10);
2836 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2837 emit_float_constant(cbuf, $con$$constant);
2838 %}
2839
2840 enc_class load_conD (regD dst, immD con) %{ // Load double constant
2841 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2842 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2843 if ($dst$$reg >= 8) {
2844 emit_opcode(cbuf, Assembler::REX_R);
2845 }
2846 emit_opcode(cbuf, 0x0F);
2847 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2848 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2849 emit_double_constant(cbuf, $con$$constant);
2850 %}
2851
2852 // Encode a reg-reg copy. If it is useless, then empty encoding.
2853 enc_class enc_copy(rRegI dst, rRegI src)
2854 %{
2855 encode_copy(cbuf, $dst$$reg, $src$$reg);
2856 %}
2857
2858 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2859 enc_class enc_CopyXD( RegD dst, RegD src ) %{
2860 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2861 %}
2862
2863 enc_class enc_copy_always(rRegI dst, rRegI src)
2864 %{
2865 int srcenc = $src$$reg;
2866 int dstenc = $dst$$reg;
2867
2868 if (dstenc < 8) {
2869 if (srcenc >= 8) {
2870 emit_opcode(cbuf, Assembler::REX_B);
2871 srcenc -= 8;
2872 }
2873 } else {
2874 if (srcenc < 8) {
2875 emit_opcode(cbuf, Assembler::REX_R);
2876 } else {
2877 emit_opcode(cbuf, Assembler::REX_RB);
2878 srcenc -= 8;
2879 }
2880 dstenc -= 8;
2881 }
2882
2883 emit_opcode(cbuf, 0x8B);
2884 emit_rm(cbuf, 0x3, dstenc, srcenc);
2885 %}
2886
2887 enc_class enc_copy_wide(rRegL dst, rRegL src)
2888 %{
2889 int srcenc = $src$$reg;
2890 int dstenc = $dst$$reg;
2891
2892 if (dstenc != srcenc) {
2893 if (dstenc < 8) {
2894 if (srcenc < 8) {
2895 emit_opcode(cbuf, Assembler::REX_W);
2896 } else {
2897 emit_opcode(cbuf, Assembler::REX_WB);
2898 srcenc -= 8;
2899 }
2900 } else {
2901 if (srcenc < 8) {
2902 emit_opcode(cbuf, Assembler::REX_WR);
2903 } else {
2904 emit_opcode(cbuf, Assembler::REX_WRB);
2905 srcenc -= 8;
2906 }
2907 dstenc -= 8;
2908 }
2909 emit_opcode(cbuf, 0x8B);
2910 emit_rm(cbuf, 0x3, dstenc, srcenc);
2911 }
2912 %}
2913
2914 enc_class Con32(immI src)
2915 %{
2916 // Output immediate
2917 $$$emit32$src$$constant;
2918 %}
2919
2920 enc_class Con64(immL src)
2921 %{
2922 // Output immediate
2923 emit_d64($src$$constant);
2924 %}
2925
2926 enc_class Con32F_as_bits(immF src)
2927 %{
2928 // Output Float immediate bits
2929 jfloat jf = $src$$constant;
2930 jint jf_as_bits = jint_cast(jf);
2931 emit_d32(cbuf, jf_as_bits);
2932 %}
2933
2934 enc_class Con16(immI src)
2935 %{
2936 // Output immediate
2937 $$$emit16$src$$constant;
2938 %}
2939
2940 // How is this different from Con32??? XXX
2941 enc_class Con_d32(immI src)
2942 %{
2943 emit_d32(cbuf,$src$$constant);
2944 %}
2945
2946 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2947 // Output immediate memory reference
2948 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2949 emit_d32(cbuf, 0x00);
2950 %}
2951
2952 enc_class jump_enc(rRegL switch_val, rRegI dest) %{
2953 MacroAssembler masm(&cbuf);
2954
2955 Register switch_reg = as_Register($switch_val$$reg);
2956 Register dest_reg = as_Register($dest$$reg);
2957 address table_base = masm.address_table_constant(_index2label);
2958
2959 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2960 // to do that and the compiler is using that register as one it can allocate.
2961 // So we build it all by hand.
2962 // Address index(noreg, switch_reg, Address::times_1);
2963 // ArrayAddress dispatch(table, index);
2964
2965 Address dispatch(dest_reg, switch_reg, Address::times_1);
2966
2967 masm.lea(dest_reg, InternalAddress(table_base));
2968 masm.jmp(dispatch);
2969 %}
2970
2971 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
2972 MacroAssembler masm(&cbuf);
2973
2974 Register switch_reg = as_Register($switch_val$$reg);
2975 Register dest_reg = as_Register($dest$$reg);
2976 address table_base = masm.address_table_constant(_index2label);
2977
2978 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2979 // to do that and the compiler is using that register as one it can allocate.
2980 // So we build it all by hand.
2981 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2982 // ArrayAddress dispatch(table, index);
2983
2984 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2985
2986 masm.lea(dest_reg, InternalAddress(table_base));
2987 masm.jmp(dispatch);
2988 %}
2989
2990 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
2991 MacroAssembler masm(&cbuf);
2992
2993 Register switch_reg = as_Register($switch_val$$reg);
2994 Register dest_reg = as_Register($dest$$reg);
2995 address table_base = masm.address_table_constant(_index2label);
2996
2997 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2998 // to do that and the compiler is using that register as one it can allocate.
2999 // So we build it all by hand.
3000 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3001 // ArrayAddress dispatch(table, index);
3002
3003 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3004 masm.lea(dest_reg, InternalAddress(table_base));
3005 masm.jmp(dispatch);
3006
3007 %}
3008
3009 enc_class lock_prefix()
3010 %{
3011 if (os::is_MP()) {
3012 emit_opcode(cbuf, 0xF0); // lock
3013 }
3014 %}
3015
3016 enc_class REX_mem(memory mem)
3017 %{
3018 if ($mem$$base >= 8) {
3019 if ($mem$$index < 8) {
3020 emit_opcode(cbuf, Assembler::REX_B);
3021 } else {
3022 emit_opcode(cbuf, Assembler::REX_XB);
3023 }
3024 } else {
3025 if ($mem$$index >= 8) {
3026 emit_opcode(cbuf, Assembler::REX_X);
3027 }
3028 }
3029 %}
3030
3031 enc_class REX_mem_wide(memory mem)
3032 %{
3033 if ($mem$$base >= 8) {
3034 if ($mem$$index < 8) {
3035 emit_opcode(cbuf, Assembler::REX_WB);
3036 } else {
3037 emit_opcode(cbuf, Assembler::REX_WXB);
3038 }
3039 } else {
3040 if ($mem$$index < 8) {
3041 emit_opcode(cbuf, Assembler::REX_W);
3042 } else {
3043 emit_opcode(cbuf, Assembler::REX_WX);
3044 }
3045 }
3046 %}
3047
3048 // for byte regs
3049 enc_class REX_breg(rRegI reg)
3050 %{
3051 if ($reg$$reg >= 4) {
3052 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3053 }
3054 %}
3055
3056 // for byte regs
3057 enc_class REX_reg_breg(rRegI dst, rRegI src)
3058 %{
3059 if ($dst$$reg < 8) {
3060 if ($src$$reg >= 4) {
3061 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3062 }
3063 } else {
3064 if ($src$$reg < 8) {
3065 emit_opcode(cbuf, Assembler::REX_R);
3066 } else {
3067 emit_opcode(cbuf, Assembler::REX_RB);
3068 }
3069 }
3070 %}
3071
3072 // for byte regs
3073 enc_class REX_breg_mem(rRegI reg, memory mem)
3074 %{
3075 if ($reg$$reg < 8) {
3076 if ($mem$$base < 8) {
3077 if ($mem$$index >= 8) {
3078 emit_opcode(cbuf, Assembler::REX_X);
3079 } else if ($reg$$reg >= 4) {
3080 emit_opcode(cbuf, Assembler::REX);
3081 }
3082 } else {
3083 if ($mem$$index < 8) {
3084 emit_opcode(cbuf, Assembler::REX_B);
3085 } else {
3086 emit_opcode(cbuf, Assembler::REX_XB);
3087 }
3088 }
3089 } else {
3090 if ($mem$$base < 8) {
3091 if ($mem$$index < 8) {
3092 emit_opcode(cbuf, Assembler::REX_R);
3093 } else {
3094 emit_opcode(cbuf, Assembler::REX_RX);
3095 }
3096 } else {
3097 if ($mem$$index < 8) {
3098 emit_opcode(cbuf, Assembler::REX_RB);
3099 } else {
3100 emit_opcode(cbuf, Assembler::REX_RXB);
3101 }
3102 }
3103 }
3104 %}
3105
3106 enc_class REX_reg(rRegI reg)
3107 %{
3108 if ($reg$$reg >= 8) {
3109 emit_opcode(cbuf, Assembler::REX_B);
3110 }
3111 %}
3112
3113 enc_class REX_reg_wide(rRegI reg)
3114 %{
3115 if ($reg$$reg < 8) {
3116 emit_opcode(cbuf, Assembler::REX_W);
3117 } else {
3118 emit_opcode(cbuf, Assembler::REX_WB);
3119 }
3120 %}
3121
3122 enc_class REX_reg_reg(rRegI dst, rRegI src)
3123 %{
3124 if ($dst$$reg < 8) {
3125 if ($src$$reg >= 8) {
3126 emit_opcode(cbuf, Assembler::REX_B);
3127 }
3128 } else {
3129 if ($src$$reg < 8) {
3130 emit_opcode(cbuf, Assembler::REX_R);
3131 } else {
3132 emit_opcode(cbuf, Assembler::REX_RB);
3133 }
3134 }
3135 %}
3136
3137 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
3138 %{
3139 if ($dst$$reg < 8) {
3140 if ($src$$reg < 8) {
3141 emit_opcode(cbuf, Assembler::REX_W);
3142 } else {
3143 emit_opcode(cbuf, Assembler::REX_WB);
3144 }
3145 } else {
3146 if ($src$$reg < 8) {
3147 emit_opcode(cbuf, Assembler::REX_WR);
3148 } else {
3149 emit_opcode(cbuf, Assembler::REX_WRB);
3150 }
3151 }
3152 %}
3153
3154 enc_class REX_reg_mem(rRegI reg, memory mem)
3155 %{
3156 if ($reg$$reg < 8) {
3157 if ($mem$$base < 8) {
3158 if ($mem$$index >= 8) {
3159 emit_opcode(cbuf, Assembler::REX_X);
3160 }
3161 } else {
3162 if ($mem$$index < 8) {
3163 emit_opcode(cbuf, Assembler::REX_B);
3164 } else {
3165 emit_opcode(cbuf, Assembler::REX_XB);
3166 }
3167 }
3168 } else {
3169 if ($mem$$base < 8) {
3170 if ($mem$$index < 8) {
3171 emit_opcode(cbuf, Assembler::REX_R);
3172 } else {
3173 emit_opcode(cbuf, Assembler::REX_RX);
3174 }
3175 } else {
3176 if ($mem$$index < 8) {
3177 emit_opcode(cbuf, Assembler::REX_RB);
3178 } else {
3179 emit_opcode(cbuf, Assembler::REX_RXB);
3180 }
3181 }
3182 }
3183 %}
3184
3185 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
3186 %{
3187 if ($reg$$reg < 8) {
3188 if ($mem$$base < 8) {
3189 if ($mem$$index < 8) {
3190 emit_opcode(cbuf, Assembler::REX_W);
3191 } else {
3192 emit_opcode(cbuf, Assembler::REX_WX);
3193 }
3194 } else {
3195 if ($mem$$index < 8) {
3196 emit_opcode(cbuf, Assembler::REX_WB);
3197 } else {
3198 emit_opcode(cbuf, Assembler::REX_WXB);
3199 }
3200 }
3201 } else {
3202 if ($mem$$base < 8) {
3203 if ($mem$$index < 8) {
3204 emit_opcode(cbuf, Assembler::REX_WR);
3205 } else {
3206 emit_opcode(cbuf, Assembler::REX_WRX);
3207 }
3208 } else {
3209 if ($mem$$index < 8) {
3210 emit_opcode(cbuf, Assembler::REX_WRB);
3211 } else {
3212 emit_opcode(cbuf, Assembler::REX_WRXB);
3213 }
3214 }
3215 }
3216 %}
3217
3218 enc_class reg_mem(rRegI ereg, memory mem)
3219 %{
3220 // High registers handle in encode_RegMem
3221 int reg = $ereg$$reg;
3222 int base = $mem$$base;
3223 int index = $mem$$index;
3224 int scale = $mem$$scale;
3225 int disp = $mem$$disp;
3226 bool disp_is_oop = $mem->disp_is_oop();
3227
3228 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
3229 %}
3230
3231 enc_class RM_opc_mem(immI rm_opcode, memory mem)
3232 %{
3233 int rm_byte_opcode = $rm_opcode$$constant;
3234
3235 // High registers handle in encode_RegMem
3236 int base = $mem$$base;
3237 int index = $mem$$index;
3238 int scale = $mem$$scale;
3239 int displace = $mem$$disp;
3240
3241 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
3242 // working with static
3243 // globals
3244 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
3245 disp_is_oop);
3246 %}
3247
3248 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
3249 %{
3250 int reg_encoding = $dst$$reg;
3251 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
3252 int index = 0x04; // 0x04 indicates no index
3253 int scale = 0x00; // 0x00 indicates no scale
3254 int displace = $src1$$constant; // 0x00 indicates no displacement
3255 bool disp_is_oop = false;
3256 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
3257 disp_is_oop);
3258 %}
3259
3260 enc_class neg_reg(rRegI dst)
3261 %{
3262 int dstenc = $dst$$reg;
3263 if (dstenc >= 8) {
3264 emit_opcode(cbuf, Assembler::REX_B);
3265 dstenc -= 8;
3266 }
3267 // NEG $dst
3268 emit_opcode(cbuf, 0xF7);
3269 emit_rm(cbuf, 0x3, 0x03, dstenc);
3270 %}
3271
3272 enc_class neg_reg_wide(rRegI dst)
3273 %{
3274 int dstenc = $dst$$reg;
3275 if (dstenc < 8) {
3276 emit_opcode(cbuf, Assembler::REX_W);
3277 } else {
3278 emit_opcode(cbuf, Assembler::REX_WB);
3279 dstenc -= 8;
3280 }
3281 // NEG $dst
3282 emit_opcode(cbuf, 0xF7);
3283 emit_rm(cbuf, 0x3, 0x03, dstenc);
3284 %}
3285
3286 enc_class setLT_reg(rRegI dst)
3287 %{
3288 int dstenc = $dst$$reg;
3289 if (dstenc >= 8) {
3290 emit_opcode(cbuf, Assembler::REX_B);
3291 dstenc -= 8;
3292 } else if (dstenc >= 4) {
3293 emit_opcode(cbuf, Assembler::REX);
3294 }
3295 // SETLT $dst
3296 emit_opcode(cbuf, 0x0F);
3297 emit_opcode(cbuf, 0x9C);
3298 emit_rm(cbuf, 0x3, 0x0, dstenc);
3299 %}
3300
3301 enc_class setNZ_reg(rRegI dst)
3302 %{
3303 int dstenc = $dst$$reg;
3304 if (dstenc >= 8) {
3305 emit_opcode(cbuf, Assembler::REX_B);
3306 dstenc -= 8;
3307 } else if (dstenc >= 4) {
3308 emit_opcode(cbuf, Assembler::REX);
3309 }
3310 // SETNZ $dst
3311 emit_opcode(cbuf, 0x0F);
3312 emit_opcode(cbuf, 0x95);
3313 emit_rm(cbuf, 0x3, 0x0, dstenc);
3314 %}
3315
3316 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
3317 rcx_RegI tmp)
3318 %{
3319 // cadd_cmpLT
3320
3321 int tmpReg = $tmp$$reg;
3322
3323 int penc = $p$$reg;
3324 int qenc = $q$$reg;
3325 int yenc = $y$$reg;
3326
3327 // subl $p,$q
3328 if (penc < 8) {
3329 if (qenc >= 8) {
3330 emit_opcode(cbuf, Assembler::REX_B);
3331 }
3332 } else {
3333 if (qenc < 8) {
3334 emit_opcode(cbuf, Assembler::REX_R);
3335 } else {
3336 emit_opcode(cbuf, Assembler::REX_RB);
3337 }
3338 }
3339 emit_opcode(cbuf, 0x2B);
3340 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
3341
3342 // sbbl $tmp, $tmp
3343 emit_opcode(cbuf, 0x1B);
3344 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
3345
3346 // andl $tmp, $y
3347 if (yenc >= 8) {
3348 emit_opcode(cbuf, Assembler::REX_B);
3349 }
3350 emit_opcode(cbuf, 0x23);
3351 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
3352
3353 // addl $p,$tmp
3354 if (penc >= 8) {
3355 emit_opcode(cbuf, Assembler::REX_R);
3356 }
3357 emit_opcode(cbuf, 0x03);
3358 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
3359 %}
3360
3361 // Compare the lonogs and set -1, 0, or 1 into dst
3362 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
3363 %{
3364 int src1enc = $src1$$reg;
3365 int src2enc = $src2$$reg;
3366 int dstenc = $dst$$reg;
3367
3368 // cmpq $src1, $src2
3369 if (src1enc < 8) {
3370 if (src2enc < 8) {
3371 emit_opcode(cbuf, Assembler::REX_W);
3372 } else {
3373 emit_opcode(cbuf, Assembler::REX_WB);
3374 }
3375 } else {
3376 if (src2enc < 8) {
3377 emit_opcode(cbuf, Assembler::REX_WR);
3378 } else {
3379 emit_opcode(cbuf, Assembler::REX_WRB);
3380 }
3381 }
3382 emit_opcode(cbuf, 0x3B);
3383 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
3384
3385 // movl $dst, -1
3386 if (dstenc >= 8) {
3387 emit_opcode(cbuf, Assembler::REX_B);
3388 }
3389 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
3390 emit_d32(cbuf, -1);
3391
3392 // jl,s done
3393 emit_opcode(cbuf, 0x7C);
3394 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
3395
3396 // setne $dst
3397 if (dstenc >= 4) {
3398 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
3399 }
3400 emit_opcode(cbuf, 0x0F);
3401 emit_opcode(cbuf, 0x95);
3402 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
3403
3404 // movzbl $dst, $dst
3405 if (dstenc >= 4) {
3406 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
3407 }
3408 emit_opcode(cbuf, 0x0F);
3409 emit_opcode(cbuf, 0xB6);
3410 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
3411 %}
3412
3413 enc_class Push_ResultXD(regD dst) %{
3414 int dstenc = $dst$$reg;
3415
3416 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
3417
3418 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
3419 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
3420 if (dstenc >= 8) {
3421 emit_opcode(cbuf, Assembler::REX_R);
3422 }
3423 emit_opcode (cbuf, 0x0F );
3424 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
3425 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
3426
3427 // add rsp,8
3428 emit_opcode(cbuf, Assembler::REX_W);
3429 emit_opcode(cbuf,0x83);
3430 emit_rm(cbuf,0x3, 0x0, RSP_enc);
3431 emit_d8(cbuf,0x08);
3432 %}
3433
3434 enc_class Push_SrcXD(regD src) %{
3435 int srcenc = $src$$reg;
3436
3437 // subq rsp,#8
3438 emit_opcode(cbuf, Assembler::REX_W);
3439 emit_opcode(cbuf, 0x83);
3440 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3441 emit_d8(cbuf, 0x8);
3442
3443 // movsd [rsp],src
3444 emit_opcode(cbuf, 0xF2);
3445 if (srcenc >= 8) {
3446 emit_opcode(cbuf, Assembler::REX_R);
3447 }
3448 emit_opcode(cbuf, 0x0F);
3449 emit_opcode(cbuf, 0x11);
3450 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
3451
3452 // fldd [rsp]
3453 emit_opcode(cbuf, 0x66);
3454 emit_opcode(cbuf, 0xDD);
3455 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
3456 %}
3457
3458
3459 enc_class movq_ld(regD dst, memory mem) %{
3460 MacroAssembler _masm(&cbuf);
3461 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3462 __ movq(as_XMMRegister($dst$$reg), madr);
3463 %}
3464
3465 enc_class movq_st(memory mem, regD src) %{
3466 MacroAssembler _masm(&cbuf);
3467 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3468 __ movq(madr, as_XMMRegister($src$$reg));
3469 %}
3470
3471 enc_class pshufd_8x8(regF dst, regF src) %{
3472 MacroAssembler _masm(&cbuf);
3473
3474 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3475 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3476 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3477 %}
3478
3479 enc_class pshufd_4x16(regF dst, regF src) %{
3480 MacroAssembler _masm(&cbuf);
3481
3482 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3483 %}
3484
3485 enc_class pshufd(regD dst, regD src, int mode) %{
3486 MacroAssembler _masm(&cbuf);
3487
3488 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3489 %}
3490
3491 enc_class pxor(regD dst, regD src) %{
3492 MacroAssembler _masm(&cbuf);
3493
3494 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3495 %}
3496
3497 enc_class mov_i2x(regD dst, rRegI src) %{
3498 MacroAssembler _masm(&cbuf);
3499
3500 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3501 %}
3502
3503 // obj: object to lock
3504 // box: box address (header location) -- killed
3505 // tmp: rax -- killed
3506 // scr: rbx -- killed
3507 //
3508 // What follows is a direct transliteration of fast_lock() and fast_unlock()
3509 // from i486.ad. See that file for comments.
3510 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
3511 // use the shorter encoding. (Movl clears the high-order 32-bits).
3512
3513
3514 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
3515 %{
3516 Register objReg = as_Register((int)$obj$$reg);
3517 Register boxReg = as_Register((int)$box$$reg);
3518 Register tmpReg = as_Register($tmp$$reg);
3519 Register scrReg = as_Register($scr$$reg);
3520 MacroAssembler masm(&cbuf);
3521
3522 // Verify uniqueness of register assignments -- necessary but not sufficient
3523 assert (objReg != boxReg && objReg != tmpReg &&
3524 objReg != scrReg && tmpReg != scrReg, "invariant") ;
3525
3526 if (_counters != NULL) {
3527 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3528 }
3529 if (EmitSync & 1) {
3530 masm.movptr (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
3531 masm.cmpq (rsp, 0) ;
3532 } else
3533 if (EmitSync & 2) {
3534 Label DONE_LABEL;
3535 if (UseBiasedLocking) {
3536 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3537 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3538 }
3539 masm.movl(tmpReg, 0x1);
3540 masm.orq(tmpReg, Address(objReg, 0));
3541 masm.movq(Address(boxReg, 0), tmpReg);
3542 if (os::is_MP()) {
3543 masm.lock();
3544 }
3545 masm.cmpxchgq(boxReg, Address(objReg, 0)); // Updates tmpReg
3546 masm.jcc(Assembler::equal, DONE_LABEL);
3547
3548 // Recursive locking
3549 masm.subq(tmpReg, rsp);
3550 masm.andq(tmpReg, 7 - os::vm_page_size());
3551 masm.movq(Address(boxReg, 0), tmpReg);
3552
3553 masm.bind(DONE_LABEL);
3554 masm.nop(); // avoid branch to branch
3555 } else {
3556 Label DONE_LABEL, IsInflated, Egress;
3557
3558 masm.movq (tmpReg, Address(objReg, 0)) ;
3559 masm.testq (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
3560 masm.jcc (Assembler::notZero, IsInflated) ;
3561
3562 // it's stack-locked, biased or neutral
3563 // TODO: optimize markword triage order to reduce the number of
3564 // conditional branches in the most common cases.
3565 // Beware -- there's a subtle invariant that fetch of the markword
3566 // at [FETCH], below, will never observe a biased encoding (*101b).
3567 // If this invariant is not held we'll suffer exclusion (safety) failure.
3568
3569 if (UseBiasedLocking) {
3570 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
3571 masm.movq (tmpReg, Address(objReg, 0)) ; // [FETCH]
3572 }
3573
3574 masm.orq (tmpReg, 1) ;
3575 masm.movq (Address(boxReg, 0), tmpReg) ;
3576 if (os::is_MP()) { masm.lock(); }
3577 masm.cmpxchgq(boxReg, Address(objReg, 0)); // Updates tmpReg
3578 if (_counters != NULL) {
3579 masm.cond_inc32(Assembler::equal,
3580 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3581 }
3582 masm.jcc (Assembler::equal, DONE_LABEL);
3583
3584 // Recursive locking
3585 masm.subq (tmpReg, rsp);
3586 masm.andq (tmpReg, 7 - os::vm_page_size());
3587 masm.movq (Address(boxReg, 0), tmpReg);
3588 if (_counters != NULL) {
3589 masm.cond_inc32(Assembler::equal,
3590 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3591 }
3592 masm.jmp (DONE_LABEL) ;
3593
3594 masm.bind (IsInflated) ;
3595 // It's inflated
3596
3597 // TODO: someday avoid the ST-before-CAS penalty by
3598 // relocating (deferring) the following ST.
3599 // We should also think about trying a CAS without having
3600 // fetched _owner. If the CAS is successful we may
3601 // avoid an RTO->RTS upgrade on the $line.
3602 masm.movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ;
3603
3604 masm.movq (boxReg, tmpReg) ;
3605 masm.movq (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3606 masm.testq (tmpReg, tmpReg) ;
3607 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3608
3609 // It's inflated and appears unlocked
3610 if (os::is_MP()) { masm.lock(); }
3611 masm.cmpxchgq(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3612 // Intentional fall-through into DONE_LABEL ...
3613
3614 masm.bind (DONE_LABEL) ;
3615 masm.nop () ; // avoid jmp to jmp
3616 }
3617 %}
3618
3619 // obj: object to unlock
3620 // box: box address (displaced header location), killed
3621 // RBX: killed tmp; cannot be obj nor box
3622 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
3623 %{
3624
3625 Register objReg = as_Register($obj$$reg);
3626 Register boxReg = as_Register($box$$reg);
3627 Register tmpReg = as_Register($tmp$$reg);
3628 MacroAssembler masm(&cbuf);
3629
3630 if (EmitSync & 4) {
3631 masm.cmpq (rsp, 0) ;
3632 } else
3633 if (EmitSync & 8) {
3634 Label DONE_LABEL;
3635 if (UseBiasedLocking) {
3636 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3637 }
3638
3639 // Check whether the displaced header is 0
3640 //(=> recursive unlock)
3641 masm.movq(tmpReg, Address(boxReg, 0));
3642 masm.testq(tmpReg, tmpReg);
3643 masm.jcc(Assembler::zero, DONE_LABEL);
3644
3645 // If not recursive lock, reset the header to displaced header
3646 if (os::is_MP()) {
3647 masm.lock();
3648 }
3649 masm.cmpxchgq(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3650 masm.bind(DONE_LABEL);
3651 masm.nop(); // avoid branch to branch
3652 } else {
3653 Label DONE_LABEL, Stacked, CheckSucc ;
3654
3655 if (UseBiasedLocking) {
3656 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3657 }
3658
3659 masm.movq (tmpReg, Address(objReg, 0)) ;
3660 masm.cmpq (Address(boxReg, 0), (int)NULL_WORD) ;
3661 masm.jcc (Assembler::zero, DONE_LABEL) ;
3662 masm.testq (tmpReg, 0x02) ;
3663 masm.jcc (Assembler::zero, Stacked) ;
3664
3665 // It's inflated
3666 masm.movq (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3667 masm.xorq (boxReg, r15_thread) ;
3668 masm.orq (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3669 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3670 masm.movq (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3671 masm.orq (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3672 masm.jcc (Assembler::notZero, CheckSucc) ;
3673 masm.mov64 (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ;
3674 masm.jmp (DONE_LABEL) ;
3675
3676 if ((EmitSync & 65536) == 0) {
3677 Label LSuccess, LGoSlowPath ;
3678 masm.bind (CheckSucc) ;
3679 masm.cmpq (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ;
3680 masm.jcc (Assembler::zero, LGoSlowPath) ;
3681
3682 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3683 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3684 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3685 // are all faster when the write buffer is populated.
3686 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int)NULL_WORD) ;
3687 if (os::is_MP()) {
3688 masm.lock () ; masm.addq (Address(rsp, 0), 0) ;
3689 }
3690 masm.cmpq (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int)NULL_WORD) ;
3691 masm.jcc (Assembler::notZero, LSuccess) ;
3692
3693 masm.movptr (boxReg, (int)NULL_WORD) ; // box is really EAX
3694 if (os::is_MP()) { masm.lock(); }
3695 masm.cmpxchgq (r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3696 masm.jcc (Assembler::notEqual, LSuccess) ;
3697 // Intentional fall-through into slow-path
3698
3699 masm.bind (LGoSlowPath) ;
3700 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3701 masm.jmp (DONE_LABEL) ;
3702
3703 masm.bind (LSuccess) ;
3704 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3705 masm.jmp (DONE_LABEL) ;
3706 }
3707
3708 masm.bind (Stacked) ;
3709 masm.movq (tmpReg, Address (boxReg, 0)) ; // re-fetch
3710 if (os::is_MP()) { masm.lock(); }
3711 masm.cmpxchgq(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3712
3713 if (EmitSync & 65536) {
3714 masm.bind (CheckSucc) ;
3715 }
3716 masm.bind(DONE_LABEL);
3717 if (EmitSync & 32768) {
3718 masm.nop(); // avoid branch to branch
3719 }
3720 }
3721 %}
3722
3723 enc_class enc_String_Compare()
3724 %{
3725 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3726 POP_LABEL, DONE_LABEL, CONT_LABEL,
3727 WHILE_HEAD_LABEL;
3728 MacroAssembler masm(&cbuf);
3729
3730 // Get the first character position in both strings
3731 // [8] char array, [12] offset, [16] count
3732 int value_offset = java_lang_String::value_offset_in_bytes();
3733 int offset_offset = java_lang_String::offset_offset_in_bytes();
3734 int count_offset = java_lang_String::count_offset_in_bytes();
3735 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3736
3737 masm.load_heap_oop(rax, Address(rsi, value_offset));
3738 masm.movl(rcx, Address(rsi, offset_offset));
3739 masm.leaq(rax, Address(rax, rcx, Address::times_2, base_offset));
3740 masm.load_heap_oop(rbx, Address(rdi, value_offset));
3741 masm.movl(rcx, Address(rdi, offset_offset));
3742 masm.leaq(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3743
3744 // Compute the minimum of the string lengths(rsi) and the
3745 // difference of the string lengths (stack)
3746
3747 masm.movl(rdi, Address(rdi, count_offset));
3748 masm.movl(rsi, Address(rsi, count_offset));
3749 masm.movl(rcx, rdi);
3750 masm.subl(rdi, rsi);
3751 masm.pushq(rdi);
3752 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3753
3754 // Is the minimum length zero?
3755 masm.bind(RCX_GOOD_LABEL);
3756 masm.testl(rsi, rsi);
3757 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3758
3759 // Load first characters
3760 masm.load_unsigned_word(rcx, Address(rbx, 0));
3761 masm.load_unsigned_word(rdi, Address(rax, 0));
3762
3763 // Compare first characters
3764 masm.subl(rcx, rdi);
3765 masm.jcc(Assembler::notZero, POP_LABEL);
3766 masm.decrementl(rsi);
3767 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL);
3768
3769 {
3770 // Check after comparing first character to see if strings are equivalent
3771 Label LSkip2;
3772 // Check if the strings start at same location
3773 masm.cmpq(rbx, rax);
3774 masm.jcc(Assembler::notEqual, LSkip2);
3775
3776 // Check if the length difference is zero (from stack)
3777 masm.cmpl(Address(rsp, 0), 0x0);
3778 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL);
3779
3780 // Strings might not be equivalent
3781 masm.bind(LSkip2);
3782 }
3783
3784 // Shift RAX and RBX to the end of the arrays, negate min
3785 masm.leaq(rax, Address(rax, rsi, Address::times_2, 2));
3786 masm.leaq(rbx, Address(rbx, rsi, Address::times_2, 2));
3787 masm.negq(rsi);
3788
3789 // Compare the rest of the characters
3790 masm.bind(WHILE_HEAD_LABEL);
3791 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3792 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3793 masm.subl(rcx, rdi);
3794 masm.jcc(Assembler::notZero, POP_LABEL);
3795 masm.incrementq(rsi);
3796 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3797
3798 // Strings are equal up to min length. Return the length difference.
3799 masm.bind(LENGTH_DIFF_LABEL);
3800 masm.popq(rcx);
3801 masm.jmp(DONE_LABEL);
3802
3803 // Discard the stored length difference
3804 masm.bind(POP_LABEL);
3805 masm.addq(rsp, 8);
3806
3807 // That's it
3808 masm.bind(DONE_LABEL);
3809 %}
3810
3811 enc_class enc_rethrow()
3812 %{
3813 cbuf.set_inst_mark();
3814 emit_opcode(cbuf, 0xE9); // jmp entry
3815 emit_d32_reloc(cbuf,
3816 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4),
3817 runtime_call_Relocation::spec(),
3818 RELOC_DISP32);
3819 %}
3820
3821 enc_class absF_encoding(regF dst)
3822 %{
3823 int dstenc = $dst$$reg;
3824 address signmask_address = (address) StubRoutines::amd64::float_sign_mask();
3825
3826 cbuf.set_inst_mark();
3827 if (dstenc >= 8) {
3828 emit_opcode(cbuf, Assembler::REX_R);
3829 dstenc -= 8;
3830 }
3831 // XXX reg_mem doesn't support RIP-relative addressing yet
3832 emit_opcode(cbuf, 0x0F);
3833 emit_opcode(cbuf, 0x54);
3834 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3835 emit_d32_reloc(cbuf, signmask_address);
3836 %}
3837
3838 enc_class absD_encoding(regD dst)
3839 %{
3840 int dstenc = $dst$$reg;
3841 address signmask_address = (address) StubRoutines::amd64::double_sign_mask();
3842
3843 cbuf.set_inst_mark();
3844 emit_opcode(cbuf, 0x66);
3845 if (dstenc >= 8) {
3846 emit_opcode(cbuf, Assembler::REX_R);
3847 dstenc -= 8;
3848 }
3849 // XXX reg_mem doesn't support RIP-relative addressing yet
3850 emit_opcode(cbuf, 0x0F);
3851 emit_opcode(cbuf, 0x54);
3852 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3853 emit_d32_reloc(cbuf, signmask_address);
3854 %}
3855
3856 enc_class negF_encoding(regF dst)
3857 %{
3858 int dstenc = $dst$$reg;
3859 address signflip_address = (address) StubRoutines::amd64::float_sign_flip();
3860
3861 cbuf.set_inst_mark();
3862 if (dstenc >= 8) {
3863 emit_opcode(cbuf, Assembler::REX_R);
3864 dstenc -= 8;
3865 }
3866 // XXX reg_mem doesn't support RIP-relative addressing yet
3867 emit_opcode(cbuf, 0x0F);
3868 emit_opcode(cbuf, 0x57);
3869 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3870 emit_d32_reloc(cbuf, signflip_address);
3871 %}
3872
3873 enc_class negD_encoding(regD dst)
3874 %{
3875 int dstenc = $dst$$reg;
3876 address signflip_address = (address) StubRoutines::amd64::double_sign_flip();
3877
3878 cbuf.set_inst_mark();
3879 emit_opcode(cbuf, 0x66);
3880 if (dstenc >= 8) {
3881 emit_opcode(cbuf, Assembler::REX_R);
3882 dstenc -= 8;
3883 }
3884 // XXX reg_mem doesn't support RIP-relative addressing yet
3885 emit_opcode(cbuf, 0x0F);
3886 emit_opcode(cbuf, 0x57);
3887 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
3888 emit_d32_reloc(cbuf, signflip_address);
3889 %}
3890
3891 enc_class f2i_fixup(rRegI dst, regF src)
3892 %{
3893 int dstenc = $dst$$reg;
3894 int srcenc = $src$$reg;
3895
3896 // cmpl $dst, #0x80000000
3897 if (dstenc >= 8) {
3898 emit_opcode(cbuf, Assembler::REX_B);
3899 }
3900 emit_opcode(cbuf, 0x81);
3901 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
3902 emit_d32(cbuf, 0x80000000);
3903
3904 // jne,s done
3905 emit_opcode(cbuf, 0x75);
3906 if (srcenc < 8 && dstenc < 8) {
3907 emit_d8(cbuf, 0xF);
3908 } else if (srcenc >= 8 && dstenc >= 8) {
3909 emit_d8(cbuf, 0x11);
3910 } else {
3911 emit_d8(cbuf, 0x10);
3912 }
3913
3914 // subq rsp, #8
3915 emit_opcode(cbuf, Assembler::REX_W);
3916 emit_opcode(cbuf, 0x83);
3917 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3918 emit_d8(cbuf, 8);
3919
3920 // movss [rsp], $src
3921 emit_opcode(cbuf, 0xF3);
3922 if (srcenc >= 8) {
3923 emit_opcode(cbuf, Assembler::REX_R);
3924 }
3925 emit_opcode(cbuf, 0x0F);
3926 emit_opcode(cbuf, 0x11);
3927 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3928
3929 // call f2i_fixup
3930 cbuf.set_inst_mark();
3931 emit_opcode(cbuf, 0xE8);
3932 emit_d32_reloc(cbuf,
3933 (int)
3934 (StubRoutines::amd64::f2i_fixup() - cbuf.code_end() - 4),
3935 runtime_call_Relocation::spec(),
3936 RELOC_DISP32);
3937
3938 // popq $dst
3939 if (dstenc >= 8) {
3940 emit_opcode(cbuf, Assembler::REX_B);
3941 }
3942 emit_opcode(cbuf, 0x58 | (dstenc & 7));
3943
3944 // done:
3945 %}
3946
3947 enc_class f2l_fixup(rRegL dst, regF src)
3948 %{
3949 int dstenc = $dst$$reg;
3950 int srcenc = $src$$reg;
3951 address const_address = (address) StubRoutines::amd64::double_sign_flip();
3952
3953 // cmpq $dst, [0x8000000000000000]
3954 cbuf.set_inst_mark();
3955 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
3956 emit_opcode(cbuf, 0x39);
3957 // XXX reg_mem doesn't support RIP-relative addressing yet
3958 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
3959 emit_d32_reloc(cbuf, const_address);
3960
3961
3962 // jne,s done
3963 emit_opcode(cbuf, 0x75);
3964 if (srcenc < 8 && dstenc < 8) {
3965 emit_d8(cbuf, 0xF);
3966 } else if (srcenc >= 8 && dstenc >= 8) {
3967 emit_d8(cbuf, 0x11);
3968 } else {
3969 emit_d8(cbuf, 0x10);
3970 }
3971
3972 // subq rsp, #8
3973 emit_opcode(cbuf, Assembler::REX_W);
3974 emit_opcode(cbuf, 0x83);
3975 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3976 emit_d8(cbuf, 8);
3977
3978 // movss [rsp], $src
3979 emit_opcode(cbuf, 0xF3);
3980 if (srcenc >= 8) {
3981 emit_opcode(cbuf, Assembler::REX_R);
3982 }
3983 emit_opcode(cbuf, 0x0F);
3984 emit_opcode(cbuf, 0x11);
3985 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
3986
3987 // call f2l_fixup
3988 cbuf.set_inst_mark();
3989 emit_opcode(cbuf, 0xE8);
3990 emit_d32_reloc(cbuf,
3991 (int)
3992 (StubRoutines::amd64::f2l_fixup() - cbuf.code_end() - 4),
3993 runtime_call_Relocation::spec(),
3994 RELOC_DISP32);
3995
3996 // popq $dst
3997 if (dstenc >= 8) {
3998 emit_opcode(cbuf, Assembler::REX_B);
3999 }
4000 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4001
4002 // done:
4003 %}
4004
4005 enc_class d2i_fixup(rRegI dst, regD src)
4006 %{
4007 int dstenc = $dst$$reg;
4008 int srcenc = $src$$reg;
4009
4010 // cmpl $dst, #0x80000000
4011 if (dstenc >= 8) {
4012 emit_opcode(cbuf, Assembler::REX_B);
4013 }
4014 emit_opcode(cbuf, 0x81);
4015 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
4016 emit_d32(cbuf, 0x80000000);
4017
4018 // jne,s done
4019 emit_opcode(cbuf, 0x75);
4020 if (srcenc < 8 && dstenc < 8) {
4021 emit_d8(cbuf, 0xF);
4022 } else if (srcenc >= 8 && dstenc >= 8) {
4023 emit_d8(cbuf, 0x11);
4024 } else {
4025 emit_d8(cbuf, 0x10);
4026 }
4027
4028 // subq rsp, #8
4029 emit_opcode(cbuf, Assembler::REX_W);
4030 emit_opcode(cbuf, 0x83);
4031 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4032 emit_d8(cbuf, 8);
4033
4034 // movsd [rsp], $src
4035 emit_opcode(cbuf, 0xF2);
4036 if (srcenc >= 8) {
4037 emit_opcode(cbuf, Assembler::REX_R);
4038 }
4039 emit_opcode(cbuf, 0x0F);
4040 emit_opcode(cbuf, 0x11);
4041 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4042
4043 // call d2i_fixup
4044 cbuf.set_inst_mark();
4045 emit_opcode(cbuf, 0xE8);
4046 emit_d32_reloc(cbuf,
4047 (int)
4048 (StubRoutines::amd64::d2i_fixup() - cbuf.code_end() - 4),
4049 runtime_call_Relocation::spec(),
4050 RELOC_DISP32);
4051
4052 // popq $dst
4053 if (dstenc >= 8) {
4054 emit_opcode(cbuf, Assembler::REX_B);
4055 }
4056 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4057
4058 // done:
4059 %}
4060
4061 enc_class d2l_fixup(rRegL dst, regD src)
4062 %{
4063 int dstenc = $dst$$reg;
4064 int srcenc = $src$$reg;
4065 address const_address = (address) StubRoutines::amd64::double_sign_flip();
4066
4067 // cmpq $dst, [0x8000000000000000]
4068 cbuf.set_inst_mark();
4069 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
4070 emit_opcode(cbuf, 0x39);
4071 // XXX reg_mem doesn't support RIP-relative addressing yet
4072 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
4073 emit_d32_reloc(cbuf, const_address);
4074
4075
4076 // jne,s done
4077 emit_opcode(cbuf, 0x75);
4078 if (srcenc < 8 && dstenc < 8) {
4079 emit_d8(cbuf, 0xF);
4080 } else if (srcenc >= 8 && dstenc >= 8) {
4081 emit_d8(cbuf, 0x11);
4082 } else {
4083 emit_d8(cbuf, 0x10);
4084 }
4085
4086 // subq rsp, #8
4087 emit_opcode(cbuf, Assembler::REX_W);
4088 emit_opcode(cbuf, 0x83);
4089 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4090 emit_d8(cbuf, 8);
4091
4092 // movsd [rsp], $src
4093 emit_opcode(cbuf, 0xF2);
4094 if (srcenc >= 8) {
4095 emit_opcode(cbuf, Assembler::REX_R);
4096 }
4097 emit_opcode(cbuf, 0x0F);
4098 emit_opcode(cbuf, 0x11);
4099 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4100
4101 // call d2l_fixup
4102 cbuf.set_inst_mark();
4103 emit_opcode(cbuf, 0xE8);
4104 emit_d32_reloc(cbuf,
4105 (int)
4106 (StubRoutines::amd64::d2l_fixup() - cbuf.code_end() - 4),
4107 runtime_call_Relocation::spec(),
4108 RELOC_DISP32);
4109
4110 // popq $dst
4111 if (dstenc >= 8) {
4112 emit_opcode(cbuf, Assembler::REX_B);
4113 }
4114 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4115
4116 // done:
4117 %}
4118
4119 enc_class enc_membar_acquire
4120 %{
4121 // [jk] not needed currently, if you enable this and it really
4122 // emits code don't forget to the remove the "size(0)" line in
4123 // membar_acquire()
4124 // MacroAssembler masm(&cbuf);
4125 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore |
4126 // Assembler::LoadLoad));
4127 %}
4128
4129 enc_class enc_membar_release
4130 %{
4131 // [jk] not needed currently, if you enable this and it really
4132 // emits code don't forget to the remove the "size(0)" line in
4133 // membar_release()
4134 // MacroAssembler masm(&cbuf);
4135 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore |
4136 // Assembler::StoreStore));
4137 %}
4138
4139 enc_class enc_membar_volatile
4140 %{
4141 MacroAssembler masm(&cbuf);
4142 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4143 Assembler::StoreStore));
4144 %}
4145
4146 // Safepoint Poll. This polls the safepoint page, and causes an
4147 // exception if it is not readable. Unfortunately, it kills
4148 // RFLAGS in the process.
4149 enc_class enc_safepoint_poll
4150 %{
4151 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
4152 // XXX reg_mem doesn't support RIP-relative addressing yet
4153 cbuf.set_inst_mark();
4154 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX
4155 emit_opcode(cbuf, 0x85); // testl
4156 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
4157 // cbuf.inst_mark() is beginning of instruction
4158 emit_d32_reloc(cbuf, os::get_polling_page());
4159 // relocInfo::poll_type,
4160 %}
4161 %}
4162
4163
4164
4165 //----------FRAME--------------------------------------------------------------
4166 // Definition of frame structure and management information.
4167 //
4168 // S T A C K L A Y O U T Allocators stack-slot number
4169 // | (to get allocators register number
4170 // G Owned by | | v add OptoReg::stack0())
4171 // r CALLER | |
4172 // o | +--------+ pad to even-align allocators stack-slot
4173 // w V | pad0 | numbers; owned by CALLER
4174 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4175 // h ^ | in | 5
4176 // | | args | 4 Holes in incoming args owned by SELF
4177 // | | | | 3
4178 // | | +--------+
4179 // V | | old out| Empty on Intel, window on Sparc
4180 // | old |preserve| Must be even aligned.
4181 // | SP-+--------+----> Matcher::_old_SP, even aligned
4182 // | | in | 3 area for Intel ret address
4183 // Owned by |preserve| Empty on Sparc.
4184 // SELF +--------+
4185 // | | pad2 | 2 pad to align old SP
4186 // | +--------+ 1
4187 // | | locks | 0
4188 // | +--------+----> OptoReg::stack0(), even aligned
4189 // | | pad1 | 11 pad to align new SP
4190 // | +--------+
4191 // | | | 10
4192 // | | spills | 9 spills
4193 // V | | 8 (pad0 slot for callee)
4194 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4195 // ^ | out | 7
4196 // | | args | 6 Holes in outgoing args owned by CALLEE
4197 // Owned by +--------+
4198 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4199 // | new |preserve| Must be even-aligned.
4200 // | SP-+--------+----> Matcher::_new_SP, even aligned
4201 // | | |
4202 //
4203 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4204 // known from SELF's arguments and the Java calling convention.
4205 // Region 6-7 is determined per call site.
4206 // Note 2: If the calling convention leaves holes in the incoming argument
4207 // area, those holes are owned by SELF. Holes in the outgoing area
4208 // are owned by the CALLEE. Holes should not be nessecary in the
4209 // incoming area, as the Java calling convention is completely under
4210 // the control of the AD file. Doubles can be sorted and packed to
4211 // avoid holes. Holes in the outgoing arguments may be nessecary for
4212 // varargs C calling conventions.
4213 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4214 // even aligned with pad0 as needed.
4215 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4216 // region 6-11 is even aligned; it may be padded out more so that
4217 // the region from SP to FP meets the minimum stack alignment.
4218 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
4219 // alignment. Region 11, pad1, may be dynamically extended so that
4220 // SP meets the minimum alignment.
4221
4222 frame
4223 %{
4224 // What direction does stack grow in (assumed to be same for C & Java)
4225 stack_direction(TOWARDS_LOW);
4226
4227 // These three registers define part of the calling convention
4228 // between compiled code and the interpreter.
4229 inline_cache_reg(RAX); // Inline Cache Register
4230 interpreter_method_oop_reg(RBX); // Method Oop Register when
4231 // calling interpreter
4232
4233 // Optional: name the operand used by cisc-spilling to access
4234 // [stack_pointer + offset]
4235 cisc_spilling_operand_name(indOffset32);
4236
4237 // Number of stack slots consumed by locking an object
4238 sync_stack_slots(2);
4239
4240 // Compiled code's Frame Pointer
4241 frame_pointer(RSP);
4242
4243 // Interpreter stores its frame pointer in a register which is
4244 // stored to the stack by I2CAdaptors.
4245 // I2CAdaptors convert from interpreted java to compiled java.
4246 interpreter_frame_pointer(RBP);
4247
4248 // Stack alignment requirement
4249 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
4250
4251 // Number of stack slots between incoming argument block and the start of
4252 // a new frame. The PROLOG must add this many slots to the stack. The
4253 // EPILOG must remove this many slots. amd64 needs two slots for
4254 // return address.
4255 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
4256
4257 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4258 // for calls to C. Supports the var-args backing area for register parms.
4259 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
4260
4261 // The after-PROLOG location of the return address. Location of
4262 // return address specifies a type (REG or STACK) and a number
4263 // representing the register number (i.e. - use a register name) or
4264 // stack slot.
4265 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4266 // Otherwise, it is above the locks and verification slot and alignment word
4267 return_addr(STACK - 2 +
4268 round_to(2 + 2 * VerifyStackAtCalls +
4269 Compile::current()->fixed_slots(),
4270 WordsPerLong * 2));
4271
4272 // Body of function which returns an integer array locating
4273 // arguments either in registers or in stack slots. Passed an array
4274 // of ideal registers called "sig" and a "length" count. Stack-slot
4275 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4276 // arguments for a CALLEE. Incoming stack arguments are
4277 // automatically biased by the preserve_stack_slots field above.
4278
4279 calling_convention
4280 %{
4281 // No difference between ingoing/outgoing just pass false
4282 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4283 %}
4284
4285 c_calling_convention
4286 %{
4287 // This is obviously always outgoing
4288 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4289 %}
4290
4291 // Location of compiled Java return values. Same as C for now.
4292 return_value
4293 %{
4294 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
4295 "only return normal values");
4296
4297 static const int lo[Op_RegL + 1] = {
4298 0,
4299 0,
4300 RAX_num, // Op_RegN
4301 RAX_num, // Op_RegI
4302 RAX_num, // Op_RegP
4303 XMM0_num, // Op_RegF
4304 XMM0_num, // Op_RegD
4305 RAX_num // Op_RegL
4306 };
4307 static const int hi[Op_RegL + 1] = {
4308 0,
4309 0,
4310 OptoReg::Bad, // Op_RegN
4311 OptoReg::Bad, // Op_RegI
4312 RAX_H_num, // Op_RegP
4313 OptoReg::Bad, // Op_RegF
4314 XMM0_H_num, // Op_RegD
4315 RAX_H_num // Op_RegL
4316 };
4317 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
4318 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
4319 %}
4320 %}
4321
4322 //----------ATTRIBUTES---------------------------------------------------------
4323 //----------Operand Attributes-------------------------------------------------
4324 op_attrib op_cost(0); // Required cost attribute
4325
4326 //----------Instruction Attributes---------------------------------------------
4327 ins_attrib ins_cost(100); // Required cost attribute
4328 ins_attrib ins_size(8); // Required size attribute (in bits)
4329 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4330 ins_attrib ins_short_branch(0); // Required flag: is this instruction
4331 // a non-matching short branch variant
4332 // of some long branch?
4333 ins_attrib ins_alignment(1); // Required alignment attribute (must
4334 // be a power of 2) specifies the
4335 // alignment that some part of the
4336 // instruction (not necessarily the
4337 // start) requires. If > 1, a
4338 // compute_padding() function must be
4339 // provided for the instruction
4340
4341 //----------OPERANDS-----------------------------------------------------------
4342 // Operand definitions must precede instruction definitions for correct parsing
4343 // in the ADLC because operands constitute user defined types which are used in
4344 // instruction definitions.
4345
4346 //----------Simple Operands----------------------------------------------------
4347 // Immediate Operands
4348 // Integer Immediate
4349 operand immI()
4350 %{
4351 match(ConI);
4352
4353 op_cost(10);
4354 format %{ %}
4355 interface(CONST_INTER);
4356 %}
4357
4358 // Constant for test vs zero
4359 operand immI0()
4360 %{
4361 predicate(n->get_int() == 0);
4362 match(ConI);
4363
4364 op_cost(0);
4365 format %{ %}
4366 interface(CONST_INTER);
4367 %}
4368
4369 // Constant for increment
4370 operand immI1()
4371 %{
4372 predicate(n->get_int() == 1);
4373 match(ConI);
4374
4375 op_cost(0);
4376 format %{ %}
4377 interface(CONST_INTER);
4378 %}
4379
4380 // Constant for decrement
4381 operand immI_M1()
4382 %{
4383 predicate(n->get_int() == -1);
4384 match(ConI);
4385
4386 op_cost(0);
4387 format %{ %}
4388 interface(CONST_INTER);
4389 %}
4390
4391 // Valid scale values for addressing modes
4392 operand immI2()
4393 %{
4394 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4395 match(ConI);
4396
4397 format %{ %}
4398 interface(CONST_INTER);
4399 %}
4400
4401 operand immI8()
4402 %{
4403 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
4404 match(ConI);
4405
4406 op_cost(5);
4407 format %{ %}
4408 interface(CONST_INTER);
4409 %}
4410
4411 operand immI16()
4412 %{
4413 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4414 match(ConI);
4415
4416 op_cost(10);
4417 format %{ %}
4418 interface(CONST_INTER);
4419 %}
4420
4421 // Constant for long shifts
4422 operand immI_32()
4423 %{
4424 predicate( n->get_int() == 32 );
4425 match(ConI);
4426
4427 op_cost(0);
4428 format %{ %}
4429 interface(CONST_INTER);
4430 %}
4431
4432 // Constant for long shifts
4433 operand immI_64()
4434 %{
4435 predicate( n->get_int() == 64 );
4436 match(ConI);
4437
4438 op_cost(0);
4439 format %{ %}
4440 interface(CONST_INTER);
4441 %}
4442
4443 // Pointer Immediate
4444 operand immP()
4445 %{
4446 match(ConP);
4447
4448 op_cost(10);
4449 format %{ %}
4450 interface(CONST_INTER);
4451 %}
4452
4453 // NULL Pointer Immediate
4454 operand immP0()
4455 %{
4456 predicate(n->get_ptr() == 0);
4457 match(ConP);
4458
4459 op_cost(5);
4460 format %{ %}
4461 interface(CONST_INTER);
4462 %}
4463
4464 // Pointer Immediate
4465 operand immN() %{
4466 match(ConN);
4467
4468 op_cost(10);
4469 format %{ %}
4470 interface(CONST_INTER);
4471 %}
4472
4473 // NULL Pointer Immediate
4474 operand immN0() %{
4475 predicate(n->get_narrowcon() == 0);
4476 match(ConN);
4477
4478 op_cost(5);
4479 format %{ %}
4480 interface(CONST_INTER);
4481 %}
4482
4483 operand immP31()
4484 %{
4485 predicate(!n->as_Type()->type()->isa_oopptr()
4486 && (n->get_ptr() >> 31) == 0);
4487 match(ConP);
4488
4489 op_cost(5);
4490 format %{ %}
4491 interface(CONST_INTER);
4492 %}
4493
4494
4495 // Long Immediate
4496 operand immL()
4497 %{
4498 match(ConL);
4499
4500 op_cost(20);
4501 format %{ %}
4502 interface(CONST_INTER);
4503 %}
4504
4505 // Long Immediate 8-bit
4506 operand immL8()
4507 %{
4508 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
4509 match(ConL);
4510
4511 op_cost(5);
4512 format %{ %}
4513 interface(CONST_INTER);
4514 %}
4515
4516 // Long Immediate 32-bit unsigned
4517 operand immUL32()
4518 %{
4519 predicate(n->get_long() == (unsigned int) (n->get_long()));
4520 match(ConL);
4521
4522 op_cost(10);
4523 format %{ %}
4524 interface(CONST_INTER);
4525 %}
4526
4527 // Long Immediate 32-bit signed
4528 operand immL32()
4529 %{
4530 predicate(n->get_long() == (int) (n->get_long()));
4531 match(ConL);
4532
4533 op_cost(15);
4534 format %{ %}
4535 interface(CONST_INTER);
4536 %}
4537
4538 // Long Immediate zero
4539 operand immL0()
4540 %{
4541 predicate(n->get_long() == 0L);
4542 match(ConL);
4543
4544 op_cost(10);
4545 format %{ %}
4546 interface(CONST_INTER);
4547 %}
4548
4549 // Constant for increment
4550 operand immL1()
4551 %{
4552 predicate(n->get_long() == 1);
4553 match(ConL);
4554
4555 format %{ %}
4556 interface(CONST_INTER);
4557 %}
4558
4559 // Constant for decrement
4560 operand immL_M1()
4561 %{
4562 predicate(n->get_long() == -1);
4563 match(ConL);
4564
4565 format %{ %}
4566 interface(CONST_INTER);
4567 %}
4568
4569 // Long Immediate: the value 10
4570 operand immL10()
4571 %{
4572 predicate(n->get_long() == 10);
4573 match(ConL);
4574
4575 format %{ %}
4576 interface(CONST_INTER);
4577 %}
4578
4579 // Long immediate from 0 to 127.
4580 // Used for a shorter form of long mul by 10.
4581 operand immL_127()
4582 %{
4583 predicate(0 <= n->get_long() && n->get_long() < 0x80);
4584 match(ConL);
4585
4586 op_cost(10);
4587 format %{ %}
4588 interface(CONST_INTER);
4589 %}
4590
4591 // Long Immediate: low 32-bit mask
4592 operand immL_32bits()
4593 %{
4594 predicate(n->get_long() == 0xFFFFFFFFL);
4595 match(ConL);
4596 op_cost(20);
4597
4598 format %{ %}
4599 interface(CONST_INTER);
4600 %}
4601
4602 // Float Immediate zero
4603 operand immF0()
4604 %{
4605 predicate(jint_cast(n->getf()) == 0);
4606 match(ConF);
4607
4608 op_cost(5);
4609 format %{ %}
4610 interface(CONST_INTER);
4611 %}
4612
4613 // Float Immediate
4614 operand immF()
4615 %{
4616 match(ConF);
4617
4618 op_cost(15);
4619 format %{ %}
4620 interface(CONST_INTER);
4621 %}
4622
4623 // Double Immediate zero
4624 operand immD0()
4625 %{
4626 predicate(jlong_cast(n->getd()) == 0);
4627 match(ConD);
4628
4629 op_cost(5);
4630 format %{ %}
4631 interface(CONST_INTER);
4632 %}
4633
4634 // Double Immediate
4635 operand immD()
4636 %{
4637 match(ConD);
4638
4639 op_cost(15);
4640 format %{ %}
4641 interface(CONST_INTER);
4642 %}
4643
4644 // Immediates for special shifts (sign extend)
4645
4646 // Constants for increment
4647 operand immI_16()
4648 %{
4649 predicate(n->get_int() == 16);
4650 match(ConI);
4651
4652 format %{ %}
4653 interface(CONST_INTER);
4654 %}
4655
4656 operand immI_24()
4657 %{
4658 predicate(n->get_int() == 24);
4659 match(ConI);
4660
4661 format %{ %}
4662 interface(CONST_INTER);
4663 %}
4664
4665 // Constant for byte-wide masking
4666 operand immI_255()
4667 %{
4668 predicate(n->get_int() == 255);
4669 match(ConI);
4670
4671 format %{ %}
4672 interface(CONST_INTER);
4673 %}
4674
4675 // Constant for short-wide masking
4676 operand immI_65535()
4677 %{
4678 predicate(n->get_int() == 65535);
4679 match(ConI);
4680
4681 format %{ %}
4682 interface(CONST_INTER);
4683 %}
4684
4685 // Constant for byte-wide masking
4686 operand immL_255()
4687 %{
4688 predicate(n->get_long() == 255);
4689 match(ConL);
4690
4691 format %{ %}
4692 interface(CONST_INTER);
4693 %}
4694
4695 // Constant for short-wide masking
4696 operand immL_65535()
4697 %{
4698 predicate(n->get_long() == 65535);
4699 match(ConL);
4700
4701 format %{ %}
4702 interface(CONST_INTER);
4703 %}
4704
4705 // Register Operands
4706 // Integer Register
4707 operand rRegI()
4708 %{
4709 constraint(ALLOC_IN_RC(int_reg));
4710 match(RegI);
4711
4712 match(rax_RegI);
4713 match(rbx_RegI);
4714 match(rcx_RegI);
4715 match(rdx_RegI);
4716 match(rdi_RegI);
4717
4718 format %{ %}
4719 interface(REG_INTER);
4720 %}
4721
4722 // Special Registers
4723 operand rax_RegI()
4724 %{
4725 constraint(ALLOC_IN_RC(int_rax_reg));
4726 match(RegI);
4727 match(rRegI);
4728
4729 format %{ "RAX" %}
4730 interface(REG_INTER);
4731 %}
4732
4733 // Special Registers
4734 operand rbx_RegI()
4735 %{
4736 constraint(ALLOC_IN_RC(int_rbx_reg));
4737 match(RegI);
4738 match(rRegI);
4739
4740 format %{ "RBX" %}
4741 interface(REG_INTER);
4742 %}
4743
4744 operand rcx_RegI()
4745 %{
4746 constraint(ALLOC_IN_RC(int_rcx_reg));
4747 match(RegI);
4748 match(rRegI);
4749
4750 format %{ "RCX" %}
4751 interface(REG_INTER);
4752 %}
4753
4754 operand rdx_RegI()
4755 %{
4756 constraint(ALLOC_IN_RC(int_rdx_reg));
4757 match(RegI);
4758 match(rRegI);
4759
4760 format %{ "RDX" %}
4761 interface(REG_INTER);
4762 %}
4763
4764 operand rdi_RegI()
4765 %{
4766 constraint(ALLOC_IN_RC(int_rdi_reg));
4767 match(RegI);
4768 match(rRegI);
4769
4770 format %{ "RDI" %}
4771 interface(REG_INTER);
4772 %}
4773
4774 operand no_rcx_RegI()
4775 %{
4776 constraint(ALLOC_IN_RC(int_no_rcx_reg));
4777 match(RegI);
4778 match(rax_RegI);
4779 match(rbx_RegI);
4780 match(rdx_RegI);
4781 match(rdi_RegI);
4782
4783 format %{ %}
4784 interface(REG_INTER);
4785 %}
4786
4787 operand no_rax_rdx_RegI()
4788 %{
4789 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
4790 match(RegI);
4791 match(rbx_RegI);
4792 match(rcx_RegI);
4793 match(rdi_RegI);
4794
4795 format %{ %}
4796 interface(REG_INTER);
4797 %}
4798
4799 // Pointer Register
4800 operand any_RegP()
4801 %{
4802 constraint(ALLOC_IN_RC(any_reg));
4803 match(RegP);
4804 match(rax_RegP);
4805 match(rbx_RegP);
4806 match(rdi_RegP);
4807 match(rsi_RegP);
4808 match(rbp_RegP);
4809 match(r15_RegP);
4810 match(rRegP);
4811
4812 format %{ %}
4813 interface(REG_INTER);
4814 %}
4815
4816 operand rRegP()
4817 %{
4818 constraint(ALLOC_IN_RC(ptr_reg));
4819 match(RegP);
4820 match(rax_RegP);
4821 match(rbx_RegP);
4822 match(rdi_RegP);
4823 match(rsi_RegP);
4824 match(rbp_RegP);
4825 match(r15_RegP); // See Q&A below about r15_RegP.
4826
4827 format %{ %}
4828 interface(REG_INTER);
4829 %}
4830
4831
4832 operand r12RegL() %{
4833 constraint(ALLOC_IN_RC(long_r12_reg));
4834 match(RegL);
4835
4836 format %{ %}
4837 interface(REG_INTER);
4838 %}
4839
4840 operand rRegN() %{
4841 constraint(ALLOC_IN_RC(int_reg));
4842 match(RegN);
4843
4844 format %{ %}
4845 interface(REG_INTER);
4846 %}
4847
4848 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
4849 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
4850 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
4851 // The output of an instruction is controlled by the allocator, which respects
4852 // register class masks, not match rules. Unless an instruction mentions
4853 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
4854 // by the allocator as an input.
4855
4856 operand no_rax_RegP()
4857 %{
4858 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
4859 match(RegP);
4860 match(rbx_RegP);
4861 match(rsi_RegP);
4862 match(rdi_RegP);
4863
4864 format %{ %}
4865 interface(REG_INTER);
4866 %}
4867
4868 operand no_rbp_RegP()
4869 %{
4870 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
4871 match(RegP);
4872 match(rbx_RegP);
4873 match(rsi_RegP);
4874 match(rdi_RegP);
4875
4876 format %{ %}
4877 interface(REG_INTER);
4878 %}
4879
4880 operand no_rax_rbx_RegP()
4881 %{
4882 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
4883 match(RegP);
4884 match(rsi_RegP);
4885 match(rdi_RegP);
4886
4887 format %{ %}
4888 interface(REG_INTER);
4889 %}
4890
4891 // Special Registers
4892 // Return a pointer value
4893 operand rax_RegP()
4894 %{
4895 constraint(ALLOC_IN_RC(ptr_rax_reg));
4896 match(RegP);
4897 match(rRegP);
4898
4899 format %{ %}
4900 interface(REG_INTER);
4901 %}
4902
4903 // Special Registers
4904 // Return a compressed pointer value
4905 operand rax_RegN()
4906 %{
4907 constraint(ALLOC_IN_RC(int_rax_reg));
4908 match(RegN);
4909 match(rRegN);
4910
4911 format %{ %}
4912 interface(REG_INTER);
4913 %}
4914
4915 // Used in AtomicAdd
4916 operand rbx_RegP()
4917 %{
4918 constraint(ALLOC_IN_RC(ptr_rbx_reg));
4919 match(RegP);
4920 match(rRegP);
4921
4922 format %{ %}
4923 interface(REG_INTER);
4924 %}
4925
4926 operand rsi_RegP()
4927 %{
4928 constraint(ALLOC_IN_RC(ptr_rsi_reg));
4929 match(RegP);
4930 match(rRegP);
4931
4932 format %{ %}
4933 interface(REG_INTER);
4934 %}
4935
4936 // Used in rep stosq
4937 operand rdi_RegP()
4938 %{
4939 constraint(ALLOC_IN_RC(ptr_rdi_reg));
4940 match(RegP);
4941 match(rRegP);
4942
4943 format %{ %}
4944 interface(REG_INTER);
4945 %}
4946
4947 operand rbp_RegP()
4948 %{
4949 constraint(ALLOC_IN_RC(ptr_rbp_reg));
4950 match(RegP);
4951 match(rRegP);
4952
4953 format %{ %}
4954 interface(REG_INTER);
4955 %}
4956
4957 operand r15_RegP()
4958 %{
4959 constraint(ALLOC_IN_RC(ptr_r15_reg));
4960 match(RegP);
4961 match(rRegP);
4962
4963 format %{ %}
4964 interface(REG_INTER);
4965 %}
4966
4967 operand rRegL()
4968 %{
4969 constraint(ALLOC_IN_RC(long_reg));
4970 match(RegL);
4971 match(rax_RegL);
4972 match(rdx_RegL);
4973
4974 format %{ %}
4975 interface(REG_INTER);
4976 %}
4977
4978 // Special Registers
4979 operand no_rax_rdx_RegL()
4980 %{
4981 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4982 match(RegL);
4983 match(rRegL);
4984
4985 format %{ %}
4986 interface(REG_INTER);
4987 %}
4988
4989 operand no_rax_RegL()
4990 %{
4991 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
4992 match(RegL);
4993 match(rRegL);
4994 match(rdx_RegL);
4995
4996 format %{ %}
4997 interface(REG_INTER);
4998 %}
4999
5000 operand no_rcx_RegL()
5001 %{
5002 constraint(ALLOC_IN_RC(long_no_rcx_reg));
5003 match(RegL);
5004 match(rRegL);
5005
5006 format %{ %}
5007 interface(REG_INTER);
5008 %}
5009
5010 operand rax_RegL()
5011 %{
5012 constraint(ALLOC_IN_RC(long_rax_reg));
5013 match(RegL);
5014 match(rRegL);
5015
5016 format %{ "RAX" %}
5017 interface(REG_INTER);
5018 %}
5019
5020 operand rcx_RegL()
5021 %{
5022 constraint(ALLOC_IN_RC(long_rcx_reg));
5023 match(RegL);
5024 match(rRegL);
5025
5026 format %{ %}
5027 interface(REG_INTER);
5028 %}
5029
5030 operand rdx_RegL()
5031 %{
5032 constraint(ALLOC_IN_RC(long_rdx_reg));
5033 match(RegL);
5034 match(rRegL);
5035
5036 format %{ %}
5037 interface(REG_INTER);
5038 %}
5039
5040 // Flags register, used as output of compare instructions
5041 operand rFlagsReg()
5042 %{
5043 constraint(ALLOC_IN_RC(int_flags));
5044 match(RegFlags);
5045
5046 format %{ "RFLAGS" %}
5047 interface(REG_INTER);
5048 %}
5049
5050 // Flags register, used as output of FLOATING POINT compare instructions
5051 operand rFlagsRegU()
5052 %{
5053 constraint(ALLOC_IN_RC(int_flags));
5054 match(RegFlags);
5055
5056 format %{ "RFLAGS_U" %}
5057 interface(REG_INTER);
5058 %}
5059
5060 // Float register operands
5061 operand regF()
5062 %{
5063 constraint(ALLOC_IN_RC(float_reg));
5064 match(RegF);
5065
5066 format %{ %}
5067 interface(REG_INTER);
5068 %}
5069
5070 // Double register operands
5071 operand regD()
5072 %{
5073 constraint(ALLOC_IN_RC(double_reg));
5074 match(RegD);
5075
5076 format %{ %}
5077 interface(REG_INTER);
5078 %}
5079
5080
5081 //----------Memory Operands----------------------------------------------------
5082 // Direct Memory Operand
5083 // operand direct(immP addr)
5084 // %{
5085 // match(addr);
5086
5087 // format %{ "[$addr]" %}
5088 // interface(MEMORY_INTER) %{
5089 // base(0xFFFFFFFF);
5090 // index(0x4);
5091 // scale(0x0);
5092 // disp($addr);
5093 // %}
5094 // %}
5095
5096 // Indirect Memory Operand
5097 operand indirect(any_RegP reg)
5098 %{
5099 constraint(ALLOC_IN_RC(ptr_reg));
5100 match(reg);
5101
5102 format %{ "[$reg]" %}
5103 interface(MEMORY_INTER) %{
5104 base($reg);
5105 index(0x4);
5106 scale(0x0);
5107 disp(0x0);
5108 %}
5109 %}
5110
5111 // Indirect Memory Plus Short Offset Operand
5112 operand indOffset8(any_RegP reg, immL8 off)
5113 %{
5114 constraint(ALLOC_IN_RC(ptr_reg));
5115 match(AddP reg off);
5116
5117 format %{ "[$reg + $off (8-bit)]" %}
5118 interface(MEMORY_INTER) %{
5119 base($reg);
5120 index(0x4);
5121 scale(0x0);
5122 disp($off);
5123 %}
5124 %}
5125
5126 // Indirect Memory Plus Long Offset Operand
5127 operand indOffset32(any_RegP reg, immL32 off)
5128 %{
5129 constraint(ALLOC_IN_RC(ptr_reg));
5130 match(AddP reg off);
5131
5132 format %{ "[$reg + $off (32-bit)]" %}
5133 interface(MEMORY_INTER) %{
5134 base($reg);
5135 index(0x4);
5136 scale(0x0);
5137 disp($off);
5138 %}
5139 %}
5140
5141 // Indirect Memory Plus Index Register Plus Offset Operand
5142 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
5143 %{
5144 constraint(ALLOC_IN_RC(ptr_reg));
5145 match(AddP (AddP reg lreg) off);
5146
5147 op_cost(10);
5148 format %{"[$reg + $off + $lreg]" %}
5149 interface(MEMORY_INTER) %{
5150 base($reg);
5151 index($lreg);
5152 scale(0x0);
5153 disp($off);
5154 %}
5155 %}
5156
5157 // Indirect Memory Plus Index Register Plus Offset Operand
5158 operand indIndex(any_RegP reg, rRegL lreg)
5159 %{
5160 constraint(ALLOC_IN_RC(ptr_reg));
5161 match(AddP reg lreg);
5162
5163 op_cost(10);
5164 format %{"[$reg + $lreg]" %}
5165 interface(MEMORY_INTER) %{
5166 base($reg);
5167 index($lreg);
5168 scale(0x0);
5169 disp(0x0);
5170 %}
5171 %}
5172
5173 // Indirect Memory Times Scale Plus Index Register
5174 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
5175 %{
5176 constraint(ALLOC_IN_RC(ptr_reg));
5177 match(AddP reg (LShiftL lreg scale));
5178
5179 op_cost(10);
5180 format %{"[$reg + $lreg << $scale]" %}
5181 interface(MEMORY_INTER) %{
5182 base($reg);
5183 index($lreg);
5184 scale($scale);
5185 disp(0x0);
5186 %}
5187 %}
5188
5189 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5190 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
5191 %{
5192 constraint(ALLOC_IN_RC(ptr_reg));
5193 match(AddP (AddP reg (LShiftL lreg scale)) off);
5194
5195 op_cost(10);
5196 format %{"[$reg + $off + $lreg << $scale]" %}
5197 interface(MEMORY_INTER) %{
5198 base($reg);
5199 index($lreg);
5200 scale($scale);
5201 disp($off);
5202 %}
5203 %}
5204
5205 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5206 operand indIndexScaleOffsetComp(rRegN src, immL32 off, r12RegL base) %{
5207 constraint(ALLOC_IN_RC(ptr_reg));
5208 match(AddP (DecodeN src base) off);
5209
5210 op_cost(10);
5211 format %{"[$base + $src << 3 + $off] (compressed)" %}
5212 interface(MEMORY_INTER) %{
5213 base($base);
5214 index($src);
5215 scale(0x3);
5216 disp($off);
5217 %}
5218 %}
5219
5220 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
5221 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
5222 %{
5223 constraint(ALLOC_IN_RC(ptr_reg));
5224 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5225 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
5226
5227 op_cost(10);
5228 format %{"[$reg + $off + $idx << $scale]" %}
5229 interface(MEMORY_INTER) %{
5230 base($reg);
5231 index($idx);
5232 scale($scale);
5233 disp($off);
5234 %}
5235 %}
5236
5237 //----------Special Memory Operands--------------------------------------------
5238 // Stack Slot Operand - This operand is used for loading and storing temporary
5239 // values on the stack where a match requires a value to
5240 // flow through memory.
5241 operand stackSlotP(sRegP reg)
5242 %{
5243 constraint(ALLOC_IN_RC(stack_slots));
5244 // No match rule because this operand is only generated in matching
5245
5246 format %{ "[$reg]" %}
5247 interface(MEMORY_INTER) %{
5248 base(0x4); // RSP
5249 index(0x4); // No Index
5250 scale(0x0); // No Scale
5251 disp($reg); // Stack Offset
5252 %}
5253 %}
5254
5255 operand stackSlotI(sRegI reg)
5256 %{
5257 constraint(ALLOC_IN_RC(stack_slots));
5258 // No match rule because this operand is only generated in matching
5259
5260 format %{ "[$reg]" %}
5261 interface(MEMORY_INTER) %{
5262 base(0x4); // RSP
5263 index(0x4); // No Index
5264 scale(0x0); // No Scale
5265 disp($reg); // Stack Offset
5266 %}
5267 %}
5268
5269 operand stackSlotF(sRegF reg)
5270 %{
5271 constraint(ALLOC_IN_RC(stack_slots));
5272 // No match rule because this operand is only generated in matching
5273
5274 format %{ "[$reg]" %}
5275 interface(MEMORY_INTER) %{
5276 base(0x4); // RSP
5277 index(0x4); // No Index
5278 scale(0x0); // No Scale
5279 disp($reg); // Stack Offset
5280 %}
5281 %}
5282
5283 operand stackSlotD(sRegD reg)
5284 %{
5285 constraint(ALLOC_IN_RC(stack_slots));
5286 // No match rule because this operand is only generated in matching
5287
5288 format %{ "[$reg]" %}
5289 interface(MEMORY_INTER) %{
5290 base(0x4); // RSP
5291 index(0x4); // No Index
5292 scale(0x0); // No Scale
5293 disp($reg); // Stack Offset
5294 %}
5295 %}
5296 operand stackSlotL(sRegL reg)
5297 %{
5298 constraint(ALLOC_IN_RC(stack_slots));
5299 // No match rule because this operand is only generated in matching
5300
5301 format %{ "[$reg]" %}
5302 interface(MEMORY_INTER) %{
5303 base(0x4); // RSP
5304 index(0x4); // No Index
5305 scale(0x0); // No Scale
5306 disp($reg); // Stack Offset
5307 %}
5308 %}
5309
5310 //----------Conditional Branch Operands----------------------------------------
5311 // Comparison Op - This is the operation of the comparison, and is limited to
5312 // the following set of codes:
5313 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5314 //
5315 // Other attributes of the comparison, such as unsignedness, are specified
5316 // by the comparison instruction that sets a condition code flags register.
5317 // That result is represented by a flags operand whose subtype is appropriate
5318 // to the unsignedness (etc.) of the comparison.
5319 //
5320 // Later, the instruction which matches both the Comparison Op (a Bool) and
5321 // the flags (produced by the Cmp) specifies the coding of the comparison op
5322 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5323
5324 // Comparision Code
5325 operand cmpOp()
5326 %{
5327 match(Bool);
5328
5329 format %{ "" %}
5330 interface(COND_INTER) %{
5331 equal(0x4);
5332 not_equal(0x5);
5333 less(0xC);
5334 greater_equal(0xD);
5335 less_equal(0xE);
5336 greater(0xF);
5337 %}
5338 %}
5339
5340 // Comparison Code, unsigned compare. Used by FP also, with
5341 // C2 (unordered) turned into GT or LT already. The other bits
5342 // C0 and C3 are turned into Carry & Zero flags.
5343 operand cmpOpU()
5344 %{
5345 match(Bool);
5346
5347 format %{ "" %}
5348 interface(COND_INTER) %{
5349 equal(0x4);
5350 not_equal(0x5);
5351 less(0x2);
5352 greater_equal(0x3);
5353 less_equal(0x6);
5354 greater(0x7);
5355 %}
5356 %}
5357
5358
5359 //----------OPERAND CLASSES----------------------------------------------------
5360 // Operand Classes are groups of operands that are used as to simplify
5361 // instruction definitions by not requiring the AD writer to specify seperate
5362 // instructions for every form of operand when the instruction accepts
5363 // multiple operand types with the same basic encoding and format. The classic
5364 // case of this is memory operands.
5365
5366 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
5367 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
5368 indIndexScaleOffsetComp);
5369
5370 //----------PIPELINE-----------------------------------------------------------
5371 // Rules which define the behavior of the target architectures pipeline.
5372 pipeline %{
5373
5374 //----------ATTRIBUTES---------------------------------------------------------
5375 attributes %{
5376 variable_size_instructions; // Fixed size instructions
5377 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5378 instruction_unit_size = 1; // An instruction is 1 bytes long
5379 instruction_fetch_unit_size = 16; // The processor fetches one line
5380 instruction_fetch_units = 1; // of 16 bytes
5381
5382 // List of nop instructions
5383 nops( MachNop );
5384 %}
5385
5386 //----------RESOURCES----------------------------------------------------------
5387 // Resources are the functional units available to the machine
5388
5389 // Generic P2/P3 pipeline
5390 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5391 // 3 instructions decoded per cycle.
5392 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5393 // 3 ALU op, only ALU0 handles mul instructions.
5394 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5395 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
5396 BR, FPU,
5397 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
5398
5399 //----------PIPELINE DESCRIPTION-----------------------------------------------
5400 // Pipeline Description specifies the stages in the machine's pipeline
5401
5402 // Generic P2/P3 pipeline
5403 pipe_desc(S0, S1, S2, S3, S4, S5);
5404
5405 //----------PIPELINE CLASSES---------------------------------------------------
5406 // Pipeline Classes describe the stages in which input and output are
5407 // referenced by the hardware pipeline.
5408
5409 // Naming convention: ialu or fpu
5410 // Then: _reg
5411 // Then: _reg if there is a 2nd register
5412 // Then: _long if it's a pair of instructions implementing a long
5413 // Then: _fat if it requires the big decoder
5414 // Or: _mem if it requires the big decoder and a memory unit.
5415
5416 // Integer ALU reg operation
5417 pipe_class ialu_reg(rRegI dst)
5418 %{
5419 single_instruction;
5420 dst : S4(write);
5421 dst : S3(read);
5422 DECODE : S0; // any decoder
5423 ALU : S3; // any alu
5424 %}
5425
5426 // Long ALU reg operation
5427 pipe_class ialu_reg_long(rRegL dst)
5428 %{
5429 instruction_count(2);
5430 dst : S4(write);
5431 dst : S3(read);
5432 DECODE : S0(2); // any 2 decoders
5433 ALU : S3(2); // both alus
5434 %}
5435
5436 // Integer ALU reg operation using big decoder
5437 pipe_class ialu_reg_fat(rRegI dst)
5438 %{
5439 single_instruction;
5440 dst : S4(write);
5441 dst : S3(read);
5442 D0 : S0; // big decoder only
5443 ALU : S3; // any alu
5444 %}
5445
5446 // Long ALU reg operation using big decoder
5447 pipe_class ialu_reg_long_fat(rRegL dst)
5448 %{
5449 instruction_count(2);
5450 dst : S4(write);
5451 dst : S3(read);
5452 D0 : S0(2); // big decoder only; twice
5453 ALU : S3(2); // any 2 alus
5454 %}
5455
5456 // Integer ALU reg-reg operation
5457 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
5458 %{
5459 single_instruction;
5460 dst : S4(write);
5461 src : S3(read);
5462 DECODE : S0; // any decoder
5463 ALU : S3; // any alu
5464 %}
5465
5466 // Long ALU reg-reg operation
5467 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
5468 %{
5469 instruction_count(2);
5470 dst : S4(write);
5471 src : S3(read);
5472 DECODE : S0(2); // any 2 decoders
5473 ALU : S3(2); // both alus
5474 %}
5475
5476 // Integer ALU reg-reg operation
5477 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
5478 %{
5479 single_instruction;
5480 dst : S4(write);
5481 src : S3(read);
5482 D0 : S0; // big decoder only
5483 ALU : S3; // any alu
5484 %}
5485
5486 // Long ALU reg-reg operation
5487 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
5488 %{
5489 instruction_count(2);
5490 dst : S4(write);
5491 src : S3(read);
5492 D0 : S0(2); // big decoder only; twice
5493 ALU : S3(2); // both alus
5494 %}
5495
5496 // Integer ALU reg-mem operation
5497 pipe_class ialu_reg_mem(rRegI dst, memory mem)
5498 %{
5499 single_instruction;
5500 dst : S5(write);
5501 mem : S3(read);
5502 D0 : S0; // big decoder only
5503 ALU : S4; // any alu
5504 MEM : S3; // any mem
5505 %}
5506
5507 // Integer mem operation (prefetch)
5508 pipe_class ialu_mem(memory mem)
5509 %{
5510 single_instruction;
5511 mem : S3(read);
5512 D0 : S0; // big decoder only
5513 MEM : S3; // any mem
5514 %}
5515
5516 // Integer Store to Memory
5517 pipe_class ialu_mem_reg(memory mem, rRegI src)
5518 %{
5519 single_instruction;
5520 mem : S3(read);
5521 src : S5(read);
5522 D0 : S0; // big decoder only
5523 ALU : S4; // any alu
5524 MEM : S3;
5525 %}
5526
5527 // // Long Store to Memory
5528 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
5529 // %{
5530 // instruction_count(2);
5531 // mem : S3(read);
5532 // src : S5(read);
5533 // D0 : S0(2); // big decoder only; twice
5534 // ALU : S4(2); // any 2 alus
5535 // MEM : S3(2); // Both mems
5536 // %}
5537
5538 // Integer Store to Memory
5539 pipe_class ialu_mem_imm(memory mem)
5540 %{
5541 single_instruction;
5542 mem : S3(read);
5543 D0 : S0; // big decoder only
5544 ALU : S4; // any alu
5545 MEM : S3;
5546 %}
5547
5548 // Integer ALU0 reg-reg operation
5549 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
5550 %{
5551 single_instruction;
5552 dst : S4(write);
5553 src : S3(read);
5554 D0 : S0; // Big decoder only
5555 ALU0 : S3; // only alu0
5556 %}
5557
5558 // Integer ALU0 reg-mem operation
5559 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
5560 %{
5561 single_instruction;
5562 dst : S5(write);
5563 mem : S3(read);
5564 D0 : S0; // big decoder only
5565 ALU0 : S4; // ALU0 only
5566 MEM : S3; // any mem
5567 %}
5568
5569 // Integer ALU reg-reg operation
5570 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
5571 %{
5572 single_instruction;
5573 cr : S4(write);
5574 src1 : S3(read);
5575 src2 : S3(read);
5576 DECODE : S0; // any decoder
5577 ALU : S3; // any alu
5578 %}
5579
5580 // Integer ALU reg-imm operation
5581 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
5582 %{
5583 single_instruction;
5584 cr : S4(write);
5585 src1 : S3(read);
5586 DECODE : S0; // any decoder
5587 ALU : S3; // any alu
5588 %}
5589
5590 // Integer ALU reg-mem operation
5591 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
5592 %{
5593 single_instruction;
5594 cr : S4(write);
5595 src1 : S3(read);
5596 src2 : S3(read);
5597 D0 : S0; // big decoder only
5598 ALU : S4; // any alu
5599 MEM : S3;
5600 %}
5601
5602 // Conditional move reg-reg
5603 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
5604 %{
5605 instruction_count(4);
5606 y : S4(read);
5607 q : S3(read);
5608 p : S3(read);
5609 DECODE : S0(4); // any decoder
5610 %}
5611
5612 // Conditional move reg-reg
5613 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
5614 %{
5615 single_instruction;
5616 dst : S4(write);
5617 src : S3(read);
5618 cr : S3(read);
5619 DECODE : S0; // any decoder
5620 %}
5621
5622 // Conditional move reg-mem
5623 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
5624 %{
5625 single_instruction;
5626 dst : S4(write);
5627 src : S3(read);
5628 cr : S3(read);
5629 DECODE : S0; // any decoder
5630 MEM : S3;
5631 %}
5632
5633 // Conditional move reg-reg long
5634 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
5635 %{
5636 single_instruction;
5637 dst : S4(write);
5638 src : S3(read);
5639 cr : S3(read);
5640 DECODE : S0(2); // any 2 decoders
5641 %}
5642
5643 // XXX
5644 // // Conditional move double reg-reg
5645 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
5646 // %{
5647 // single_instruction;
5648 // dst : S4(write);
5649 // src : S3(read);
5650 // cr : S3(read);
5651 // DECODE : S0; // any decoder
5652 // %}
5653
5654 // Float reg-reg operation
5655 pipe_class fpu_reg(regD dst)
5656 %{
5657 instruction_count(2);
5658 dst : S3(read);
5659 DECODE : S0(2); // any 2 decoders
5660 FPU : S3;
5661 %}
5662
5663 // Float reg-reg operation
5664 pipe_class fpu_reg_reg(regD dst, regD src)
5665 %{
5666 instruction_count(2);
5667 dst : S4(write);
5668 src : S3(read);
5669 DECODE : S0(2); // any 2 decoders
5670 FPU : S3;
5671 %}
5672
5673 // Float reg-reg operation
5674 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
5675 %{
5676 instruction_count(3);
5677 dst : S4(write);
5678 src1 : S3(read);
5679 src2 : S3(read);
5680 DECODE : S0(3); // any 3 decoders
5681 FPU : S3(2);
5682 %}
5683
5684 // Float reg-reg operation
5685 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
5686 %{
5687 instruction_count(4);
5688 dst : S4(write);
5689 src1 : S3(read);
5690 src2 : S3(read);
5691 src3 : S3(read);
5692 DECODE : S0(4); // any 3 decoders
5693 FPU : S3(2);
5694 %}
5695
5696 // Float reg-reg operation
5697 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
5698 %{
5699 instruction_count(4);
5700 dst : S4(write);
5701 src1 : S3(read);
5702 src2 : S3(read);
5703 src3 : S3(read);
5704 DECODE : S1(3); // any 3 decoders
5705 D0 : S0; // Big decoder only
5706 FPU : S3(2);
5707 MEM : S3;
5708 %}
5709
5710 // Float reg-mem operation
5711 pipe_class fpu_reg_mem(regD dst, memory mem)
5712 %{
5713 instruction_count(2);
5714 dst : S5(write);
5715 mem : S3(read);
5716 D0 : S0; // big decoder only
5717 DECODE : S1; // any decoder for FPU POP
5718 FPU : S4;
5719 MEM : S3; // any mem
5720 %}
5721
5722 // Float reg-mem operation
5723 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
5724 %{
5725 instruction_count(3);
5726 dst : S5(write);
5727 src1 : S3(read);
5728 mem : S3(read);
5729 D0 : S0; // big decoder only
5730 DECODE : S1(2); // any decoder for FPU POP
5731 FPU : S4;
5732 MEM : S3; // any mem
5733 %}
5734
5735 // Float mem-reg operation
5736 pipe_class fpu_mem_reg(memory mem, regD src)
5737 %{
5738 instruction_count(2);
5739 src : S5(read);
5740 mem : S3(read);
5741 DECODE : S0; // any decoder for FPU PUSH
5742 D0 : S1; // big decoder only
5743 FPU : S4;
5744 MEM : S3; // any mem
5745 %}
5746
5747 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
5748 %{
5749 instruction_count(3);
5750 src1 : S3(read);
5751 src2 : S3(read);
5752 mem : S3(read);
5753 DECODE : S0(2); // any decoder for FPU PUSH
5754 D0 : S1; // big decoder only
5755 FPU : S4;
5756 MEM : S3; // any mem
5757 %}
5758
5759 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
5760 %{
5761 instruction_count(3);
5762 src1 : S3(read);
5763 src2 : S3(read);
5764 mem : S4(read);
5765 DECODE : S0; // any decoder for FPU PUSH
5766 D0 : S0(2); // big decoder only
5767 FPU : S4;
5768 MEM : S3(2); // any mem
5769 %}
5770
5771 pipe_class fpu_mem_mem(memory dst, memory src1)
5772 %{
5773 instruction_count(2);
5774 src1 : S3(read);
5775 dst : S4(read);
5776 D0 : S0(2); // big decoder only
5777 MEM : S3(2); // any mem
5778 %}
5779
5780 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
5781 %{
5782 instruction_count(3);
5783 src1 : S3(read);
5784 src2 : S3(read);
5785 dst : S4(read);
5786 D0 : S0(3); // big decoder only
5787 FPU : S4;
5788 MEM : S3(3); // any mem
5789 %}
5790
5791 pipe_class fpu_mem_reg_con(memory mem, regD src1)
5792 %{
5793 instruction_count(3);
5794 src1 : S4(read);
5795 mem : S4(read);
5796 DECODE : S0; // any decoder for FPU PUSH
5797 D0 : S0(2); // big decoder only
5798 FPU : S4;
5799 MEM : S3(2); // any mem
5800 %}
5801
5802 // Float load constant
5803 pipe_class fpu_reg_con(regD dst)
5804 %{
5805 instruction_count(2);
5806 dst : S5(write);
5807 D0 : S0; // big decoder only for the load
5808 DECODE : S1; // any decoder for FPU POP
5809 FPU : S4;
5810 MEM : S3; // any mem
5811 %}
5812
5813 // Float load constant
5814 pipe_class fpu_reg_reg_con(regD dst, regD src)
5815 %{
5816 instruction_count(3);
5817 dst : S5(write);
5818 src : S3(read);
5819 D0 : S0; // big decoder only for the load
5820 DECODE : S1(2); // any decoder for FPU POP
5821 FPU : S4;
5822 MEM : S3; // any mem
5823 %}
5824
5825 // UnConditional branch
5826 pipe_class pipe_jmp(label labl)
5827 %{
5828 single_instruction;
5829 BR : S3;
5830 %}
5831
5832 // Conditional branch
5833 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
5834 %{
5835 single_instruction;
5836 cr : S1(read);
5837 BR : S3;
5838 %}
5839
5840 // Allocation idiom
5841 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
5842 %{
5843 instruction_count(1); force_serialization;
5844 fixed_latency(6);
5845 heap_ptr : S3(read);
5846 DECODE : S0(3);
5847 D0 : S2;
5848 MEM : S3;
5849 ALU : S3(2);
5850 dst : S5(write);
5851 BR : S5;
5852 %}
5853
5854 // Generic big/slow expanded idiom
5855 pipe_class pipe_slow()
5856 %{
5857 instruction_count(10); multiple_bundles; force_serialization;
5858 fixed_latency(100);
5859 D0 : S0(2);
5860 MEM : S3(2);
5861 %}
5862
5863 // The real do-nothing guy
5864 pipe_class empty()
5865 %{
5866 instruction_count(0);
5867 %}
5868
5869 // Define the class for the Nop node
5870 define
5871 %{
5872 MachNop = empty;
5873 %}
5874
5875 %}
5876
5877 //----------INSTRUCTIONS-------------------------------------------------------
5878 //
5879 // match -- States which machine-independent subtree may be replaced
5880 // by this instruction.
5881 // ins_cost -- The estimated cost of this instruction is used by instruction
5882 // selection to identify a minimum cost tree of machine
5883 // instructions that matches a tree of machine-independent
5884 // instructions.
5885 // format -- A string providing the disassembly for this instruction.
5886 // The value of an instruction's operand may be inserted
5887 // by referring to it with a '$' prefix.
5888 // opcode -- Three instruction opcodes may be provided. These are referred
5889 // to within an encode class as $primary, $secondary, and $tertiary
5890 // rrspectively. The primary opcode is commonly used to
5891 // indicate the type of machine instruction, while secondary
5892 // and tertiary are often used for prefix options or addressing
5893 // modes.
5894 // ins_encode -- A list of encode classes with parameters. The encode class
5895 // name must have been defined in an 'enc_class' specification
5896 // in the encode section of the architecture description.
5897
5898
5899 //----------Load/Store/Move Instructions---------------------------------------
5900 //----------Load Instructions--------------------------------------------------
5901
5902 // Load Byte (8 bit signed)
5903 instruct loadB(rRegI dst, memory mem)
5904 %{
5905 match(Set dst (LoadB mem));
5906
5907 ins_cost(125);
5908 format %{ "movsbl $dst, $mem\t# byte" %}
5909 opcode(0x0F, 0xBE);
5910 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5911 ins_pipe(ialu_reg_mem);
5912 %}
5913
5914 // Load Byte (8 bit signed) into long
5915 // instruct loadB2L(rRegL dst, memory mem)
5916 // %{
5917 // match(Set dst (ConvI2L (LoadB mem)));
5918
5919 // ins_cost(125);
5920 // format %{ "movsbq $dst, $mem\t# byte -> long" %}
5921 // opcode(0x0F, 0xBE);
5922 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5923 // ins_pipe(ialu_reg_mem);
5924 // %}
5925
5926 // Load Byte (8 bit UNsigned)
5927 instruct loadUB(rRegI dst, memory mem, immI_255 bytemask)
5928 %{
5929 match(Set dst (AndI (LoadB mem) bytemask));
5930
5931 ins_cost(125);
5932 format %{ "movzbl $dst, $mem\t# ubyte" %}
5933 opcode(0x0F, 0xB6);
5934 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5935 ins_pipe(ialu_reg_mem);
5936 %}
5937
5938 // Load Byte (8 bit UNsigned) into long
5939 // instruct loadUB2L(rRegL dst, memory mem, immI_255 bytemask)
5940 // %{
5941 // match(Set dst (ConvI2L (AndI (LoadB mem) bytemask)));
5942
5943 // ins_cost(125);
5944 // format %{ "movzbl $dst, $mem\t# ubyte -> long" %}
5945 // opcode(0x0F, 0xB6);
5946 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5947 // ins_pipe(ialu_reg_mem);
5948 // %}
5949
5950 // Load Short (16 bit signed)
5951 instruct loadS(rRegI dst, memory mem)
5952 %{
5953 match(Set dst (LoadS mem));
5954
5955 ins_cost(125); // XXX
5956 format %{ "movswl $dst, $mem\t# short" %}
5957 opcode(0x0F, 0xBF);
5958 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5959 ins_pipe(ialu_reg_mem);
5960 %}
5961
5962 // Load Short (16 bit signed) into long
5963 // instruct loadS2L(rRegL dst, memory mem)
5964 // %{
5965 // match(Set dst (ConvI2L (LoadS mem)));
5966
5967 // ins_cost(125); // XXX
5968 // format %{ "movswq $dst, $mem\t# short -> long" %}
5969 // opcode(0x0F, 0xBF);
5970 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5971 // ins_pipe(ialu_reg_mem);
5972 // %}
5973
5974 // Load Char (16 bit UNsigned)
5975 instruct loadC(rRegI dst, memory mem)
5976 %{
5977 match(Set dst (LoadC mem));
5978
5979 ins_cost(125);
5980 format %{ "movzwl $dst, $mem\t# char" %}
5981 opcode(0x0F, 0xB7);
5982 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5983 ins_pipe(ialu_reg_mem);
5984 %}
5985
5986 // Load Char (16 bit UNsigned) into long
5987 // instruct loadC2L(rRegL dst, memory mem)
5988 // %{
5989 // match(Set dst (ConvI2L (LoadC mem)));
5990
5991 // ins_cost(125);
5992 // format %{ "movzwl $dst, $mem\t# char -> long" %}
5993 // opcode(0x0F, 0xB7);
5994 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
5995 // ins_pipe(ialu_reg_mem);
5996 // %}
5997
5998 // Load Integer
5999 instruct loadI(rRegI dst, memory mem)
6000 %{
6001 match(Set dst (LoadI mem));
6002
6003 ins_cost(125); // XXX
6004 format %{ "movl $dst, $mem\t# int" %}
6005 opcode(0x8B);
6006 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6007 ins_pipe(ialu_reg_mem);
6008 %}
6009
6010 // Load Long
6011 instruct loadL(rRegL dst, memory mem)
6012 %{
6013 match(Set dst (LoadL mem));
6014
6015 ins_cost(125); // XXX
6016 format %{ "movq $dst, $mem\t# long" %}
6017 opcode(0x8B);
6018 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6019 ins_pipe(ialu_reg_mem); // XXX
6020 %}
6021
6022 // Load Range
6023 instruct loadRange(rRegI dst, memory mem)
6024 %{
6025 match(Set dst (LoadRange mem));
6026
6027 ins_cost(125); // XXX
6028 format %{ "movl $dst, $mem\t# range" %}
6029 opcode(0x8B);
6030 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6031 ins_pipe(ialu_reg_mem);
6032 %}
6033
6034 // Load Pointer
6035 instruct loadP(rRegP dst, memory mem)
6036 %{
6037 match(Set dst (LoadP mem));
6038
6039 ins_cost(125); // XXX
6040 format %{ "movq $dst, $mem\t# ptr" %}
6041 opcode(0x8B);
6042 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6043 ins_pipe(ialu_reg_mem); // XXX
6044 %}
6045
6046 // Load Compressed Pointer
6047 instruct loadN(rRegN dst, memory mem, rFlagsReg cr)
6048 %{
6049 match(Set dst (LoadN mem));
6050 effect(KILL cr);
6051
6052 ins_cost(125); // XXX
6053 format %{ "movl $dst, $mem\t# compressed ptr" %}
6054 ins_encode %{
6055 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6056 Register dst = as_Register($dst$$reg);
6057 __ movl(dst, addr);
6058 %}
6059 ins_pipe(ialu_reg_mem); // XXX
6060 %}
6061
6062
6063 // Load Klass Pointer
6064 instruct loadKlass(rRegP dst, memory mem)
6065 %{
6066 match(Set dst (LoadKlass mem));
6067 predicate(!n->in(MemNode::Address)->bottom_type()->is_narrow());
6068
6069 ins_cost(125); // XXX
6070 format %{ "movq $dst, $mem\t# class" %}
6071 opcode(0x8B);
6072 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6073 ins_pipe(ialu_reg_mem); // XXX
6074 %}
6075
6076 // Load Klass Pointer
6077 instruct loadKlassComp(rRegP dst, memory mem)
6078 %{
6079 match(Set dst (LoadKlass mem));
6080 predicate(n->in(MemNode::Address)->bottom_type()->is_narrow());
6081
6082 ins_cost(125); // XXX
6083 format %{ "movl $dst, $mem\t# compressed class\n\t"
6084 "decode_heap_oop $dst,$dst" %}
6085 ins_encode %{
6086 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6087 Register dst = as_Register($dst$$reg);
6088 __ movl(dst, addr);
6089 // klass is never null in the header but this is generated for all
6090 // klass loads not just the _klass field in the header.
6091 __ decode_heap_oop(dst);
6092 %}
6093 ins_pipe(ialu_reg_mem); // XXX
6094 %}
6095
6096 // Load Float
6097 instruct loadF(regF dst, memory mem)
6098 %{
6099 match(Set dst (LoadF mem));
6100
6101 ins_cost(145); // XXX
6102 format %{ "movss $dst, $mem\t# float" %}
6103 opcode(0xF3, 0x0F, 0x10);
6104 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6105 ins_pipe(pipe_slow); // XXX
6106 %}
6107
6108 // Load Double
6109 instruct loadD_partial(regD dst, memory mem)
6110 %{
6111 predicate(!UseXmmLoadAndClearUpper);
6112 match(Set dst (LoadD mem));
6113
6114 ins_cost(145); // XXX
6115 format %{ "movlpd $dst, $mem\t# double" %}
6116 opcode(0x66, 0x0F, 0x12);
6117 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6118 ins_pipe(pipe_slow); // XXX
6119 %}
6120
6121 instruct loadD(regD dst, memory mem)
6122 %{
6123 predicate(UseXmmLoadAndClearUpper);
6124 match(Set dst (LoadD mem));
6125
6126 ins_cost(145); // XXX
6127 format %{ "movsd $dst, $mem\t# double" %}
6128 opcode(0xF2, 0x0F, 0x10);
6129 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6130 ins_pipe(pipe_slow); // XXX
6131 %}
6132
6133 // Load Aligned Packed Byte to XMM register
6134 instruct loadA8B(regD dst, memory mem) %{
6135 match(Set dst (Load8B mem));
6136 ins_cost(125);
6137 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6138 ins_encode( movq_ld(dst, mem));
6139 ins_pipe( pipe_slow );
6140 %}
6141
6142 // Load Aligned Packed Short to XMM register
6143 instruct loadA4S(regD dst, memory mem) %{
6144 match(Set dst (Load4S mem));
6145 ins_cost(125);
6146 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6147 ins_encode( movq_ld(dst, mem));
6148 ins_pipe( pipe_slow );
6149 %}
6150
6151 // Load Aligned Packed Char to XMM register
6152 instruct loadA4C(regD dst, memory mem) %{
6153 match(Set dst (Load4C mem));
6154 ins_cost(125);
6155 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6156 ins_encode( movq_ld(dst, mem));
6157 ins_pipe( pipe_slow );
6158 %}
6159
6160 // Load Aligned Packed Integer to XMM register
6161 instruct load2IU(regD dst, memory mem) %{
6162 match(Set dst (Load2I mem));
6163 ins_cost(125);
6164 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6165 ins_encode( movq_ld(dst, mem));
6166 ins_pipe( pipe_slow );
6167 %}
6168
6169 // Load Aligned Packed Single to XMM
6170 instruct loadA2F(regD dst, memory mem) %{
6171 match(Set dst (Load2F mem));
6172 ins_cost(145);
6173 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6174 ins_encode( movq_ld(dst, mem));
6175 ins_pipe( pipe_slow );
6176 %}
6177
6178 // Load Effective Address
6179 instruct leaP8(rRegP dst, indOffset8 mem)
6180 %{
6181 match(Set dst mem);
6182
6183 ins_cost(110); // XXX
6184 format %{ "leaq $dst, $mem\t# ptr 8" %}
6185 opcode(0x8D);
6186 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6187 ins_pipe(ialu_reg_reg_fat);
6188 %}
6189
6190 instruct leaP32(rRegP dst, indOffset32 mem)
6191 %{
6192 match(Set dst mem);
6193
6194 ins_cost(110);
6195 format %{ "leaq $dst, $mem\t# ptr 32" %}
6196 opcode(0x8D);
6197 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6198 ins_pipe(ialu_reg_reg_fat);
6199 %}
6200
6201 // instruct leaPIdx(rRegP dst, indIndex mem)
6202 // %{
6203 // match(Set dst mem);
6204
6205 // ins_cost(110);
6206 // format %{ "leaq $dst, $mem\t# ptr idx" %}
6207 // opcode(0x8D);
6208 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6209 // ins_pipe(ialu_reg_reg_fat);
6210 // %}
6211
6212 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
6213 %{
6214 match(Set dst mem);
6215
6216 ins_cost(110);
6217 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
6218 opcode(0x8D);
6219 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6220 ins_pipe(ialu_reg_reg_fat);
6221 %}
6222
6223 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
6224 %{
6225 match(Set dst mem);
6226
6227 ins_cost(110);
6228 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
6229 opcode(0x8D);
6230 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6231 ins_pipe(ialu_reg_reg_fat);
6232 %}
6233
6234 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
6235 %{
6236 match(Set dst mem);
6237
6238 ins_cost(110);
6239 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
6240 opcode(0x8D);
6241 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6242 ins_pipe(ialu_reg_reg_fat);
6243 %}
6244
6245 instruct loadConI(rRegI dst, immI src)
6246 %{
6247 match(Set dst src);
6248
6249 format %{ "movl $dst, $src\t# int" %}
6250 ins_encode(load_immI(dst, src));
6251 ins_pipe(ialu_reg_fat); // XXX
6252 %}
6253
6254 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
6255 %{
6256 match(Set dst src);
6257 effect(KILL cr);
6258
6259 ins_cost(50);
6260 format %{ "xorl $dst, $dst\t# int" %}
6261 opcode(0x33); /* + rd */
6262 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6263 ins_pipe(ialu_reg);
6264 %}
6265
6266 instruct loadConL(rRegL dst, immL src)
6267 %{
6268 match(Set dst src);
6269
6270 ins_cost(150);
6271 format %{ "movq $dst, $src\t# long" %}
6272 ins_encode(load_immL(dst, src));
6273 ins_pipe(ialu_reg);
6274 %}
6275
6276 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
6277 %{
6278 match(Set dst src);
6279 effect(KILL cr);
6280
6281 ins_cost(50);
6282 format %{ "xorl $dst, $dst\t# long" %}
6283 opcode(0x33); /* + rd */
6284 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6285 ins_pipe(ialu_reg); // XXX
6286 %}
6287
6288 instruct loadConUL32(rRegL dst, immUL32 src)
6289 %{
6290 match(Set dst src);
6291
6292 ins_cost(60);
6293 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
6294 ins_encode(load_immUL32(dst, src));
6295 ins_pipe(ialu_reg);
6296 %}
6297
6298 instruct loadConL32(rRegL dst, immL32 src)
6299 %{
6300 match(Set dst src);
6301
6302 ins_cost(70);
6303 format %{ "movq $dst, $src\t# long (32-bit)" %}
6304 ins_encode(load_immL32(dst, src));
6305 ins_pipe(ialu_reg);
6306 %}
6307
6308 instruct loadConP(rRegP dst, immP src)
6309 %{
6310 match(Set dst src);
6311
6312 format %{ "movq $dst, $src\t# ptr" %}
6313 ins_encode(load_immP(dst, src));
6314 ins_pipe(ialu_reg_fat); // XXX
6315 %}
6316
6317 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
6318 %{
6319 match(Set dst src);
6320 effect(KILL cr);
6321
6322 ins_cost(50);
6323 format %{ "xorl $dst, $dst\t# ptr" %}
6324 opcode(0x33); /* + rd */
6325 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6326 ins_pipe(ialu_reg);
6327 %}
6328
6329 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
6330 %{
6331 match(Set dst src);
6332 effect(KILL cr);
6333
6334 ins_cost(60);
6335 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6336 ins_encode(load_immP31(dst, src));
6337 ins_pipe(ialu_reg);
6338 %}
6339
6340 instruct loadConF(regF dst, immF src)
6341 %{
6342 match(Set dst src);
6343 ins_cost(125);
6344
6345 format %{ "movss $dst, [$src]" %}
6346 ins_encode(load_conF(dst, src));
6347 ins_pipe(pipe_slow);
6348 %}
6349
6350 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6351 match(Set dst src);
6352 effect(KILL cr);
6353 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6354 ins_encode %{
6355 Register dst = $dst$$Register;
6356 __ xorq(dst, dst);
6357 %}
6358 ins_pipe(ialu_reg);
6359 %}
6360
6361 instruct loadConN(rRegN dst, immN src) %{
6362 match(Set dst src);
6363
6364 ins_cost(125);
6365 format %{ "movq $dst, $src\t# compressed ptr\n\t"
6366 "encode_heap_oop_not_null $dst,$dst" %}
6367 ins_encode %{
6368 address con = (address)$src$$constant;
6369 Register dst = $dst$$Register;
6370 if (con == NULL) {
6371 ShouldNotReachHere();
6372 } else {
6373 __ movoop(dst, (jobject)$src$$constant);
6374 __ encode_heap_oop_not_null(dst);
6375 }
6376 %}
6377 ins_pipe(ialu_reg_fat); // XXX
6378 %}
6379
6380 instruct loadConF0(regF dst, immF0 src)
6381 %{
6382 match(Set dst src);
6383 ins_cost(100);
6384
6385 format %{ "xorps $dst, $dst\t# float 0.0" %}
6386 opcode(0x0F, 0x57);
6387 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
6388 ins_pipe(pipe_slow);
6389 %}
6390
6391 // Use the same format since predicate() can not be used here.
6392 instruct loadConD(regD dst, immD src)
6393 %{
6394 match(Set dst src);
6395 ins_cost(125);
6396
6397 format %{ "movsd $dst, [$src]" %}
6398 ins_encode(load_conD(dst, src));
6399 ins_pipe(pipe_slow);
6400 %}
6401
6402 instruct loadConD0(regD dst, immD0 src)
6403 %{
6404 match(Set dst src);
6405 ins_cost(100);
6406
6407 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6408 opcode(0x66, 0x0F, 0x57);
6409 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
6410 ins_pipe(pipe_slow);
6411 %}
6412
6413 instruct loadSSI(rRegI dst, stackSlotI src)
6414 %{
6415 match(Set dst src);
6416
6417 ins_cost(125);
6418 format %{ "movl $dst, $src\t# int stk" %}
6419 opcode(0x8B);
6420 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6421 ins_pipe(ialu_reg_mem);
6422 %}
6423
6424 instruct loadSSL(rRegL dst, stackSlotL src)
6425 %{
6426 match(Set dst src);
6427
6428 ins_cost(125);
6429 format %{ "movq $dst, $src\t# long stk" %}
6430 opcode(0x8B);
6431 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6432 ins_pipe(ialu_reg_mem);
6433 %}
6434
6435 instruct loadSSP(rRegP dst, stackSlotP src)
6436 %{
6437 match(Set dst src);
6438
6439 ins_cost(125);
6440 format %{ "movq $dst, $src\t# ptr stk" %}
6441 opcode(0x8B);
6442 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6443 ins_pipe(ialu_reg_mem);
6444 %}
6445
6446 instruct loadSSF(regF dst, stackSlotF src)
6447 %{
6448 match(Set dst src);
6449
6450 ins_cost(125);
6451 format %{ "movss $dst, $src\t# float stk" %}
6452 opcode(0xF3, 0x0F, 0x10);
6453 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
6454 ins_pipe(pipe_slow); // XXX
6455 %}
6456
6457 // Use the same format since predicate() can not be used here.
6458 instruct loadSSD(regD dst, stackSlotD src)
6459 %{
6460 match(Set dst src);
6461
6462 ins_cost(125);
6463 format %{ "movsd $dst, $src\t# double stk" %}
6464 ins_encode %{
6465 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6466 %}
6467 ins_pipe(pipe_slow); // XXX
6468 %}
6469
6470 // Prefetch instructions.
6471 // Must be safe to execute with invalid address (cannot fault).
6472
6473 instruct prefetchr( memory mem ) %{
6474 predicate(ReadPrefetchInstr==3);
6475 match(PrefetchRead mem);
6476 ins_cost(125);
6477
6478 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6479 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
6480 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6481 ins_pipe(ialu_mem);
6482 %}
6483
6484 instruct prefetchrNTA( memory mem ) %{
6485 predicate(ReadPrefetchInstr==0);
6486 match(PrefetchRead mem);
6487 ins_cost(125);
6488
6489 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6490 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6491 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6492 ins_pipe(ialu_mem);
6493 %}
6494
6495 instruct prefetchrT0( memory mem ) %{
6496 predicate(ReadPrefetchInstr==1);
6497 match(PrefetchRead mem);
6498 ins_cost(125);
6499
6500 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6501 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6502 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6503 ins_pipe(ialu_mem);
6504 %}
6505
6506 instruct prefetchrT2( memory mem ) %{
6507 predicate(ReadPrefetchInstr==2);
6508 match(PrefetchRead mem);
6509 ins_cost(125);
6510
6511 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6512 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6513 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6514 ins_pipe(ialu_mem);
6515 %}
6516
6517 instruct prefetchw( memory mem ) %{
6518 predicate(AllocatePrefetchInstr==3);
6519 match(PrefetchWrite mem);
6520 ins_cost(125);
6521
6522 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
6523 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6524 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6525 ins_pipe(ialu_mem);
6526 %}
6527
6528 instruct prefetchwNTA( memory mem ) %{
6529 predicate(AllocatePrefetchInstr==0);
6530 match(PrefetchWrite mem);
6531 ins_cost(125);
6532
6533 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6534 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6535 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6536 ins_pipe(ialu_mem);
6537 %}
6538
6539 instruct prefetchwT0( memory mem ) %{
6540 predicate(AllocatePrefetchInstr==1);
6541 match(PrefetchWrite mem);
6542 ins_cost(125);
6543
6544 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
6545 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6546 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6547 ins_pipe(ialu_mem);
6548 %}
6549
6550 instruct prefetchwT2( memory mem ) %{
6551 predicate(AllocatePrefetchInstr==2);
6552 match(PrefetchWrite mem);
6553 ins_cost(125);
6554
6555 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
6556 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6557 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6558 ins_pipe(ialu_mem);
6559 %}
6560
6561 //----------Store Instructions-------------------------------------------------
6562
6563 // Store Byte
6564 instruct storeB(memory mem, rRegI src)
6565 %{
6566 match(Set mem (StoreB mem src));
6567
6568 ins_cost(125); // XXX
6569 format %{ "movb $mem, $src\t# byte" %}
6570 opcode(0x88);
6571 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6572 ins_pipe(ialu_mem_reg);
6573 %}
6574
6575 // Store Char/Short
6576 instruct storeC(memory mem, rRegI src)
6577 %{
6578 match(Set mem (StoreC mem src));
6579
6580 ins_cost(125); // XXX
6581 format %{ "movw $mem, $src\t# char/short" %}
6582 opcode(0x89);
6583 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6584 ins_pipe(ialu_mem_reg);
6585 %}
6586
6587 // Store Integer
6588 instruct storeI(memory mem, rRegI src)
6589 %{
6590 match(Set mem (StoreI mem src));
6591
6592 ins_cost(125); // XXX
6593 format %{ "movl $mem, $src\t# int" %}
6594 opcode(0x89);
6595 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6596 ins_pipe(ialu_mem_reg);
6597 %}
6598
6599 // Store Long
6600 instruct storeL(memory mem, rRegL src)
6601 %{
6602 match(Set mem (StoreL mem src));
6603
6604 ins_cost(125); // XXX
6605 format %{ "movq $mem, $src\t# long" %}
6606 opcode(0x89);
6607 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6608 ins_pipe(ialu_mem_reg); // XXX
6609 %}
6610
6611 // Store Pointer
6612 instruct storeP(memory mem, any_RegP src)
6613 %{
6614 match(Set mem (StoreP mem src));
6615
6616 ins_cost(125); // XXX
6617 format %{ "movq $mem, $src\t# ptr" %}
6618 opcode(0x89);
6619 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
6620 ins_pipe(ialu_mem_reg);
6621 %}
6622
6623 // Store NULL Pointer, mark word, or other simple pointer constant.
6624 instruct storeImmP(memory mem, immP31 src)
6625 %{
6626 match(Set mem (StoreP mem src));
6627
6628 ins_cost(125); // XXX
6629 format %{ "movq $mem, $src\t# ptr" %}
6630 opcode(0xC7); /* C7 /0 */
6631 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6632 ins_pipe(ialu_mem_imm);
6633 %}
6634
6635 // Store Compressed Pointer
6636 instruct storeN(memory mem, rRegN src, rFlagsReg cr)
6637 %{
6638 match(Set mem (StoreN mem src));
6639 effect(KILL cr);
6640
6641 ins_cost(125); // XXX
6642 format %{ "movl $mem, $src\t# ptr" %}
6643 ins_encode %{
6644 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6645 Register src = as_Register($src$$reg);
6646 __ movl(addr, src);
6647 %}
6648 ins_pipe(ialu_mem_reg);
6649 %}
6650
6651 // Store Integer Immediate
6652 instruct storeImmI(memory mem, immI src)
6653 %{
6654 match(Set mem (StoreI mem src));
6655
6656 ins_cost(150);
6657 format %{ "movl $mem, $src\t# int" %}
6658 opcode(0xC7); /* C7 /0 */
6659 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6660 ins_pipe(ialu_mem_imm);
6661 %}
6662
6663 // Store Long Immediate
6664 instruct storeImmL(memory mem, immL32 src)
6665 %{
6666 match(Set mem (StoreL mem src));
6667
6668 ins_cost(150);
6669 format %{ "movq $mem, $src\t# long" %}
6670 opcode(0xC7); /* C7 /0 */
6671 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
6672 ins_pipe(ialu_mem_imm);
6673 %}
6674
6675 // Store Short/Char Immediate
6676 instruct storeImmI16(memory mem, immI16 src)
6677 %{
6678 predicate(UseStoreImmI16);
6679 match(Set mem (StoreC mem src));
6680
6681 ins_cost(150);
6682 format %{ "movw $mem, $src\t# short/char" %}
6683 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6684 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
6685 ins_pipe(ialu_mem_imm);
6686 %}
6687
6688 // Store Byte Immediate
6689 instruct storeImmB(memory mem, immI8 src)
6690 %{
6691 match(Set mem (StoreB mem src));
6692
6693 ins_cost(150); // XXX
6694 format %{ "movb $mem, $src\t# byte" %}
6695 opcode(0xC6); /* C6 /0 */
6696 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6697 ins_pipe(ialu_mem_imm);
6698 %}
6699
6700 // Store Aligned Packed Byte XMM register to memory
6701 instruct storeA8B(memory mem, regD src) %{
6702 match(Set mem (Store8B mem src));
6703 ins_cost(145);
6704 format %{ "MOVQ $mem,$src\t! packed8B" %}
6705 ins_encode( movq_st(mem, src));
6706 ins_pipe( pipe_slow );
6707 %}
6708
6709 // Store Aligned Packed Char/Short XMM register to memory
6710 instruct storeA4C(memory mem, regD src) %{
6711 match(Set mem (Store4C mem src));
6712 ins_cost(145);
6713 format %{ "MOVQ $mem,$src\t! packed4C" %}
6714 ins_encode( movq_st(mem, src));
6715 ins_pipe( pipe_slow );
6716 %}
6717
6718 // Store Aligned Packed Integer XMM register to memory
6719 instruct storeA2I(memory mem, regD src) %{
6720 match(Set mem (Store2I mem src));
6721 ins_cost(145);
6722 format %{ "MOVQ $mem,$src\t! packed2I" %}
6723 ins_encode( movq_st(mem, src));
6724 ins_pipe( pipe_slow );
6725 %}
6726
6727 // Store CMS card-mark Immediate
6728 instruct storeImmCM0(memory mem, immI0 src)
6729 %{
6730 match(Set mem (StoreCM mem src));
6731
6732 ins_cost(150); // XXX
6733 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6734 opcode(0xC6); /* C6 /0 */
6735 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
6736 ins_pipe(ialu_mem_imm);
6737 %}
6738
6739 // Store Aligned Packed Single Float XMM register to memory
6740 instruct storeA2F(memory mem, regD src) %{
6741 match(Set mem (Store2F mem src));
6742 ins_cost(145);
6743 format %{ "MOVQ $mem,$src\t! packed2F" %}
6744 ins_encode( movq_st(mem, src));
6745 ins_pipe( pipe_slow );
6746 %}
6747
6748 // Store Float
6749 instruct storeF(memory mem, regF src)
6750 %{
6751 match(Set mem (StoreF mem src));
6752
6753 ins_cost(95); // XXX
6754 format %{ "movss $mem, $src\t# float" %}
6755 opcode(0xF3, 0x0F, 0x11);
6756 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
6757 ins_pipe(pipe_slow); // XXX
6758 %}
6759
6760 // Store immediate Float value (it is faster than store from XMM register)
6761 instruct storeF_imm(memory mem, immF src)
6762 %{
6763 match(Set mem (StoreF mem src));
6764
6765 ins_cost(50);
6766 format %{ "movl $mem, $src\t# float" %}
6767 opcode(0xC7); /* C7 /0 */
6768 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6769 ins_pipe(ialu_mem_imm);
6770 %}
6771
6772 // Store Double
6773 instruct storeD(memory mem, regD src)
6774 %{
6775 match(Set mem (StoreD mem src));
6776
6777 ins_cost(95); // XXX
6778 format %{ "movsd $mem, $src\t# double" %}
6779 opcode(0xF2, 0x0F, 0x11);
6780 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
6781 ins_pipe(pipe_slow); // XXX
6782 %}
6783
6784 // Store immediate double 0.0 (it is faster than store from XMM register)
6785 instruct storeD0_imm(memory mem, immD0 src)
6786 %{
6787 match(Set mem (StoreD mem src));
6788
6789 ins_cost(50);
6790 format %{ "movq $mem, $src\t# double 0." %}
6791 opcode(0xC7); /* C7 /0 */
6792 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
6793 ins_pipe(ialu_mem_imm);
6794 %}
6795
6796 instruct storeSSI(stackSlotI dst, rRegI src)
6797 %{
6798 match(Set dst src);
6799
6800 ins_cost(100);
6801 format %{ "movl $dst, $src\t# int stk" %}
6802 opcode(0x89);
6803 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6804 ins_pipe( ialu_mem_reg );
6805 %}
6806
6807 instruct storeSSL(stackSlotL dst, rRegL src)
6808 %{
6809 match(Set dst src);
6810
6811 ins_cost(100);
6812 format %{ "movq $dst, $src\t# long stk" %}
6813 opcode(0x89);
6814 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6815 ins_pipe(ialu_mem_reg);
6816 %}
6817
6818 instruct storeSSP(stackSlotP dst, rRegP src)
6819 %{
6820 match(Set dst src);
6821
6822 ins_cost(100);
6823 format %{ "movq $dst, $src\t# ptr stk" %}
6824 opcode(0x89);
6825 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6826 ins_pipe(ialu_mem_reg);
6827 %}
6828
6829 instruct storeSSF(stackSlotF dst, regF src)
6830 %{
6831 match(Set dst src);
6832
6833 ins_cost(95); // XXX
6834 format %{ "movss $dst, $src\t# float stk" %}
6835 opcode(0xF3, 0x0F, 0x11);
6836 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
6837 ins_pipe(pipe_slow); // XXX
6838 %}
6839
6840 instruct storeSSD(stackSlotD dst, regD src)
6841 %{
6842 match(Set dst src);
6843
6844 ins_cost(95); // XXX
6845 format %{ "movsd $dst, $src\t# double stk" %}
6846 opcode(0xF2, 0x0F, 0x11);
6847 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
6848 ins_pipe(pipe_slow); // XXX
6849 %}
6850
6851 //----------BSWAP Instructions-------------------------------------------------
6852 instruct bytes_reverse_int(rRegI dst) %{
6853 match(Set dst (ReverseBytesI dst));
6854
6855 format %{ "bswapl $dst" %}
6856 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6857 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6858 ins_pipe( ialu_reg );
6859 %}
6860
6861 instruct bytes_reverse_long(rRegL dst) %{
6862 match(Set dst (ReverseBytesL dst));
6863
6864 format %{ "bswapq $dst" %}
6865
6866 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6867 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6868 ins_pipe( ialu_reg);
6869 %}
6870
6871 instruct loadI_reversed(rRegI dst, memory src) %{
6872 match(Set dst (ReverseBytesI (LoadI src)));
6873
6874 format %{ "bswap_movl $dst, $src" %}
6875 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
6876 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst));
6877 ins_pipe( ialu_reg_mem );
6878 %}
6879
6880 instruct loadL_reversed(rRegL dst, memory src) %{
6881 match(Set dst (ReverseBytesL (LoadL src)));
6882
6883 format %{ "bswap_movq $dst, $src" %}
6884 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
6885 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst));
6886 ins_pipe( ialu_reg_mem );
6887 %}
6888
6889 instruct storeI_reversed(memory dst, rRegI src) %{
6890 match(Set dst (StoreI dst (ReverseBytesI src)));
6891
6892 format %{ "movl_bswap $dst, $src" %}
6893 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
6894 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
6895 ins_pipe( ialu_mem_reg );
6896 %}
6897
6898 instruct storeL_reversed(memory dst, rRegL src) %{
6899 match(Set dst (StoreL dst (ReverseBytesL src)));
6900
6901 format %{ "movq_bswap $dst, $src" %}
6902 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
6903 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
6904 ins_pipe( ialu_mem_reg );
6905 %}
6906
6907 //----------MemBar Instructions-----------------------------------------------
6908 // Memory barrier flavors
6909
6910 instruct membar_acquire()
6911 %{
6912 match(MemBarAcquire);
6913 ins_cost(0);
6914
6915 size(0);
6916 format %{ "MEMBAR-acquire" %}
6917 ins_encode();
6918 ins_pipe(empty);
6919 %}
6920
6921 instruct membar_acquire_lock()
6922 %{
6923 match(MemBarAcquire);
6924 predicate(Matcher::prior_fast_lock(n));
6925 ins_cost(0);
6926
6927 size(0);
6928 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6929 ins_encode();
6930 ins_pipe(empty);
6931 %}
6932
6933 instruct membar_release()
6934 %{
6935 match(MemBarRelease);
6936 ins_cost(0);
6937
6938 size(0);
6939 format %{ "MEMBAR-release" %}
6940 ins_encode();
6941 ins_pipe(empty);
6942 %}
6943
6944 instruct membar_release_lock()
6945 %{
6946 match(MemBarRelease);
6947 predicate(Matcher::post_fast_unlock(n));
6948 ins_cost(0);
6949
6950 size(0);
6951 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6952 ins_encode();
6953 ins_pipe(empty);
6954 %}
6955
6956 instruct membar_volatile()
6957 %{
6958 match(MemBarVolatile);
6959 ins_cost(400);
6960
6961 format %{ "MEMBAR-volatile" %}
6962 ins_encode(enc_membar_volatile);
6963 ins_pipe(pipe_slow);
6964 %}
6965
6966 instruct unnecessary_membar_volatile()
6967 %{
6968 match(MemBarVolatile);
6969 predicate(Matcher::post_store_load_barrier(n));
6970 ins_cost(0);
6971
6972 size(0);
6973 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6974 ins_encode();
6975 ins_pipe(empty);
6976 %}
6977
6978 //----------Move Instructions--------------------------------------------------
6979
6980 instruct castX2P(rRegP dst, rRegL src)
6981 %{
6982 match(Set dst (CastX2P src));
6983
6984 format %{ "movq $dst, $src\t# long->ptr" %}
6985 ins_encode(enc_copy_wide(dst, src));
6986 ins_pipe(ialu_reg_reg); // XXX
6987 %}
6988
6989 instruct castP2X(rRegL dst, rRegP src)
6990 %{
6991 match(Set dst (CastP2X src));
6992
6993 format %{ "movq $dst, $src\t# ptr -> long" %}
6994 ins_encode(enc_copy_wide(dst, src));
6995 ins_pipe(ialu_reg_reg); // XXX
6996 %}
6997
6998
6999 // Convert oop pointer into compressed form
7000 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7001 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() != TypePtr::NotNull);
7002 match(Set dst (EncodeP src));
7003 effect(KILL cr);
7004 format %{ "encode_heap_oop $dst,$src" %}
7005 ins_encode %{
7006 Register s = $src$$Register;
7007 Register d = $dst$$Register;
7008 if (s != d) {
7009 __ movq(d, s);
7010 }
7011 __ encode_heap_oop(d);
7012 %}
7013 ins_pipe(ialu_reg_long);
7014 %}
7015
7016 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7017 predicate(n->bottom_type()->is_narrowoop()->make_oopptr()->ptr() == TypePtr::NotNull);
7018 match(Set dst (EncodeP src));
7019 effect(KILL cr);
7020 format %{ "encode_heap_oop_not_null $dst,$src" %}
7021 ins_encode %{
7022 Register s = $src$$Register;
7023 Register d = $dst$$Register;
7024 __ encode_heap_oop_not_null(d, s);
7025 %}
7026 ins_pipe(ialu_reg_long);
7027 %}
7028
7029 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7030 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull);
7031 match(Set dst (DecodeN src));
7032 effect(KILL cr);
7033 format %{ "decode_heap_oop $dst,$src" %}
7034 ins_encode %{
7035 Register s = $src$$Register;
7036 Register d = $dst$$Register;
7037 if (s != d) {
7038 __ movq(d, s);
7039 }
7040 __ decode_heap_oop(d);
7041 %}
7042 ins_pipe(ialu_reg_long);
7043 %}
7044
7045 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{
7046 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull);
7047 match(Set dst (DecodeN src));
7048 format %{ "decode_heap_oop_not_null $dst,$src" %}
7049 ins_encode %{
7050 Register s = $src$$Register;
7051 Register d = $dst$$Register;
7052 __ decode_heap_oop_not_null(d, s);
7053 %}
7054 ins_pipe(ialu_reg_long);
7055 %}
7056
7057
7058 //----------Conditional Move---------------------------------------------------
7059 // Jump
7060 // dummy instruction for generating temp registers
7061 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7062 match(Jump (LShiftL switch_val shift));
7063 ins_cost(350);
7064 predicate(false);
7065 effect(TEMP dest);
7066
7067 format %{ "leaq $dest, table_base\n\t"
7068 "jmp [$dest + $switch_val << $shift]\n\t" %}
7069 ins_encode(jump_enc_offset(switch_val, shift, dest));
7070 ins_pipe(pipe_jmp);
7071 ins_pc_relative(1);
7072 %}
7073
7074 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7075 match(Jump (AddL (LShiftL switch_val shift) offset));
7076 ins_cost(350);
7077 effect(TEMP dest);
7078
7079 format %{ "leaq $dest, table_base\n\t"
7080 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7081 ins_encode(jump_enc_addr(switch_val, shift, offset, dest));
7082 ins_pipe(pipe_jmp);
7083 ins_pc_relative(1);
7084 %}
7085
7086 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7087 match(Jump switch_val);
7088 ins_cost(350);
7089 effect(TEMP dest);
7090
7091 format %{ "leaq $dest, table_base\n\t"
7092 "jmp [$dest + $switch_val]\n\t" %}
7093 ins_encode(jump_enc(switch_val, dest));
7094 ins_pipe(pipe_jmp);
7095 ins_pc_relative(1);
7096 %}
7097
7098 // Conditional move
7099 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7100 %{
7101 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7102
7103 ins_cost(200); // XXX
7104 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7105 opcode(0x0F, 0x40);
7106 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7107 ins_pipe(pipe_cmov_reg);
7108 %}
7109
7110 instruct cmovI_regU(rRegI dst, rRegI src, rFlagsRegU cr, cmpOpU cop)
7111 %{
7112 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7113
7114 ins_cost(200); // XXX
7115 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7116 opcode(0x0F, 0x40);
7117 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7118 ins_pipe(pipe_cmov_reg);
7119 %}
7120
7121 // Conditional move
7122 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src)
7123 %{
7124 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7125
7126 ins_cost(250); // XXX
7127 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7128 opcode(0x0F, 0x40);
7129 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7130 ins_pipe(pipe_cmov_mem);
7131 %}
7132
7133 // Conditional move
7134 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7135 %{
7136 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7137
7138 ins_cost(250); // XXX
7139 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7140 opcode(0x0F, 0x40);
7141 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7142 ins_pipe(pipe_cmov_mem);
7143 %}
7144
7145 // Conditional move
7146 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7147 %{
7148 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7149
7150 ins_cost(200); // XXX
7151 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7152 opcode(0x0F, 0x40);
7153 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7154 ins_pipe(pipe_cmov_reg); // XXX
7155 %}
7156
7157 // Conditional move
7158 instruct cmovP_regU(rRegP dst, rRegP src, rFlagsRegU cr, cmpOpU cop)
7159 %{
7160 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7161
7162 ins_cost(200); // XXX
7163 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7164 opcode(0x0F, 0x40);
7165 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7166 ins_pipe(pipe_cmov_reg); // XXX
7167 %}
7168
7169 // DISABLED: Requires the ADLC to emit a bottom_type call that
7170 // correctly meets the two pointer arguments; one is an incoming
7171 // register but the other is a memory operand. ALSO appears to
7172 // be buggy with implicit null checks.
7173 //
7174 //// Conditional move
7175 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7176 //%{
7177 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7178 // ins_cost(250);
7179 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7180 // opcode(0x0F,0x40);
7181 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7182 // ins_pipe( pipe_cmov_mem );
7183 //%}
7184 //
7185 //// Conditional move
7186 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7187 //%{
7188 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7189 // ins_cost(250);
7190 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7191 // opcode(0x0F,0x40);
7192 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7193 // ins_pipe( pipe_cmov_mem );
7194 //%}
7195
7196 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7197 %{
7198 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7199
7200 ins_cost(200); // XXX
7201 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7202 opcode(0x0F, 0x40);
7203 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7204 ins_pipe(pipe_cmov_reg); // XXX
7205 %}
7206
7207 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7208 %{
7209 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7210
7211 ins_cost(200); // XXX
7212 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7213 opcode(0x0F, 0x40);
7214 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7215 ins_pipe(pipe_cmov_mem); // XXX
7216 %}
7217
7218 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7219 %{
7220 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7221
7222 ins_cost(200); // XXX
7223 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7224 opcode(0x0F, 0x40);
7225 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7226 ins_pipe(pipe_cmov_reg); // XXX
7227 %}
7228
7229 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7230 %{
7231 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7232
7233 ins_cost(200); // XXX
7234 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7235 opcode(0x0F, 0x40);
7236 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7237 ins_pipe(pipe_cmov_mem); // XXX
7238 %}
7239
7240 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7241 %{
7242 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7243
7244 ins_cost(200); // XXX
7245 format %{ "jn$cop skip\t# signed cmove float\n\t"
7246 "movss $dst, $src\n"
7247 "skip:" %}
7248 ins_encode(enc_cmovf_branch(cop, dst, src));
7249 ins_pipe(pipe_slow);
7250 %}
7251
7252 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7253 // %{
7254 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7255
7256 // ins_cost(200); // XXX
7257 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7258 // "movss $dst, $src\n"
7259 // "skip:" %}
7260 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7261 // ins_pipe(pipe_slow);
7262 // %}
7263
7264 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7265 %{
7266 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7267
7268 ins_cost(200); // XXX
7269 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7270 "movss $dst, $src\n"
7271 "skip:" %}
7272 ins_encode(enc_cmovf_branch(cop, dst, src));
7273 ins_pipe(pipe_slow);
7274 %}
7275
7276 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7277 %{
7278 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7279
7280 ins_cost(200); // XXX
7281 format %{ "jn$cop skip\t# signed cmove double\n\t"
7282 "movsd $dst, $src\n"
7283 "skip:" %}
7284 ins_encode(enc_cmovd_branch(cop, dst, src));
7285 ins_pipe(pipe_slow);
7286 %}
7287
7288 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7289 %{
7290 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7291
7292 ins_cost(200); // XXX
7293 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7294 "movsd $dst, $src\n"
7295 "skip:" %}
7296 ins_encode(enc_cmovd_branch(cop, dst, src));
7297 ins_pipe(pipe_slow);
7298 %}
7299
7300 //----------Arithmetic Instructions--------------------------------------------
7301 //----------Addition Instructions----------------------------------------------
7302
7303 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7304 %{
7305 match(Set dst (AddI dst src));
7306 effect(KILL cr);
7307
7308 format %{ "addl $dst, $src\t# int" %}
7309 opcode(0x03);
7310 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7311 ins_pipe(ialu_reg_reg);
7312 %}
7313
7314 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7315 %{
7316 match(Set dst (AddI dst src));
7317 effect(KILL cr);
7318
7319 format %{ "addl $dst, $src\t# int" %}
7320 opcode(0x81, 0x00); /* /0 id */
7321 ins_encode(OpcSErm(dst, src), Con8or32(src));
7322 ins_pipe( ialu_reg );
7323 %}
7324
7325 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7326 %{
7327 match(Set dst (AddI dst (LoadI src)));
7328 effect(KILL cr);
7329
7330 ins_cost(125); // XXX
7331 format %{ "addl $dst, $src\t# int" %}
7332 opcode(0x03);
7333 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7334 ins_pipe(ialu_reg_mem);
7335 %}
7336
7337 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7338 %{
7339 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7340 effect(KILL cr);
7341
7342 ins_cost(150); // XXX
7343 format %{ "addl $dst, $src\t# int" %}
7344 opcode(0x01); /* Opcode 01 /r */
7345 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7346 ins_pipe(ialu_mem_reg);
7347 %}
7348
7349 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7350 %{
7351 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7352 effect(KILL cr);
7353
7354 ins_cost(125); // XXX
7355 format %{ "addl $dst, $src\t# int" %}
7356 opcode(0x81); /* Opcode 81 /0 id */
7357 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7358 ins_pipe(ialu_mem_imm);
7359 %}
7360
7361 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7362 %{
7363 predicate(UseIncDec);
7364 match(Set dst (AddI dst src));
7365 effect(KILL cr);
7366
7367 format %{ "incl $dst\t# int" %}
7368 opcode(0xFF, 0x00); // FF /0
7369 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7370 ins_pipe(ialu_reg);
7371 %}
7372
7373 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7374 %{
7375 predicate(UseIncDec);
7376 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7377 effect(KILL cr);
7378
7379 ins_cost(125); // XXX
7380 format %{ "incl $dst\t# int" %}
7381 opcode(0xFF); /* Opcode FF /0 */
7382 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7383 ins_pipe(ialu_mem_imm);
7384 %}
7385
7386 // XXX why does that use AddI
7387 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7388 %{
7389 predicate(UseIncDec);
7390 match(Set dst (AddI dst src));
7391 effect(KILL cr);
7392
7393 format %{ "decl $dst\t# int" %}
7394 opcode(0xFF, 0x01); // FF /1
7395 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7396 ins_pipe(ialu_reg);
7397 %}
7398
7399 // XXX why does that use AddI
7400 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7401 %{
7402 predicate(UseIncDec);
7403 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7404 effect(KILL cr);
7405
7406 ins_cost(125); // XXX
7407 format %{ "decl $dst\t# int" %}
7408 opcode(0xFF); /* Opcode FF /1 */
7409 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7410 ins_pipe(ialu_mem_imm);
7411 %}
7412
7413 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7414 %{
7415 match(Set dst (AddI src0 src1));
7416
7417 ins_cost(110);
7418 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7419 opcode(0x8D); /* 0x8D /r */
7420 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7421 ins_pipe(ialu_reg_reg);
7422 %}
7423
7424 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7425 %{
7426 match(Set dst (AddL dst src));
7427 effect(KILL cr);
7428
7429 format %{ "addq $dst, $src\t# long" %}
7430 opcode(0x03);
7431 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7432 ins_pipe(ialu_reg_reg);
7433 %}
7434
7435 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7436 %{
7437 match(Set dst (AddL dst src));
7438 effect(KILL cr);
7439
7440 format %{ "addq $dst, $src\t# long" %}
7441 opcode(0x81, 0x00); /* /0 id */
7442 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7443 ins_pipe( ialu_reg );
7444 %}
7445
7446 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7447 %{
7448 match(Set dst (AddL dst (LoadL src)));
7449 effect(KILL cr);
7450
7451 ins_cost(125); // XXX
7452 format %{ "addq $dst, $src\t# long" %}
7453 opcode(0x03);
7454 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7455 ins_pipe(ialu_reg_mem);
7456 %}
7457
7458 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7459 %{
7460 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7461 effect(KILL cr);
7462
7463 ins_cost(150); // XXX
7464 format %{ "addq $dst, $src\t# long" %}
7465 opcode(0x01); /* Opcode 01 /r */
7466 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7467 ins_pipe(ialu_mem_reg);
7468 %}
7469
7470 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7471 %{
7472 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7473 effect(KILL cr);
7474
7475 ins_cost(125); // XXX
7476 format %{ "addq $dst, $src\t# long" %}
7477 opcode(0x81); /* Opcode 81 /0 id */
7478 ins_encode(REX_mem_wide(dst),
7479 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7480 ins_pipe(ialu_mem_imm);
7481 %}
7482
7483 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7484 %{
7485 predicate(UseIncDec);
7486 match(Set dst (AddL dst src));
7487 effect(KILL cr);
7488
7489 format %{ "incq $dst\t# long" %}
7490 opcode(0xFF, 0x00); // FF /0
7491 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7492 ins_pipe(ialu_reg);
7493 %}
7494
7495 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7496 %{
7497 predicate(UseIncDec);
7498 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7499 effect(KILL cr);
7500
7501 ins_cost(125); // XXX
7502 format %{ "incq $dst\t# long" %}
7503 opcode(0xFF); /* Opcode FF /0 */
7504 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7505 ins_pipe(ialu_mem_imm);
7506 %}
7507
7508 // XXX why does that use AddL
7509 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7510 %{
7511 predicate(UseIncDec);
7512 match(Set dst (AddL dst src));
7513 effect(KILL cr);
7514
7515 format %{ "decq $dst\t# long" %}
7516 opcode(0xFF, 0x01); // FF /1
7517 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7518 ins_pipe(ialu_reg);
7519 %}
7520
7521 // XXX why does that use AddL
7522 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7523 %{
7524 predicate(UseIncDec);
7525 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7526 effect(KILL cr);
7527
7528 ins_cost(125); // XXX
7529 format %{ "decq $dst\t# long" %}
7530 opcode(0xFF); /* Opcode FF /1 */
7531 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7532 ins_pipe(ialu_mem_imm);
7533 %}
7534
7535 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7536 %{
7537 match(Set dst (AddL src0 src1));
7538
7539 ins_cost(110);
7540 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7541 opcode(0x8D); /* 0x8D /r */
7542 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7543 ins_pipe(ialu_reg_reg);
7544 %}
7545
7546 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7547 %{
7548 match(Set dst (AddP dst src));
7549 effect(KILL cr);
7550
7551 format %{ "addq $dst, $src\t# ptr" %}
7552 opcode(0x03);
7553 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7554 ins_pipe(ialu_reg_reg);
7555 %}
7556
7557 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7558 %{
7559 match(Set dst (AddP dst src));
7560 effect(KILL cr);
7561
7562 format %{ "addq $dst, $src\t# ptr" %}
7563 opcode(0x81, 0x00); /* /0 id */
7564 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7565 ins_pipe( ialu_reg );
7566 %}
7567
7568 // XXX addP mem ops ????
7569
7570 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7571 %{
7572 match(Set dst (AddP src0 src1));
7573
7574 ins_cost(110);
7575 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7576 opcode(0x8D); /* 0x8D /r */
7577 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7578 ins_pipe(ialu_reg_reg);
7579 %}
7580
7581 instruct checkCastPP(rRegP dst)
7582 %{
7583 match(Set dst (CheckCastPP dst));
7584
7585 size(0);
7586 format %{ "# checkcastPP of $dst" %}
7587 ins_encode(/* empty encoding */);
7588 ins_pipe(empty);
7589 %}
7590
7591 instruct castPP(rRegP dst)
7592 %{
7593 match(Set dst (CastPP dst));
7594
7595 size(0);
7596 format %{ "# castPP of $dst" %}
7597 ins_encode(/* empty encoding */);
7598 ins_pipe(empty);
7599 %}
7600
7601 instruct castII(rRegI dst)
7602 %{
7603 match(Set dst (CastII dst));
7604
7605 size(0);
7606 format %{ "# castII of $dst" %}
7607 ins_encode(/* empty encoding */);
7608 ins_cost(0);
7609 ins_pipe(empty);
7610 %}
7611
7612 // LoadP-locked same as a regular LoadP when used with compare-swap
7613 instruct loadPLocked(rRegP dst, memory mem)
7614 %{
7615 match(Set dst (LoadPLocked mem));
7616
7617 ins_cost(125); // XXX
7618 format %{ "movq $dst, $mem\t# ptr locked" %}
7619 opcode(0x8B);
7620 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7621 ins_pipe(ialu_reg_mem); // XXX
7622 %}
7623
7624 // LoadL-locked - same as a regular LoadL when used with compare-swap
7625 instruct loadLLocked(rRegL dst, memory mem)
7626 %{
7627 match(Set dst (LoadLLocked mem));
7628
7629 ins_cost(125); // XXX
7630 format %{ "movq $dst, $mem\t# long locked" %}
7631 opcode(0x8B);
7632 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7633 ins_pipe(ialu_reg_mem); // XXX
7634 %}
7635
7636 // Conditional-store of the updated heap-top.
7637 // Used during allocation of the shared heap.
7638 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7639
7640 instruct storePConditional(memory heap_top_ptr,
7641 rax_RegP oldval, rRegP newval,
7642 rFlagsReg cr)
7643 %{
7644 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7645
7646 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7647 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7648 opcode(0x0F, 0xB1);
7649 ins_encode(lock_prefix,
7650 REX_reg_mem_wide(newval, heap_top_ptr),
7651 OpcP, OpcS,
7652 reg_mem(newval, heap_top_ptr));
7653 ins_pipe(pipe_cmpxchg);
7654 %}
7655
7656 // Conditional-store of a long value
7657 // Returns a boolean value (0/1) on success. Implemented with a
7658 // CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI
7659
7660 instruct storeLConditional(rRegI res,
7661 memory mem_ptr,
7662 rax_RegL oldval, rRegL newval,
7663 rFlagsReg cr)
7664 %{
7665 match(Set res (StoreLConditional mem_ptr (Binary oldval newval)));
7666 effect(KILL cr);
7667
7668 format %{ "cmpxchgq $mem_ptr, $newval\t# (long) "
7669 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7670 "sete $res\n\t"
7671 "movzbl $res, $res" %}
7672 opcode(0x0F, 0xB1);
7673 ins_encode(lock_prefix,
7674 REX_reg_mem_wide(newval, mem_ptr),
7675 OpcP, OpcS,
7676 reg_mem(newval, mem_ptr),
7677 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7678 REX_reg_breg(res, res), // movzbl
7679 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7680 ins_pipe(pipe_cmpxchg);
7681 %}
7682
7683 // Conditional-store of a long value
7684 // ZF flag is set on success, reset otherwise. Implemented with a
7685 // CMPXCHG8 on Intel. mem_ptr can actually be in either RSI or RDI
7686 instruct storeLConditional_flags(memory mem_ptr,
7687 rax_RegL oldval, rRegL newval,
7688 rFlagsReg cr,
7689 immI0 zero)
7690 %{
7691 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero));
7692
7693 format %{ "cmpxchgq $mem_ptr, $newval\t# (long) "
7694 "If rax == $mem_ptr then store $newval into $mem_ptr" %}
7695 opcode(0x0F, 0xB1);
7696 ins_encode(lock_prefix,
7697 REX_reg_mem_wide(newval, mem_ptr),
7698 OpcP, OpcS,
7699 reg_mem(newval, mem_ptr));
7700 ins_pipe(pipe_cmpxchg);
7701 %}
7702
7703 instruct compareAndSwapP(rRegI res,
7704 memory mem_ptr,
7705 rax_RegP oldval, rRegP newval,
7706 rFlagsReg cr)
7707 %{
7708 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7709 effect(KILL cr, KILL oldval);
7710
7711 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7712 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7713 "sete $res\n\t"
7714 "movzbl $res, $res" %}
7715 opcode(0x0F, 0xB1);
7716 ins_encode(lock_prefix,
7717 REX_reg_mem_wide(newval, mem_ptr),
7718 OpcP, OpcS,
7719 reg_mem(newval, mem_ptr),
7720 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7721 REX_reg_breg(res, res), // movzbl
7722 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7723 ins_pipe( pipe_cmpxchg );
7724 %}
7725
7726 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7727 instruct compareAndSwapL(rRegI res,
7728 memory mem_ptr,
7729 rax_RegL oldval, rRegL newval,
7730 rFlagsReg cr)
7731 %{
7732 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7733 effect(KILL cr, KILL oldval);
7734
7735 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7736 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7737 "sete $res\n\t"
7738 "movzbl $res, $res" %}
7739 opcode(0x0F, 0xB1);
7740 ins_encode(lock_prefix,
7741 REX_reg_mem_wide(newval, mem_ptr),
7742 OpcP, OpcS,
7743 reg_mem(newval, mem_ptr),
7744 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7745 REX_reg_breg(res, res), // movzbl
7746 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7747 ins_pipe( pipe_cmpxchg );
7748 %}
7749
7750 instruct compareAndSwapI(rRegI res,
7751 memory mem_ptr,
7752 rax_RegI oldval, rRegI newval,
7753 rFlagsReg cr)
7754 %{
7755 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7756 effect(KILL cr, KILL oldval);
7757
7758 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7759 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7760 "sete $res\n\t"
7761 "movzbl $res, $res" %}
7762 opcode(0x0F, 0xB1);
7763 ins_encode(lock_prefix,
7764 REX_reg_mem(newval, mem_ptr),
7765 OpcP, OpcS,
7766 reg_mem(newval, mem_ptr),
7767 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7768 REX_reg_breg(res, res), // movzbl
7769 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7770 ins_pipe( pipe_cmpxchg );
7771 %}
7772
7773
7774 instruct compareAndSwapN(rRegI res,
7775 memory mem_ptr,
7776 rax_RegN oldval, rRegN newval,
7777 rFlagsReg cr) %{
7778 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7779 effect(KILL cr, KILL oldval);
7780
7781 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7782 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7783 "sete $res\n\t"
7784 "movzbl $res, $res" %}
7785 opcode(0x0F, 0xB1);
7786 ins_encode(lock_prefix,
7787 REX_reg_mem(newval, mem_ptr),
7788 OpcP, OpcS,
7789 reg_mem(newval, mem_ptr),
7790 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7791 REX_reg_breg(res, res), // movzbl
7792 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7793 ins_pipe( pipe_cmpxchg );
7794 %}
7795
7796 //----------Subtraction Instructions-------------------------------------------
7797
7798 // Integer Subtraction Instructions
7799 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7800 %{
7801 match(Set dst (SubI dst src));
7802 effect(KILL cr);
7803
7804 format %{ "subl $dst, $src\t# int" %}
7805 opcode(0x2B);
7806 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7807 ins_pipe(ialu_reg_reg);
7808 %}
7809
7810 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7811 %{
7812 match(Set dst (SubI dst src));
7813 effect(KILL cr);
7814
7815 format %{ "subl $dst, $src\t# int" %}
7816 opcode(0x81, 0x05); /* Opcode 81 /5 */
7817 ins_encode(OpcSErm(dst, src), Con8or32(src));
7818 ins_pipe(ialu_reg);
7819 %}
7820
7821 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7822 %{
7823 match(Set dst (SubI dst (LoadI src)));
7824 effect(KILL cr);
7825
7826 ins_cost(125);
7827 format %{ "subl $dst, $src\t# int" %}
7828 opcode(0x2B);
7829 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7830 ins_pipe(ialu_reg_mem);
7831 %}
7832
7833 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7834 %{
7835 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7836 effect(KILL cr);
7837
7838 ins_cost(150);
7839 format %{ "subl $dst, $src\t# int" %}
7840 opcode(0x29); /* Opcode 29 /r */
7841 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7842 ins_pipe(ialu_mem_reg);
7843 %}
7844
7845 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7846 %{
7847 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7848 effect(KILL cr);
7849
7850 ins_cost(125); // XXX
7851 format %{ "subl $dst, $src\t# int" %}
7852 opcode(0x81); /* Opcode 81 /5 id */
7853 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7854 ins_pipe(ialu_mem_imm);
7855 %}
7856
7857 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7858 %{
7859 match(Set dst (SubL dst src));
7860 effect(KILL cr);
7861
7862 format %{ "subq $dst, $src\t# long" %}
7863 opcode(0x2B);
7864 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7865 ins_pipe(ialu_reg_reg);
7866 %}
7867
7868 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7869 %{
7870 match(Set dst (SubL dst src));
7871 effect(KILL cr);
7872
7873 format %{ "subq $dst, $src\t# long" %}
7874 opcode(0x81, 0x05); /* Opcode 81 /5 */
7875 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7876 ins_pipe(ialu_reg);
7877 %}
7878
7879 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7880 %{
7881 match(Set dst (SubL dst (LoadL src)));
7882 effect(KILL cr);
7883
7884 ins_cost(125);
7885 format %{ "subq $dst, $src\t# long" %}
7886 opcode(0x2B);
7887 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7888 ins_pipe(ialu_reg_mem);
7889 %}
7890
7891 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7892 %{
7893 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7894 effect(KILL cr);
7895
7896 ins_cost(150);
7897 format %{ "subq $dst, $src\t# long" %}
7898 opcode(0x29); /* Opcode 29 /r */
7899 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7900 ins_pipe(ialu_mem_reg);
7901 %}
7902
7903 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7904 %{
7905 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7906 effect(KILL cr);
7907
7908 ins_cost(125); // XXX
7909 format %{ "subq $dst, $src\t# long" %}
7910 opcode(0x81); /* Opcode 81 /5 id */
7911 ins_encode(REX_mem_wide(dst),
7912 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7913 ins_pipe(ialu_mem_imm);
7914 %}
7915
7916 // Subtract from a pointer
7917 // XXX hmpf???
7918 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7919 %{
7920 match(Set dst (AddP dst (SubI zero src)));
7921 effect(KILL cr);
7922
7923 format %{ "subq $dst, $src\t# ptr - int" %}
7924 opcode(0x2B);
7925 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7926 ins_pipe(ialu_reg_reg);
7927 %}
7928
7929 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7930 %{
7931 match(Set dst (SubI zero dst));
7932 effect(KILL cr);
7933
7934 format %{ "negl $dst\t# int" %}
7935 opcode(0xF7, 0x03); // Opcode F7 /3
7936 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7937 ins_pipe(ialu_reg);
7938 %}
7939
7940 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7941 %{
7942 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7943 effect(KILL cr);
7944
7945 format %{ "negl $dst\t# int" %}
7946 opcode(0xF7, 0x03); // Opcode F7 /3
7947 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7948 ins_pipe(ialu_reg);
7949 %}
7950
7951 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7952 %{
7953 match(Set dst (SubL zero dst));
7954 effect(KILL cr);
7955
7956 format %{ "negq $dst\t# long" %}
7957 opcode(0xF7, 0x03); // Opcode F7 /3
7958 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7959 ins_pipe(ialu_reg);
7960 %}
7961
7962 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7963 %{
7964 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7965 effect(KILL cr);
7966
7967 format %{ "negq $dst\t# long" %}
7968 opcode(0xF7, 0x03); // Opcode F7 /3
7969 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7970 ins_pipe(ialu_reg);
7971 %}
7972
7973
7974 //----------Multiplication/Division Instructions-------------------------------
7975 // Integer Multiplication Instructions
7976 // Multiply Register
7977
7978 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7979 %{
7980 match(Set dst (MulI dst src));
7981 effect(KILL cr);
7982
7983 ins_cost(300);
7984 format %{ "imull $dst, $src\t# int" %}
7985 opcode(0x0F, 0xAF);
7986 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7987 ins_pipe(ialu_reg_reg_alu0);
7988 %}
7989
7990 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7991 %{
7992 match(Set dst (MulI src imm));
7993 effect(KILL cr);
7994
7995 ins_cost(300);
7996 format %{ "imull $dst, $src, $imm\t# int" %}
7997 opcode(0x69); /* 69 /r id */
7998 ins_encode(REX_reg_reg(dst, src),
7999 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8000 ins_pipe(ialu_reg_reg_alu0);
8001 %}
8002
8003 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8004 %{
8005 match(Set dst (MulI dst (LoadI src)));
8006 effect(KILL cr);
8007
8008 ins_cost(350);
8009 format %{ "imull $dst, $src\t# int" %}
8010 opcode(0x0F, 0xAF);
8011 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8012 ins_pipe(ialu_reg_mem_alu0);
8013 %}
8014
8015 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8016 %{
8017 match(Set dst (MulI (LoadI src) imm));
8018 effect(KILL cr);
8019
8020 ins_cost(300);
8021 format %{ "imull $dst, $src, $imm\t# int" %}
8022 opcode(0x69); /* 69 /r id */
8023 ins_encode(REX_reg_mem(dst, src),
8024 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8025 ins_pipe(ialu_reg_mem_alu0);
8026 %}
8027
8028 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8029 %{
8030 match(Set dst (MulL dst src));
8031 effect(KILL cr);
8032
8033 ins_cost(300);
8034 format %{ "imulq $dst, $src\t# long" %}
8035 opcode(0x0F, 0xAF);
8036 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8037 ins_pipe(ialu_reg_reg_alu0);
8038 %}
8039
8040 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8041 %{
8042 match(Set dst (MulL src imm));
8043 effect(KILL cr);
8044
8045 ins_cost(300);
8046 format %{ "imulq $dst, $src, $imm\t# long" %}
8047 opcode(0x69); /* 69 /r id */
8048 ins_encode(REX_reg_reg_wide(dst, src),
8049 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8050 ins_pipe(ialu_reg_reg_alu0);
8051 %}
8052
8053 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8054 %{
8055 match(Set dst (MulL dst (LoadL src)));
8056 effect(KILL cr);
8057
8058 ins_cost(350);
8059 format %{ "imulq $dst, $src\t# long" %}
8060 opcode(0x0F, 0xAF);
8061 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8062 ins_pipe(ialu_reg_mem_alu0);
8063 %}
8064
8065 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8066 %{
8067 match(Set dst (MulL (LoadL src) imm));
8068 effect(KILL cr);
8069
8070 ins_cost(300);
8071 format %{ "imulq $dst, $src, $imm\t# long" %}
8072 opcode(0x69); /* 69 /r id */
8073 ins_encode(REX_reg_mem_wide(dst, src),
8074 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8075 ins_pipe(ialu_reg_mem_alu0);
8076 %}
8077
8078 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8079 rFlagsReg cr)
8080 %{
8081 match(Set rax (DivI rax div));
8082 effect(KILL rdx, KILL cr);
8083
8084 ins_cost(30*100+10*100); // XXX
8085 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8086 "jne,s normal\n\t"
8087 "xorl rdx, rdx\n\t"
8088 "cmpl $div, -1\n\t"
8089 "je,s done\n"
8090 "normal: cdql\n\t"
8091 "idivl $div\n"
8092 "done:" %}
8093 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8094 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8095 ins_pipe(ialu_reg_reg_alu0);
8096 %}
8097
8098 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8099 rFlagsReg cr)
8100 %{
8101 match(Set rax (DivL rax div));
8102 effect(KILL rdx, KILL cr);
8103
8104 ins_cost(30*100+10*100); // XXX
8105 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8106 "cmpq rax, rdx\n\t"
8107 "jne,s normal\n\t"
8108 "xorl rdx, rdx\n\t"
8109 "cmpq $div, -1\n\t"
8110 "je,s done\n"
8111 "normal: cdqq\n\t"
8112 "idivq $div\n"
8113 "done:" %}
8114 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8115 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8116 ins_pipe(ialu_reg_reg_alu0);
8117 %}
8118
8119 // Integer DIVMOD with Register, both quotient and mod results
8120 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8121 rFlagsReg cr)
8122 %{
8123 match(DivModI rax div);
8124 effect(KILL cr);
8125
8126 ins_cost(30*100+10*100); // XXX
8127 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8128 "jne,s normal\n\t"
8129 "xorl rdx, rdx\n\t"
8130 "cmpl $div, -1\n\t"
8131 "je,s done\n"
8132 "normal: cdql\n\t"
8133 "idivl $div\n"
8134 "done:" %}
8135 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8136 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8137 ins_pipe(pipe_slow);
8138 %}
8139
8140 // Long DIVMOD with Register, both quotient and mod results
8141 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8142 rFlagsReg cr)
8143 %{
8144 match(DivModL rax div);
8145 effect(KILL cr);
8146
8147 ins_cost(30*100+10*100); // XXX
8148 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8149 "cmpq rax, rdx\n\t"
8150 "jne,s normal\n\t"
8151 "xorl rdx, rdx\n\t"
8152 "cmpq $div, -1\n\t"
8153 "je,s done\n"
8154 "normal: cdqq\n\t"
8155 "idivq $div\n"
8156 "done:" %}
8157 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8158 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8159 ins_pipe(pipe_slow);
8160 %}
8161
8162 //----------- DivL-By-Constant-Expansions--------------------------------------
8163 // DivI cases are handled by the compiler
8164
8165 // Magic constant, reciprical of 10
8166 instruct loadConL_0x6666666666666667(rRegL dst)
8167 %{
8168 effect(DEF dst);
8169
8170 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8171 ins_encode(load_immL(dst, 0x6666666666666667));
8172 ins_pipe(ialu_reg);
8173 %}
8174
8175 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8176 %{
8177 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8178
8179 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8180 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8181 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8182 ins_pipe(ialu_reg_reg_alu0);
8183 %}
8184
8185 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8186 %{
8187 effect(USE_DEF dst, KILL cr);
8188
8189 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8190 opcode(0xC1, 0x7); /* C1 /7 ib */
8191 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8192 ins_pipe(ialu_reg);
8193 %}
8194
8195 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8196 %{
8197 effect(USE_DEF dst, KILL cr);
8198
8199 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8200 opcode(0xC1, 0x7); /* C1 /7 ib */
8201 ins_encode(reg_opc_imm_wide(dst, 0x2));
8202 ins_pipe(ialu_reg);
8203 %}
8204
8205 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8206 %{
8207 match(Set dst (DivL src div));
8208
8209 ins_cost((5+8)*100);
8210 expand %{
8211 rax_RegL rax; // Killed temp
8212 rFlagsReg cr; // Killed
8213 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8214 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8215 sarL_rReg_63(src, cr); // sarq src, 63
8216 sarL_rReg_2(dst, cr); // sarq rdx, 2
8217 subL_rReg(dst, src, cr); // subl rdx, src
8218 %}
8219 %}
8220
8221 //-----------------------------------------------------------------------------
8222
8223 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8224 rFlagsReg cr)
8225 %{
8226 match(Set rdx (ModI rax div));
8227 effect(KILL rax, KILL cr);
8228
8229 ins_cost(300); // XXX
8230 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8231 "jne,s normal\n\t"
8232 "xorl rdx, rdx\n\t"
8233 "cmpl $div, -1\n\t"
8234 "je,s done\n"
8235 "normal: cdql\n\t"
8236 "idivl $div\n"
8237 "done:" %}
8238 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8239 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8240 ins_pipe(ialu_reg_reg_alu0);
8241 %}
8242
8243 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8244 rFlagsReg cr)
8245 %{
8246 match(Set rdx (ModL rax div));
8247 effect(KILL rax, KILL cr);
8248
8249 ins_cost(300); // XXX
8250 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8251 "cmpq rax, rdx\n\t"
8252 "jne,s normal\n\t"
8253 "xorl rdx, rdx\n\t"
8254 "cmpq $div, -1\n\t"
8255 "je,s done\n"
8256 "normal: cdqq\n\t"
8257 "idivq $div\n"
8258 "done:" %}
8259 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8260 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8261 ins_pipe(ialu_reg_reg_alu0);
8262 %}
8263
8264 // Integer Shift Instructions
8265 // Shift Left by one
8266 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8267 %{
8268 match(Set dst (LShiftI dst shift));
8269 effect(KILL cr);
8270
8271 format %{ "sall $dst, $shift" %}
8272 opcode(0xD1, 0x4); /* D1 /4 */
8273 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8274 ins_pipe(ialu_reg);
8275 %}
8276
8277 // Shift Left by one
8278 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8279 %{
8280 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8281 effect(KILL cr);
8282
8283 format %{ "sall $dst, $shift\t" %}
8284 opcode(0xD1, 0x4); /* D1 /4 */
8285 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8286 ins_pipe(ialu_mem_imm);
8287 %}
8288
8289 // Shift Left by 8-bit immediate
8290 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8291 %{
8292 match(Set dst (LShiftI dst shift));
8293 effect(KILL cr);
8294
8295 format %{ "sall $dst, $shift" %}
8296 opcode(0xC1, 0x4); /* C1 /4 ib */
8297 ins_encode(reg_opc_imm(dst, shift));
8298 ins_pipe(ialu_reg);
8299 %}
8300
8301 // Shift Left by 8-bit immediate
8302 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8303 %{
8304 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8305 effect(KILL cr);
8306
8307 format %{ "sall $dst, $shift" %}
8308 opcode(0xC1, 0x4); /* C1 /4 ib */
8309 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8310 ins_pipe(ialu_mem_imm);
8311 %}
8312
8313 // Shift Left by variable
8314 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8315 %{
8316 match(Set dst (LShiftI dst shift));
8317 effect(KILL cr);
8318
8319 format %{ "sall $dst, $shift" %}
8320 opcode(0xD3, 0x4); /* D3 /4 */
8321 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8322 ins_pipe(ialu_reg_reg);
8323 %}
8324
8325 // Shift Left by variable
8326 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8327 %{
8328 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8329 effect(KILL cr);
8330
8331 format %{ "sall $dst, $shift" %}
8332 opcode(0xD3, 0x4); /* D3 /4 */
8333 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8334 ins_pipe(ialu_mem_reg);
8335 %}
8336
8337 // Arithmetic shift right by one
8338 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8339 %{
8340 match(Set dst (RShiftI dst shift));
8341 effect(KILL cr);
8342
8343 format %{ "sarl $dst, $shift" %}
8344 opcode(0xD1, 0x7); /* D1 /7 */
8345 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8346 ins_pipe(ialu_reg);
8347 %}
8348
8349 // Arithmetic shift right by one
8350 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8351 %{
8352 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8353 effect(KILL cr);
8354
8355 format %{ "sarl $dst, $shift" %}
8356 opcode(0xD1, 0x7); /* D1 /7 */
8357 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8358 ins_pipe(ialu_mem_imm);
8359 %}
8360
8361 // Arithmetic Shift Right by 8-bit immediate
8362 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8363 %{
8364 match(Set dst (RShiftI dst shift));
8365 effect(KILL cr);
8366
8367 format %{ "sarl $dst, $shift" %}
8368 opcode(0xC1, 0x7); /* C1 /7 ib */
8369 ins_encode(reg_opc_imm(dst, shift));
8370 ins_pipe(ialu_mem_imm);
8371 %}
8372
8373 // Arithmetic Shift Right by 8-bit immediate
8374 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8375 %{
8376 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8377 effect(KILL cr);
8378
8379 format %{ "sarl $dst, $shift" %}
8380 opcode(0xC1, 0x7); /* C1 /7 ib */
8381 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8382 ins_pipe(ialu_mem_imm);
8383 %}
8384
8385 // Arithmetic Shift Right by variable
8386 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8387 %{
8388 match(Set dst (RShiftI dst shift));
8389 effect(KILL cr);
8390
8391 format %{ "sarl $dst, $shift" %}
8392 opcode(0xD3, 0x7); /* D3 /7 */
8393 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8394 ins_pipe(ialu_reg_reg);
8395 %}
8396
8397 // Arithmetic Shift Right by variable
8398 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8399 %{
8400 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8401 effect(KILL cr);
8402
8403 format %{ "sarl $dst, $shift" %}
8404 opcode(0xD3, 0x7); /* D3 /7 */
8405 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8406 ins_pipe(ialu_mem_reg);
8407 %}
8408
8409 // Logical shift right by one
8410 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8411 %{
8412 match(Set dst (URShiftI dst shift));
8413 effect(KILL cr);
8414
8415 format %{ "shrl $dst, $shift" %}
8416 opcode(0xD1, 0x5); /* D1 /5 */
8417 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8418 ins_pipe(ialu_reg);
8419 %}
8420
8421 // Logical shift right by one
8422 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8423 %{
8424 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8425 effect(KILL cr);
8426
8427 format %{ "shrl $dst, $shift" %}
8428 opcode(0xD1, 0x5); /* D1 /5 */
8429 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8430 ins_pipe(ialu_mem_imm);
8431 %}
8432
8433 // Logical Shift Right by 8-bit immediate
8434 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8435 %{
8436 match(Set dst (URShiftI dst shift));
8437 effect(KILL cr);
8438
8439 format %{ "shrl $dst, $shift" %}
8440 opcode(0xC1, 0x5); /* C1 /5 ib */
8441 ins_encode(reg_opc_imm(dst, shift));
8442 ins_pipe(ialu_reg);
8443 %}
8444
8445 // Logical Shift Right by 8-bit immediate
8446 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8447 %{
8448 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8449 effect(KILL cr);
8450
8451 format %{ "shrl $dst, $shift" %}
8452 opcode(0xC1, 0x5); /* C1 /5 ib */
8453 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8454 ins_pipe(ialu_mem_imm);
8455 %}
8456
8457 // Logical Shift Right by variable
8458 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8459 %{
8460 match(Set dst (URShiftI dst shift));
8461 effect(KILL cr);
8462
8463 format %{ "shrl $dst, $shift" %}
8464 opcode(0xD3, 0x5); /* D3 /5 */
8465 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8466 ins_pipe(ialu_reg_reg);
8467 %}
8468
8469 // Logical Shift Right by variable
8470 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8471 %{
8472 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8473 effect(KILL cr);
8474
8475 format %{ "shrl $dst, $shift" %}
8476 opcode(0xD3, 0x5); /* D3 /5 */
8477 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8478 ins_pipe(ialu_mem_reg);
8479 %}
8480
8481 // Long Shift Instructions
8482 // Shift Left by one
8483 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8484 %{
8485 match(Set dst (LShiftL dst shift));
8486 effect(KILL cr);
8487
8488 format %{ "salq $dst, $shift" %}
8489 opcode(0xD1, 0x4); /* D1 /4 */
8490 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8491 ins_pipe(ialu_reg);
8492 %}
8493
8494 // Shift Left by one
8495 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8496 %{
8497 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8498 effect(KILL cr);
8499
8500 format %{ "salq $dst, $shift" %}
8501 opcode(0xD1, 0x4); /* D1 /4 */
8502 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8503 ins_pipe(ialu_mem_imm);
8504 %}
8505
8506 // Shift Left by 8-bit immediate
8507 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8508 %{
8509 match(Set dst (LShiftL dst shift));
8510 effect(KILL cr);
8511
8512 format %{ "salq $dst, $shift" %}
8513 opcode(0xC1, 0x4); /* C1 /4 ib */
8514 ins_encode(reg_opc_imm_wide(dst, shift));
8515 ins_pipe(ialu_reg);
8516 %}
8517
8518 // Shift Left by 8-bit immediate
8519 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8520 %{
8521 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8522 effect(KILL cr);
8523
8524 format %{ "salq $dst, $shift" %}
8525 opcode(0xC1, 0x4); /* C1 /4 ib */
8526 ins_encode(REX_mem_wide(dst), OpcP,
8527 RM_opc_mem(secondary, dst), Con8or32(shift));
8528 ins_pipe(ialu_mem_imm);
8529 %}
8530
8531 // Shift Left by variable
8532 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8533 %{
8534 match(Set dst (LShiftL dst shift));
8535 effect(KILL cr);
8536
8537 format %{ "salq $dst, $shift" %}
8538 opcode(0xD3, 0x4); /* D3 /4 */
8539 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8540 ins_pipe(ialu_reg_reg);
8541 %}
8542
8543 // Shift Left by variable
8544 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8545 %{
8546 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8547 effect(KILL cr);
8548
8549 format %{ "salq $dst, $shift" %}
8550 opcode(0xD3, 0x4); /* D3 /4 */
8551 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8552 ins_pipe(ialu_mem_reg);
8553 %}
8554
8555 // Arithmetic shift right by one
8556 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8557 %{
8558 match(Set dst (RShiftL dst shift));
8559 effect(KILL cr);
8560
8561 format %{ "sarq $dst, $shift" %}
8562 opcode(0xD1, 0x7); /* D1 /7 */
8563 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8564 ins_pipe(ialu_reg);
8565 %}
8566
8567 // Arithmetic shift right by one
8568 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8569 %{
8570 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8571 effect(KILL cr);
8572
8573 format %{ "sarq $dst, $shift" %}
8574 opcode(0xD1, 0x7); /* D1 /7 */
8575 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8576 ins_pipe(ialu_mem_imm);
8577 %}
8578
8579 // Arithmetic Shift Right by 8-bit immediate
8580 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8581 %{
8582 match(Set dst (RShiftL dst shift));
8583 effect(KILL cr);
8584
8585 format %{ "sarq $dst, $shift" %}
8586 opcode(0xC1, 0x7); /* C1 /7 ib */
8587 ins_encode(reg_opc_imm_wide(dst, shift));
8588 ins_pipe(ialu_mem_imm);
8589 %}
8590
8591 // Arithmetic Shift Right by 8-bit immediate
8592 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8593 %{
8594 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8595 effect(KILL cr);
8596
8597 format %{ "sarq $dst, $shift" %}
8598 opcode(0xC1, 0x7); /* C1 /7 ib */
8599 ins_encode(REX_mem_wide(dst), OpcP,
8600 RM_opc_mem(secondary, dst), Con8or32(shift));
8601 ins_pipe(ialu_mem_imm);
8602 %}
8603
8604 // Arithmetic Shift Right by variable
8605 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8606 %{
8607 match(Set dst (RShiftL dst shift));
8608 effect(KILL cr);
8609
8610 format %{ "sarq $dst, $shift" %}
8611 opcode(0xD3, 0x7); /* D3 /7 */
8612 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8613 ins_pipe(ialu_reg_reg);
8614 %}
8615
8616 // Arithmetic Shift Right by variable
8617 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8618 %{
8619 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8620 effect(KILL cr);
8621
8622 format %{ "sarq $dst, $shift" %}
8623 opcode(0xD3, 0x7); /* D3 /7 */
8624 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8625 ins_pipe(ialu_mem_reg);
8626 %}
8627
8628 // Logical shift right by one
8629 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8630 %{
8631 match(Set dst (URShiftL dst shift));
8632 effect(KILL cr);
8633
8634 format %{ "shrq $dst, $shift" %}
8635 opcode(0xD1, 0x5); /* D1 /5 */
8636 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8637 ins_pipe(ialu_reg);
8638 %}
8639
8640 // Logical shift right by one
8641 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8642 %{
8643 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8644 effect(KILL cr);
8645
8646 format %{ "shrq $dst, $shift" %}
8647 opcode(0xD1, 0x5); /* D1 /5 */
8648 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8649 ins_pipe(ialu_mem_imm);
8650 %}
8651
8652 // Logical Shift Right by 8-bit immediate
8653 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8654 %{
8655 match(Set dst (URShiftL dst shift));
8656 effect(KILL cr);
8657
8658 format %{ "shrq $dst, $shift" %}
8659 opcode(0xC1, 0x5); /* C1 /5 ib */
8660 ins_encode(reg_opc_imm_wide(dst, shift));
8661 ins_pipe(ialu_reg);
8662 %}
8663
8664 // Logical Shift Right by 8-bit immediate
8665 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8666 %{
8667 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8668 effect(KILL cr);
8669
8670 format %{ "shrq $dst, $shift" %}
8671 opcode(0xC1, 0x5); /* C1 /5 ib */
8672 ins_encode(REX_mem_wide(dst), OpcP,
8673 RM_opc_mem(secondary, dst), Con8or32(shift));
8674 ins_pipe(ialu_mem_imm);
8675 %}
8676
8677 // Logical Shift Right by variable
8678 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8679 %{
8680 match(Set dst (URShiftL dst shift));
8681 effect(KILL cr);
8682
8683 format %{ "shrq $dst, $shift" %}
8684 opcode(0xD3, 0x5); /* D3 /5 */
8685 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8686 ins_pipe(ialu_reg_reg);
8687 %}
8688
8689 // Logical Shift Right by variable
8690 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8691 %{
8692 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8693 effect(KILL cr);
8694
8695 format %{ "shrq $dst, $shift" %}
8696 opcode(0xD3, 0x5); /* D3 /5 */
8697 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8698 ins_pipe(ialu_mem_reg);
8699 %}
8700
8701 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8702 // This idiom is used by the compiler for the i2b bytecode.
8703 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8704 %{
8705 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8706
8707 format %{ "movsbl $dst, $src\t# i2b" %}
8708 opcode(0x0F, 0xBE);
8709 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8710 ins_pipe(ialu_reg_reg);
8711 %}
8712
8713 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8714 // This idiom is used by the compiler the i2s bytecode.
8715 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8716 %{
8717 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8718
8719 format %{ "movswl $dst, $src\t# i2s" %}
8720 opcode(0x0F, 0xBF);
8721 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8722 ins_pipe(ialu_reg_reg);
8723 %}
8724
8725 // ROL/ROR instructions
8726
8727 // ROL expand
8728 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8729 effect(KILL cr, USE_DEF dst);
8730
8731 format %{ "roll $dst" %}
8732 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8733 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8734 ins_pipe(ialu_reg);
8735 %}
8736
8737 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8738 effect(USE_DEF dst, USE shift, KILL cr);
8739
8740 format %{ "roll $dst, $shift" %}
8741 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8742 ins_encode( reg_opc_imm(dst, shift) );
8743 ins_pipe(ialu_reg);
8744 %}
8745
8746 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8747 %{
8748 effect(USE_DEF dst, USE shift, KILL cr);
8749
8750 format %{ "roll $dst, $shift" %}
8751 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8752 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8753 ins_pipe(ialu_reg_reg);
8754 %}
8755 // end of ROL expand
8756
8757 // Rotate Left by one
8758 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8759 %{
8760 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8761
8762 expand %{
8763 rolI_rReg_imm1(dst, cr);
8764 %}
8765 %}
8766
8767 // Rotate Left by 8-bit immediate
8768 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8769 %{
8770 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8771 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8772
8773 expand %{
8774 rolI_rReg_imm8(dst, lshift, cr);
8775 %}
8776 %}
8777
8778 // Rotate Left by variable
8779 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8780 %{
8781 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8782
8783 expand %{
8784 rolI_rReg_CL(dst, shift, cr);
8785 %}
8786 %}
8787
8788 // Rotate Left by variable
8789 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8790 %{
8791 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8792
8793 expand %{
8794 rolI_rReg_CL(dst, shift, cr);
8795 %}
8796 %}
8797
8798 // ROR expand
8799 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8800 %{
8801 effect(USE_DEF dst, KILL cr);
8802
8803 format %{ "rorl $dst" %}
8804 opcode(0xD1, 0x1); /* D1 /1 */
8805 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8806 ins_pipe(ialu_reg);
8807 %}
8808
8809 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8810 %{
8811 effect(USE_DEF dst, USE shift, KILL cr);
8812
8813 format %{ "rorl $dst, $shift" %}
8814 opcode(0xC1, 0x1); /* C1 /1 ib */
8815 ins_encode(reg_opc_imm(dst, shift));
8816 ins_pipe(ialu_reg);
8817 %}
8818
8819 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8820 %{
8821 effect(USE_DEF dst, USE shift, KILL cr);
8822
8823 format %{ "rorl $dst, $shift" %}
8824 opcode(0xD3, 0x1); /* D3 /1 */
8825 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8826 ins_pipe(ialu_reg_reg);
8827 %}
8828 // end of ROR expand
8829
8830 // Rotate Right by one
8831 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8832 %{
8833 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8834
8835 expand %{
8836 rorI_rReg_imm1(dst, cr);
8837 %}
8838 %}
8839
8840 // Rotate Right by 8-bit immediate
8841 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8842 %{
8843 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8844 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8845
8846 expand %{
8847 rorI_rReg_imm8(dst, rshift, cr);
8848 %}
8849 %}
8850
8851 // Rotate Right by variable
8852 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8853 %{
8854 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8855
8856 expand %{
8857 rorI_rReg_CL(dst, shift, cr);
8858 %}
8859 %}
8860
8861 // Rotate Right by variable
8862 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8863 %{
8864 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8865
8866 expand %{
8867 rorI_rReg_CL(dst, shift, cr);
8868 %}
8869 %}
8870
8871 // for long rotate
8872 // ROL expand
8873 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8874 effect(USE_DEF dst, KILL cr);
8875
8876 format %{ "rolq $dst" %}
8877 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8878 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8879 ins_pipe(ialu_reg);
8880 %}
8881
8882 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8883 effect(USE_DEF dst, USE shift, KILL cr);
8884
8885 format %{ "rolq $dst, $shift" %}
8886 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8887 ins_encode( reg_opc_imm_wide(dst, shift) );
8888 ins_pipe(ialu_reg);
8889 %}
8890
8891 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8892 %{
8893 effect(USE_DEF dst, USE shift, KILL cr);
8894
8895 format %{ "rolq $dst, $shift" %}
8896 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8897 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8898 ins_pipe(ialu_reg_reg);
8899 %}
8900 // end of ROL expand
8901
8902 // Rotate Left by one
8903 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8904 %{
8905 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8906
8907 expand %{
8908 rolL_rReg_imm1(dst, cr);
8909 %}
8910 %}
8911
8912 // Rotate Left by 8-bit immediate
8913 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8914 %{
8915 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8916 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8917
8918 expand %{
8919 rolL_rReg_imm8(dst, lshift, cr);
8920 %}
8921 %}
8922
8923 // Rotate Left by variable
8924 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8925 %{
8926 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8927
8928 expand %{
8929 rolL_rReg_CL(dst, shift, cr);
8930 %}
8931 %}
8932
8933 // Rotate Left by variable
8934 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8935 %{
8936 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8937
8938 expand %{
8939 rolL_rReg_CL(dst, shift, cr);
8940 %}
8941 %}
8942
8943 // ROR expand
8944 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8945 %{
8946 effect(USE_DEF dst, KILL cr);
8947
8948 format %{ "rorq $dst" %}
8949 opcode(0xD1, 0x1); /* D1 /1 */
8950 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8951 ins_pipe(ialu_reg);
8952 %}
8953
8954 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8955 %{
8956 effect(USE_DEF dst, USE shift, KILL cr);
8957
8958 format %{ "rorq $dst, $shift" %}
8959 opcode(0xC1, 0x1); /* C1 /1 ib */
8960 ins_encode(reg_opc_imm_wide(dst, shift));
8961 ins_pipe(ialu_reg);
8962 %}
8963
8964 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8965 %{
8966 effect(USE_DEF dst, USE shift, KILL cr);
8967
8968 format %{ "rorq $dst, $shift" %}
8969 opcode(0xD3, 0x1); /* D3 /1 */
8970 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8971 ins_pipe(ialu_reg_reg);
8972 %}
8973 // end of ROR expand
8974
8975 // Rotate Right by one
8976 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8977 %{
8978 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8979
8980 expand %{
8981 rorL_rReg_imm1(dst, cr);
8982 %}
8983 %}
8984
8985 // Rotate Right by 8-bit immediate
8986 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8987 %{
8988 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8989 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8990
8991 expand %{
8992 rorL_rReg_imm8(dst, rshift, cr);
8993 %}
8994 %}
8995
8996 // Rotate Right by variable
8997 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8998 %{
8999 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9000
9001 expand %{
9002 rorL_rReg_CL(dst, shift, cr);
9003 %}
9004 %}
9005
9006 // Rotate Right by variable
9007 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9008 %{
9009 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9010
9011 expand %{
9012 rorL_rReg_CL(dst, shift, cr);
9013 %}
9014 %}
9015
9016 // Logical Instructions
9017
9018 // Integer Logical Instructions
9019
9020 // And Instructions
9021 // And Register with Register
9022 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9023 %{
9024 match(Set dst (AndI dst src));
9025 effect(KILL cr);
9026
9027 format %{ "andl $dst, $src\t# int" %}
9028 opcode(0x23);
9029 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9030 ins_pipe(ialu_reg_reg);
9031 %}
9032
9033 // And Register with Immediate 255
9034 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9035 %{
9036 match(Set dst (AndI dst src));
9037
9038 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9039 opcode(0x0F, 0xB6);
9040 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9041 ins_pipe(ialu_reg);
9042 %}
9043
9044 // And Register with Immediate 255 and promote to long
9045 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9046 %{
9047 match(Set dst (ConvI2L (AndI src mask)));
9048
9049 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9050 opcode(0x0F, 0xB6);
9051 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9052 ins_pipe(ialu_reg);
9053 %}
9054
9055 // And Register with Immediate 65535
9056 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9057 %{
9058 match(Set dst (AndI dst src));
9059
9060 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9061 opcode(0x0F, 0xB7);
9062 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9063 ins_pipe(ialu_reg);
9064 %}
9065
9066 // And Register with Immediate 65535 and promote to long
9067 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9068 %{
9069 match(Set dst (ConvI2L (AndI src mask)));
9070
9071 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9072 opcode(0x0F, 0xB7);
9073 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9074 ins_pipe(ialu_reg);
9075 %}
9076
9077 // And Register with Immediate
9078 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9079 %{
9080 match(Set dst (AndI dst src));
9081 effect(KILL cr);
9082
9083 format %{ "andl $dst, $src\t# int" %}
9084 opcode(0x81, 0x04); /* Opcode 81 /4 */
9085 ins_encode(OpcSErm(dst, src), Con8or32(src));
9086 ins_pipe(ialu_reg);
9087 %}
9088
9089 // And Register with Memory
9090 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9091 %{
9092 match(Set dst (AndI dst (LoadI src)));
9093 effect(KILL cr);
9094
9095 ins_cost(125);
9096 format %{ "andl $dst, $src\t# int" %}
9097 opcode(0x23);
9098 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9099 ins_pipe(ialu_reg_mem);
9100 %}
9101
9102 // And Memory with Register
9103 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9104 %{
9105 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9106 effect(KILL cr);
9107
9108 ins_cost(150);
9109 format %{ "andl $dst, $src\t# int" %}
9110 opcode(0x21); /* Opcode 21 /r */
9111 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9112 ins_pipe(ialu_mem_reg);
9113 %}
9114
9115 // And Memory with Immediate
9116 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9117 %{
9118 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9119 effect(KILL cr);
9120
9121 ins_cost(125);
9122 format %{ "andl $dst, $src\t# int" %}
9123 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9124 ins_encode(REX_mem(dst), OpcSE(src),
9125 RM_opc_mem(secondary, dst), Con8or32(src));
9126 ins_pipe(ialu_mem_imm);
9127 %}
9128
9129 // Or Instructions
9130 // Or Register with Register
9131 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9132 %{
9133 match(Set dst (OrI dst src));
9134 effect(KILL cr);
9135
9136 format %{ "orl $dst, $src\t# int" %}
9137 opcode(0x0B);
9138 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9139 ins_pipe(ialu_reg_reg);
9140 %}
9141
9142 // Or Register with Immediate
9143 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9144 %{
9145 match(Set dst (OrI dst src));
9146 effect(KILL cr);
9147
9148 format %{ "orl $dst, $src\t# int" %}
9149 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9150 ins_encode(OpcSErm(dst, src), Con8or32(src));
9151 ins_pipe(ialu_reg);
9152 %}
9153
9154 // Or Register with Memory
9155 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9156 %{
9157 match(Set dst (OrI dst (LoadI src)));
9158 effect(KILL cr);
9159
9160 ins_cost(125);
9161 format %{ "orl $dst, $src\t# int" %}
9162 opcode(0x0B);
9163 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9164 ins_pipe(ialu_reg_mem);
9165 %}
9166
9167 // Or Memory with Register
9168 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9169 %{
9170 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9171 effect(KILL cr);
9172
9173 ins_cost(150);
9174 format %{ "orl $dst, $src\t# int" %}
9175 opcode(0x09); /* Opcode 09 /r */
9176 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9177 ins_pipe(ialu_mem_reg);
9178 %}
9179
9180 // Or Memory with Immediate
9181 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9182 %{
9183 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9184 effect(KILL cr);
9185
9186 ins_cost(125);
9187 format %{ "orl $dst, $src\t# int" %}
9188 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9189 ins_encode(REX_mem(dst), OpcSE(src),
9190 RM_opc_mem(secondary, dst), Con8or32(src));
9191 ins_pipe(ialu_mem_imm);
9192 %}
9193
9194 // Xor Instructions
9195 // Xor Register with Register
9196 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9197 %{
9198 match(Set dst (XorI dst src));
9199 effect(KILL cr);
9200
9201 format %{ "xorl $dst, $src\t# int" %}
9202 opcode(0x33);
9203 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9204 ins_pipe(ialu_reg_reg);
9205 %}
9206
9207 // Xor Register with Immediate
9208 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9209 %{
9210 match(Set dst (XorI dst src));
9211 effect(KILL cr);
9212
9213 format %{ "xorl $dst, $src\t# int" %}
9214 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9215 ins_encode(OpcSErm(dst, src), Con8or32(src));
9216 ins_pipe(ialu_reg);
9217 %}
9218
9219 // Xor Register with Memory
9220 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9221 %{
9222 match(Set dst (XorI dst (LoadI src)));
9223 effect(KILL cr);
9224
9225 ins_cost(125);
9226 format %{ "xorl $dst, $src\t# int" %}
9227 opcode(0x33);
9228 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9229 ins_pipe(ialu_reg_mem);
9230 %}
9231
9232 // Xor Memory with Register
9233 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9234 %{
9235 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9236 effect(KILL cr);
9237
9238 ins_cost(150);
9239 format %{ "xorl $dst, $src\t# int" %}
9240 opcode(0x31); /* Opcode 31 /r */
9241 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9242 ins_pipe(ialu_mem_reg);
9243 %}
9244
9245 // Xor Memory with Immediate
9246 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9247 %{
9248 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9249 effect(KILL cr);
9250
9251 ins_cost(125);
9252 format %{ "xorl $dst, $src\t# int" %}
9253 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9254 ins_encode(REX_mem(dst), OpcSE(src),
9255 RM_opc_mem(secondary, dst), Con8or32(src));
9256 ins_pipe(ialu_mem_imm);
9257 %}
9258
9259
9260 // Long Logical Instructions
9261
9262 // And Instructions
9263 // And Register with Register
9264 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9265 %{
9266 match(Set dst (AndL dst src));
9267 effect(KILL cr);
9268
9269 format %{ "andq $dst, $src\t# long" %}
9270 opcode(0x23);
9271 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9272 ins_pipe(ialu_reg_reg);
9273 %}
9274
9275 // And Register with Immediate 255
9276 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9277 %{
9278 match(Set dst (AndL dst src));
9279
9280 format %{ "movzbq $dst, $src\t# long & 0xFF" %}
9281 opcode(0x0F, 0xB6);
9282 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9283 ins_pipe(ialu_reg);
9284 %}
9285
9286 // And Register with Immediate 65535
9287 instruct andL_rReg_imm65535(rRegI dst, immL_65535 src)
9288 %{
9289 match(Set dst (AndL dst src));
9290
9291 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9292 opcode(0x0F, 0xB7);
9293 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9294 ins_pipe(ialu_reg);
9295 %}
9296
9297 // And Register with Immediate
9298 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9299 %{
9300 match(Set dst (AndL dst src));
9301 effect(KILL cr);
9302
9303 format %{ "andq $dst, $src\t# long" %}
9304 opcode(0x81, 0x04); /* Opcode 81 /4 */
9305 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9306 ins_pipe(ialu_reg);
9307 %}
9308
9309 // And Register with Memory
9310 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9311 %{
9312 match(Set dst (AndL dst (LoadL src)));
9313 effect(KILL cr);
9314
9315 ins_cost(125);
9316 format %{ "andq $dst, $src\t# long" %}
9317 opcode(0x23);
9318 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9319 ins_pipe(ialu_reg_mem);
9320 %}
9321
9322 // And Memory with Register
9323 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9324 %{
9325 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9326 effect(KILL cr);
9327
9328 ins_cost(150);
9329 format %{ "andq $dst, $src\t# long" %}
9330 opcode(0x21); /* Opcode 21 /r */
9331 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9332 ins_pipe(ialu_mem_reg);
9333 %}
9334
9335 // And Memory with Immediate
9336 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9337 %{
9338 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9339 effect(KILL cr);
9340
9341 ins_cost(125);
9342 format %{ "andq $dst, $src\t# long" %}
9343 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9344 ins_encode(REX_mem_wide(dst), OpcSE(src),
9345 RM_opc_mem(secondary, dst), Con8or32(src));
9346 ins_pipe(ialu_mem_imm);
9347 %}
9348
9349 // Or Instructions
9350 // Or Register with Register
9351 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9352 %{
9353 match(Set dst (OrL dst src));
9354 effect(KILL cr);
9355
9356 format %{ "orq $dst, $src\t# long" %}
9357 opcode(0x0B);
9358 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9359 ins_pipe(ialu_reg_reg);
9360 %}
9361
9362 // Or Register with Immediate
9363 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9364 %{
9365 match(Set dst (OrL dst src));
9366 effect(KILL cr);
9367
9368 format %{ "orq $dst, $src\t# long" %}
9369 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9370 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9371 ins_pipe(ialu_reg);
9372 %}
9373
9374 // Or Register with Memory
9375 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9376 %{
9377 match(Set dst (OrL dst (LoadL src)));
9378 effect(KILL cr);
9379
9380 ins_cost(125);
9381 format %{ "orq $dst, $src\t# long" %}
9382 opcode(0x0B);
9383 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9384 ins_pipe(ialu_reg_mem);
9385 %}
9386
9387 // Or Memory with Register
9388 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9389 %{
9390 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9391 effect(KILL cr);
9392
9393 ins_cost(150);
9394 format %{ "orq $dst, $src\t# long" %}
9395 opcode(0x09); /* Opcode 09 /r */
9396 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9397 ins_pipe(ialu_mem_reg);
9398 %}
9399
9400 // Or Memory with Immediate
9401 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9402 %{
9403 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9404 effect(KILL cr);
9405
9406 ins_cost(125);
9407 format %{ "orq $dst, $src\t# long" %}
9408 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9409 ins_encode(REX_mem_wide(dst), OpcSE(src),
9410 RM_opc_mem(secondary, dst), Con8or32(src));
9411 ins_pipe(ialu_mem_imm);
9412 %}
9413
9414 // Xor Instructions
9415 // Xor Register with Register
9416 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9417 %{
9418 match(Set dst (XorL dst src));
9419 effect(KILL cr);
9420
9421 format %{ "xorq $dst, $src\t# long" %}
9422 opcode(0x33);
9423 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9424 ins_pipe(ialu_reg_reg);
9425 %}
9426
9427 // Xor Register with Immediate
9428 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9429 %{
9430 match(Set dst (XorL dst src));
9431 effect(KILL cr);
9432
9433 format %{ "xorq $dst, $src\t# long" %}
9434 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9435 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9436 ins_pipe(ialu_reg);
9437 %}
9438
9439 // Xor Register with Memory
9440 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9441 %{
9442 match(Set dst (XorL dst (LoadL src)));
9443 effect(KILL cr);
9444
9445 ins_cost(125);
9446 format %{ "xorq $dst, $src\t# long" %}
9447 opcode(0x33);
9448 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9449 ins_pipe(ialu_reg_mem);
9450 %}
9451
9452 // Xor Memory with Register
9453 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9454 %{
9455 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9456 effect(KILL cr);
9457
9458 ins_cost(150);
9459 format %{ "xorq $dst, $src\t# long" %}
9460 opcode(0x31); /* Opcode 31 /r */
9461 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9462 ins_pipe(ialu_mem_reg);
9463 %}
9464
9465 // Xor Memory with Immediate
9466 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9467 %{
9468 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9469 effect(KILL cr);
9470
9471 ins_cost(125);
9472 format %{ "xorq $dst, $src\t# long" %}
9473 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9474 ins_encode(REX_mem_wide(dst), OpcSE(src),
9475 RM_opc_mem(secondary, dst), Con8or32(src));
9476 ins_pipe(ialu_mem_imm);
9477 %}
9478
9479 // Convert Int to Boolean
9480 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9481 %{
9482 match(Set dst (Conv2B src));
9483 effect(KILL cr);
9484
9485 format %{ "testl $src, $src\t# ci2b\n\t"
9486 "setnz $dst\n\t"
9487 "movzbl $dst, $dst" %}
9488 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9489 setNZ_reg(dst),
9490 REX_reg_breg(dst, dst), // movzbl
9491 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9492 ins_pipe(pipe_slow); // XXX
9493 %}
9494
9495 // Convert Pointer to Boolean
9496 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9497 %{
9498 match(Set dst (Conv2B src));
9499 effect(KILL cr);
9500
9501 format %{ "testq $src, $src\t# cp2b\n\t"
9502 "setnz $dst\n\t"
9503 "movzbl $dst, $dst" %}
9504 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9505 setNZ_reg(dst),
9506 REX_reg_breg(dst, dst), // movzbl
9507 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9508 ins_pipe(pipe_slow); // XXX
9509 %}
9510
9511 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9512 %{
9513 match(Set dst (CmpLTMask p q));
9514 effect(KILL cr);
9515
9516 ins_cost(400); // XXX
9517 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9518 "setlt $dst\n\t"
9519 "movzbl $dst, $dst\n\t"
9520 "negl $dst" %}
9521 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9522 setLT_reg(dst),
9523 REX_reg_breg(dst, dst), // movzbl
9524 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9525 neg_reg(dst));
9526 ins_pipe(pipe_slow);
9527 %}
9528
9529 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9530 %{
9531 match(Set dst (CmpLTMask dst zero));
9532 effect(KILL cr);
9533
9534 ins_cost(100); // XXX
9535 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9536 opcode(0xC1, 0x7); /* C1 /7 ib */
9537 ins_encode(reg_opc_imm(dst, 0x1F));
9538 ins_pipe(ialu_reg);
9539 %}
9540
9541
9542 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y,
9543 rRegI tmp,
9544 rFlagsReg cr)
9545 %{
9546 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9547 effect(TEMP tmp, KILL cr);
9548
9549 ins_cost(400); // XXX
9550 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
9551 "sbbl $tmp, $tmp\n\t"
9552 "andl $tmp, $y\n\t"
9553 "addl $p, $tmp" %}
9554 ins_encode(enc_cmpLTP(p, q, y, tmp));
9555 ins_pipe(pipe_cmplt);
9556 %}
9557
9558 /* If I enable this, I encourage spilling in the inner loop of compress.
9559 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
9560 %{
9561 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9562 effect( TEMP tmp, KILL cr );
9563 ins_cost(400);
9564
9565 format %{ "SUB $p,$q\n\t"
9566 "SBB RCX,RCX\n\t"
9567 "AND RCX,$y\n\t"
9568 "ADD $p,RCX" %}
9569 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9570 %}
9571 */
9572
9573 //---------- FP Instructions------------------------------------------------
9574
9575 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9576 %{
9577 match(Set cr (CmpF src1 src2));
9578
9579 ins_cost(145);
9580 format %{ "ucomiss $src1, $src2\n\t"
9581 "jnp,s exit\n\t"
9582 "pushfq\t# saw NaN, set CF\n\t"
9583 "andq [rsp], #0xffffff2b\n\t"
9584 "popfq\n"
9585 "exit: nop\t# avoid branch to branch" %}
9586 opcode(0x0F, 0x2E);
9587 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
9588 cmpfp_fixup);
9589 ins_pipe(pipe_slow);
9590 %}
9591
9592 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9593 %{
9594 match(Set cr (CmpF src1 (LoadF src2)));
9595
9596 ins_cost(145);
9597 format %{ "ucomiss $src1, $src2\n\t"
9598 "jnp,s exit\n\t"
9599 "pushfq\t# saw NaN, set CF\n\t"
9600 "andq [rsp], #0xffffff2b\n\t"
9601 "popfq\n"
9602 "exit: nop\t# avoid branch to branch" %}
9603 opcode(0x0F, 0x2E);
9604 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
9605 cmpfp_fixup);
9606 ins_pipe(pipe_slow);
9607 %}
9608
9609 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2)
9610 %{
9611 match(Set cr (CmpF src1 src2));
9612
9613 ins_cost(145);
9614 format %{ "ucomiss $src1, $src2\n\t"
9615 "jnp,s exit\n\t"
9616 "pushfq\t# saw NaN, set CF\n\t"
9617 "andq [rsp], #0xffffff2b\n\t"
9618 "popfq\n"
9619 "exit: nop\t# avoid branch to branch" %}
9620 opcode(0x0F, 0x2E);
9621 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
9622 cmpfp_fixup);
9623 ins_pipe(pipe_slow);
9624 %}
9625
9626 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9627 %{
9628 match(Set cr (CmpD src1 src2));
9629
9630 ins_cost(145);
9631 format %{ "ucomisd $src1, $src2\n\t"
9632 "jnp,s exit\n\t"
9633 "pushfq\t# saw NaN, set CF\n\t"
9634 "andq [rsp], #0xffffff2b\n\t"
9635 "popfq\n"
9636 "exit: nop\t# avoid branch to branch" %}
9637 opcode(0x66, 0x0F, 0x2E);
9638 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
9639 cmpfp_fixup);
9640 ins_pipe(pipe_slow);
9641 %}
9642
9643 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9644 %{
9645 match(Set cr (CmpD src1 (LoadD src2)));
9646
9647 ins_cost(145);
9648 format %{ "ucomisd $src1, $src2\n\t"
9649 "jnp,s exit\n\t"
9650 "pushfq\t# saw NaN, set CF\n\t"
9651 "andq [rsp], #0xffffff2b\n\t"
9652 "popfq\n"
9653 "exit: nop\t# avoid branch to branch" %}
9654 opcode(0x66, 0x0F, 0x2E);
9655 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
9656 cmpfp_fixup);
9657 ins_pipe(pipe_slow);
9658 %}
9659
9660 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2)
9661 %{
9662 match(Set cr (CmpD src1 src2));
9663
9664 ins_cost(145);
9665 format %{ "ucomisd $src1, [$src2]\n\t"
9666 "jnp,s exit\n\t"
9667 "pushfq\t# saw NaN, set CF\n\t"
9668 "andq [rsp], #0xffffff2b\n\t"
9669 "popfq\n"
9670 "exit: nop\t# avoid branch to branch" %}
9671 opcode(0x66, 0x0F, 0x2E);
9672 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
9673 cmpfp_fixup);
9674 ins_pipe(pipe_slow);
9675 %}
9676
9677 // Compare into -1,0,1
9678 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9679 %{
9680 match(Set dst (CmpF3 src1 src2));
9681 effect(KILL cr);
9682
9683 ins_cost(275);
9684 format %{ "ucomiss $src1, $src2\n\t"
9685 "movl $dst, #-1\n\t"
9686 "jp,s done\n\t"
9687 "jb,s done\n\t"
9688 "setne $dst\n\t"
9689 "movzbl $dst, $dst\n"
9690 "done:" %}
9691
9692 opcode(0x0F, 0x2E);
9693 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
9694 cmpfp3(dst));
9695 ins_pipe(pipe_slow);
9696 %}
9697
9698 // Compare into -1,0,1
9699 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9700 %{
9701 match(Set dst (CmpF3 src1 (LoadF src2)));
9702 effect(KILL cr);
9703
9704 ins_cost(275);
9705 format %{ "ucomiss $src1, $src2\n\t"
9706 "movl $dst, #-1\n\t"
9707 "jp,s done\n\t"
9708 "jb,s done\n\t"
9709 "setne $dst\n\t"
9710 "movzbl $dst, $dst\n"
9711 "done:" %}
9712
9713 opcode(0x0F, 0x2E);
9714 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
9715 cmpfp3(dst));
9716 ins_pipe(pipe_slow);
9717 %}
9718
9719 // Compare into -1,0,1
9720 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr)
9721 %{
9722 match(Set dst (CmpF3 src1 src2));
9723 effect(KILL cr);
9724
9725 ins_cost(275);
9726 format %{ "ucomiss $src1, [$src2]\n\t"
9727 "movl $dst, #-1\n\t"
9728 "jp,s done\n\t"
9729 "jb,s done\n\t"
9730 "setne $dst\n\t"
9731 "movzbl $dst, $dst\n"
9732 "done:" %}
9733
9734 opcode(0x0F, 0x2E);
9735 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
9736 cmpfp3(dst));
9737 ins_pipe(pipe_slow);
9738 %}
9739
9740 // Compare into -1,0,1
9741 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9742 %{
9743 match(Set dst (CmpD3 src1 src2));
9744 effect(KILL cr);
9745
9746 ins_cost(275);
9747 format %{ "ucomisd $src1, $src2\n\t"
9748 "movl $dst, #-1\n\t"
9749 "jp,s done\n\t"
9750 "jb,s done\n\t"
9751 "setne $dst\n\t"
9752 "movzbl $dst, $dst\n"
9753 "done:" %}
9754
9755 opcode(0x66, 0x0F, 0x2E);
9756 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
9757 cmpfp3(dst));
9758 ins_pipe(pipe_slow);
9759 %}
9760
9761 // Compare into -1,0,1
9762 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9763 %{
9764 match(Set dst (CmpD3 src1 (LoadD src2)));
9765 effect(KILL cr);
9766
9767 ins_cost(275);
9768 format %{ "ucomisd $src1, $src2\n\t"
9769 "movl $dst, #-1\n\t"
9770 "jp,s done\n\t"
9771 "jb,s done\n\t"
9772 "setne $dst\n\t"
9773 "movzbl $dst, $dst\n"
9774 "done:" %}
9775
9776 opcode(0x66, 0x0F, 0x2E);
9777 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
9778 cmpfp3(dst));
9779 ins_pipe(pipe_slow);
9780 %}
9781
9782 // Compare into -1,0,1
9783 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr)
9784 %{
9785 match(Set dst (CmpD3 src1 src2));
9786 effect(KILL cr);
9787
9788 ins_cost(275);
9789 format %{ "ucomisd $src1, [$src2]\n\t"
9790 "movl $dst, #-1\n\t"
9791 "jp,s done\n\t"
9792 "jb,s done\n\t"
9793 "setne $dst\n\t"
9794 "movzbl $dst, $dst\n"
9795 "done:" %}
9796
9797 opcode(0x66, 0x0F, 0x2E);
9798 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
9799 cmpfp3(dst));
9800 ins_pipe(pipe_slow);
9801 %}
9802
9803 instruct addF_reg(regF dst, regF src)
9804 %{
9805 match(Set dst (AddF dst src));
9806
9807 format %{ "addss $dst, $src" %}
9808 ins_cost(150); // XXX
9809 opcode(0xF3, 0x0F, 0x58);
9810 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9811 ins_pipe(pipe_slow);
9812 %}
9813
9814 instruct addF_mem(regF dst, memory src)
9815 %{
9816 match(Set dst (AddF dst (LoadF src)));
9817
9818 format %{ "addss $dst, $src" %}
9819 ins_cost(150); // XXX
9820 opcode(0xF3, 0x0F, 0x58);
9821 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9822 ins_pipe(pipe_slow);
9823 %}
9824
9825 instruct addF_imm(regF dst, immF src)
9826 %{
9827 match(Set dst (AddF dst src));
9828
9829 format %{ "addss $dst, [$src]" %}
9830 ins_cost(150); // XXX
9831 opcode(0xF3, 0x0F, 0x58);
9832 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
9833 ins_pipe(pipe_slow);
9834 %}
9835
9836 instruct addD_reg(regD dst, regD src)
9837 %{
9838 match(Set dst (AddD dst src));
9839
9840 format %{ "addsd $dst, $src" %}
9841 ins_cost(150); // XXX
9842 opcode(0xF2, 0x0F, 0x58);
9843 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9844 ins_pipe(pipe_slow);
9845 %}
9846
9847 instruct addD_mem(regD dst, memory src)
9848 %{
9849 match(Set dst (AddD dst (LoadD src)));
9850
9851 format %{ "addsd $dst, $src" %}
9852 ins_cost(150); // XXX
9853 opcode(0xF2, 0x0F, 0x58);
9854 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9855 ins_pipe(pipe_slow);
9856 %}
9857
9858 instruct addD_imm(regD dst, immD src)
9859 %{
9860 match(Set dst (AddD dst src));
9861
9862 format %{ "addsd $dst, [$src]" %}
9863 ins_cost(150); // XXX
9864 opcode(0xF2, 0x0F, 0x58);
9865 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
9866 ins_pipe(pipe_slow);
9867 %}
9868
9869 instruct subF_reg(regF dst, regF src)
9870 %{
9871 match(Set dst (SubF dst src));
9872
9873 format %{ "subss $dst, $src" %}
9874 ins_cost(150); // XXX
9875 opcode(0xF3, 0x0F, 0x5C);
9876 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9877 ins_pipe(pipe_slow);
9878 %}
9879
9880 instruct subF_mem(regF dst, memory src)
9881 %{
9882 match(Set dst (SubF dst (LoadF src)));
9883
9884 format %{ "subss $dst, $src" %}
9885 ins_cost(150); // XXX
9886 opcode(0xF3, 0x0F, 0x5C);
9887 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9888 ins_pipe(pipe_slow);
9889 %}
9890
9891 instruct subF_imm(regF dst, immF src)
9892 %{
9893 match(Set dst (SubF dst src));
9894
9895 format %{ "subss $dst, [$src]" %}
9896 ins_cost(150); // XXX
9897 opcode(0xF3, 0x0F, 0x5C);
9898 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
9899 ins_pipe(pipe_slow);
9900 %}
9901
9902 instruct subD_reg(regD dst, regD src)
9903 %{
9904 match(Set dst (SubD dst src));
9905
9906 format %{ "subsd $dst, $src" %}
9907 ins_cost(150); // XXX
9908 opcode(0xF2, 0x0F, 0x5C);
9909 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9910 ins_pipe(pipe_slow);
9911 %}
9912
9913 instruct subD_mem(regD dst, memory src)
9914 %{
9915 match(Set dst (SubD dst (LoadD src)));
9916
9917 format %{ "subsd $dst, $src" %}
9918 ins_cost(150); // XXX
9919 opcode(0xF2, 0x0F, 0x5C);
9920 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9921 ins_pipe(pipe_slow);
9922 %}
9923
9924 instruct subD_imm(regD dst, immD src)
9925 %{
9926 match(Set dst (SubD dst src));
9927
9928 format %{ "subsd $dst, [$src]" %}
9929 ins_cost(150); // XXX
9930 opcode(0xF2, 0x0F, 0x5C);
9931 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
9932 ins_pipe(pipe_slow);
9933 %}
9934
9935 instruct mulF_reg(regF dst, regF src)
9936 %{
9937 match(Set dst (MulF dst src));
9938
9939 format %{ "mulss $dst, $src" %}
9940 ins_cost(150); // XXX
9941 opcode(0xF3, 0x0F, 0x59);
9942 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9943 ins_pipe(pipe_slow);
9944 %}
9945
9946 instruct mulF_mem(regF dst, memory src)
9947 %{
9948 match(Set dst (MulF dst (LoadF src)));
9949
9950 format %{ "mulss $dst, $src" %}
9951 ins_cost(150); // XXX
9952 opcode(0xF3, 0x0F, 0x59);
9953 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9954 ins_pipe(pipe_slow);
9955 %}
9956
9957 instruct mulF_imm(regF dst, immF src)
9958 %{
9959 match(Set dst (MulF dst src));
9960
9961 format %{ "mulss $dst, [$src]" %}
9962 ins_cost(150); // XXX
9963 opcode(0xF3, 0x0F, 0x59);
9964 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
9965 ins_pipe(pipe_slow);
9966 %}
9967
9968 instruct mulD_reg(regD dst, regD src)
9969 %{
9970 match(Set dst (MulD dst src));
9971
9972 format %{ "mulsd $dst, $src" %}
9973 ins_cost(150); // XXX
9974 opcode(0xF2, 0x0F, 0x59);
9975 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
9976 ins_pipe(pipe_slow);
9977 %}
9978
9979 instruct mulD_mem(regD dst, memory src)
9980 %{
9981 match(Set dst (MulD dst (LoadD src)));
9982
9983 format %{ "mulsd $dst, $src" %}
9984 ins_cost(150); // XXX
9985 opcode(0xF2, 0x0F, 0x59);
9986 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
9987 ins_pipe(pipe_slow);
9988 %}
9989
9990 instruct mulD_imm(regD dst, immD src)
9991 %{
9992 match(Set dst (MulD dst src));
9993
9994 format %{ "mulsd $dst, [$src]" %}
9995 ins_cost(150); // XXX
9996 opcode(0xF2, 0x0F, 0x59);
9997 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
9998 ins_pipe(pipe_slow);
9999 %}
10000
10001 instruct divF_reg(regF dst, regF src)
10002 %{
10003 match(Set dst (DivF dst src));
10004
10005 format %{ "divss $dst, $src" %}
10006 ins_cost(150); // XXX
10007 opcode(0xF3, 0x0F, 0x5E);
10008 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10009 ins_pipe(pipe_slow);
10010 %}
10011
10012 instruct divF_mem(regF dst, memory src)
10013 %{
10014 match(Set dst (DivF dst (LoadF src)));
10015
10016 format %{ "divss $dst, $src" %}
10017 ins_cost(150); // XXX
10018 opcode(0xF3, 0x0F, 0x5E);
10019 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10020 ins_pipe(pipe_slow);
10021 %}
10022
10023 instruct divF_imm(regF dst, immF src)
10024 %{
10025 match(Set dst (DivF dst src));
10026
10027 format %{ "divss $dst, [$src]" %}
10028 ins_cost(150); // XXX
10029 opcode(0xF3, 0x0F, 0x5E);
10030 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10031 ins_pipe(pipe_slow);
10032 %}
10033
10034 instruct divD_reg(regD dst, regD src)
10035 %{
10036 match(Set dst (DivD dst src));
10037
10038 format %{ "divsd $dst, $src" %}
10039 ins_cost(150); // XXX
10040 opcode(0xF2, 0x0F, 0x5E);
10041 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10042 ins_pipe(pipe_slow);
10043 %}
10044
10045 instruct divD_mem(regD dst, memory src)
10046 %{
10047 match(Set dst (DivD dst (LoadD src)));
10048
10049 format %{ "divsd $dst, $src" %}
10050 ins_cost(150); // XXX
10051 opcode(0xF2, 0x0F, 0x5E);
10052 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10053 ins_pipe(pipe_slow);
10054 %}
10055
10056 instruct divD_imm(regD dst, immD src)
10057 %{
10058 match(Set dst (DivD dst src));
10059
10060 format %{ "divsd $dst, [$src]" %}
10061 ins_cost(150); // XXX
10062 opcode(0xF2, 0x0F, 0x5E);
10063 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10064 ins_pipe(pipe_slow);
10065 %}
10066
10067 instruct sqrtF_reg(regF dst, regF src)
10068 %{
10069 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10070
10071 format %{ "sqrtss $dst, $src" %}
10072 ins_cost(150); // XXX
10073 opcode(0xF3, 0x0F, 0x51);
10074 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10075 ins_pipe(pipe_slow);
10076 %}
10077
10078 instruct sqrtF_mem(regF dst, memory src)
10079 %{
10080 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
10081
10082 format %{ "sqrtss $dst, $src" %}
10083 ins_cost(150); // XXX
10084 opcode(0xF3, 0x0F, 0x51);
10085 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10086 ins_pipe(pipe_slow);
10087 %}
10088
10089 instruct sqrtF_imm(regF dst, immF src)
10090 %{
10091 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10092
10093 format %{ "sqrtss $dst, [$src]" %}
10094 ins_cost(150); // XXX
10095 opcode(0xF3, 0x0F, 0x51);
10096 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10097 ins_pipe(pipe_slow);
10098 %}
10099
10100 instruct sqrtD_reg(regD dst, regD src)
10101 %{
10102 match(Set dst (SqrtD src));
10103
10104 format %{ "sqrtsd $dst, $src" %}
10105 ins_cost(150); // XXX
10106 opcode(0xF2, 0x0F, 0x51);
10107 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10108 ins_pipe(pipe_slow);
10109 %}
10110
10111 instruct sqrtD_mem(regD dst, memory src)
10112 %{
10113 match(Set dst (SqrtD (LoadD src)));
10114
10115 format %{ "sqrtsd $dst, $src" %}
10116 ins_cost(150); // XXX
10117 opcode(0xF2, 0x0F, 0x51);
10118 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10119 ins_pipe(pipe_slow);
10120 %}
10121
10122 instruct sqrtD_imm(regD dst, immD src)
10123 %{
10124 match(Set dst (SqrtD src));
10125
10126 format %{ "sqrtsd $dst, [$src]" %}
10127 ins_cost(150); // XXX
10128 opcode(0xF2, 0x0F, 0x51);
10129 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10130 ins_pipe(pipe_slow);
10131 %}
10132
10133 instruct absF_reg(regF dst)
10134 %{
10135 match(Set dst (AbsF dst));
10136
10137 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
10138 ins_encode(absF_encoding(dst));
10139 ins_pipe(pipe_slow);
10140 %}
10141
10142 instruct absD_reg(regD dst)
10143 %{
10144 match(Set dst (AbsD dst));
10145
10146 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
10147 "# abs double by sign masking" %}
10148 ins_encode(absD_encoding(dst));
10149 ins_pipe(pipe_slow);
10150 %}
10151
10152 instruct negF_reg(regF dst)
10153 %{
10154 match(Set dst (NegF dst));
10155
10156 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
10157 ins_encode(negF_encoding(dst));
10158 ins_pipe(pipe_slow);
10159 %}
10160
10161 instruct negD_reg(regD dst)
10162 %{
10163 match(Set dst (NegD dst));
10164
10165 format %{ "xorpd $dst, [0x8000000000000000]\t"
10166 "# neg double by sign flipping" %}
10167 ins_encode(negD_encoding(dst));
10168 ins_pipe(pipe_slow);
10169 %}
10170
10171 // -----------Trig and Trancendental Instructions------------------------------
10172 instruct cosD_reg(regD dst) %{
10173 match(Set dst (CosD dst));
10174
10175 format %{ "dcos $dst\n\t" %}
10176 opcode(0xD9, 0xFF);
10177 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10178 ins_pipe( pipe_slow );
10179 %}
10180
10181 instruct sinD_reg(regD dst) %{
10182 match(Set dst (SinD dst));
10183
10184 format %{ "dsin $dst\n\t" %}
10185 opcode(0xD9, 0xFE);
10186 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10187 ins_pipe( pipe_slow );
10188 %}
10189
10190 instruct tanD_reg(regD dst) %{
10191 match(Set dst (TanD dst));
10192
10193 format %{ "dtan $dst\n\t" %}
10194 ins_encode( Push_SrcXD(dst),
10195 Opcode(0xD9), Opcode(0xF2), //fptan
10196 Opcode(0xDD), Opcode(0xD8), //fstp st
10197 Push_ResultXD(dst) );
10198 ins_pipe( pipe_slow );
10199 %}
10200
10201 instruct log10D_reg(regD dst) %{
10202 // The source and result Double operands in XMM registers
10203 match(Set dst (Log10D dst));
10204 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10205 // fyl2x ; compute log_10(2) * log_2(x)
10206 format %{ "fldlg2\t\t\t#Log10\n\t"
10207 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
10208 %}
10209 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
10210 Push_SrcXD(dst),
10211 Opcode(0xD9), Opcode(0xF1), // fyl2x
10212 Push_ResultXD(dst));
10213
10214 ins_pipe( pipe_slow );
10215 %}
10216
10217 instruct logD_reg(regD dst) %{
10218 // The source and result Double operands in XMM registers
10219 match(Set dst (LogD dst));
10220 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10221 // fyl2x ; compute log_e(2) * log_2(x)
10222 format %{ "fldln2\t\t\t#Log_e\n\t"
10223 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
10224 %}
10225 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10226 Push_SrcXD(dst),
10227 Opcode(0xD9), Opcode(0xF1), // fyl2x
10228 Push_ResultXD(dst));
10229 ins_pipe( pipe_slow );
10230 %}
10231
10232
10233
10234 //----------Arithmetic Conversion Instructions---------------------------------
10235
10236 instruct roundFloat_nop(regF dst)
10237 %{
10238 match(Set dst (RoundFloat dst));
10239
10240 ins_cost(0);
10241 ins_encode();
10242 ins_pipe(empty);
10243 %}
10244
10245 instruct roundDouble_nop(regD dst)
10246 %{
10247 match(Set dst (RoundDouble dst));
10248
10249 ins_cost(0);
10250 ins_encode();
10251 ins_pipe(empty);
10252 %}
10253
10254 instruct convF2D_reg_reg(regD dst, regF src)
10255 %{
10256 match(Set dst (ConvF2D src));
10257
10258 format %{ "cvtss2sd $dst, $src" %}
10259 opcode(0xF3, 0x0F, 0x5A);
10260 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10261 ins_pipe(pipe_slow); // XXX
10262 %}
10263
10264 instruct convF2D_reg_mem(regD dst, memory src)
10265 %{
10266 match(Set dst (ConvF2D (LoadF src)));
10267
10268 format %{ "cvtss2sd $dst, $src" %}
10269 opcode(0xF3, 0x0F, 0x5A);
10270 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10271 ins_pipe(pipe_slow); // XXX
10272 %}
10273
10274 instruct convD2F_reg_reg(regF dst, regD src)
10275 %{
10276 match(Set dst (ConvD2F src));
10277
10278 format %{ "cvtsd2ss $dst, $src" %}
10279 opcode(0xF2, 0x0F, 0x5A);
10280 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10281 ins_pipe(pipe_slow); // XXX
10282 %}
10283
10284 instruct convD2F_reg_mem(regF dst, memory src)
10285 %{
10286 match(Set dst (ConvD2F (LoadD src)));
10287
10288 format %{ "cvtsd2ss $dst, $src" %}
10289 opcode(0xF2, 0x0F, 0x5A);
10290 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10291 ins_pipe(pipe_slow); // XXX
10292 %}
10293
10294 // XXX do mem variants
10295 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10296 %{
10297 match(Set dst (ConvF2I src));
10298 effect(KILL cr);
10299
10300 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10301 "cmpl $dst, #0x80000000\n\t"
10302 "jne,s done\n\t"
10303 "subq rsp, #8\n\t"
10304 "movss [rsp], $src\n\t"
10305 "call f2i_fixup\n\t"
10306 "popq $dst\n"
10307 "done: "%}
10308 opcode(0xF3, 0x0F, 0x2C);
10309 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10310 f2i_fixup(dst, src));
10311 ins_pipe(pipe_slow);
10312 %}
10313
10314 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10315 %{
10316 match(Set dst (ConvF2L src));
10317 effect(KILL cr);
10318
10319 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10320 "cmpq $dst, [0x8000000000000000]\n\t"
10321 "jne,s done\n\t"
10322 "subq rsp, #8\n\t"
10323 "movss [rsp], $src\n\t"
10324 "call f2l_fixup\n\t"
10325 "popq $dst\n"
10326 "done: "%}
10327 opcode(0xF3, 0x0F, 0x2C);
10328 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
10329 f2l_fixup(dst, src));
10330 ins_pipe(pipe_slow);
10331 %}
10332
10333 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10334 %{
10335 match(Set dst (ConvD2I src));
10336 effect(KILL cr);
10337
10338 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10339 "cmpl $dst, #0x80000000\n\t"
10340 "jne,s done\n\t"
10341 "subq rsp, #8\n\t"
10342 "movsd [rsp], $src\n\t"
10343 "call d2i_fixup\n\t"
10344 "popq $dst\n"
10345 "done: "%}
10346 opcode(0xF2, 0x0F, 0x2C);
10347 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10348 d2i_fixup(dst, src));
10349 ins_pipe(pipe_slow);
10350 %}
10351
10352 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10353 %{
10354 match(Set dst (ConvD2L src));
10355 effect(KILL cr);
10356
10357 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10358 "cmpq $dst, [0x8000000000000000]\n\t"
10359 "jne,s done\n\t"
10360 "subq rsp, #8\n\t"
10361 "movsd [rsp], $src\n\t"
10362 "call d2l_fixup\n\t"
10363 "popq $dst\n"
10364 "done: "%}
10365 opcode(0xF2, 0x0F, 0x2C);
10366 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
10367 d2l_fixup(dst, src));
10368 ins_pipe(pipe_slow);
10369 %}
10370
10371 instruct convI2F_reg_reg(regF dst, rRegI src)
10372 %{
10373 predicate(!UseXmmI2F);
10374 match(Set dst (ConvI2F src));
10375
10376 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10377 opcode(0xF3, 0x0F, 0x2A);
10378 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10379 ins_pipe(pipe_slow); // XXX
10380 %}
10381
10382 instruct convI2F_reg_mem(regF dst, memory src)
10383 %{
10384 match(Set dst (ConvI2F (LoadI src)));
10385
10386 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10387 opcode(0xF3, 0x0F, 0x2A);
10388 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10389 ins_pipe(pipe_slow); // XXX
10390 %}
10391
10392 instruct convI2D_reg_reg(regD dst, rRegI src)
10393 %{
10394 predicate(!UseXmmI2D);
10395 match(Set dst (ConvI2D src));
10396
10397 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10398 opcode(0xF2, 0x0F, 0x2A);
10399 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10400 ins_pipe(pipe_slow); // XXX
10401 %}
10402
10403 instruct convI2D_reg_mem(regD dst, memory src)
10404 %{
10405 match(Set dst (ConvI2D (LoadI src)));
10406
10407 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10408 opcode(0xF2, 0x0F, 0x2A);
10409 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10410 ins_pipe(pipe_slow); // XXX
10411 %}
10412
10413 instruct convXI2F_reg(regF dst, rRegI src)
10414 %{
10415 predicate(UseXmmI2F);
10416 match(Set dst (ConvI2F src));
10417
10418 format %{ "movdl $dst, $src\n\t"
10419 "cvtdq2psl $dst, $dst\t# i2f" %}
10420 ins_encode %{
10421 __ movdl($dst$$XMMRegister, $src$$Register);
10422 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10423 %}
10424 ins_pipe(pipe_slow); // XXX
10425 %}
10426
10427 instruct convXI2D_reg(regD dst, rRegI src)
10428 %{
10429 predicate(UseXmmI2D);
10430 match(Set dst (ConvI2D src));
10431
10432 format %{ "movdl $dst, $src\n\t"
10433 "cvtdq2pdl $dst, $dst\t# i2d" %}
10434 ins_encode %{
10435 __ movdl($dst$$XMMRegister, $src$$Register);
10436 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10437 %}
10438 ins_pipe(pipe_slow); // XXX
10439 %}
10440
10441 instruct convL2F_reg_reg(regF dst, rRegL src)
10442 %{
10443 match(Set dst (ConvL2F src));
10444
10445 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10446 opcode(0xF3, 0x0F, 0x2A);
10447 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
10448 ins_pipe(pipe_slow); // XXX
10449 %}
10450
10451 instruct convL2F_reg_mem(regF dst, memory src)
10452 %{
10453 match(Set dst (ConvL2F (LoadL src)));
10454
10455 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10456 opcode(0xF3, 0x0F, 0x2A);
10457 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
10458 ins_pipe(pipe_slow); // XXX
10459 %}
10460
10461 instruct convL2D_reg_reg(regD dst, rRegL src)
10462 %{
10463 match(Set dst (ConvL2D src));
10464
10465 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10466 opcode(0xF2, 0x0F, 0x2A);
10467 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
10468 ins_pipe(pipe_slow); // XXX
10469 %}
10470
10471 instruct convL2D_reg_mem(regD dst, memory src)
10472 %{
10473 match(Set dst (ConvL2D (LoadL src)));
10474
10475 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10476 opcode(0xF2, 0x0F, 0x2A);
10477 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
10478 ins_pipe(pipe_slow); // XXX
10479 %}
10480
10481 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10482 %{
10483 match(Set dst (ConvI2L src));
10484
10485 ins_cost(125);
10486 format %{ "movslq $dst, $src\t# i2l" %}
10487 opcode(0x63); // needs REX.W
10488 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10489 ins_pipe(ialu_reg_reg);
10490 %}
10491
10492 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10493 // %{
10494 // match(Set dst (ConvI2L src));
10495 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10496 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10497 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10498 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10499 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10500 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10501
10502 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10503 // ins_encode(enc_copy(dst, src));
10504 // // opcode(0x63); // needs REX.W
10505 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10506 // ins_pipe(ialu_reg_reg);
10507 // %}
10508
10509 instruct convI2L_reg_mem(rRegL dst, memory src)
10510 %{
10511 match(Set dst (ConvI2L (LoadI src)));
10512
10513 format %{ "movslq $dst, $src\t# i2l" %}
10514 opcode(0x63); // needs REX.W
10515 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst,src));
10516 ins_pipe(ialu_reg_mem);
10517 %}
10518
10519 // Zero-extend convert int to long
10520 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10521 %{
10522 match(Set dst (AndL (ConvI2L src) mask));
10523
10524 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10525 ins_encode(enc_copy(dst, src));
10526 ins_pipe(ialu_reg_reg);
10527 %}
10528
10529 // Zero-extend convert int to long
10530 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10531 %{
10532 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10533
10534 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10535 opcode(0x8B);
10536 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
10537 ins_pipe(ialu_reg_mem);
10538 %}
10539
10540 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10541 %{
10542 match(Set dst (AndL src mask));
10543
10544 format %{ "movl $dst, $src\t# zero-extend long" %}
10545 ins_encode(enc_copy_always(dst, src));
10546 ins_pipe(ialu_reg_reg);
10547 %}
10548
10549 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10550 %{
10551 match(Set dst (ConvL2I src));
10552
10553 format %{ "movl $dst, $src\t# l2i" %}
10554 ins_encode(enc_copy_always(dst, src));
10555 ins_pipe(ialu_reg_reg);
10556 %}
10557
10558
10559 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10560 match(Set dst (MoveF2I src));
10561 effect(DEF dst, USE src);
10562
10563 ins_cost(125);
10564 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10565 opcode(0x8B);
10566 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
10567 ins_pipe(ialu_reg_mem);
10568 %}
10569
10570 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10571 match(Set dst (MoveI2F src));
10572 effect(DEF dst, USE src);
10573
10574 ins_cost(125);
10575 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10576 opcode(0xF3, 0x0F, 0x10);
10577 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10578 ins_pipe(pipe_slow);
10579 %}
10580
10581 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10582 match(Set dst (MoveD2L src));
10583 effect(DEF dst, USE src);
10584
10585 ins_cost(125);
10586 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10587 opcode(0x8B);
10588 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
10589 ins_pipe(ialu_reg_mem);
10590 %}
10591
10592 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10593 predicate(!UseXmmLoadAndClearUpper);
10594 match(Set dst (MoveL2D src));
10595 effect(DEF dst, USE src);
10596
10597 ins_cost(125);
10598 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10599 opcode(0x66, 0x0F, 0x12);
10600 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10601 ins_pipe(pipe_slow);
10602 %}
10603
10604 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10605 predicate(UseXmmLoadAndClearUpper);
10606 match(Set dst (MoveL2D src));
10607 effect(DEF dst, USE src);
10608
10609 ins_cost(125);
10610 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10611 opcode(0xF2, 0x0F, 0x10);
10612 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10613 ins_pipe(pipe_slow);
10614 %}
10615
10616
10617 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10618 match(Set dst (MoveF2I src));
10619 effect(DEF dst, USE src);
10620
10621 ins_cost(95); // XXX
10622 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10623 opcode(0xF3, 0x0F, 0x11);
10624 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
10625 ins_pipe(pipe_slow);
10626 %}
10627
10628 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10629 match(Set dst (MoveI2F src));
10630 effect(DEF dst, USE src);
10631
10632 ins_cost(100);
10633 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10634 opcode(0x89);
10635 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
10636 ins_pipe( ialu_mem_reg );
10637 %}
10638
10639 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10640 match(Set dst (MoveD2L src));
10641 effect(DEF dst, USE src);
10642
10643 ins_cost(95); // XXX
10644 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10645 opcode(0xF2, 0x0F, 0x11);
10646 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
10647 ins_pipe(pipe_slow);
10648 %}
10649
10650 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10651 match(Set dst (MoveL2D src));
10652 effect(DEF dst, USE src);
10653
10654 ins_cost(100);
10655 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10656 opcode(0x89);
10657 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
10658 ins_pipe(ialu_mem_reg);
10659 %}
10660
10661 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10662 match(Set dst (MoveF2I src));
10663 effect(DEF dst, USE src);
10664 ins_cost(85);
10665 format %{ "movd $dst,$src\t# MoveF2I" %}
10666 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
10667 ins_pipe( pipe_slow );
10668 %}
10669
10670 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10671 match(Set dst (MoveD2L src));
10672 effect(DEF dst, USE src);
10673 ins_cost(85);
10674 format %{ "movd $dst,$src\t# MoveD2L" %}
10675 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
10676 ins_pipe( pipe_slow );
10677 %}
10678
10679 // The next instructions have long latency and use Int unit. Set high cost.
10680 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10681 match(Set dst (MoveI2F src));
10682 effect(DEF dst, USE src);
10683 ins_cost(300);
10684 format %{ "movd $dst,$src\t# MoveI2F" %}
10685 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
10686 ins_pipe( pipe_slow );
10687 %}
10688
10689 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10690 match(Set dst (MoveL2D src));
10691 effect(DEF dst, USE src);
10692 ins_cost(300);
10693 format %{ "movd $dst,$src\t# MoveL2D" %}
10694 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
10695 ins_pipe( pipe_slow );
10696 %}
10697
10698 // Replicate scalar to packed byte (1 byte) values in xmm
10699 instruct Repl8B_reg(regD dst, regD src) %{
10700 match(Set dst (Replicate8B src));
10701 format %{ "MOVDQA $dst,$src\n\t"
10702 "PUNPCKLBW $dst,$dst\n\t"
10703 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10704 ins_encode( pshufd_8x8(dst, src));
10705 ins_pipe( pipe_slow );
10706 %}
10707
10708 // Replicate scalar to packed byte (1 byte) values in xmm
10709 instruct Repl8B_rRegI(regD dst, rRegI src) %{
10710 match(Set dst (Replicate8B src));
10711 format %{ "MOVD $dst,$src\n\t"
10712 "PUNPCKLBW $dst,$dst\n\t"
10713 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
10714 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
10715 ins_pipe( pipe_slow );
10716 %}
10717
10718 // Replicate scalar zero to packed byte (1 byte) values in xmm
10719 instruct Repl8B_immI0(regD dst, immI0 zero) %{
10720 match(Set dst (Replicate8B zero));
10721 format %{ "PXOR $dst,$dst\t! replicate8B" %}
10722 ins_encode( pxor(dst, dst));
10723 ins_pipe( fpu_reg_reg );
10724 %}
10725
10726 // Replicate scalar to packed shore (2 byte) values in xmm
10727 instruct Repl4S_reg(regD dst, regD src) %{
10728 match(Set dst (Replicate4S src));
10729 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
10730 ins_encode( pshufd_4x16(dst, src));
10731 ins_pipe( fpu_reg_reg );
10732 %}
10733
10734 // Replicate scalar to packed shore (2 byte) values in xmm
10735 instruct Repl4S_rRegI(regD dst, rRegI src) %{
10736 match(Set dst (Replicate4S src));
10737 format %{ "MOVD $dst,$src\n\t"
10738 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
10739 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
10740 ins_pipe( fpu_reg_reg );
10741 %}
10742
10743 // Replicate scalar zero to packed short (2 byte) values in xmm
10744 instruct Repl4S_immI0(regD dst, immI0 zero) %{
10745 match(Set dst (Replicate4S zero));
10746 format %{ "PXOR $dst,$dst\t! replicate4S" %}
10747 ins_encode( pxor(dst, dst));
10748 ins_pipe( fpu_reg_reg );
10749 %}
10750
10751 // Replicate scalar to packed char (2 byte) values in xmm
10752 instruct Repl4C_reg(regD dst, regD src) %{
10753 match(Set dst (Replicate4C src));
10754 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
10755 ins_encode( pshufd_4x16(dst, src));
10756 ins_pipe( fpu_reg_reg );
10757 %}
10758
10759 // Replicate scalar to packed char (2 byte) values in xmm
10760 instruct Repl4C_rRegI(regD dst, rRegI src) %{
10761 match(Set dst (Replicate4C src));
10762 format %{ "MOVD $dst,$src\n\t"
10763 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
10764 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
10765 ins_pipe( fpu_reg_reg );
10766 %}
10767
10768 // Replicate scalar zero to packed char (2 byte) values in xmm
10769 instruct Repl4C_immI0(regD dst, immI0 zero) %{
10770 match(Set dst (Replicate4C zero));
10771 format %{ "PXOR $dst,$dst\t! replicate4C" %}
10772 ins_encode( pxor(dst, dst));
10773 ins_pipe( fpu_reg_reg );
10774 %}
10775
10776 // Replicate scalar to packed integer (4 byte) values in xmm
10777 instruct Repl2I_reg(regD dst, regD src) %{
10778 match(Set dst (Replicate2I src));
10779 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
10780 ins_encode( pshufd(dst, src, 0x00));
10781 ins_pipe( fpu_reg_reg );
10782 %}
10783
10784 // Replicate scalar to packed integer (4 byte) values in xmm
10785 instruct Repl2I_rRegI(regD dst, rRegI src) %{
10786 match(Set dst (Replicate2I src));
10787 format %{ "MOVD $dst,$src\n\t"
10788 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
10789 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
10790 ins_pipe( fpu_reg_reg );
10791 %}
10792
10793 // Replicate scalar zero to packed integer (2 byte) values in xmm
10794 instruct Repl2I_immI0(regD dst, immI0 zero) %{
10795 match(Set dst (Replicate2I zero));
10796 format %{ "PXOR $dst,$dst\t! replicate2I" %}
10797 ins_encode( pxor(dst, dst));
10798 ins_pipe( fpu_reg_reg );
10799 %}
10800
10801 // Replicate scalar to packed single precision floating point values in xmm
10802 instruct Repl2F_reg(regD dst, regD src) %{
10803 match(Set dst (Replicate2F src));
10804 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10805 ins_encode( pshufd(dst, src, 0xe0));
10806 ins_pipe( fpu_reg_reg );
10807 %}
10808
10809 // Replicate scalar to packed single precision floating point values in xmm
10810 instruct Repl2F_regF(regD dst, regF src) %{
10811 match(Set dst (Replicate2F src));
10812 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
10813 ins_encode( pshufd(dst, src, 0xe0));
10814 ins_pipe( fpu_reg_reg );
10815 %}
10816
10817 // Replicate scalar to packed single precision floating point values in xmm
10818 instruct Repl2F_immF0(regD dst, immF0 zero) %{
10819 match(Set dst (Replicate2F zero));
10820 format %{ "PXOR $dst,$dst\t! replicate2F" %}
10821 ins_encode( pxor(dst, dst));
10822 ins_pipe( fpu_reg_reg );
10823 %}
10824
10825
10826 // =======================================================================
10827 // fast clearing of an array
10828 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10829 rFlagsReg cr)
10830 %{
10831 match(Set dummy (ClearArray cnt base));
10832 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10833
10834 format %{ "xorl rax, rax\t# ClearArray:\n\t"
10835 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10836 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
10837 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
10838 ins_pipe(pipe_slow);
10839 %}
10840
10841 instruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1,
10842 rbx_RegI tmp2, rcx_RegI result, rFlagsReg cr)
10843 %{
10844 match(Set result (StrComp str1 str2));
10845 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr);
10846 //ins_cost(300);
10847
10848 format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %}
10849 ins_encode( enc_String_Compare() );
10850 ins_pipe( pipe_slow );
10851 %}
10852
10853 //----------Control Flow Instructions------------------------------------------
10854 // Signed compare Instructions
10855
10856 // XXX more variants!!
10857 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10858 %{
10859 match(Set cr (CmpI op1 op2));
10860 effect(DEF cr, USE op1, USE op2);
10861
10862 format %{ "cmpl $op1, $op2" %}
10863 opcode(0x3B); /* Opcode 3B /r */
10864 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10865 ins_pipe(ialu_cr_reg_reg);
10866 %}
10867
10868 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10869 %{
10870 match(Set cr (CmpI op1 op2));
10871
10872 format %{ "cmpl $op1, $op2" %}
10873 opcode(0x81, 0x07); /* Opcode 81 /7 */
10874 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10875 ins_pipe(ialu_cr_reg_imm);
10876 %}
10877
10878 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10879 %{
10880 match(Set cr (CmpI op1 (LoadI op2)));
10881
10882 ins_cost(500); // XXX
10883 format %{ "cmpl $op1, $op2" %}
10884 opcode(0x3B); /* Opcode 3B /r */
10885 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10886 ins_pipe(ialu_cr_reg_mem);
10887 %}
10888
10889 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10890 %{
10891 match(Set cr (CmpI src zero));
10892
10893 format %{ "testl $src, $src" %}
10894 opcode(0x85);
10895 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10896 ins_pipe(ialu_cr_reg_imm);
10897 %}
10898
10899 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10900 %{
10901 match(Set cr (CmpI (AndI src con) zero));
10902
10903 format %{ "testl $src, $con" %}
10904 opcode(0xF7, 0x00);
10905 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10906 ins_pipe(ialu_cr_reg_imm);
10907 %}
10908
10909 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10910 %{
10911 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10912
10913 format %{ "testl $src, $mem" %}
10914 opcode(0x85);
10915 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10916 ins_pipe(ialu_cr_reg_mem);
10917 %}
10918
10919 // Unsigned compare Instructions; really, same as signed except they
10920 // produce an rFlagsRegU instead of rFlagsReg.
10921 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10922 %{
10923 match(Set cr (CmpU op1 op2));
10924
10925 format %{ "cmpl $op1, $op2\t# unsigned" %}
10926 opcode(0x3B); /* Opcode 3B /r */
10927 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10928 ins_pipe(ialu_cr_reg_reg);
10929 %}
10930
10931 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10932 %{
10933 match(Set cr (CmpU op1 op2));
10934
10935 format %{ "cmpl $op1, $op2\t# unsigned" %}
10936 opcode(0x81,0x07); /* Opcode 81 /7 */
10937 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10938 ins_pipe(ialu_cr_reg_imm);
10939 %}
10940
10941 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10942 %{
10943 match(Set cr (CmpU op1 (LoadI op2)));
10944
10945 ins_cost(500); // XXX
10946 format %{ "cmpl $op1, $op2\t# unsigned" %}
10947 opcode(0x3B); /* Opcode 3B /r */
10948 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10949 ins_pipe(ialu_cr_reg_mem);
10950 %}
10951
10952 // // // Cisc-spilled version of cmpU_rReg
10953 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10954 // //%{
10955 // // match(Set cr (CmpU (LoadI op1) op2));
10956 // //
10957 // // format %{ "CMPu $op1,$op2" %}
10958 // // ins_cost(500);
10959 // // opcode(0x39); /* Opcode 39 /r */
10960 // // ins_encode( OpcP, reg_mem( op1, op2) );
10961 // //%}
10962
10963 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10964 %{
10965 match(Set cr (CmpU src zero));
10966
10967 format %{ "testl $src, $src\t# unsigned" %}
10968 opcode(0x85);
10969 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10970 ins_pipe(ialu_cr_reg_imm);
10971 %}
10972
10973 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10974 %{
10975 match(Set cr (CmpP op1 op2));
10976
10977 format %{ "cmpq $op1, $op2\t# ptr" %}
10978 opcode(0x3B); /* Opcode 3B /r */
10979 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10980 ins_pipe(ialu_cr_reg_reg);
10981 %}
10982
10983 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10984 %{
10985 match(Set cr (CmpP op1 (LoadP op2)));
10986
10987 ins_cost(500); // XXX
10988 format %{ "cmpq $op1, $op2\t# ptr" %}
10989 opcode(0x3B); /* Opcode 3B /r */
10990 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10991 ins_pipe(ialu_cr_reg_mem);
10992 %}
10993
10994 // // // Cisc-spilled version of cmpP_rReg
10995 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10996 // //%{
10997 // // match(Set cr (CmpP (LoadP op1) op2));
10998 // //
10999 // // format %{ "CMPu $op1,$op2" %}
11000 // // ins_cost(500);
11001 // // opcode(0x39); /* Opcode 39 /r */
11002 // // ins_encode( OpcP, reg_mem( op1, op2) );
11003 // //%}
11004
11005 // XXX this is generalized by compP_rReg_mem???
11006 // Compare raw pointer (used in out-of-heap check).
11007 // Only works because non-oop pointers must be raw pointers
11008 // and raw pointers have no anti-dependencies.
11009 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11010 %{
11011 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
11012 match(Set cr (CmpP op1 (LoadP op2)));
11013
11014 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11015 opcode(0x3B); /* Opcode 3B /r */
11016 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11017 ins_pipe(ialu_cr_reg_mem);
11018 %}
11019
11020 // This will generate a signed flags result. This should be OK since
11021 // any compare to a zero should be eq/neq.
11022 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11023 %{
11024 match(Set cr (CmpP src zero));
11025
11026 format %{ "testq $src, $src\t# ptr" %}
11027 opcode(0x85);
11028 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11029 ins_pipe(ialu_cr_reg_imm);
11030 %}
11031
11032 // This will generate a signed flags result. This should be OK since
11033 // any compare to a zero should be eq/neq.
11034 instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero)
11035 %{
11036 match(Set cr (CmpP (LoadP op) zero));
11037
11038 ins_cost(500); // XXX
11039 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11040 opcode(0xF7); /* Opcode F7 /0 */
11041 ins_encode(REX_mem_wide(op),
11042 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11043 ins_pipe(ialu_cr_reg_imm);
11044 %}
11045
11046 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11047 match(Set cr (CmpN src zero));
11048
11049 format %{ "testl $src, $src" %}
11050 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11051 ins_pipe(ialu_cr_reg_imm);
11052 %}
11053
11054 // Yanked all unsigned pointer compare operations.
11055 // Pointer compares are done with CmpP which is already unsigned.
11056
11057 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11058 %{
11059 match(Set cr (CmpL op1 op2));
11060
11061 format %{ "cmpq $op1, $op2" %}
11062 opcode(0x3B); /* Opcode 3B /r */
11063 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11064 ins_pipe(ialu_cr_reg_reg);
11065 %}
11066
11067 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11068 %{
11069 match(Set cr (CmpL op1 op2));
11070
11071 format %{ "cmpq $op1, $op2" %}
11072 opcode(0x81, 0x07); /* Opcode 81 /7 */
11073 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11074 ins_pipe(ialu_cr_reg_imm);
11075 %}
11076
11077 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11078 %{
11079 match(Set cr (CmpL op1 (LoadL op2)));
11080
11081 ins_cost(500); // XXX
11082 format %{ "cmpq $op1, $op2" %}
11083 opcode(0x3B); /* Opcode 3B /r */
11084 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11085 ins_pipe(ialu_cr_reg_mem);
11086 %}
11087
11088 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11089 %{
11090 match(Set cr (CmpL src zero));
11091
11092 format %{ "testq $src, $src" %}
11093 opcode(0x85);
11094 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11095 ins_pipe(ialu_cr_reg_imm);
11096 %}
11097
11098 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11099 %{
11100 match(Set cr (CmpL (AndL src con) zero));
11101
11102 format %{ "testq $src, $con\t# long" %}
11103 opcode(0xF7, 0x00);
11104 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11105 ins_pipe(ialu_cr_reg_imm);
11106 %}
11107
11108 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11109 %{
11110 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11111
11112 format %{ "testq $src, $mem" %}
11113 opcode(0x85);
11114 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11115 ins_pipe(ialu_cr_reg_mem);
11116 %}
11117
11118 // Manifest a CmpL result in an integer register. Very painful.
11119 // This is the test to avoid.
11120 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11121 %{
11122 match(Set dst (CmpL3 src1 src2));
11123 effect(KILL flags);
11124
11125 ins_cost(275); // XXX
11126 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11127 "movl $dst, -1\n\t"
11128 "jl,s done\n\t"
11129 "setne $dst\n\t"
11130 "movzbl $dst, $dst\n\t"
11131 "done:" %}
11132 ins_encode(cmpl3_flag(src1, src2, dst));
11133 ins_pipe(pipe_slow);
11134 %}
11135
11136 //----------Max and Min--------------------------------------------------------
11137 // Min Instructions
11138
11139 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11140 %{
11141 effect(USE_DEF dst, USE src, USE cr);
11142
11143 format %{ "cmovlgt $dst, $src\t# min" %}
11144 opcode(0x0F, 0x4F);
11145 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11146 ins_pipe(pipe_cmov_reg);
11147 %}
11148
11149
11150 instruct minI_rReg(rRegI dst, rRegI src)
11151 %{
11152 match(Set dst (MinI dst src));
11153
11154 ins_cost(200);
11155 expand %{
11156 rFlagsReg cr;
11157 compI_rReg(cr, dst, src);
11158 cmovI_reg_g(dst, src, cr);
11159 %}
11160 %}
11161
11162 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11163 %{
11164 effect(USE_DEF dst, USE src, USE cr);
11165
11166 format %{ "cmovllt $dst, $src\t# max" %}
11167 opcode(0x0F, 0x4C);
11168 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11169 ins_pipe(pipe_cmov_reg);
11170 %}
11171
11172
11173 instruct maxI_rReg(rRegI dst, rRegI src)
11174 %{
11175 match(Set dst (MaxI dst src));
11176
11177 ins_cost(200);
11178 expand %{
11179 rFlagsReg cr;
11180 compI_rReg(cr, dst, src);
11181 cmovI_reg_l(dst, src, cr);
11182 %}
11183 %}
11184
11185 // ============================================================================
11186 // Branch Instructions
11187
11188 // Jump Direct - Label defines a relative address from JMP+1
11189 instruct jmpDir(label labl)
11190 %{
11191 match(Goto);
11192 effect(USE labl);
11193
11194 ins_cost(300);
11195 format %{ "jmp $labl" %}
11196 size(5);
11197 opcode(0xE9);
11198 ins_encode(OpcP, Lbl(labl));
11199 ins_pipe(pipe_jmp);
11200 ins_pc_relative(1);
11201 %}
11202
11203 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11204 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11205 %{
11206 match(If cop cr);
11207 effect(USE labl);
11208
11209 ins_cost(300);
11210 format %{ "j$cop $labl" %}
11211 size(6);
11212 opcode(0x0F, 0x80);
11213 ins_encode(Jcc(cop, labl));
11214 ins_pipe(pipe_jcc);
11215 ins_pc_relative(1);
11216 %}
11217
11218 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11219 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11220 %{
11221 match(CountedLoopEnd cop cr);
11222 effect(USE labl);
11223
11224 ins_cost(300);
11225 format %{ "j$cop $labl\t# loop end" %}
11226 size(6);
11227 opcode(0x0F, 0x80);
11228 ins_encode(Jcc(cop, labl));
11229 ins_pipe(pipe_jcc);
11230 ins_pc_relative(1);
11231 %}
11232
11233 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11234 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl)
11235 %{
11236 match(CountedLoopEnd cop cmp);
11237 effect(USE labl);
11238
11239 ins_cost(300);
11240 format %{ "j$cop,u $labl\t# loop end" %}
11241 size(6);
11242 opcode(0x0F, 0x80);
11243 ins_encode(Jcc(cop, labl));
11244 ins_pipe(pipe_jcc);
11245 ins_pc_relative(1);
11246 %}
11247
11248 // Jump Direct Conditional - using unsigned comparison
11249 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl)
11250 %{
11251 match(If cop cmp);
11252 effect(USE labl);
11253
11254 ins_cost(300);
11255 format %{ "j$cop,u $labl" %}
11256 size(6);
11257 opcode(0x0F, 0x80);
11258 ins_encode(Jcc(cop, labl));
11259 ins_pipe(pipe_jcc);
11260 ins_pc_relative(1);
11261 %}
11262
11263 // ============================================================================
11264 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11265 // superklass array for an instance of the superklass. Set a hidden
11266 // internal cache on a hit (cache is checked with exposed code in
11267 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11268 // encoding ALSO sets flags.
11269
11270 instruct partialSubtypeCheck(rdi_RegP result,
11271 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11272 rFlagsReg cr)
11273 %{
11274 match(Set result (PartialSubtypeCheck sub super));
11275 effect(KILL rcx, KILL cr);
11276
11277 ins_cost(1100); // slightly larger than the next version
11278 format %{ "cmpq rax, rsi\n\t"
11279 "jeq,s hit\n\t"
11280 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
11281 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11282 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11283 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11284 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11285 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
11286 "hit:\n\t"
11287 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11288 "miss:\t" %}
11289
11290 opcode(0x1); // Force a XOR of RDI
11291 ins_encode(enc_PartialSubtypeCheck());
11292 ins_pipe(pipe_slow);
11293 %}
11294
11295 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11296 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11297 immP0 zero,
11298 rdi_RegP result)
11299 %{
11300 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11301 predicate(!UseCompressedOops); // decoding oop kills condition codes
11302 effect(KILL rcx, KILL result);
11303
11304 ins_cost(1000);
11305 format %{ "cmpq rax, rsi\n\t"
11306 "jeq,s miss\t# Actually a hit; we are done.\n\t"
11307 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
11308 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
11309 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
11310 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11311 "jne,s miss\t\t# Missed: flags nz\n\t"
11312 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
11313 "miss:\t" %}
11314
11315 opcode(0x0); // No need to XOR RDI
11316 ins_encode(enc_PartialSubtypeCheck());
11317 ins_pipe(pipe_slow);
11318 %}
11319
11320 // ============================================================================
11321 // Branch Instructions -- short offset versions
11322 //
11323 // These instructions are used to replace jumps of a long offset (the default
11324 // match) with jumps of a shorter offset. These instructions are all tagged
11325 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11326 // match rules in general matching. Instead, the ADLC generates a conversion
11327 // method in the MachNode which can be used to do in-place replacement of the
11328 // long variant with the shorter variant. The compiler will determine if a
11329 // branch can be taken by the is_short_branch_offset() predicate in the machine
11330 // specific code section of the file.
11331
11332 // Jump Direct - Label defines a relative address from JMP+1
11333 instruct jmpDir_short(label labl)
11334 %{
11335 match(Goto);
11336 effect(USE labl);
11337
11338 ins_cost(300);
11339 format %{ "jmp,s $labl" %}
11340 size(2);
11341 opcode(0xEB);
11342 ins_encode(OpcP, LblShort(labl));
11343 ins_pipe(pipe_jmp);
11344 ins_pc_relative(1);
11345 ins_short_branch(1);
11346 %}
11347
11348 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11349 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl)
11350 %{
11351 match(If cop cr);
11352 effect(USE labl);
11353
11354 ins_cost(300);
11355 format %{ "j$cop,s $labl" %}
11356 size(2);
11357 opcode(0x70);
11358 ins_encode(JccShort(cop, labl));
11359 ins_pipe(pipe_jcc);
11360 ins_pc_relative(1);
11361 ins_short_branch(1);
11362 %}
11363
11364 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11365 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl)
11366 %{
11367 match(CountedLoopEnd cop cr);
11368 effect(USE labl);
11369
11370 ins_cost(300);
11371 format %{ "j$cop,s $labl" %}
11372 size(2);
11373 opcode(0x70);
11374 ins_encode(JccShort(cop, labl));
11375 ins_pipe(pipe_jcc);
11376 ins_pc_relative(1);
11377 ins_short_branch(1);
11378 %}
11379
11380 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11381 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl)
11382 %{
11383 match(CountedLoopEnd cop cmp);
11384 effect(USE labl);
11385
11386 ins_cost(300);
11387 format %{ "j$cop,us $labl" %}
11388 size(2);
11389 opcode(0x70);
11390 ins_encode(JccShort(cop, labl));
11391 ins_pipe(pipe_jcc);
11392 ins_pc_relative(1);
11393 ins_short_branch(1);
11394 %}
11395
11396 // Jump Direct Conditional - using unsigned comparison
11397 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl)
11398 %{
11399 match(If cop cmp);
11400 effect(USE labl);
11401
11402 ins_cost(300);
11403 format %{ "j$cop,us $labl" %}
11404 size(2);
11405 opcode(0x70);
11406 ins_encode(JccShort(cop, labl));
11407 ins_pipe(pipe_jcc);
11408 ins_pc_relative(1);
11409 ins_short_branch(1);
11410 %}
11411
11412 // ============================================================================
11413 // inlined locking and unlocking
11414
11415 instruct cmpFastLock(rFlagsReg cr,
11416 rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
11417 %{
11418 match(Set cr (FastLock object box));
11419 effect(TEMP tmp, TEMP scr);
11420
11421 ins_cost(300);
11422 format %{ "fastlock $object,$box,$tmp,$scr" %}
11423 ins_encode(Fast_Lock(object, box, tmp, scr));
11424 ins_pipe(pipe_slow);
11425 ins_pc_relative(1);
11426 %}
11427
11428 instruct cmpFastUnlock(rFlagsReg cr,
11429 rRegP object, rax_RegP box, rRegP tmp)
11430 %{
11431 match(Set cr (FastUnlock object box));
11432 effect(TEMP tmp);
11433
11434 ins_cost(300);
11435 format %{ "fastunlock $object, $box, $tmp" %}
11436 ins_encode(Fast_Unlock(object, box, tmp));
11437 ins_pipe(pipe_slow);
11438 ins_pc_relative(1);
11439 %}
11440
11441
11442 // ============================================================================
11443 // Safepoint Instructions
11444 instruct safePoint_poll(rFlagsReg cr)
11445 %{
11446 match(SafePoint);
11447 effect(KILL cr);
11448
11449 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11450 "# Safepoint: poll for GC" %}
11451 size(6); // Opcode + ModRM + Disp32 == 6 bytes
11452 ins_cost(125);
11453 ins_encode(enc_safepoint_poll);
11454 ins_pipe(ialu_reg_mem);
11455 %}
11456
11457 // ============================================================================
11458 // Procedure Call/Return Instructions
11459 // Call Java Static Instruction
11460 // Note: If this code changes, the corresponding ret_addr_offset() and
11461 // compute_padding() functions will have to be adjusted.
11462 instruct CallStaticJavaDirect(method meth)
11463 %{
11464 match(CallStaticJava);
11465 effect(USE meth);
11466
11467 ins_cost(300);
11468 format %{ "call,static " %}
11469 opcode(0xE8); /* E8 cd */
11470 ins_encode(Java_Static_Call(meth), call_epilog);
11471 ins_pipe(pipe_slow);
11472 ins_pc_relative(1);
11473 ins_alignment(4);
11474 %}
11475
11476 // Call Java Dynamic Instruction
11477 // Note: If this code changes, the corresponding ret_addr_offset() and
11478 // compute_padding() functions will have to be adjusted.
11479 instruct CallDynamicJavaDirect(method meth)
11480 %{
11481 match(CallDynamicJava);
11482 effect(USE meth);
11483
11484 ins_cost(300);
11485 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11486 "call,dynamic " %}
11487 opcode(0xE8); /* E8 cd */
11488 ins_encode(Java_Dynamic_Call(meth), call_epilog);
11489 ins_pipe(pipe_slow);
11490 ins_pc_relative(1);
11491 ins_alignment(4);
11492 %}
11493
11494 // Call Runtime Instruction
11495 instruct CallRuntimeDirect(method meth)
11496 %{
11497 match(CallRuntime);
11498 effect(USE meth);
11499
11500 ins_cost(300);
11501 format %{ "call,runtime " %}
11502 opcode(0xE8); /* E8 cd */
11503 ins_encode(Java_To_Runtime(meth));
11504 ins_pipe(pipe_slow);
11505 ins_pc_relative(1);
11506 %}
11507
11508 // Call runtime without safepoint
11509 instruct CallLeafDirect(method meth)
11510 %{
11511 match(CallLeaf);
11512 effect(USE meth);
11513
11514 ins_cost(300);
11515 format %{ "call_leaf,runtime " %}
11516 opcode(0xE8); /* E8 cd */
11517 ins_encode(Java_To_Runtime(meth));
11518 ins_pipe(pipe_slow);
11519 ins_pc_relative(1);
11520 %}
11521
11522 // Call runtime without safepoint
11523 instruct CallLeafNoFPDirect(method meth)
11524 %{
11525 match(CallLeafNoFP);
11526 effect(USE meth);
11527
11528 ins_cost(300);
11529 format %{ "call_leaf_nofp,runtime " %}
11530 opcode(0xE8); /* E8 cd */
11531 ins_encode(Java_To_Runtime(meth));
11532 ins_pipe(pipe_slow);
11533 ins_pc_relative(1);
11534 %}
11535
11536 // Return Instruction
11537 // Remove the return address & jump to it.
11538 // Notice: We always emit a nop after a ret to make sure there is room
11539 // for safepoint patching
11540 instruct Ret()
11541 %{
11542 match(Return);
11543
11544 format %{ "ret" %}
11545 opcode(0xC3);
11546 ins_encode(OpcP);
11547 ins_pipe(pipe_jmp);
11548 %}
11549
11550 // Tail Call; Jump from runtime stub to Java code.
11551 // Also known as an 'interprocedural jump'.
11552 // Target of jump will eventually return to caller.
11553 // TailJump below removes the return address.
11554 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11555 %{
11556 match(TailCall jump_target method_oop);
11557
11558 ins_cost(300);
11559 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11560 opcode(0xFF, 0x4); /* Opcode FF /4 */
11561 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11562 ins_pipe(pipe_jmp);
11563 %}
11564
11565 // Tail Jump; remove the return address; jump to target.
11566 // TailCall above leaves the return address around.
11567 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11568 %{
11569 match(TailJump jump_target ex_oop);
11570
11571 ins_cost(300);
11572 format %{ "popq rdx\t# pop return address\n\t"
11573 "jmp $jump_target" %}
11574 opcode(0xFF, 0x4); /* Opcode FF /4 */
11575 ins_encode(Opcode(0x5a), // popq rdx
11576 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11577 ins_pipe(pipe_jmp);
11578 %}
11579
11580 // Create exception oop: created by stack-crawling runtime code.
11581 // Created exception is now available to this handler, and is setup
11582 // just prior to jumping to this handler. No code emitted.
11583 instruct CreateException(rax_RegP ex_oop)
11584 %{
11585 match(Set ex_oop (CreateEx));
11586
11587 size(0);
11588 // use the following format syntax
11589 format %{ "# exception oop is in rax; no code emitted" %}
11590 ins_encode();
11591 ins_pipe(empty);
11592 %}
11593
11594 // Rethrow exception:
11595 // The exception oop will come in the first argument position.
11596 // Then JUMP (not call) to the rethrow stub code.
11597 instruct RethrowException()
11598 %{
11599 match(Rethrow);
11600
11601 // use the following format syntax
11602 format %{ "jmp rethrow_stub" %}
11603 ins_encode(enc_rethrow);
11604 ins_pipe(pipe_jmp);
11605 %}
11606
11607
11608 //----------PEEPHOLE RULES-----------------------------------------------------
11609 // These must follow all instruction definitions as they use the names
11610 // defined in the instructions definitions.
11611 //
11612 // peepmatch ( root_instr_name [precerding_instruction]* );
11613 //
11614 // peepconstraint %{
11615 // (instruction_number.operand_name relational_op instruction_number.operand_name
11616 // [, ...] );
11617 // // instruction numbers are zero-based using left to right order in peepmatch
11618 //
11619 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11620 // // provide an instruction_number.operand_name for each operand that appears
11621 // // in the replacement instruction's match rule
11622 //
11623 // ---------VM FLAGS---------------------------------------------------------
11624 //
11625 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11626 //
11627 // Each peephole rule is given an identifying number starting with zero and
11628 // increasing by one in the order seen by the parser. An individual peephole
11629 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11630 // on the command-line.
11631 //
11632 // ---------CURRENT LIMITATIONS----------------------------------------------
11633 //
11634 // Only match adjacent instructions in same basic block
11635 // Only equality constraints
11636 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11637 // Only one replacement instruction
11638 //
11639 // ---------EXAMPLE----------------------------------------------------------
11640 //
11641 // // pertinent parts of existing instructions in architecture description
11642 // instruct movI(rRegI dst, rRegI src)
11643 // %{
11644 // match(Set dst (CopyI src));
11645 // %}
11646 //
11647 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11648 // %{
11649 // match(Set dst (AddI dst src));
11650 // effect(KILL cr);
11651 // %}
11652 //
11653 // // Change (inc mov) to lea
11654 // peephole %{
11655 // // increment preceeded by register-register move
11656 // peepmatch ( incI_rReg movI );
11657 // // require that the destination register of the increment
11658 // // match the destination register of the move
11659 // peepconstraint ( 0.dst == 1.dst );
11660 // // construct a replacement instruction that sets
11661 // // the destination to ( move's source register + one )
11662 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11663 // %}
11664 //
11665
11666 // Implementation no longer uses movX instructions since
11667 // machine-independent system no longer uses CopyX nodes.
11668 //
11669 // peephole
11670 // %{
11671 // peepmatch (incI_rReg movI);
11672 // peepconstraint (0.dst == 1.dst);
11673 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11674 // %}
11675
11676 // peephole
11677 // %{
11678 // peepmatch (decI_rReg movI);
11679 // peepconstraint (0.dst == 1.dst);
11680 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11681 // %}
11682
11683 // peephole
11684 // %{
11685 // peepmatch (addI_rReg_imm movI);
11686 // peepconstraint (0.dst == 1.dst);
11687 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11688 // %}
11689
11690 // peephole
11691 // %{
11692 // peepmatch (incL_rReg movL);
11693 // peepconstraint (0.dst == 1.dst);
11694 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11695 // %}
11696
11697 // peephole
11698 // %{
11699 // peepmatch (decL_rReg movL);
11700 // peepconstraint (0.dst == 1.dst);
11701 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11702 // %}
11703
11704 // peephole
11705 // %{
11706 // peepmatch (addL_rReg_imm movL);
11707 // peepconstraint (0.dst == 1.dst);
11708 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11709 // %}
11710
11711 // peephole
11712 // %{
11713 // peepmatch (addP_rReg_imm movP);
11714 // peepconstraint (0.dst == 1.dst);
11715 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11716 // %}
11717
11718 // // Change load of spilled value to only a spill
11719 // instruct storeI(memory mem, rRegI src)
11720 // %{
11721 // match(Set mem (StoreI mem src));
11722 // %}
11723 //
11724 // instruct loadI(rRegI dst, memory mem)
11725 // %{
11726 // match(Set dst (LoadI mem));
11727 // %}
11728 //
11729
11730 peephole
11731 %{
11732 peepmatch (loadI storeI);
11733 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11734 peepreplace (storeI(1.mem 1.mem 1.src));
11735 %}
11736
11737 peephole
11738 %{
11739 peepmatch (loadL storeL);
11740 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11741 peepreplace (storeL(1.mem 1.mem 1.src));
11742 %}
11743
11744 //----------SMARTSPILL RULES---------------------------------------------------
11745 // These must follow all instruction definitions as they use the names
11746 // defined in the instructions definitions.