src/share/vm/opto/divnode.cpp

*** 108,123 ****
        // we don't need to round a positive dividend
        needs_rounding = false;
      } else if( dividend->Opcode() == Op_AndI ) {
        // An AND mask of sufficient size clears the low bits and
        // I can avoid rounding.
!       const TypeInt *andconi = phase->type( dividend->in(2) )->isa_int();
!       if( andconi && andconi->is_con(-d) ) {
          dividend = dividend->in(1);
          needs_rounding = false;
        }
      }
  
      // Add rounding to the shift to handle the sign bit
      int l = log2_intptr(d-1)+1;
      if (needs_rounding) {
        // Divide-by-power-of-2 can be made into a shift, but you have to do
--- 108,126 ----
        // we don't need to round a positive dividend
        needs_rounding = false;
      } else if( dividend->Opcode() == Op_AndI ) {
        // An AND mask of sufficient size clears the low bits and
        // I can avoid rounding.
!       const TypeInt *andconi_t = phase->type( dividend->in(2) )->isa_int();
!       if( andconi_t && andconi_t->is_con() ) {
!         jint andconi = andconi_t->get_con();
!         if( andconi < 0 && is_power_of_2(-andconi) && (-andconi) >= d ) {
            dividend = dividend->in(1);
            needs_rounding = false;
          }
        }
+     }
  
      // Add rounding to the shift to handle the sign bit
      int l = log2_intptr(d-1)+1;
      if (needs_rounding) {
        // Divide-by-power-of-2 can be made into a shift, but you have to do
*** 314,329 ****
        // we don't need to round a positive dividend
        needs_rounding = false;
      } else if( dividend->Opcode() == Op_AndL ) {
        // An AND mask of sufficient size clears the low bits and
        // I can avoid rounding.
!       const TypeLong *andconl = phase->type( dividend->in(2) )->isa_long();
!       if( andconl && andconl->is_con(-d)) {
          dividend = dividend->in(1);
          needs_rounding = false;
        }
      }
  
      // Add rounding to the shift to handle the sign bit
      int l = log2_long(d-1)+1;
      if (needs_rounding) {
        // Divide-by-power-of-2 can be made into a shift, but you have to do
--- 317,335 ----
        // we don't need to round a positive dividend
        needs_rounding = false;
      } else if( dividend->Opcode() == Op_AndL ) {
        // An AND mask of sufficient size clears the low bits and
        // I can avoid rounding.
!       const TypeLong *andconl_t = phase->type( dividend->in(2) )->isa_long();
!       if( andconl_t && andconl_t->is_con() ) {
!         jlong andconl = andconl_t->get_con();
!         if( andconl < 0 && is_power_of_2_long(-andconl) && (-andconl) >= d ) {
            dividend = dividend->in(1);
            needs_rounding = false;
          }
        }
+     }
  
      // Add rounding to the shift to handle the sign bit
      int l = log2_long(d-1)+1;
      if (needs_rounding) {
        // Divide-by-power-of-2 can be made into a shift, but you have to do