225 _stepping = 0;
226 _cpuFeatures = 0;
227 _logical_processors_per_package = 1;
228 if (!Use486InstrsOnly) {
229 // Get raw processor info
230 getPsrInfo_stub(&_cpuid_info);
231 assert_is_initialized();
232 _cpu = extended_cpu_family();
233 _model = extended_cpu_model();
234 _stepping = cpu_stepping();
235 if (cpu_family() > 4) { // it supports CPUID
236 _cpuFeatures = feature_flags();
237 // Logical processors are only available on P4s and above,
238 // and only if hyperthreading is available.
239 _logical_processors_per_package = logical_processor_count();
240 }
241 }
242 _supports_cx8 = supports_cmpxchg8();
243 // if the OS doesn't support SSE, we can't use this feature even if the HW does
244 if( !os::supports_sse())
245 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4|CPU_SSE4A);
246 if (UseSSE < 4)
247 _cpuFeatures &= ~CPU_SSE4;
248 if (UseSSE < 3) {
249 _cpuFeatures &= ~CPU_SSE3;
250 _cpuFeatures &= ~CPU_SSSE3;
251 _cpuFeatures &= ~CPU_SSE4A;
252 }
253 if (UseSSE < 2)
254 _cpuFeatures &= ~CPU_SSE2;
255 if (UseSSE < 1)
256 _cpuFeatures &= ~CPU_SSE;
257
258 if (logical_processors_per_package() == 1) {
259 // HT processor could be installed on a system which doesn't support HT.
260 _cpuFeatures &= ~CPU_HT;
261 }
262
263 char buf[256];
264 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
265 cores_per_cpu(), threads_per_core(),
266 cpu_family(), _model, _stepping,
267 (supports_cmov() ? ", cmov" : ""),
268 (supports_cmpxchg8() ? ", cx8" : ""),
269 (supports_fxsr() ? ", fxsr" : ""),
270 (supports_mmx() ? ", mmx" : ""),
271 (supports_sse() ? ", sse" : ""),
272 (supports_sse2() ? ", sse2" : ""),
273 (supports_sse3() ? ", sse3" : ""),
274 (supports_ssse3()? ", ssse3": ""),
275 (supports_sse4() ? ", sse4" : ""),
276 (supports_mmx_ext() ? ", mmxext" : ""),
277 (supports_3dnow() ? ", 3dnow" : ""),
278 (supports_3dnow2() ? ", 3dnowext" : ""),
279 (supports_sse4a() ? ", sse4a": ""),
280 (supports_ht() ? ", ht": ""));
281 _features_str = strdup(buf);
282
283 // UseSSE is set to the smaller of what hardware supports and what
284 // the command line requires. I.e., you cannot set UseSSE to 2 on
285 // older Pentiums which do not support it.
286 if( UseSSE > 4 ) UseSSE=4;
287 if( UseSSE < 0 ) UseSSE=0;
288 if( !supports_sse4() ) // Drop to 3 if no SSE4 support
289 UseSSE = MIN2((intx)3,UseSSE);
290 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
291 UseSSE = MIN2((intx)2,UseSSE);
292 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
293 UseSSE = MIN2((intx)1,UseSSE);
294 if( !supports_sse () ) // Drop to 0 if no SSE support
295 UseSSE = 0;
296
297 // On new cpus instructions which update whole XMM register should be used
298 // to prevent partial register stall due to dependencies on high half.
299 //
300 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
301 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
302 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
303 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
304
305 if( is_amd() ) { // AMD cpus specific settings
306 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
307 // Use it on new AMD cpus starting from Opteron.
308 UseAddressNop = true;
358 if( supports_sse3() ) {
359 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
360 } else {
361 UseXmmRegToRegMoveAll = false;
362 }
363 }
364 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
365 #ifdef COMPILER2
366 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
367 // For new Intel cpus do the next optimization:
368 // don't align the beginning of a loop if there are enough instructions
369 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
370 // in current fetch line (OptoLoopAlignment) or the padding
371 // is big (> MaxLoopPad).
372 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
373 // generated NOP instructions. 11 is the largest size of one
374 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
375 MaxLoopPad = 11;
376 }
377 #endif // COMPILER2
378 }
379 }
380
381 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
382 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
383
384 // set valid Prefetch instruction
385 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
386 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
387 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
388 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
389
390 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
391 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
392 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
393 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
394
395 // Allocation prefetch settings
396 intx cache_line_size = L1_data_cache_line_size();
397 if( cache_line_size > AllocatePrefetchStepSize )
398 AllocatePrefetchStepSize = cache_line_size;
399 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
400 AllocatePrefetchLines = 3; // Optimistic value
401 assert(AllocatePrefetchLines > 0, "invalid value");
402 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
403 AllocatePrefetchLines = 1; // Conservative value
404
405 AllocatePrefetchDistance = allocate_prefetch_distance();
406 AllocatePrefetchStyle = allocate_prefetch_style();
407
408 if( AllocatePrefetchStyle == 2 && is_intel() &&
409 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
410 AllocatePrefetchDistance = 320;
411 }
412 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
413
414 #ifndef PRODUCT
415 if (PrintMiscellaneous && Verbose) {
416 tty->print_cr("Logical CPUs per package: %u",
417 logical_processors_per_package());
418 tty->print_cr("UseSSE=%d",UseSSE);
419 tty->print("Allocation: ");
420 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
421 tty->print_cr("no prefetching");
422 } else {
423 if (UseSSE == 0 && supports_3dnow()) {
424 tty->print("PREFETCHW");
425 } else if (UseSSE >= 1) {
426 if (AllocatePrefetchInstr == 0) {
427 tty->print("PREFETCHNTA");
428 } else if (AllocatePrefetchInstr == 1) {
429 tty->print("PREFETCHT0");
430 } else if (AllocatePrefetchInstr == 2) {
431 tty->print("PREFETCHT2");
432 } else if (AllocatePrefetchInstr == 3) {
433 tty->print("PREFETCHW");
434 }
435 }
436 if (AllocatePrefetchLines > 1) {
|
225 _stepping = 0;
226 _cpuFeatures = 0;
227 _logical_processors_per_package = 1;
228 if (!Use486InstrsOnly) {
229 // Get raw processor info
230 getPsrInfo_stub(&_cpuid_info);
231 assert_is_initialized();
232 _cpu = extended_cpu_family();
233 _model = extended_cpu_model();
234 _stepping = cpu_stepping();
235 if (cpu_family() > 4) { // it supports CPUID
236 _cpuFeatures = feature_flags();
237 // Logical processors are only available on P4s and above,
238 // and only if hyperthreading is available.
239 _logical_processors_per_package = logical_processor_count();
240 }
241 }
242 _supports_cx8 = supports_cmpxchg8();
243 // if the OS doesn't support SSE, we can't use this feature even if the HW does
244 if( !os::supports_sse())
245 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
246 if (UseSSE < 4)
247 _cpuFeatures &= ~CPU_SSE4_1;
248 _cpuFeatures &= ~CPU_SSE4_2;
249 if (UseSSE < 3) {
250 _cpuFeatures &= ~CPU_SSE3;
251 _cpuFeatures &= ~CPU_SSSE3;
252 _cpuFeatures &= ~CPU_SSE4A;
253 }
254 if (UseSSE < 2)
255 _cpuFeatures &= ~CPU_SSE2;
256 if (UseSSE < 1)
257 _cpuFeatures &= ~CPU_SSE;
258
259 if (logical_processors_per_package() == 1) {
260 // HT processor could be installed on a system which doesn't support HT.
261 _cpuFeatures &= ~CPU_HT;
262 }
263
264 char buf[256];
265 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
266 cores_per_cpu(), threads_per_core(),
267 cpu_family(), _model, _stepping,
268 (supports_cmov() ? ", cmov" : ""),
269 (supports_cmpxchg8() ? ", cx8" : ""),
270 (supports_fxsr() ? ", fxsr" : ""),
271 (supports_mmx() ? ", mmx" : ""),
272 (supports_sse() ? ", sse" : ""),
273 (supports_sse2() ? ", sse2" : ""),
274 (supports_sse3() ? ", sse3" : ""),
275 (supports_ssse3()? ", ssse3": ""),
276 (supports_sse4_1() ? ", sse4.1" : ""),
277 (supports_sse4_2() ? ", sse4.2" : ""),
278 (supports_mmx_ext() ? ", mmxext" : ""),
279 (supports_3dnow() ? ", 3dnow" : ""),
280 (supports_3dnow2() ? ", 3dnowext" : ""),
281 (supports_sse4a() ? ", sse4a": ""),
282 (supports_ht() ? ", ht": ""));
283 _features_str = strdup(buf);
284
285 // UseSSE is set to the smaller of what hardware supports and what
286 // the command line requires. I.e., you cannot set UseSSE to 2 on
287 // older Pentiums which do not support it.
288 if( UseSSE > 4 ) UseSSE=4;
289 if( UseSSE < 0 ) UseSSE=0;
290 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
291 UseSSE = MIN2((intx)3,UseSSE);
292 if( !supports_sse3() ) // Drop to 2 if no SSE3 support
293 UseSSE = MIN2((intx)2,UseSSE);
294 if( !supports_sse2() ) // Drop to 1 if no SSE2 support
295 UseSSE = MIN2((intx)1,UseSSE);
296 if( !supports_sse () ) // Drop to 0 if no SSE support
297 UseSSE = 0;
298
299 // On new cpus instructions which update whole XMM register should be used
300 // to prevent partial register stall due to dependencies on high half.
301 //
302 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
303 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
304 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
305 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
306
307 if( is_amd() ) { // AMD cpus specific settings
308 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
309 // Use it on new AMD cpus starting from Opteron.
310 UseAddressNop = true;
360 if( supports_sse3() ) {
361 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
362 } else {
363 UseXmmRegToRegMoveAll = false;
364 }
365 }
366 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
367 #ifdef COMPILER2
368 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
369 // For new Intel cpus do the next optimization:
370 // don't align the beginning of a loop if there are enough instructions
371 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
372 // in current fetch line (OptoLoopAlignment) or the padding
373 // is big (> MaxLoopPad).
374 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
375 // generated NOP instructions. 11 is the largest size of one
376 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
377 MaxLoopPad = 11;
378 }
379 #endif // COMPILER2
380 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
381 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
382 }
383 if( supports_sse4_1() && supports_ht() ) { // Newest Intel cpus
384 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
385 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
386 }
387 }
388 }
389 }
390
391 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
392 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
393
394 // set valid Prefetch instruction
395 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
396 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
397 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
398 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
399
400 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
401 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
402 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
403 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
404
405 // Allocation prefetch settings
406 intx cache_line_size = L1_data_cache_line_size();
407 if( cache_line_size > AllocatePrefetchStepSize )
408 AllocatePrefetchStepSize = cache_line_size;
409 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
410 AllocatePrefetchLines = 3; // Optimistic value
411 assert(AllocatePrefetchLines > 0, "invalid value");
412 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
413 AllocatePrefetchLines = 1; // Conservative value
414
415 AllocatePrefetchDistance = allocate_prefetch_distance();
416 AllocatePrefetchStyle = allocate_prefetch_style();
417
418 if( AllocatePrefetchStyle == 2 && is_intel() &&
419 cpu_family() == 6 && supports_sse3() ) { // watermark prefetching on Core
420 AllocatePrefetchDistance = 320;
421 }
422 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
423
424 #ifndef PRODUCT
425 if (PrintMiscellaneous && Verbose) {
426 tty->print_cr("Logical CPUs per core: %u",
427 logical_processors_per_package());
428 tty->print_cr("UseSSE=%d",UseSSE);
429 tty->print("Allocation: ");
430 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow()) {
431 tty->print_cr("no prefetching");
432 } else {
433 if (UseSSE == 0 && supports_3dnow()) {
434 tty->print("PREFETCHW");
435 } else if (UseSSE >= 1) {
436 if (AllocatePrefetchInstr == 0) {
437 tty->print("PREFETCHNTA");
438 } else if (AllocatePrefetchInstr == 1) {
439 tty->print("PREFETCHT0");
440 } else if (AllocatePrefetchInstr == 2) {
441 tty->print("PREFETCHT2");
442 } else if (AllocatePrefetchInstr == 3) {
443 tty->print("PREFETCHW");
444 }
445 }
446 if (AllocatePrefetchLines > 1) {
|