1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for x86 assembly code generation.
28
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
48
49
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
53
54 #ifdef _WIN64
55
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
60
61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
65
66 #else
67
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
74
75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
83
84 #endif // _WIN64
85
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
101
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
114
115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
123
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
126
127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
129
130 #else
131 // rscratch1 will apear in 32bit code that is dead but of course must compile
132 // Using noreg ensures if the dead code is incorrectly live and executed it
133 // will cause an assertion failure
134 #define rscratch1 noreg
135
136 #endif // _LP64
137
138 // Address is an abstraction used to represent a memory location
139 // using any of the amd64 addressing modes with one object.
140 //
141 // Note: A register location is represented via a Register, not
142 // via an address for efficiency & simplicity reasons.
143
144 class ArrayAddress;
145
146 class Address VALUE_OBJ_CLASS_SPEC {
147 public:
148 enum ScaleFactor {
149 no_scale = -1,
150 times_1 = 0,
151 times_2 = 1,
152 times_4 = 2,
153 times_8 = 3,
154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
155 };
156
157 private:
158 Register _base;
159 Register _index;
160 ScaleFactor _scale;
161 int _disp;
162 RelocationHolder _rspec;
163
164 // Easily misused constructors make them private
165 // %%% can we make these go away?
166 NOT_LP64(Address(address loc, RelocationHolder spec);)
167 Address(int disp, address loc, relocInfo::relocType rtype);
168 Address(int disp, address loc, RelocationHolder spec);
169
170 public:
171
172 int disp() { return _disp; }
173 // creation
174 Address()
175 : _base(noreg),
176 _index(noreg),
177 _scale(no_scale),
178 _disp(0) {
179 }
180
181 // No default displacement otherwise Register can be implicitly
182 // converted to 0(Register) which is quite a different animal.
183
184 Address(Register base, int disp)
185 : _base(base),
186 _index(noreg),
187 _scale(no_scale),
188 _disp(disp) {
189 }
190
191 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
192 : _base (base),
193 _index(index),
194 _scale(scale),
195 _disp (disp) {
196 assert(!index->is_valid() == (scale == Address::no_scale),
197 "inconsistent address");
198 }
199
200 // The following two overloads are used in connection with the
201 // ByteSize type (see sizes.hpp). They simplify the use of
202 // ByteSize'd arguments in assembly code. Note that their equivalent
203 // for the optimized build are the member functions with int disp
204 // argument since ByteSize is mapped to an int type in that case.
205 //
206 // Note: DO NOT introduce similar overloaded functions for WordSize
207 // arguments as in the optimized mode, both ByteSize and WordSize
208 // are mapped to the same type and thus the compiler cannot make a
209 // distinction anymore (=> compiler errors).
210
211 #ifdef ASSERT
212 Address(Register base, ByteSize disp)
213 : _base(base),
214 _index(noreg),
215 _scale(no_scale),
216 _disp(in_bytes(disp)) {
217 }
218
219 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
220 : _base(base),
221 _index(index),
222 _scale(scale),
223 _disp(in_bytes(disp)) {
224 assert(!index->is_valid() == (scale == Address::no_scale),
225 "inconsistent address");
226 }
227 #endif // ASSERT
228
229 // accessors
230 bool uses(Register reg) const { return _base == reg || _index == reg; }
231 Register base() const { return _base; }
232 Register index() const { return _index; }
233 ScaleFactor scale() const { return _scale; }
234 int disp() const { return _disp; }
235
236 // Convert the raw encoding form into the form expected by the constructor for
237 // Address. An index of 4 (rsp) corresponds to having no index, so convert
238 // that to noreg for the Address constructor.
239 static Address make_raw(int base, int index, int scale, int disp);
240
241 static Address make_array(ArrayAddress);
242
243
244 private:
245 bool base_needs_rex() const {
246 return _base != noreg && _base->encoding() >= 8;
247 }
248
249 bool index_needs_rex() const {
250 return _index != noreg &&_index->encoding() >= 8;
251 }
252
253 relocInfo::relocType reloc() const { return _rspec.type(); }
254
255 friend class Assembler;
256 friend class MacroAssembler;
257 friend class LIR_Assembler; // base/index/scale/disp
258 };
259
260 //
261 // AddressLiteral has been split out from Address because operands of this type
262 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
263 // the few instructions that need to deal with address literals are unique and the
264 // MacroAssembler does not have to implement every instruction in the Assembler
265 // in order to search for address literals that may need special handling depending
266 // on the instruction and the platform. As small step on the way to merging i486/amd64
267 // directories.
268 //
269 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
270 friend class ArrayAddress;
271 RelocationHolder _rspec;
272 // Typically we use AddressLiterals we want to use their rval
273 // However in some situations we want the lval (effect address) of the item.
274 // We provide a special factory for making those lvals.
275 bool _is_lval;
276
277 // If the target is far we'll need to load the ea of this to
278 // a register to reach it. Otherwise if near we can do rip
279 // relative addressing.
280
281 address _target;
282
283 protected:
284 // creation
285 AddressLiteral()
286 : _is_lval(false),
287 _target(NULL)
288 {}
289
290 public:
291
292
293 AddressLiteral(address target, relocInfo::relocType rtype);
294
295 AddressLiteral(address target, RelocationHolder const& rspec)
296 : _rspec(rspec),
297 _is_lval(false),
298 _target(target)
299 {}
300
301 AddressLiteral addr() {
302 AddressLiteral ret = *this;
303 ret._is_lval = true;
304 return ret;
305 }
306
307
308 private:
309
310 address target() { return _target; }
311 bool is_lval() { return _is_lval; }
312
313 relocInfo::relocType reloc() const { return _rspec.type(); }
314 const RelocationHolder& rspec() const { return _rspec; }
315
316 friend class Assembler;
317 friend class MacroAssembler;
318 friend class Address;
319 friend class LIR_Assembler;
320 };
321
322 // Convience classes
323 class RuntimeAddress: public AddressLiteral {
324
325 public:
326
327 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
328
329 };
330
331 class OopAddress: public AddressLiteral {
332
333 public:
334
335 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
336
337 };
338
339 class ExternalAddress: public AddressLiteral {
340
341 public:
342
343 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
344
345 };
346
347 class InternalAddress: public AddressLiteral {
348
349 public:
350
351 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
352
353 };
354
355 // x86 can do array addressing as a single operation since disp can be an absolute
356 // address amd64 can't. We create a class that expresses the concept but does extra
357 // magic on amd64 to get the final result
358
359 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
360 private:
361
362 AddressLiteral _base;
363 Address _index;
364
365 public:
366
367 ArrayAddress() {};
368 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
369 AddressLiteral base() { return _base; }
370 Address index() { return _index; }
371
372 };
373
374 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
375
376 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
377 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
378 // is what you get. The Assembler is generating code into a CodeBuffer.
379
380 class Assembler : public AbstractAssembler {
381 friend class AbstractAssembler; // for the non-virtual hack
382 friend class LIR_Assembler; // as_Address()
383 friend class StubGenerator;
384
385 public:
386 enum Condition { // The x86 condition codes used for conditional jumps/moves.
387 zero = 0x4,
388 notZero = 0x5,
389 equal = 0x4,
390 notEqual = 0x5,
391 less = 0xc,
392 lessEqual = 0xe,
393 greater = 0xf,
394 greaterEqual = 0xd,
395 below = 0x2,
396 belowEqual = 0x6,
397 above = 0x7,
398 aboveEqual = 0x3,
399 overflow = 0x0,
400 noOverflow = 0x1,
401 carrySet = 0x2,
402 carryClear = 0x3,
403 negative = 0x8,
404 positive = 0x9,
405 parity = 0xa,
406 noParity = 0xb
407 };
408
409 enum Prefix {
410 // segment overrides
411 CS_segment = 0x2e,
412 SS_segment = 0x36,
413 DS_segment = 0x3e,
414 ES_segment = 0x26,
415 FS_segment = 0x64,
416 GS_segment = 0x65,
417
418 REX = 0x40,
419
420 REX_B = 0x41,
421 REX_X = 0x42,
422 REX_XB = 0x43,
423 REX_R = 0x44,
424 REX_RB = 0x45,
425 REX_RX = 0x46,
426 REX_RXB = 0x47,
427
428 REX_W = 0x48,
429
430 REX_WB = 0x49,
431 REX_WX = 0x4A,
432 REX_WXB = 0x4B,
433 REX_WR = 0x4C,
434 REX_WRB = 0x4D,
435 REX_WRX = 0x4E,
436 REX_WRXB = 0x4F
437 };
438
439 enum WhichOperand {
440 // input to locate_operand, and format code for relocations
441 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
442 disp32_operand = 1, // embedded 32-bit displacement or address
443 call32_operand = 2, // embedded 32-bit self-relative displacement
444 #ifndef _LP64
445 _WhichOperand_limit = 3
446 #else
447 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
448 _WhichOperand_limit = 4
449 #endif
450 };
451
452
453
454 // NOTE: The general philopsophy of the declarations here is that 64bit versions
455 // of instructions are freely declared without the need for wrapping them an ifdef.
456 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
457 // In the .cpp file the implementations are wrapped so that they are dropped out
458 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
459 // to the size it was prior to merging up the 32bit and 64bit assemblers.
460 //
461 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
462 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
463
464 private:
465
466
467 // 64bit prefixes
468 int prefix_and_encode(int reg_enc, bool byteinst = false);
469 int prefixq_and_encode(int reg_enc);
470
471 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
472 int prefixq_and_encode(int dst_enc, int src_enc);
473
474 void prefix(Register reg);
475 void prefix(Address adr);
476 void prefixq(Address adr);
477
478 void prefix(Address adr, Register reg, bool byteinst = false);
479 void prefixq(Address adr, Register reg);
480
481 void prefix(Address adr, XMMRegister reg);
482
483 void prefetch_prefix(Address src);
484
485 // Helper functions for groups of instructions
486 void emit_arith_b(int op1, int op2, Register dst, int imm8);
487
488 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
489 // only 32bit??
490 void emit_arith(int op1, int op2, Register dst, jobject obj);
491 void emit_arith(int op1, int op2, Register dst, Register src);
492
493 void emit_operand(Register reg,
494 Register base, Register index, Address::ScaleFactor scale,
495 int disp,
496 RelocationHolder const& rspec,
497 int rip_relative_correction = 0);
498
499 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
500
501 // operands that only take the original 32bit registers
502 void emit_operand32(Register reg, Address adr);
503
504 void emit_operand(XMMRegister reg,
505 Register base, Register index, Address::ScaleFactor scale,
506 int disp,
507 RelocationHolder const& rspec);
508
509 void emit_operand(XMMRegister reg, Address adr);
510
511 void emit_operand(MMXRegister reg, Address adr);
512
513 // workaround gcc (3.2.1-7) bug
514 void emit_operand(Address adr, MMXRegister reg);
515
516
517 // Immediate-to-memory forms
518 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
519
520 void emit_farith(int b1, int b2, int i);
521
522
523 protected:
524 #ifdef ASSERT
525 void check_relocation(RelocationHolder const& rspec, int format);
526 #endif
527
528 inline void emit_long64(jlong x);
529
530 void emit_data(jint data, relocInfo::relocType rtype, int format);
531 void emit_data(jint data, RelocationHolder const& rspec, int format);
532 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
533 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
534
535
536 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
537
538 // These are all easily abused and hence protected
539
540 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0);
541
542 // 32BIT ONLY SECTION
543 #ifndef _LP64
544 // Make these disappear in 64bit mode since they would never be correct
545 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
546 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
547
548 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
549
550 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
551 #else
552 // 64BIT ONLY SECTION
553 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
554 #endif // _LP64
555
556 // These are unique in that we are ensured by the caller that the 32bit
557 // relative in these instructions will always be able to reach the potentially
558 // 64bit address described by entry. Since they can take a 64bit address they
559 // don't have the 32 suffix like the other instructions in this class.
560
561 void call_literal(address entry, RelocationHolder const& rspec);
562 void jmp_literal(address entry, RelocationHolder const& rspec);
563
564 // Avoid using directly section
565 // Instructions in this section are actually usable by anyone without danger
566 // of failure but have performance issues that are addressed my enhanced
567 // instructions which will do the proper thing base on the particular cpu.
568 // We protect them because we don't trust you...
569
570 // Don't use next inc() and dec() methods directly. INC & DEC instructions
571 // could cause a partial flag stall since they don't set CF flag.
572 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
573 // which call inc() & dec() or add() & sub() in accordance with
574 // the product flag UseIncDec value.
575
576 void decl(Register dst);
577 void decl(Address dst);
578 void decq(Register dst);
579 void decq(Address dst);
580
581 void incl(Register dst);
582 void incl(Address dst);
583 void incq(Register dst);
584 void incq(Address dst);
585
586 // New cpus require use of movsd and movss to avoid partial register stall
587 // when loading from memory. But for old Opteron use movlpd instead of movsd.
588 // The selection is done in MacroAssembler::movdbl() and movflt().
589
590 // Move Scalar Single-Precision Floating-Point Values
591 void movss(XMMRegister dst, Address src);
592 void movss(XMMRegister dst, XMMRegister src);
593 void movss(Address dst, XMMRegister src);
594
595 // Move Scalar Double-Precision Floating-Point Values
596 void movsd(XMMRegister dst, Address src);
597 void movsd(XMMRegister dst, XMMRegister src);
598 void movsd(Address dst, XMMRegister src);
599 void movlpd(XMMRegister dst, Address src);
600
601 // New cpus require use of movaps and movapd to avoid partial register stall
602 // when moving between registers.
603 void movaps(XMMRegister dst, XMMRegister src);
604 void movapd(XMMRegister dst, XMMRegister src);
605
606 // End avoid using directly
607
608
609 // Instruction prefixes
610 void prefix(Prefix p);
611
612 public:
613
614 // Creation
615 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
616
617 // Decoding
618 static address locate_operand(address inst, WhichOperand which);
619 static address locate_next_instruction(address inst);
620
621 // Utilities
622
623 #ifdef _LP64
624 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
625 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
626 #else
627 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
628 static bool is_simm32(int32_t x) { return true; }
629 #endif // LP64
630
631 // Generic instructions
632 // Does 32bit or 64bit as needed for the platform. In some sense these
633 // belong in macro assembler but there is no need for both varieties to exist
634
635 void lea(Register dst, Address src);
636
637 void mov(Register dst, Register src);
638
639 void pusha();
640 void popa();
641
642 void pushf();
643 void popf();
644
645 void push(int32_t imm32);
646
647 void push(Register src);
648
649 void pop(Register dst);
650
651 // These are dummies to prevent surprise implicit conversions to Register
652 void push(void* v);
653 void pop(void* v);
654
655
656 // These do register sized moves/scans
657 void rep_mov();
658 void rep_set();
659 void repne_scan();
660 #ifdef _LP64
661 void repne_scanl();
662 #endif
663
664 // Vanilla instructions in lexical order
665
666 void adcl(Register dst, int32_t imm32);
667 void adcl(Register dst, Address src);
668 void adcl(Register dst, Register src);
669
670 void adcq(Register dst, int32_t imm32);
671 void adcq(Register dst, Address src);
672 void adcq(Register dst, Register src);
673
674
675 void addl(Address dst, int32_t imm32);
676 void addl(Address dst, Register src);
677 void addl(Register dst, int32_t imm32);
678 void addl(Register dst, Address src);
679 void addl(Register dst, Register src);
680
681 void addq(Address dst, int32_t imm32);
682 void addq(Address dst, Register src);
683 void addq(Register dst, int32_t imm32);
684 void addq(Register dst, Address src);
685 void addq(Register dst, Register src);
686
687
688 void addr_nop_4();
689 void addr_nop_5();
690 void addr_nop_7();
691 void addr_nop_8();
692
693 // Add Scalar Double-Precision Floating-Point Values
694 void addsd(XMMRegister dst, Address src);
695 void addsd(XMMRegister dst, XMMRegister src);
696
697 // Add Scalar Single-Precision Floating-Point Values
698 void addss(XMMRegister dst, Address src);
699 void addss(XMMRegister dst, XMMRegister src);
700
701 void andl(Register dst, int32_t imm32);
702 void andl(Register dst, Address src);
703 void andl(Register dst, Register src);
704
705 void andq(Register dst, int32_t imm32);
706 void andq(Register dst, Address src);
707 void andq(Register dst, Register src);
708
709
710 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
711 void andpd(XMMRegister dst, Address src);
712 void andpd(XMMRegister dst, XMMRegister src);
713
714 void bswapl(Register reg);
715
716 void bswapq(Register reg);
717
718 void call(Label& L, relocInfo::relocType rtype);
719 void call(Register reg); // push pc; pc <- reg
720 void call(Address adr); // push pc; pc <- adr
721
722 void cdql();
723
724 void cdqq();
725
726 void cld() { emit_byte(0xfc); }
727
728 void clflush(Address adr);
729
730 void cmovl(Condition cc, Register dst, Register src);
731 void cmovl(Condition cc, Register dst, Address src);
732
733 void cmovq(Condition cc, Register dst, Register src);
734 void cmovq(Condition cc, Register dst, Address src);
735
736
737 void cmpb(Address dst, int imm8);
738
739 void cmpl(Address dst, int32_t imm32);
740
741 void cmpl(Register dst, int32_t imm32);
742 void cmpl(Register dst, Register src);
743 void cmpl(Register dst, Address src);
744
745 void cmpq(Address dst, int32_t imm32);
746 void cmpq(Address dst, Register src);
747
748 void cmpq(Register dst, int32_t imm32);
749 void cmpq(Register dst, Register src);
750 void cmpq(Register dst, Address src);
751
752 // these are dummies used to catch attempting to convert NULL to Register
753 void cmpl(Register dst, void* junk); // dummy
754 void cmpq(Register dst, void* junk); // dummy
755
756 void cmpw(Address dst, int imm16);
757
758 void cmpxchg8 (Address adr);
759
760 void cmpxchgl(Register reg, Address adr);
761
762 void cmpxchgq(Register reg, Address adr);
763
764 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
765 void comisd(XMMRegister dst, Address src);
766
767 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
768 void comiss(XMMRegister dst, Address src);
769
770 // Identify processor type and features
771 void cpuid() {
772 emit_byte(0x0F);
773 emit_byte(0xA2);
774 }
775
776 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
777 void cvtsd2ss(XMMRegister dst, XMMRegister src);
778
779 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
780 void cvtsi2sdl(XMMRegister dst, Register src);
781 void cvtsi2sdq(XMMRegister dst, Register src);
782
783 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
784 void cvtsi2ssl(XMMRegister dst, Register src);
785 void cvtsi2ssq(XMMRegister dst, Register src);
786
787 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
788 void cvtdq2pd(XMMRegister dst, XMMRegister src);
789
790 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
791 void cvtdq2ps(XMMRegister dst, XMMRegister src);
792
793 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
794 void cvtss2sd(XMMRegister dst, XMMRegister src);
795
796 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
797 void cvttsd2sil(Register dst, Address src);
798 void cvttsd2sil(Register dst, XMMRegister src);
799 void cvttsd2siq(Register dst, XMMRegister src);
800
801 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
802 void cvttss2sil(Register dst, XMMRegister src);
803 void cvttss2siq(Register dst, XMMRegister src);
804
805 // Divide Scalar Double-Precision Floating-Point Values
806 void divsd(XMMRegister dst, Address src);
807 void divsd(XMMRegister dst, XMMRegister src);
808
809 // Divide Scalar Single-Precision Floating-Point Values
810 void divss(XMMRegister dst, Address src);
811 void divss(XMMRegister dst, XMMRegister src);
812
813 void emms();
814
815 void fabs();
816
817 void fadd(int i);
818
819 void fadd_d(Address src);
820 void fadd_s(Address src);
821
822 // "Alternate" versions of x87 instructions place result down in FPU
823 // stack instead of on TOS
824
825 void fadda(int i); // "alternate" fadd
826 void faddp(int i = 1);
827
828 void fchs();
829
830 void fcom(int i);
831
832 void fcomp(int i = 1);
833 void fcomp_d(Address src);
834 void fcomp_s(Address src);
835
836 void fcompp();
837
838 void fcos();
839
840 void fdecstp();
841
842 void fdiv(int i);
843 void fdiv_d(Address src);
844 void fdivr_s(Address src);
845 void fdiva(int i); // "alternate" fdiv
846 void fdivp(int i = 1);
847
848 void fdivr(int i);
849 void fdivr_d(Address src);
850 void fdiv_s(Address src);
851
852 void fdivra(int i); // "alternate" reversed fdiv
853
854 void fdivrp(int i = 1);
855
856 void ffree(int i = 0);
857
858 void fild_d(Address adr);
859 void fild_s(Address adr);
860
861 void fincstp();
862
863 void finit();
864
865 void fist_s (Address adr);
866 void fistp_d(Address adr);
867 void fistp_s(Address adr);
868
869 void fld1();
870
871 void fld_d(Address adr);
872 void fld_s(Address adr);
873 void fld_s(int index);
874 void fld_x(Address adr); // extended-precision (80-bit) format
875
876 void fldcw(Address src);
877
878 void fldenv(Address src);
879
880 void fldlg2();
881
882 void fldln2();
883
884 void fldz();
885
886 void flog();
887 void flog10();
888
889 void fmul(int i);
890
891 void fmul_d(Address src);
892 void fmul_s(Address src);
893
894 void fmula(int i); // "alternate" fmul
895
896 void fmulp(int i = 1);
897
898 void fnsave(Address dst);
899
900 void fnstcw(Address src);
901
902 void fnstsw_ax();
903
904 void fprem();
905 void fprem1();
906
907 void frstor(Address src);
908
909 void fsin();
910
911 void fsqrt();
912
913 void fst_d(Address adr);
914 void fst_s(Address adr);
915
916 void fstp_d(Address adr);
917 void fstp_d(int index);
918 void fstp_s(Address adr);
919 void fstp_x(Address adr); // extended-precision (80-bit) format
920
921 void fsub(int i);
922 void fsub_d(Address src);
923 void fsub_s(Address src);
924
925 void fsuba(int i); // "alternate" fsub
926
927 void fsubp(int i = 1);
928
929 void fsubr(int i);
930 void fsubr_d(Address src);
931 void fsubr_s(Address src);
932
933 void fsubra(int i); // "alternate" reversed fsub
934
935 void fsubrp(int i = 1);
936
937 void ftan();
938
939 void ftst();
940
941 void fucomi(int i = 1);
942 void fucomip(int i = 1);
943
944 void fwait();
945
946 void fxch(int i = 1);
947
948 void fxrstor(Address src);
949
950 void fxsave(Address dst);
951
952 void fyl2x();
953
954 void hlt();
955
956 void idivl(Register src);
957
958 void idivq(Register src);
959
960 void imull(Register dst, Register src);
961 void imull(Register dst, Register src, int value);
962
963 void imulq(Register dst, Register src);
964 void imulq(Register dst, Register src, int value);
965
966
967 // jcc is the generic conditional branch generator to run-
968 // time routines, jcc is used for branches to labels. jcc
969 // takes a branch opcode (cc) and a label (L) and generates
970 // either a backward branch or a forward branch and links it
971 // to the label fixup chain. Usage:
972 //
973 // Label L; // unbound label
974 // jcc(cc, L); // forward branch to unbound label
975 // bind(L); // bind label to the current pc
976 // jcc(cc, L); // backward branch to bound label
977 // bind(L); // illegal: a label may be bound only once
978 //
979 // Note: The same Label can be used for forward and backward branches
980 // but it may be bound only once.
981
982 void jcc(Condition cc, Label& L,
983 relocInfo::relocType rtype = relocInfo::none);
984
985 // Conditional jump to a 8-bit offset to L.
986 // WARNING: be very careful using this for forward jumps. If the label is
987 // not bound within an 8-bit offset of this instruction, a run-time error
988 // will occur.
989 void jccb(Condition cc, Label& L);
990
991 void jmp(Address entry); // pc <- entry
992
993 // Label operations & relative jumps (PPUM Appendix D)
994 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
995
996 void jmp(Register entry); // pc <- entry
997
998 // Unconditional 8-bit offset jump to L.
999 // WARNING: be very careful using this for forward jumps. If the label is
1000 // not bound within an 8-bit offset of this instruction, a run-time error
1001 // will occur.
1002 void jmpb(Label& L);
1003
1004 void ldmxcsr( Address src );
1005
1006 void leal(Register dst, Address src);
1007
1008 void leaq(Register dst, Address src);
1009
1010 void lfence() {
1011 emit_byte(0x0F);
1012 emit_byte(0xAE);
1013 emit_byte(0xE8);
1014 }
1015
1016 void lock();
1017
1018 enum Membar_mask_bits {
1019 StoreStore = 1 << 3,
1020 LoadStore = 1 << 2,
1021 StoreLoad = 1 << 1,
1022 LoadLoad = 1 << 0
1023 };
1024
1025 // Serializes memory.
1026 void membar(Membar_mask_bits order_constraint) {
1027 // We only have to handle StoreLoad and LoadLoad
1028 if (order_constraint & StoreLoad) {
1029 // MFENCE subsumes LFENCE
1030 mfence();
1031 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
1032 lfence();
1033 } */
1034 }
1035
1036 void mfence();
1037
1038 // Moves
1039
1040 void mov64(Register dst, int64_t imm64);
1041
1042 void movb(Address dst, Register src);
1043 void movb(Address dst, int imm8);
1044 void movb(Register dst, Address src);
1045
1046 void movdl(XMMRegister dst, Register src);
1047 void movdl(Register dst, XMMRegister src);
1048
1049 // Move Double Quadword
1050 void movdq(XMMRegister dst, Register src);
1051 void movdq(Register dst, XMMRegister src);
1052
1053 // Move Aligned Double Quadword
1054 void movdqa(Address dst, XMMRegister src);
1055 void movdqa(XMMRegister dst, Address src);
1056 void movdqa(XMMRegister dst, XMMRegister src);
1057
1058 // Move Unaligned Double Quadword
1059 void movdqu(Address dst, XMMRegister src);
1060 void movdqu(XMMRegister dst, Address src);
1061 void movdqu(XMMRegister dst, XMMRegister src);
1062
1063 void movl(Register dst, int32_t imm32);
1064 void movl(Address dst, int32_t imm32);
1065 void movl(Register dst, Register src);
1066 void movl(Register dst, Address src);
1067 void movl(Address dst, Register src);
1068
1069 // These dummies prevent using movl from converting a zero (like NULL) into Register
1070 // by giving the compiler two choices it can't resolve
1071
1072 void movl(Address dst, void* junk);
1073 void movl(Register dst, void* junk);
1074
1075 #ifdef _LP64
1076 void movq(Register dst, Register src);
1077 void movq(Register dst, Address src);
1078 void movq(Address dst, Register src);
1079 #endif
1080
1081 void movq(Address dst, MMXRegister src );
1082 void movq(MMXRegister dst, Address src );
1083
1084 #ifdef _LP64
1085 // These dummies prevent using movq from converting a zero (like NULL) into Register
1086 // by giving the compiler two choices it can't resolve
1087
1088 void movq(Address dst, void* dummy);
1089 void movq(Register dst, void* dummy);
1090 #endif
1091
1092 // Move Quadword
1093 void movq(Address dst, XMMRegister src);
1094 void movq(XMMRegister dst, Address src);
1095
1096 void movsbl(Register dst, Address src);
1097 void movsbl(Register dst, Register src);
1098
1099 #ifdef _LP64
1100 // Move signed 32bit immediate to 64bit extending sign
1101 void movslq(Address dst, int32_t imm64);
1102 void movslq(Register dst, int32_t imm64);
1103
1104 void movslq(Register dst, Address src);
1105 void movslq(Register dst, Register src);
1106 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1107 #endif
1108
1109 void movswl(Register dst, Address src);
1110 void movswl(Register dst, Register src);
1111
1112 void movw(Address dst, int imm16);
1113 void movw(Register dst, Address src);
1114 void movw(Address dst, Register src);
1115
1116 void movzbl(Register dst, Address src);
1117 void movzbl(Register dst, Register src);
1118
1119 void movzwl(Register dst, Address src);
1120 void movzwl(Register dst, Register src);
1121
1122 void mull(Address src);
1123 void mull(Register src);
1124
1125 // Multiply Scalar Double-Precision Floating-Point Values
1126 void mulsd(XMMRegister dst, Address src);
1127 void mulsd(XMMRegister dst, XMMRegister src);
1128
1129 // Multiply Scalar Single-Precision Floating-Point Values
1130 void mulss(XMMRegister dst, Address src);
1131 void mulss(XMMRegister dst, XMMRegister src);
1132
1133 void negl(Register dst);
1134
1135 #ifdef _LP64
1136 void negq(Register dst);
1137 #endif
1138
1139 void nop(int i = 1);
1140
1141 void notl(Register dst);
1142
1143 #ifdef _LP64
1144 void notq(Register dst);
1145 #endif
1146
1147 void orl(Address dst, int32_t imm32);
1148 void orl(Register dst, int32_t imm32);
1149 void orl(Register dst, Address src);
1150 void orl(Register dst, Register src);
1151
1152 void orq(Address dst, int32_t imm32);
1153 void orq(Register dst, int32_t imm32);
1154 void orq(Register dst, Address src);
1155 void orq(Register dst, Register src);
1156
1157 void popl(Address dst);
1158
1159 #ifdef _LP64
1160 void popq(Address dst);
1161 #endif
1162
1163 // Prefetches (SSE, SSE2, 3DNOW only)
1164
1165 void prefetchnta(Address src);
1166 void prefetchr(Address src);
1167 void prefetcht0(Address src);
1168 void prefetcht1(Address src);
1169 void prefetcht2(Address src);
1170 void prefetchw(Address src);
1171
1172 // Shuffle Packed Doublewords
1173 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1174 void pshufd(XMMRegister dst, Address src, int mode);
1175
1176 // Shuffle Packed Low Words
1177 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1178 void pshuflw(XMMRegister dst, Address src, int mode);
1179
1180 // Shift Right Logical Quadword Immediate
1181 void psrlq(XMMRegister dst, int shift);
1182
1183 // Interleave Low Bytes
1184 void punpcklbw(XMMRegister dst, XMMRegister src);
1185
1186 void pushl(Address src);
1187
1188 void pushq(Address src);
1189
1190 // Xor Packed Byte Integer Values
1191 void pxor(XMMRegister dst, Address src);
1192 void pxor(XMMRegister dst, XMMRegister src);
1193
1194 void rcll(Register dst, int imm8);
1195
1196 void rclq(Register dst, int imm8);
1197
1198 void ret(int imm16);
1199
1200 void sahf();
1201
1202 void sarl(Register dst, int imm8);
1203 void sarl(Register dst);
1204
1205 void sarq(Register dst, int imm8);
1206 void sarq(Register dst);
1207
1208 void sbbl(Address dst, int32_t imm32);
1209 void sbbl(Register dst, int32_t imm32);
1210 void sbbl(Register dst, Address src);
1211 void sbbl(Register dst, Register src);
1212
1213 void sbbq(Address dst, int32_t imm32);
1214 void sbbq(Register dst, int32_t imm32);
1215 void sbbq(Register dst, Address src);
1216 void sbbq(Register dst, Register src);
1217
1218 void setb(Condition cc, Register dst);
1219
1220 void shldl(Register dst, Register src);
1221
1222 void shll(Register dst, int imm8);
1223 void shll(Register dst);
1224
1225 void shlq(Register dst, int imm8);
1226 void shlq(Register dst);
1227
1228 void shrdl(Register dst, Register src);
1229
1230 void shrl(Register dst, int imm8);
1231 void shrl(Register dst);
1232
1233 void shrq(Register dst, int imm8);
1234 void shrq(Register dst);
1235
1236 void smovl(); // QQQ generic?
1237
1238 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1239 void sqrtsd(XMMRegister dst, Address src);
1240 void sqrtsd(XMMRegister dst, XMMRegister src);
1241
1242 void std() { emit_byte(0xfd); }
1243
1244 void stmxcsr( Address dst );
1245
1246 void subl(Address dst, int32_t imm32);
1247 void subl(Address dst, Register src);
1248 void subl(Register dst, int32_t imm32);
1249 void subl(Register dst, Address src);
1250 void subl(Register dst, Register src);
1251
1252 void subq(Address dst, int32_t imm32);
1253 void subq(Address dst, Register src);
1254 void subq(Register dst, int32_t imm32);
1255 void subq(Register dst, Address src);
1256 void subq(Register dst, Register src);
1257
1258
1259 // Subtract Scalar Double-Precision Floating-Point Values
1260 void subsd(XMMRegister dst, Address src);
1261 void subsd(XMMRegister dst, XMMRegister src);
1262
1263 // Subtract Scalar Single-Precision Floating-Point Values
1264 void subss(XMMRegister dst, Address src);
1265 void subss(XMMRegister dst, XMMRegister src);
1266
1267 void testb(Register dst, int imm8);
1268
1269 void testl(Register dst, int32_t imm32);
1270 void testl(Register dst, Register src);
1271 void testl(Register dst, Address src);
1272
1273 void testq(Register dst, int32_t imm32);
1274 void testq(Register dst, Register src);
1275
1276
1277 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1278 void ucomisd(XMMRegister dst, Address src);
1279 void ucomisd(XMMRegister dst, XMMRegister src);
1280
1281 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1282 void ucomiss(XMMRegister dst, Address src);
1283 void ucomiss(XMMRegister dst, XMMRegister src);
1284
1285 void xaddl(Address dst, Register src);
1286
1287 void xaddq(Address dst, Register src);
1288
1289 void xchgl(Register reg, Address adr);
1290 void xchgl(Register dst, Register src);
1291
1292 void xchgq(Register reg, Address adr);
1293 void xchgq(Register dst, Register src);
1294
1295 void xorl(Register dst, int32_t imm32);
1296 void xorl(Register dst, Address src);
1297 void xorl(Register dst, Register src);
1298
1299 void xorq(Register dst, Address src);
1300 void xorq(Register dst, Register src);
1301
1302 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1303 void xorpd(XMMRegister dst, Address src);
1304 void xorpd(XMMRegister dst, XMMRegister src);
1305
1306 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1307 void xorps(XMMRegister dst, Address src);
1308 void xorps(XMMRegister dst, XMMRegister src);
1309
1310 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1311 };
1312
1313
1314 // MacroAssembler extends Assembler by frequently used macros.
1315 //
1316 // Instructions for which a 'better' code sequence exists depending
1317 // on arguments should also go in here.
1318
1319 class MacroAssembler: public Assembler {
1320 friend class LIR_Assembler;
1321 friend class Runtime1; // as_Address()
1322 protected:
1323
1324 Address as_Address(AddressLiteral adr);
1325 Address as_Address(ArrayAddress adr);
1326
1327 // Support for VM calls
1328 //
1329 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1330 // may customize this version by overriding it for its purposes (e.g., to save/restore
1331 // additional registers when doing a VM call).
1332 #ifdef CC_INTERP
1333 // c++ interpreter never wants to use interp_masm version of call_VM
1334 #define VIRTUAL
1335 #else
1336 #define VIRTUAL virtual
1337 #endif
1338
1339 VIRTUAL void call_VM_leaf_base(
1340 address entry_point, // the entry point
1341 int number_of_arguments // the number of arguments to pop after the call
1342 );
1343
1344 // This is the base routine called by the different versions of call_VM. The interpreter
1345 // may customize this version by overriding it for its purposes (e.g., to save/restore
1346 // additional registers when doing a VM call).
1347 //
1348 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1349 // returns the register which contains the thread upon return. If a thread register has been
1350 // specified, the return value will correspond to that register. If no last_java_sp is specified
1351 // (noreg) than rsp will be used instead.
1352 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1353 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1354 Register java_thread, // the thread if computed before ; use noreg otherwise
1355 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1356 address entry_point, // the entry point
1357 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1358 bool check_exceptions // whether to check for pending exceptions after return
1359 );
1360
1361 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1362 // The implementation is only non-empty for the InterpreterMacroAssembler,
1363 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1364 virtual void check_and_handle_popframe(Register java_thread);
1365 virtual void check_and_handle_earlyret(Register java_thread);
1366
1367 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1368
1369 // helpers for FPU flag access
1370 // tmp is a temporary register, if none is available use noreg
1371 void save_rax (Register tmp);
1372 void restore_rax(Register tmp);
1373
1374 public:
1375 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1376
1377 // Support for NULL-checks
1378 //
1379 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1380 // If the accessed location is M[reg + offset] and the offset is known, provide the
1381 // offset. No explicit code generation is needed if the offset is within a certain
1382 // range (0 <= offset <= page_size).
1383
1384 void null_check(Register reg, int offset = -1);
1385 static bool needs_explicit_null_check(intptr_t offset);
1386
1387 // Required platform-specific helpers for Label::patch_instructions.
1388 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1389 void pd_patch_instruction(address branch, address target);
1390 #ifndef PRODUCT
1391 static void pd_print_patched_instruction(address branch);
1392 #endif
1393
1394 // The following 4 methods return the offset of the appropriate move instruction
1395
1396 // Support for fast byte/word loading with zero extension (depending on particular CPU)
1397 int load_unsigned_byte(Register dst, Address src);
1398 int load_unsigned_word(Register dst, Address src);
1399
1400 // Support for fast byte/word loading with sign extension (depending on particular CPU)
1401 int load_signed_byte(Register dst, Address src);
1402 int load_signed_word(Register dst, Address src);
1403
1404 // Support for sign-extension (hi:lo = extend_sign(lo))
1405 void extend_sign(Register hi, Register lo);
1406
1407 // Support for inc/dec with optimal instruction selection depending on value
1408
1409 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1410 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1411
1412 void decrementl(Address dst, int value = 1);
1413 void decrementl(Register reg, int value = 1);
1414
1415 void decrementq(Register reg, int value = 1);
1416 void decrementq(Address dst, int value = 1);
1417
1418 void incrementl(Address dst, int value = 1);
1419 void incrementl(Register reg, int value = 1);
1420
1421 void incrementq(Register reg, int value = 1);
1422 void incrementq(Address dst, int value = 1);
1423
1424
1425 // Support optimal SSE move instructions.
1426 void movflt(XMMRegister dst, XMMRegister src) {
1427 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1428 else { movss (dst, src); return; }
1429 }
1430 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1431 void movflt(XMMRegister dst, AddressLiteral src);
1432 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1433
1434 void movdbl(XMMRegister dst, XMMRegister src) {
1435 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1436 else { movsd (dst, src); return; }
1437 }
1438
1439 void movdbl(XMMRegister dst, AddressLiteral src);
1440
1441 void movdbl(XMMRegister dst, Address src) {
1442 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1443 else { movlpd(dst, src); return; }
1444 }
1445 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1446
1447 void incrementl(AddressLiteral dst);
1448 void incrementl(ArrayAddress dst);
1449
1450 // Alignment
1451 void align(int modulus);
1452
1453 // Misc
1454 void fat_nop(); // 5 byte nop
1455
1456 // Stack frame creation/removal
1457 void enter();
1458 void leave();
1459
1460 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1461 // The pointer will be loaded into the thread register.
1462 void get_thread(Register thread);
1463
1464
1465 // Support for VM calls
1466 //
1467 // It is imperative that all calls into the VM are handled via the call_VM macros.
1468 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1469 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1470
1471
1472 void call_VM(Register oop_result,
1473 address entry_point,
1474 bool check_exceptions = true);
1475 void call_VM(Register oop_result,
1476 address entry_point,
1477 Register arg_1,
1478 bool check_exceptions = true);
1479 void call_VM(Register oop_result,
1480 address entry_point,
1481 Register arg_1, Register arg_2,
1482 bool check_exceptions = true);
1483 void call_VM(Register oop_result,
1484 address entry_point,
1485 Register arg_1, Register arg_2, Register arg_3,
1486 bool check_exceptions = true);
1487
1488 // Overloadings with last_Java_sp
1489 void call_VM(Register oop_result,
1490 Register last_java_sp,
1491 address entry_point,
1492 int number_of_arguments = 0,
1493 bool check_exceptions = true);
1494 void call_VM(Register oop_result,
1495 Register last_java_sp,
1496 address entry_point,
1497 Register arg_1, bool
1498 check_exceptions = true);
1499 void call_VM(Register oop_result,
1500 Register last_java_sp,
1501 address entry_point,
1502 Register arg_1, Register arg_2,
1503 bool check_exceptions = true);
1504 void call_VM(Register oop_result,
1505 Register last_java_sp,
1506 address entry_point,
1507 Register arg_1, Register arg_2, Register arg_3,
1508 bool check_exceptions = true);
1509
1510 void call_VM_leaf(address entry_point,
1511 int number_of_arguments = 0);
1512 void call_VM_leaf(address entry_point,
1513 Register arg_1);
1514 void call_VM_leaf(address entry_point,
1515 Register arg_1, Register arg_2);
1516 void call_VM_leaf(address entry_point,
1517 Register arg_1, Register arg_2, Register arg_3);
1518
1519 // last Java Frame (fills frame anchor)
1520 void set_last_Java_frame(Register thread,
1521 Register last_java_sp,
1522 Register last_java_fp,
1523 address last_java_pc);
1524
1525 // thread in the default location (r15_thread on 64bit)
1526 void set_last_Java_frame(Register last_java_sp,
1527 Register last_java_fp,
1528 address last_java_pc);
1529
1530 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1531
1532 // thread in the default location (r15_thread on 64bit)
1533 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1534
1535 // Stores
1536 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1537 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1538
1539 void g1_write_barrier_pre(Register obj,
1540 #ifndef _LP64
1541 Register thread,
1542 #endif
1543 Register tmp,
1544 Register tmp2,
1545 bool tosca_live);
1546 void g1_write_barrier_post(Register store_addr,
1547 Register new_val,
1548 #ifndef _LP64
1549 Register thread,
1550 #endif
1551 Register tmp,
1552 Register tmp2);
1553
1554
1555 // split store_check(Register obj) to enhance instruction interleaving
1556 void store_check_part_1(Register obj);
1557 void store_check_part_2(Register obj);
1558
1559 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1560 void c2bool(Register x);
1561
1562 // C++ bool manipulation
1563
1564 void movbool(Register dst, Address src);
1565 void movbool(Address dst, bool boolconst);
1566 void movbool(Address dst, Register src);
1567 void testbool(Register dst);
1568
1569 // oop manipulations
1570 void load_klass(Register dst, Register src);
1571 void store_klass(Register dst, Register src);
1572
1573 void load_prototype_header(Register dst, Register src);
1574
1575 #ifdef _LP64
1576 void store_klass_gap(Register dst, Register src);
1577
1578 void load_heap_oop(Register dst, Address src);
1579 void store_heap_oop(Address dst, Register src);
1580 void encode_heap_oop(Register r);
1581 void decode_heap_oop(Register r);
1582 void encode_heap_oop_not_null(Register r);
1583 void decode_heap_oop_not_null(Register r);
1584 void encode_heap_oop_not_null(Register dst, Register src);
1585 void decode_heap_oop_not_null(Register dst, Register src);
1586
1587 void set_narrow_oop(Register dst, jobject obj);
1588
1589 // if heap base register is used - reinit it with the correct value
1590 void reinit_heapbase();
1591 #endif // _LP64
1592
1593 // Int division/remainder for Java
1594 // (as idivl, but checks for special case as described in JVM spec.)
1595 // returns idivl instruction offset for implicit exception handling
1596 int corrected_idivl(Register reg);
1597
1598 // Long division/remainder for Java
1599 // (as idivq, but checks for special case as described in JVM spec.)
1600 // returns idivq instruction offset for implicit exception handling
1601 int corrected_idivq(Register reg);
1602
1603 void int3();
1604
1605 // Long operation macros for a 32bit cpu
1606 // Long negation for Java
1607 void lneg(Register hi, Register lo);
1608
1609 // Long multiplication for Java
1610 // (destroys contents of eax, ebx, ecx and edx)
1611 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1612
1613 // Long shifts for Java
1614 // (semantics as described in JVM spec.)
1615 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1616 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1617
1618 // Long compare for Java
1619 // (semantics as described in JVM spec.)
1620 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1621
1622
1623 // misc
1624
1625 // Sign extension
1626 void sign_extend_short(Register reg);
1627 void sign_extend_byte(Register reg);
1628
1629 // Division by power of 2, rounding towards 0
1630 void division_with_shift(Register reg, int shift_value);
1631
1632 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1633 //
1634 // CF (corresponds to C0) if x < y
1635 // PF (corresponds to C2) if unordered
1636 // ZF (corresponds to C3) if x = y
1637 //
1638 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1639 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1640 void fcmp(Register tmp);
1641 // Variant of the above which allows y to be further down the stack
1642 // and which only pops x and y if specified. If pop_right is
1643 // specified then pop_left must also be specified.
1644 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1645
1646 // Floating-point comparison for Java
1647 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1648 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1649 // (semantics as described in JVM spec.)
1650 void fcmp2int(Register dst, bool unordered_is_less);
1651 // Variant of the above which allows y to be further down the stack
1652 // and which only pops x and y if specified. If pop_right is
1653 // specified then pop_left must also be specified.
1654 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1655
1656 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1657 // tmp is a temporary register, if none is available use noreg
1658 void fremr(Register tmp);
1659
1660
1661 // same as fcmp2int, but using SSE2
1662 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1663 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1664
1665 // Inlined sin/cos generator for Java; must not use CPU instruction
1666 // directly on Intel as it does not have high enough precision
1667 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1668 // number of FPU stack slots in use; all but the topmost will
1669 // require saving if a slow case is necessary. Assumes argument is
1670 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1671 // this code.
1672 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1673
1674 // branch to L if FPU flag C2 is set/not set
1675 // tmp is a temporary register, if none is available use noreg
1676 void jC2 (Register tmp, Label& L);
1677 void jnC2(Register tmp, Label& L);
1678
1679 // Pop ST (ffree & fincstp combined)
1680 void fpop();
1681
1682 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1683 void push_fTOS();
1684
1685 // pops double TOS element from CPU stack and pushes on FPU stack
1686 void pop_fTOS();
1687
1688 void empty_FPU_stack();
1689
1690 void push_IU_state();
1691 void pop_IU_state();
1692
1693 void push_FPU_state();
1694 void pop_FPU_state();
1695
1696 void push_CPU_state();
1697 void pop_CPU_state();
1698
1699 // Round up to a power of two
1700 void round_to(Register reg, int modulus);
1701
1702 // Callee saved registers handling
1703 void push_callee_saved_registers();
1704 void pop_callee_saved_registers();
1705
1706 // allocation
1707 void eden_allocate(
1708 Register obj, // result: pointer to object after successful allocation
1709 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1710 int con_size_in_bytes, // object size in bytes if known at compile time
1711 Register t1, // temp register
1712 Label& slow_case // continuation point if fast allocation fails
1713 );
1714 void tlab_allocate(
1715 Register obj, // result: pointer to object after successful allocation
1716 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1717 int con_size_in_bytes, // object size in bytes if known at compile time
1718 Register t1, // temp register
1719 Register t2, // temp register
1720 Label& slow_case // continuation point if fast allocation fails
1721 );
1722 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1723
1724 //----
1725 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1726
1727 // Debugging
1728
1729 // only if +VerifyOops
1730 void verify_oop(Register reg, const char* s = "broken oop");
1731 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1732
1733 // only if +VerifyFPU
1734 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1735
1736 // prints msg, dumps registers and stops execution
1737 void stop(const char* msg);
1738
1739 // prints msg and continues
1740 void warn(const char* msg);
1741
1742 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1743 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1744
1745 void os_breakpoint();
1746
1747 void untested() { stop("untested"); }
1748
1749 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
1750
1751 void should_not_reach_here() { stop("should not reach here"); }
1752
1753 void print_CPU_state();
1754
1755 // Stack overflow checking
1756 void bang_stack_with_offset(int offset) {
1757 // stack grows down, caller passes positive offset
1758 assert(offset > 0, "must bang with negative offset");
1759 movl(Address(rsp, (-offset)), rax);
1760 }
1761
1762 // Writes to stack successive pages until offset reached to check for
1763 // stack overflow + shadow pages. Also, clobbers tmp
1764 void bang_stack_size(Register size, Register tmp);
1765
1766 // Support for serializing memory accesses between threads
1767 void serialize_memory(Register thread, Register tmp);
1768
1769 void verify_tlab();
1770
1771 // Biased locking support
1772 // lock_reg and obj_reg must be loaded up with the appropriate values.
1773 // swap_reg must be rax, and is killed.
1774 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1775 // be killed; if not supplied, push/pop will be used internally to
1776 // allocate a temporary (inefficient, avoid if possible).
1777 // Optional slow case is for implementations (interpreter and C1) which branch to
1778 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1779 // Returns offset of first potentially-faulting instruction for null
1780 // check info (currently consumed only by C1). If
1781 // swap_reg_contains_mark is true then returns -1 as it is assumed
1782 // the calling code has already passed any potential faults.
1783 int biased_locking_enter(Register lock_reg, Register obj_reg, Register swap_reg, Register tmp_reg,
1784 bool swap_reg_contains_mark,
1785 Label& done, Label* slow_case = NULL,
1786 BiasedLockingCounters* counters = NULL);
1787 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1788
1789
1790 Condition negate_condition(Condition cond);
1791
1792 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1793 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1794 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1795 // here in MacroAssembler. The major exception to this rule is call
1796
1797 // Arithmetics
1798
1799
1800 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1801 void addptr(Address dst, Register src);
1802
1803 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1804 void addptr(Register dst, int32_t src);
1805 void addptr(Register dst, Register src);
1806
1807 void andptr(Register dst, int32_t src);
1808 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1809
1810 void cmp8(AddressLiteral src1, int imm);
1811
1812 // renamed to drag out the casting of address to int32_t/intptr_t
1813 void cmp32(Register src1, int32_t imm);
1814
1815 void cmp32(AddressLiteral src1, int32_t imm);
1816 // compare reg - mem, or reg - &mem
1817 void cmp32(Register src1, AddressLiteral src2);
1818
1819 void cmp32(Register src1, Address src2);
1820
1821 #ifndef _LP64
1822 void cmpoop(Address dst, jobject obj);
1823 void cmpoop(Register dst, jobject obj);
1824 #endif // _LP64
1825
1826 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1827 void cmpptr(Address src1, AddressLiteral src2);
1828
1829 void cmpptr(Register src1, AddressLiteral src2);
1830
1831 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1832 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1833 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1834
1835 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1836 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1837
1838 // cmp64 to avoild hiding cmpq
1839 void cmp64(Register src1, AddressLiteral src);
1840
1841 void cmpxchgptr(Register reg, Address adr);
1842
1843 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
1844
1845
1846 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
1847
1848
1849 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
1850
1851 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
1852
1853 void shlptr(Register dst, int32_t shift);
1854 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
1855
1856 void shrptr(Register dst, int32_t shift);
1857 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
1858
1859 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
1860 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
1861
1862 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
1863
1864 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
1865 void subptr(Register dst, int32_t src);
1866 void subptr(Register dst, Register src);
1867
1868
1869 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
1870 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
1871
1872 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
1873 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
1874
1875 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
1876
1877
1878
1879 // Helper functions for statistics gathering.
1880 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1881 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1882 // Unconditional atomic increment.
1883 void atomic_incl(AddressLiteral counter_addr);
1884
1885 void lea(Register dst, AddressLiteral adr);
1886 void lea(Address dst, AddressLiteral adr);
1887 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
1888
1889 void leal32(Register dst, Address src) { leal(dst, src); }
1890
1891 void test32(Register src1, AddressLiteral src2);
1892
1893 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1894 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1895 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1896
1897 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
1898 void testptr(Register src1, Register src2);
1899
1900 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
1901 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
1902
1903 // Calls
1904
1905 void call(Label& L, relocInfo::relocType rtype);
1906 void call(Register entry);
1907
1908 // NOTE: this call tranfers to the effective address of entry NOT
1909 // the address contained by entry. This is because this is more natural
1910 // for jumps/calls.
1911 void call(AddressLiteral entry);
1912
1913 // Jumps
1914
1915 // NOTE: these jumps tranfer to the effective address of dst NOT
1916 // the address contained by dst. This is because this is more natural
1917 // for jumps/calls.
1918 void jump(AddressLiteral dst);
1919 void jump_cc(Condition cc, AddressLiteral dst);
1920
1921 // 32bit can do a case table jump in one instruction but we no longer allow the base
1922 // to be installed in the Address class. This jump will tranfers to the address
1923 // contained in the location described by entry (not the address of entry)
1924 void jump(ArrayAddress entry);
1925
1926 // Floating
1927
1928 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1929 void andpd(XMMRegister dst, AddressLiteral src);
1930
1931 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1932 void comiss(XMMRegister dst, AddressLiteral src);
1933
1934 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1935 void comisd(XMMRegister dst, AddressLiteral src);
1936
1937 void fldcw(Address src) { Assembler::fldcw(src); }
1938 void fldcw(AddressLiteral src);
1939
1940 void fld_s(int index) { Assembler::fld_s(index); }
1941 void fld_s(Address src) { Assembler::fld_s(src); }
1942 void fld_s(AddressLiteral src);
1943
1944 void fld_d(Address src) { Assembler::fld_d(src); }
1945 void fld_d(AddressLiteral src);
1946
1947 void fld_x(Address src) { Assembler::fld_x(src); }
1948 void fld_x(AddressLiteral src);
1949
1950 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1951 void ldmxcsr(AddressLiteral src);
1952
1953 private:
1954 // these are private because users should be doing movflt/movdbl
1955
1956 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1957 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1958 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1959 void movss(XMMRegister dst, AddressLiteral src);
1960
1961 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1962 void movlpd(XMMRegister dst, AddressLiteral src);
1963
1964 public:
1965
1966 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1967 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1968 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1969 void movsd(XMMRegister dst, AddressLiteral src);
1970
1971 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1972 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1973 void ucomiss(XMMRegister dst, AddressLiteral src);
1974
1975 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1976 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1977 void ucomisd(XMMRegister dst, AddressLiteral src);
1978
1979 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1980 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1981 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1982 void xorpd(XMMRegister dst, AddressLiteral src);
1983
1984 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1985 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1986 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1987 void xorps(XMMRegister dst, AddressLiteral src);
1988
1989 // Data
1990
1991 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
1992
1993 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
1994 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
1995
1996 void movoop(Register dst, jobject obj);
1997 void movoop(Address dst, jobject obj);
1998
1999 void movptr(ArrayAddress dst, Register src);
2000 // can this do an lea?
2001 void movptr(Register dst, ArrayAddress src);
2002
2003 void movptr(Register dst, Address src);
2004
2005 void movptr(Register dst, AddressLiteral src);
2006
2007 void movptr(Register dst, intptr_t src);
2008 void movptr(Register dst, Register src);
2009 void movptr(Address dst, intptr_t src);
2010
2011 void movptr(Address dst, Register src);
2012
2013 #ifdef _LP64
2014 // Generally the next two are only used for moving NULL
2015 // Although there are situations in initializing the mark word where
2016 // they could be used. They are dangerous.
2017
2018 // They only exist on LP64 so that int32_t and intptr_t are not the same
2019 // and we have ambiguous declarations.
2020
2021 void movptr(Address dst, int32_t imm32);
2022 void movptr(Register dst, int32_t imm32);
2023 #endif // _LP64
2024
2025 // to avoid hiding movl
2026 void mov32(AddressLiteral dst, Register src);
2027 void mov32(Register dst, AddressLiteral src);
2028
2029 // to avoid hiding movb
2030 void movbyte(ArrayAddress dst, int src);
2031
2032 // Can push value or effective address
2033 void pushptr(AddressLiteral src);
2034
2035 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2036 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2037
2038 void pushoop(jobject obj);
2039
2040 // sign extend as need a l to ptr sized element
2041 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2042 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2043
2044
2045 #undef VIRTUAL
2046
2047 };
2048
2049 /**
2050 * class SkipIfEqual:
2051 *
2052 * Instantiating this class will result in assembly code being output that will
2053 * jump around any code emitted between the creation of the instance and it's
2054 * automatic destruction at the end of a scope block, depending on the value of
2055 * the flag passed to the constructor, which will be checked at run-time.
2056 */
2057 class SkipIfEqual {
2058 private:
2059 MacroAssembler* _masm;
2060 Label _label;
2061
2062 public:
2063 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2064 ~SkipIfEqual();
2065 };
2066
2067 #ifdef ASSERT
2068 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2069 #endif