rev 522 : [mq]: meth.patch
1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // Contains all the definitions needed for x86 assembly code generation.
28
29 // Calling convention
30 class Argument VALUE_OBJ_CLASS_SPEC {
31 public:
32 enum {
33 #ifdef _LP64
34 #ifdef _WIN64
35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
37 #else
38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
40 #endif // _WIN64
41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
43 #else
44 n_register_parameters = 0 // 0 registers used to pass arguments
45 #endif // _LP64
46 };
47 };
48
49
50 #ifdef _LP64
51 // Symbolically name the register arguments used by the c calling convention.
52 // Windows is different from linux/solaris. So much for standards...
53
54 #ifdef _WIN64
55
56 REGISTER_DECLARATION(Register, c_rarg0, rcx);
57 REGISTER_DECLARATION(Register, c_rarg1, rdx);
58 REGISTER_DECLARATION(Register, c_rarg2, r8);
59 REGISTER_DECLARATION(Register, c_rarg3, r9);
60
61 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
62 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
63 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
64 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
65
66 #else
67
68 REGISTER_DECLARATION(Register, c_rarg0, rdi);
69 REGISTER_DECLARATION(Register, c_rarg1, rsi);
70 REGISTER_DECLARATION(Register, c_rarg2, rdx);
71 REGISTER_DECLARATION(Register, c_rarg3, rcx);
72 REGISTER_DECLARATION(Register, c_rarg4, r8);
73 REGISTER_DECLARATION(Register, c_rarg5, r9);
74
75 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
76 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
77 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
78 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
79 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
80 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
81 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
82 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
83
84 #endif // _WIN64
85
86 // Symbolically name the register arguments used by the Java calling convention.
87 // We have control over the convention for java so we can do what we please.
88 // What pleases us is to offset the java calling convention so that when
89 // we call a suitable jni method the arguments are lined up and we don't
90 // have to do little shuffling. A suitable jni method is non-static and a
91 // small number of arguments (two fewer args on windows)
92 //
93 // |-------------------------------------------------------|
94 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
95 // |-------------------------------------------------------|
96 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
97 // | rdi rsi rdx rcx r8 r9 | solaris/linux
98 // |-------------------------------------------------------|
99 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
100 // |-------------------------------------------------------|
101
102 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
103 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
104 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
105 // Windows runs out of register args here
106 #ifdef _WIN64
107 REGISTER_DECLARATION(Register, j_rarg3, rdi);
108 REGISTER_DECLARATION(Register, j_rarg4, rsi);
109 #else
110 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
111 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
112 #endif /* _WIN64 */
113 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
114
115 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
116 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
117 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
118 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
119 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
120 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
121 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
122 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
123
124 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
125 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
126
127 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
128 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
129
130 #else
131 // rscratch1 will apear in 32bit code that is dead but of course must compile
132 // Using noreg ensures if the dead code is incorrectly live and executed it
133 // will cause an assertion failure
134 #define rscratch1 noreg
135
136 #endif // _LP64
137
138 // A union type for code which has to assemble both constant and non-constant operands.
139 class RegisterConstant VALUE_OBJ_CLASS_SPEC {
140 private:
141 Register _r;
142 intptr_t _c;
143
144 public:
145 RegisterConstant(): _r(noreg), _c(0) {}
146 RegisterConstant(Register r): _r(r), _c(0) {}
147 RegisterConstant(intptr_t c): _r(noreg), _c(c) {}
148
149 Register as_register() const { assert(is_register(),""); return _r; }
150 intptr_t as_constant() const { assert(is_constant(),""); return _c; }
151
152 Register register_or_noreg() const { return _r; }
153 intptr_t constant_or_zero() const { return _c; }
154
155 bool is_register() const { return _r != noreg; }
156 bool is_constant() const { return _r == noreg; }
157 };
158
159 // Address is an abstraction used to represent a memory location
160 // using any of the amd64 addressing modes with one object.
161 //
162 // Note: A register location is represented via a Register, not
163 // via an address for efficiency & simplicity reasons.
164
165 class ArrayAddress;
166
167 class Address VALUE_OBJ_CLASS_SPEC {
168 public:
169 enum ScaleFactor {
170 no_scale = -1,
171 times_1 = 0,
172 times_2 = 1,
173 times_4 = 2,
174 times_8 = 3,
175 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
176 };
177
178 static ScaleFactor times(int size) {
179 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
180 if (size == 8) return times_8;
181 if (size == 4) return times_4;
182 if (size == 2) return times_2;
183 return times_1;
184 }
185
186 private:
187 Register _base;
188 Register _index;
189 ScaleFactor _scale;
190 int _disp;
191 RelocationHolder _rspec;
192
193 // Easily misused constructors make them private
194 // %%% can we make these go away?
195 NOT_LP64(Address(address loc, RelocationHolder spec);)
196 Address(int disp, address loc, relocInfo::relocType rtype);
197 Address(int disp, address loc, RelocationHolder spec);
198
199 public:
200
201 int disp() { return _disp; }
202 // creation
203 Address()
204 : _base(noreg),
205 _index(noreg),
206 _scale(no_scale),
207 _disp(0) {
208 }
209
210 // No default displacement otherwise Register can be implicitly
211 // converted to 0(Register) which is quite a different animal.
212
213 Address(Register base, int disp)
214 : _base(base),
215 _index(noreg),
216 _scale(no_scale),
217 _disp(disp) {
218 }
219
220 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
221 : _base (base),
222 _index(index),
223 _scale(scale),
224 _disp (disp) {
225 assert(!index->is_valid() == (scale == Address::no_scale),
226 "inconsistent address");
227 }
228
229 Address(Register base, RegisterConstant index, ScaleFactor scale = times_1, int disp = 0)
230 : _base (base),
231 _index(index.register_or_noreg()),
232 _scale(scale),
233 _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
234 if (!index.is_register()) scale = Address::no_scale;
235 assert(!_index->is_valid() == (scale == Address::no_scale),
236 "inconsistent address");
237 }
238
239 Address plus_disp(int disp) {
240 Address result = (*this);
241 result._disp += disp;
242 return result;
243 }
244
245 // The following two overloads are used in connection with the
246 // ByteSize type (see sizes.hpp). They simplify the use of
247 // ByteSize'd arguments in assembly code. Note that their equivalent
248 // for the optimized build are the member functions with int disp
249 // argument since ByteSize is mapped to an int type in that case.
250 //
251 // Note: DO NOT introduce similar overloaded functions for WordSize
252 // arguments as in the optimized mode, both ByteSize and WordSize
253 // are mapped to the same type and thus the compiler cannot make a
254 // distinction anymore (=> compiler errors).
255
256 #ifdef ASSERT
257 Address(Register base, ByteSize disp)
258 : _base(base),
259 _index(noreg),
260 _scale(no_scale),
261 _disp(in_bytes(disp)) {
262 }
263
264 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
265 : _base(base),
266 _index(index),
267 _scale(scale),
268 _disp(in_bytes(disp)) {
269 assert(!index->is_valid() == (scale == Address::no_scale),
270 "inconsistent address");
271 }
272
273 Address(Register base, RegisterConstant index, ScaleFactor scale, ByteSize disp)
274 : _base (base),
275 _index(index.register_or_noreg()),
276 _scale(scale),
277 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
278 if (!index.is_register()) scale = Address::no_scale;
279 assert(!_index->is_valid() == (scale == Address::no_scale),
280 "inconsistent address");
281 }
282
283 #endif // ASSERT
284
285 // accessors
286 bool uses(Register reg) const { return _base == reg || _index == reg; }
287 Register base() const { return _base; }
288 Register index() const { return _index; }
289 ScaleFactor scale() const { return _scale; }
290 int disp() const { return _disp; }
291
292 // Convert the raw encoding form into the form expected by the constructor for
293 // Address. An index of 4 (rsp) corresponds to having no index, so convert
294 // that to noreg for the Address constructor.
295 static Address make_raw(int base, int index, int scale, int disp);
296
297 static Address make_array(ArrayAddress);
298
299 static int scale_size(ScaleFactor scale) {
300 assert(scale != no_scale, "");
301 assert(((1 << (int)times_1) == 1 &&
302 (1 << (int)times_2) == 2 &&
303 (1 << (int)times_4) == 4 &&
304 (1 << (int)times_8) == 8), "");
305 return (1 << (int)scale);
306 }
307
308 private:
309 bool base_needs_rex() const {
310 return _base != noreg && _base->encoding() >= 8;
311 }
312
313 bool index_needs_rex() const {
314 return _index != noreg &&_index->encoding() >= 8;
315 }
316
317 relocInfo::relocType reloc() const { return _rspec.type(); }
318
319 friend class Assembler;
320 friend class MacroAssembler;
321 friend class LIR_Assembler; // base/index/scale/disp
322 };
323
324 //
325 // AddressLiteral has been split out from Address because operands of this type
326 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
327 // the few instructions that need to deal with address literals are unique and the
328 // MacroAssembler does not have to implement every instruction in the Assembler
329 // in order to search for address literals that may need special handling depending
330 // on the instruction and the platform. As small step on the way to merging i486/amd64
331 // directories.
332 //
333 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
334 friend class ArrayAddress;
335 RelocationHolder _rspec;
336 // Typically we use AddressLiterals we want to use their rval
337 // However in some situations we want the lval (effect address) of the item.
338 // We provide a special factory for making those lvals.
339 bool _is_lval;
340
341 // If the target is far we'll need to load the ea of this to
342 // a register to reach it. Otherwise if near we can do rip
343 // relative addressing.
344
345 address _target;
346
347 protected:
348 // creation
349 AddressLiteral()
350 : _is_lval(false),
351 _target(NULL)
352 {}
353
354 public:
355
356
357 AddressLiteral(address target, relocInfo::relocType rtype);
358
359 AddressLiteral(address target, RelocationHolder const& rspec)
360 : _rspec(rspec),
361 _is_lval(false),
362 _target(target)
363 {}
364
365 AddressLiteral addr() {
366 AddressLiteral ret = *this;
367 ret._is_lval = true;
368 return ret;
369 }
370
371
372 private:
373
374 address target() { return _target; }
375 bool is_lval() { return _is_lval; }
376
377 relocInfo::relocType reloc() const { return _rspec.type(); }
378 const RelocationHolder& rspec() const { return _rspec; }
379
380 friend class Assembler;
381 friend class MacroAssembler;
382 friend class Address;
383 friend class LIR_Assembler;
384 };
385
386 // Convience classes
387 class RuntimeAddress: public AddressLiteral {
388
389 public:
390
391 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
392
393 };
394
395 class OopAddress: public AddressLiteral {
396
397 public:
398
399 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){}
400
401 };
402
403 class ExternalAddress: public AddressLiteral {
404
405 public:
406
407 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){}
408
409 };
410
411 class InternalAddress: public AddressLiteral {
412
413 public:
414
415 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
416
417 };
418
419 // x86 can do array addressing as a single operation since disp can be an absolute
420 // address amd64 can't. We create a class that expresses the concept but does extra
421 // magic on amd64 to get the final result
422
423 class ArrayAddress VALUE_OBJ_CLASS_SPEC {
424 private:
425
426 AddressLiteral _base;
427 Address _index;
428
429 public:
430
431 ArrayAddress() {};
432 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
433 AddressLiteral base() { return _base; }
434 Address index() { return _index; }
435
436 };
437
438 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize);
439
440 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
441 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
442 // is what you get. The Assembler is generating code into a CodeBuffer.
443
444 class Assembler : public AbstractAssembler {
445 friend class AbstractAssembler; // for the non-virtual hack
446 friend class LIR_Assembler; // as_Address()
447 friend class StubGenerator;
448
449 public:
450 enum Condition { // The x86 condition codes used for conditional jumps/moves.
451 zero = 0x4,
452 notZero = 0x5,
453 equal = 0x4,
454 notEqual = 0x5,
455 less = 0xc,
456 lessEqual = 0xe,
457 greater = 0xf,
458 greaterEqual = 0xd,
459 below = 0x2,
460 belowEqual = 0x6,
461 above = 0x7,
462 aboveEqual = 0x3,
463 overflow = 0x0,
464 noOverflow = 0x1,
465 carrySet = 0x2,
466 carryClear = 0x3,
467 negative = 0x8,
468 positive = 0x9,
469 parity = 0xa,
470 noParity = 0xb
471 };
472
473 enum Prefix {
474 // segment overrides
475 CS_segment = 0x2e,
476 SS_segment = 0x36,
477 DS_segment = 0x3e,
478 ES_segment = 0x26,
479 FS_segment = 0x64,
480 GS_segment = 0x65,
481
482 REX = 0x40,
483
484 REX_B = 0x41,
485 REX_X = 0x42,
486 REX_XB = 0x43,
487 REX_R = 0x44,
488 REX_RB = 0x45,
489 REX_RX = 0x46,
490 REX_RXB = 0x47,
491
492 REX_W = 0x48,
493
494 REX_WB = 0x49,
495 REX_WX = 0x4A,
496 REX_WXB = 0x4B,
497 REX_WR = 0x4C,
498 REX_WRB = 0x4D,
499 REX_WRX = 0x4E,
500 REX_WRXB = 0x4F
501 };
502
503 enum WhichOperand {
504 // input to locate_operand, and format code for relocations
505 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
506 disp32_operand = 1, // embedded 32-bit displacement or address
507 call32_operand = 2, // embedded 32-bit self-relative displacement
508 #ifndef _LP64
509 _WhichOperand_limit = 3
510 #else
511 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
512 _WhichOperand_limit = 4
513 #endif
514 };
515
516
517
518 // NOTE: The general philopsophy of the declarations here is that 64bit versions
519 // of instructions are freely declared without the need for wrapping them an ifdef.
520 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
521 // In the .cpp file the implementations are wrapped so that they are dropped out
522 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL
523 // to the size it was prior to merging up the 32bit and 64bit assemblers.
524 //
525 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
526 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
527
528 private:
529
530
531 // 64bit prefixes
532 int prefix_and_encode(int reg_enc, bool byteinst = false);
533 int prefixq_and_encode(int reg_enc);
534
535 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false);
536 int prefixq_and_encode(int dst_enc, int src_enc);
537
538 void prefix(Register reg);
539 void prefix(Address adr);
540 void prefixq(Address adr);
541
542 void prefix(Address adr, Register reg, bool byteinst = false);
543 void prefixq(Address adr, Register reg);
544
545 void prefix(Address adr, XMMRegister reg);
546
547 void prefetch_prefix(Address src);
548
549 // Helper functions for groups of instructions
550 void emit_arith_b(int op1, int op2, Register dst, int imm8);
551
552 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
553 // only 32bit??
554 void emit_arith(int op1, int op2, Register dst, jobject obj);
555 void emit_arith(int op1, int op2, Register dst, Register src);
556
557 void emit_operand(Register reg,
558 Register base, Register index, Address::ScaleFactor scale,
559 int disp,
560 RelocationHolder const& rspec,
561 int rip_relative_correction = 0);
562
563 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
564
565 // operands that only take the original 32bit registers
566 void emit_operand32(Register reg, Address adr);
567
568 void emit_operand(XMMRegister reg,
569 Register base, Register index, Address::ScaleFactor scale,
570 int disp,
571 RelocationHolder const& rspec);
572
573 void emit_operand(XMMRegister reg, Address adr);
574
575 void emit_operand(MMXRegister reg, Address adr);
576
577 // workaround gcc (3.2.1-7) bug
578 void emit_operand(Address adr, MMXRegister reg);
579
580
581 // Immediate-to-memory forms
582 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
583
584 void emit_farith(int b1, int b2, int i);
585
586
587 protected:
588 #ifdef ASSERT
589 void check_relocation(RelocationHolder const& rspec, int format);
590 #endif
591
592 inline void emit_long64(jlong x);
593
594 void emit_data(jint data, relocInfo::relocType rtype, int format);
595 void emit_data(jint data, RelocationHolder const& rspec, int format);
596 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
597 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
598
599
600 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
601
602 // These are all easily abused and hence protected
603
604 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0);
605
606 // 32BIT ONLY SECTION
607 #ifndef _LP64
608 // Make these disappear in 64bit mode since they would never be correct
609 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
610 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
611
612 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
613
614 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
615 #else
616 // 64BIT ONLY SECTION
617 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
618 #endif // _LP64
619
620 // These are unique in that we are ensured by the caller that the 32bit
621 // relative in these instructions will always be able to reach the potentially
622 // 64bit address described by entry. Since they can take a 64bit address they
623 // don't have the 32 suffix like the other instructions in this class.
624
625 void call_literal(address entry, RelocationHolder const& rspec);
626 void jmp_literal(address entry, RelocationHolder const& rspec);
627
628 // Avoid using directly section
629 // Instructions in this section are actually usable by anyone without danger
630 // of failure but have performance issues that are addressed my enhanced
631 // instructions which will do the proper thing base on the particular cpu.
632 // We protect them because we don't trust you...
633
634 // Don't use next inc() and dec() methods directly. INC & DEC instructions
635 // could cause a partial flag stall since they don't set CF flag.
636 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
637 // which call inc() & dec() or add() & sub() in accordance with
638 // the product flag UseIncDec value.
639
640 void decl(Register dst);
641 void decl(Address dst);
642 void decq(Register dst);
643 void decq(Address dst);
644
645 void incl(Register dst);
646 void incl(Address dst);
647 void incq(Register dst);
648 void incq(Address dst);
649
650 // New cpus require use of movsd and movss to avoid partial register stall
651 // when loading from memory. But for old Opteron use movlpd instead of movsd.
652 // The selection is done in MacroAssembler::movdbl() and movflt().
653
654 // Move Scalar Single-Precision Floating-Point Values
655 void movss(XMMRegister dst, Address src);
656 void movss(XMMRegister dst, XMMRegister src);
657 void movss(Address dst, XMMRegister src);
658
659 // Move Scalar Double-Precision Floating-Point Values
660 void movsd(XMMRegister dst, Address src);
661 void movsd(XMMRegister dst, XMMRegister src);
662 void movsd(Address dst, XMMRegister src);
663 void movlpd(XMMRegister dst, Address src);
664
665 // New cpus require use of movaps and movapd to avoid partial register stall
666 // when moving between registers.
667 void movaps(XMMRegister dst, XMMRegister src);
668 void movapd(XMMRegister dst, XMMRegister src);
669
670 // End avoid using directly
671
672
673 // Instruction prefixes
674 void prefix(Prefix p);
675
676 public:
677
678 // Creation
679 Assembler(CodeBuffer* code) : AbstractAssembler(code) {}
680
681 // Decoding
682 static address locate_operand(address inst, WhichOperand which);
683 static address locate_next_instruction(address inst);
684
685 // Utilities
686
687 #ifdef _LP64
688 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); }
689 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; }
690 #else
691 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); }
692 static bool is_simm32(int32_t x) { return true; }
693 #endif // LP64
694
695 // Generic instructions
696 // Does 32bit or 64bit as needed for the platform. In some sense these
697 // belong in macro assembler but there is no need for both varieties to exist
698
699 void lea(Register dst, Address src);
700
701 void mov(Register dst, Register src);
702
703 void pusha();
704 void popa();
705
706 void pushf();
707 void popf();
708
709 void push(int32_t imm32);
710
711 void push(Register src);
712
713 void pop(Register dst);
714
715 // These are dummies to prevent surprise implicit conversions to Register
716 void push(void* v);
717 void pop(void* v);
718
719
720 // These do register sized moves/scans
721 void rep_mov();
722 void rep_set();
723 void repne_scan();
724 #ifdef _LP64
725 void repne_scanl();
726 #endif
727
728 // Vanilla instructions in lexical order
729
730 void adcl(Register dst, int32_t imm32);
731 void adcl(Register dst, Address src);
732 void adcl(Register dst, Register src);
733
734 void adcq(Register dst, int32_t imm32);
735 void adcq(Register dst, Address src);
736 void adcq(Register dst, Register src);
737
738
739 void addl(Address dst, int32_t imm32);
740 void addl(Address dst, Register src);
741 void addl(Register dst, int32_t imm32);
742 void addl(Register dst, Address src);
743 void addl(Register dst, Register src);
744
745 void addq(Address dst, int32_t imm32);
746 void addq(Address dst, Register src);
747 void addq(Register dst, int32_t imm32);
748 void addq(Register dst, Address src);
749 void addq(Register dst, Register src);
750
751
752 void addr_nop_4();
753 void addr_nop_5();
754 void addr_nop_7();
755 void addr_nop_8();
756
757 // Add Scalar Double-Precision Floating-Point Values
758 void addsd(XMMRegister dst, Address src);
759 void addsd(XMMRegister dst, XMMRegister src);
760
761 // Add Scalar Single-Precision Floating-Point Values
762 void addss(XMMRegister dst, Address src);
763 void addss(XMMRegister dst, XMMRegister src);
764
765 void andl(Register dst, int32_t imm32);
766 void andl(Register dst, Address src);
767 void andl(Register dst, Register src);
768
769 void andq(Register dst, int32_t imm32);
770 void andq(Register dst, Address src);
771 void andq(Register dst, Register src);
772
773
774 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
775 void andpd(XMMRegister dst, Address src);
776 void andpd(XMMRegister dst, XMMRegister src);
777
778 void bswapl(Register reg);
779
780 void bswapq(Register reg);
781
782 void call(Label& L, relocInfo::relocType rtype);
783 void call(Register reg); // push pc; pc <- reg
784 void call(Address adr); // push pc; pc <- adr
785
786 void cdql();
787
788 void cdqq();
789
790 void cld() { emit_byte(0xfc); }
791
792 void clflush(Address adr);
793
794 void cmovl(Condition cc, Register dst, Register src);
795 void cmovl(Condition cc, Register dst, Address src);
796
797 void cmovq(Condition cc, Register dst, Register src);
798 void cmovq(Condition cc, Register dst, Address src);
799
800
801 void cmpb(Address dst, int imm8);
802
803 void cmpl(Address dst, int32_t imm32);
804
805 void cmpl(Register dst, int32_t imm32);
806 void cmpl(Register dst, Register src);
807 void cmpl(Register dst, Address src);
808
809 void cmpq(Address dst, int32_t imm32);
810 void cmpq(Address dst, Register src);
811
812 void cmpq(Register dst, int32_t imm32);
813 void cmpq(Register dst, Register src);
814 void cmpq(Register dst, Address src);
815
816 // these are dummies used to catch attempting to convert NULL to Register
817 void cmpl(Register dst, void* junk); // dummy
818 void cmpq(Register dst, void* junk); // dummy
819
820 void cmpw(Address dst, int imm16);
821
822 void cmpxchg8 (Address adr);
823
824 void cmpxchgl(Register reg, Address adr);
825
826 void cmpxchgq(Register reg, Address adr);
827
828 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
829 void comisd(XMMRegister dst, Address src);
830
831 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
832 void comiss(XMMRegister dst, Address src);
833
834 // Identify processor type and features
835 void cpuid() {
836 emit_byte(0x0F);
837 emit_byte(0xA2);
838 }
839
840 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
841 void cvtsd2ss(XMMRegister dst, XMMRegister src);
842
843 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
844 void cvtsi2sdl(XMMRegister dst, Register src);
845 void cvtsi2sdq(XMMRegister dst, Register src);
846
847 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
848 void cvtsi2ssl(XMMRegister dst, Register src);
849 void cvtsi2ssq(XMMRegister dst, Register src);
850
851 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
852 void cvtdq2pd(XMMRegister dst, XMMRegister src);
853
854 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
855 void cvtdq2ps(XMMRegister dst, XMMRegister src);
856
857 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
858 void cvtss2sd(XMMRegister dst, XMMRegister src);
859
860 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
861 void cvttsd2sil(Register dst, Address src);
862 void cvttsd2sil(Register dst, XMMRegister src);
863 void cvttsd2siq(Register dst, XMMRegister src);
864
865 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
866 void cvttss2sil(Register dst, XMMRegister src);
867 void cvttss2siq(Register dst, XMMRegister src);
868
869 // Divide Scalar Double-Precision Floating-Point Values
870 void divsd(XMMRegister dst, Address src);
871 void divsd(XMMRegister dst, XMMRegister src);
872
873 // Divide Scalar Single-Precision Floating-Point Values
874 void divss(XMMRegister dst, Address src);
875 void divss(XMMRegister dst, XMMRegister src);
876
877 void emms();
878
879 void fabs();
880
881 void fadd(int i);
882
883 void fadd_d(Address src);
884 void fadd_s(Address src);
885
886 // "Alternate" versions of x87 instructions place result down in FPU
887 // stack instead of on TOS
888
889 void fadda(int i); // "alternate" fadd
890 void faddp(int i = 1);
891
892 void fchs();
893
894 void fcom(int i);
895
896 void fcomp(int i = 1);
897 void fcomp_d(Address src);
898 void fcomp_s(Address src);
899
900 void fcompp();
901
902 void fcos();
903
904 void fdecstp();
905
906 void fdiv(int i);
907 void fdiv_d(Address src);
908 void fdivr_s(Address src);
909 void fdiva(int i); // "alternate" fdiv
910 void fdivp(int i = 1);
911
912 void fdivr(int i);
913 void fdivr_d(Address src);
914 void fdiv_s(Address src);
915
916 void fdivra(int i); // "alternate" reversed fdiv
917
918 void fdivrp(int i = 1);
919
920 void ffree(int i = 0);
921
922 void fild_d(Address adr);
923 void fild_s(Address adr);
924
925 void fincstp();
926
927 void finit();
928
929 void fist_s (Address adr);
930 void fistp_d(Address adr);
931 void fistp_s(Address adr);
932
933 void fld1();
934
935 void fld_d(Address adr);
936 void fld_s(Address adr);
937 void fld_s(int index);
938 void fld_x(Address adr); // extended-precision (80-bit) format
939
940 void fldcw(Address src);
941
942 void fldenv(Address src);
943
944 void fldlg2();
945
946 void fldln2();
947
948 void fldz();
949
950 void flog();
951 void flog10();
952
953 void fmul(int i);
954
955 void fmul_d(Address src);
956 void fmul_s(Address src);
957
958 void fmula(int i); // "alternate" fmul
959
960 void fmulp(int i = 1);
961
962 void fnsave(Address dst);
963
964 void fnstcw(Address src);
965
966 void fnstsw_ax();
967
968 void fprem();
969 void fprem1();
970
971 void frstor(Address src);
972
973 void fsin();
974
975 void fsqrt();
976
977 void fst_d(Address adr);
978 void fst_s(Address adr);
979
980 void fstp_d(Address adr);
981 void fstp_d(int index);
982 void fstp_s(Address adr);
983 void fstp_x(Address adr); // extended-precision (80-bit) format
984
985 void fsub(int i);
986 void fsub_d(Address src);
987 void fsub_s(Address src);
988
989 void fsuba(int i); // "alternate" fsub
990
991 void fsubp(int i = 1);
992
993 void fsubr(int i);
994 void fsubr_d(Address src);
995 void fsubr_s(Address src);
996
997 void fsubra(int i); // "alternate" reversed fsub
998
999 void fsubrp(int i = 1);
1000
1001 void ftan();
1002
1003 void ftst();
1004
1005 void fucomi(int i = 1);
1006 void fucomip(int i = 1);
1007
1008 void fwait();
1009
1010 void fxch(int i = 1);
1011
1012 void fxrstor(Address src);
1013
1014 void fxsave(Address dst);
1015
1016 void fyl2x();
1017
1018 void hlt();
1019
1020 void idivl(Register src);
1021
1022 void idivq(Register src);
1023
1024 void imull(Register dst, Register src);
1025 void imull(Register dst, Register src, int value);
1026
1027 void imulq(Register dst, Register src);
1028 void imulq(Register dst, Register src, int value);
1029
1030
1031 // jcc is the generic conditional branch generator to run-
1032 // time routines, jcc is used for branches to labels. jcc
1033 // takes a branch opcode (cc) and a label (L) and generates
1034 // either a backward branch or a forward branch and links it
1035 // to the label fixup chain. Usage:
1036 //
1037 // Label L; // unbound label
1038 // jcc(cc, L); // forward branch to unbound label
1039 // bind(L); // bind label to the current pc
1040 // jcc(cc, L); // backward branch to bound label
1041 // bind(L); // illegal: a label may be bound only once
1042 //
1043 // Note: The same Label can be used for forward and backward branches
1044 // but it may be bound only once.
1045
1046 void jcc(Condition cc, Label& L,
1047 relocInfo::relocType rtype = relocInfo::none);
1048
1049 // Conditional jump to a 8-bit offset to L.
1050 // WARNING: be very careful using this for forward jumps. If the label is
1051 // not bound within an 8-bit offset of this instruction, a run-time error
1052 // will occur.
1053 void jccb(Condition cc, Label& L);
1054
1055 void jmp(Address entry); // pc <- entry
1056
1057 // Label operations & relative jumps (PPUM Appendix D)
1058 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L
1059
1060 void jmp(Register entry); // pc <- entry
1061
1062 // Unconditional 8-bit offset jump to L.
1063 // WARNING: be very careful using this for forward jumps. If the label is
1064 // not bound within an 8-bit offset of this instruction, a run-time error
1065 // will occur.
1066 void jmpb(Label& L);
1067
1068 void ldmxcsr( Address src );
1069
1070 void leal(Register dst, Address src);
1071
1072 void leaq(Register dst, Address src);
1073
1074 void lfence() {
1075 emit_byte(0x0F);
1076 emit_byte(0xAE);
1077 emit_byte(0xE8);
1078 }
1079
1080 void lock();
1081
1082 enum Membar_mask_bits {
1083 StoreStore = 1 << 3,
1084 LoadStore = 1 << 2,
1085 StoreLoad = 1 << 1,
1086 LoadLoad = 1 << 0
1087 };
1088
1089 // Serializes memory.
1090 void membar(Membar_mask_bits order_constraint) {
1091 // We only have to handle StoreLoad and LoadLoad
1092 if (order_constraint & StoreLoad) {
1093 // MFENCE subsumes LFENCE
1094 mfence();
1095 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) {
1096 lfence();
1097 } */
1098 }
1099
1100 void mfence();
1101
1102 // Moves
1103
1104 void mov64(Register dst, int64_t imm64);
1105
1106 void movb(Address dst, Register src);
1107 void movb(Address dst, int imm8);
1108 void movb(Register dst, Address src);
1109
1110 void movdl(XMMRegister dst, Register src);
1111 void movdl(Register dst, XMMRegister src);
1112
1113 // Move Double Quadword
1114 void movdq(XMMRegister dst, Register src);
1115 void movdq(Register dst, XMMRegister src);
1116
1117 // Move Aligned Double Quadword
1118 void movdqa(Address dst, XMMRegister src);
1119 void movdqa(XMMRegister dst, Address src);
1120 void movdqa(XMMRegister dst, XMMRegister src);
1121
1122 // Move Unaligned Double Quadword
1123 void movdqu(Address dst, XMMRegister src);
1124 void movdqu(XMMRegister dst, Address src);
1125 void movdqu(XMMRegister dst, XMMRegister src);
1126
1127 void movl(Register dst, int32_t imm32);
1128 void movl(Address dst, int32_t imm32);
1129 void movl(Register dst, Register src);
1130 void movl(Register dst, Address src);
1131 void movl(Address dst, Register src);
1132
1133 // These dummies prevent using movl from converting a zero (like NULL) into Register
1134 // by giving the compiler two choices it can't resolve
1135
1136 void movl(Address dst, void* junk);
1137 void movl(Register dst, void* junk);
1138
1139 #ifdef _LP64
1140 void movq(Register dst, Register src);
1141 void movq(Register dst, Address src);
1142 void movq(Address dst, Register src);
1143 #endif
1144
1145 void movq(Address dst, MMXRegister src );
1146 void movq(MMXRegister dst, Address src );
1147
1148 #ifdef _LP64
1149 // These dummies prevent using movq from converting a zero (like NULL) into Register
1150 // by giving the compiler two choices it can't resolve
1151
1152 void movq(Address dst, void* dummy);
1153 void movq(Register dst, void* dummy);
1154 #endif
1155
1156 // Move Quadword
1157 void movq(Address dst, XMMRegister src);
1158 void movq(XMMRegister dst, Address src);
1159
1160 void movsbl(Register dst, Address src);
1161 void movsbl(Register dst, Register src);
1162
1163 #ifdef _LP64
1164 // Move signed 32bit immediate to 64bit extending sign
1165 void movslq(Address dst, int32_t imm64);
1166 void movslq(Register dst, int32_t imm64);
1167
1168 void movslq(Register dst, Address src);
1169 void movslq(Register dst, Register src);
1170 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1171 #endif
1172
1173 void movswl(Register dst, Address src);
1174 void movswl(Register dst, Register src);
1175
1176 void movw(Address dst, int imm16);
1177 void movw(Register dst, Address src);
1178 void movw(Address dst, Register src);
1179
1180 void movzbl(Register dst, Address src);
1181 void movzbl(Register dst, Register src);
1182
1183 void movzwl(Register dst, Address src);
1184 void movzwl(Register dst, Register src);
1185
1186 void mull(Address src);
1187 void mull(Register src);
1188
1189 // Multiply Scalar Double-Precision Floating-Point Values
1190 void mulsd(XMMRegister dst, Address src);
1191 void mulsd(XMMRegister dst, XMMRegister src);
1192
1193 // Multiply Scalar Single-Precision Floating-Point Values
1194 void mulss(XMMRegister dst, Address src);
1195 void mulss(XMMRegister dst, XMMRegister src);
1196
1197 void negl(Register dst);
1198
1199 #ifdef _LP64
1200 void negq(Register dst);
1201 #endif
1202
1203 void nop(int i = 1);
1204
1205 void notl(Register dst);
1206
1207 #ifdef _LP64
1208 void notq(Register dst);
1209 #endif
1210
1211 void orl(Address dst, int32_t imm32);
1212 void orl(Register dst, int32_t imm32);
1213 void orl(Register dst, Address src);
1214 void orl(Register dst, Register src);
1215
1216 void orq(Address dst, int32_t imm32);
1217 void orq(Register dst, int32_t imm32);
1218 void orq(Register dst, Address src);
1219 void orq(Register dst, Register src);
1220
1221 void popl(Address dst);
1222
1223 #ifdef _LP64
1224 void popq(Address dst);
1225 #endif
1226
1227 // Prefetches (SSE, SSE2, 3DNOW only)
1228
1229 void prefetchnta(Address src);
1230 void prefetchr(Address src);
1231 void prefetcht0(Address src);
1232 void prefetcht1(Address src);
1233 void prefetcht2(Address src);
1234 void prefetchw(Address src);
1235
1236 // Shuffle Packed Doublewords
1237 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1238 void pshufd(XMMRegister dst, Address src, int mode);
1239
1240 // Shuffle Packed Low Words
1241 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1242 void pshuflw(XMMRegister dst, Address src, int mode);
1243
1244 // Shift Right Logical Quadword Immediate
1245 void psrlq(XMMRegister dst, int shift);
1246
1247 // Interleave Low Bytes
1248 void punpcklbw(XMMRegister dst, XMMRegister src);
1249
1250 void pushl(Address src);
1251
1252 void pushq(Address src);
1253
1254 // Xor Packed Byte Integer Values
1255 void pxor(XMMRegister dst, Address src);
1256 void pxor(XMMRegister dst, XMMRegister src);
1257
1258 void rcll(Register dst, int imm8);
1259
1260 void rclq(Register dst, int imm8);
1261
1262 void ret(int imm16);
1263
1264 void sahf();
1265
1266 void sarl(Register dst, int imm8);
1267 void sarl(Register dst);
1268
1269 void sarq(Register dst, int imm8);
1270 void sarq(Register dst);
1271
1272 void sbbl(Address dst, int32_t imm32);
1273 void sbbl(Register dst, int32_t imm32);
1274 void sbbl(Register dst, Address src);
1275 void sbbl(Register dst, Register src);
1276
1277 void sbbq(Address dst, int32_t imm32);
1278 void sbbq(Register dst, int32_t imm32);
1279 void sbbq(Register dst, Address src);
1280 void sbbq(Register dst, Register src);
1281
1282 void setb(Condition cc, Register dst);
1283
1284 void shldl(Register dst, Register src);
1285
1286 void shll(Register dst, int imm8);
1287 void shll(Register dst);
1288
1289 void shlq(Register dst, int imm8);
1290 void shlq(Register dst);
1291
1292 void shrdl(Register dst, Register src);
1293
1294 void shrl(Register dst, int imm8);
1295 void shrl(Register dst);
1296
1297 void shrq(Register dst, int imm8);
1298 void shrq(Register dst);
1299
1300 void smovl(); // QQQ generic?
1301
1302 // Compute Square Root of Scalar Double-Precision Floating-Point Value
1303 void sqrtsd(XMMRegister dst, Address src);
1304 void sqrtsd(XMMRegister dst, XMMRegister src);
1305
1306 void std() { emit_byte(0xfd); }
1307
1308 void stmxcsr( Address dst );
1309
1310 void subl(Address dst, int32_t imm32);
1311 void subl(Address dst, Register src);
1312 void subl(Register dst, int32_t imm32);
1313 void subl(Register dst, Address src);
1314 void subl(Register dst, Register src);
1315
1316 void subq(Address dst, int32_t imm32);
1317 void subq(Address dst, Register src);
1318 void subq(Register dst, int32_t imm32);
1319 void subq(Register dst, Address src);
1320 void subq(Register dst, Register src);
1321
1322
1323 // Subtract Scalar Double-Precision Floating-Point Values
1324 void subsd(XMMRegister dst, Address src);
1325 void subsd(XMMRegister dst, XMMRegister src);
1326
1327 // Subtract Scalar Single-Precision Floating-Point Values
1328 void subss(XMMRegister dst, Address src);
1329 void subss(XMMRegister dst, XMMRegister src);
1330
1331 void testb(Register dst, int imm8);
1332
1333 void testl(Register dst, int32_t imm32);
1334 void testl(Register dst, Register src);
1335 void testl(Register dst, Address src);
1336
1337 void testq(Register dst, int32_t imm32);
1338 void testq(Register dst, Register src);
1339
1340
1341 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1342 void ucomisd(XMMRegister dst, Address src);
1343 void ucomisd(XMMRegister dst, XMMRegister src);
1344
1345 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1346 void ucomiss(XMMRegister dst, Address src);
1347 void ucomiss(XMMRegister dst, XMMRegister src);
1348
1349 void xaddl(Address dst, Register src);
1350
1351 void xaddq(Address dst, Register src);
1352
1353 void xchgl(Register reg, Address adr);
1354 void xchgl(Register dst, Register src);
1355
1356 void xchgq(Register reg, Address adr);
1357 void xchgq(Register dst, Register src);
1358
1359 void xorl(Register dst, int32_t imm32);
1360 void xorl(Register dst, Address src);
1361 void xorl(Register dst, Register src);
1362
1363 void xorq(Register dst, Address src);
1364 void xorq(Register dst, Register src);
1365
1366 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1367 void xorpd(XMMRegister dst, Address src);
1368 void xorpd(XMMRegister dst, XMMRegister src);
1369
1370 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1371 void xorps(XMMRegister dst, Address src);
1372 void xorps(XMMRegister dst, XMMRegister src);
1373
1374 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1375 };
1376
1377
1378 // MacroAssembler extends Assembler by frequently used macros.
1379 //
1380 // Instructions for which a 'better' code sequence exists depending
1381 // on arguments should also go in here.
1382
1383 class MacroAssembler: public Assembler {
1384 friend class LIR_Assembler;
1385 friend class Runtime1; // as_Address()
1386 protected:
1387
1388 Address as_Address(AddressLiteral adr);
1389 Address as_Address(ArrayAddress adr);
1390
1391 // Support for VM calls
1392 //
1393 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1394 // may customize this version by overriding it for its purposes (e.g., to save/restore
1395 // additional registers when doing a VM call).
1396 #ifdef CC_INTERP
1397 // c++ interpreter never wants to use interp_masm version of call_VM
1398 #define VIRTUAL
1399 #else
1400 #define VIRTUAL virtual
1401 #endif
1402
1403 VIRTUAL void call_VM_leaf_base(
1404 address entry_point, // the entry point
1405 int number_of_arguments // the number of arguments to pop after the call
1406 );
1407
1408 // This is the base routine called by the different versions of call_VM. The interpreter
1409 // may customize this version by overriding it for its purposes (e.g., to save/restore
1410 // additional registers when doing a VM call).
1411 //
1412 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
1413 // returns the register which contains the thread upon return. If a thread register has been
1414 // specified, the return value will correspond to that register. If no last_java_sp is specified
1415 // (noreg) than rsp will be used instead.
1416 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
1417 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1418 Register java_thread, // the thread if computed before ; use noreg otherwise
1419 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1420 address entry_point, // the entry point
1421 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
1422 bool check_exceptions // whether to check for pending exceptions after return
1423 );
1424
1425 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1426 // The implementation is only non-empty for the InterpreterMacroAssembler,
1427 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
1428 virtual void check_and_handle_popframe(Register java_thread);
1429 virtual void check_and_handle_earlyret(Register java_thread);
1430
1431 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
1432
1433 // helpers for FPU flag access
1434 // tmp is a temporary register, if none is available use noreg
1435 void save_rax (Register tmp);
1436 void restore_rax(Register tmp);
1437
1438 public:
1439 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1440
1441 // Support for NULL-checks
1442 //
1443 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1444 // If the accessed location is M[reg + offset] and the offset is known, provide the
1445 // offset. No explicit code generation is needed if the offset is within a certain
1446 // range (0 <= offset <= page_size).
1447
1448 void null_check(Register reg, int offset = -1);
1449 static bool needs_explicit_null_check(intptr_t offset);
1450
1451 // Required platform-specific helpers for Label::patch_instructions.
1452 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1453 void pd_patch_instruction(address branch, address target);
1454 #ifndef PRODUCT
1455 static void pd_print_patched_instruction(address branch);
1456 #endif
1457
1458 // The following 4 methods return the offset of the appropriate move instruction
1459
1460 // Support for fast byte/word loading with zero extension (depending on particular CPU)
1461 int load_unsigned_byte(Register dst, Address src);
1462 int load_unsigned_word(Register dst, Address src);
1463
1464 // Support for fast byte/word loading with sign extension (depending on particular CPU)
1465 int load_signed_byte(Register dst, Address src);
1466 int load_signed_word(Register dst, Address src);
1467
1468 // Support for sign-extension (hi:lo = extend_sign(lo))
1469 void extend_sign(Register hi, Register lo);
1470
1471 // Loading values by size and signed-ness
1472 void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed);
1473
1474 // Support for inc/dec with optimal instruction selection depending on value
1475
1476 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
1477 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
1478
1479 void decrementl(Address dst, int value = 1);
1480 void decrementl(Register reg, int value = 1);
1481
1482 void decrementq(Register reg, int value = 1);
1483 void decrementq(Address dst, int value = 1);
1484
1485 void incrementl(Address dst, int value = 1);
1486 void incrementl(Register reg, int value = 1);
1487
1488 void incrementq(Register reg, int value = 1);
1489 void incrementq(Address dst, int value = 1);
1490
1491
1492 // Support optimal SSE move instructions.
1493 void movflt(XMMRegister dst, XMMRegister src) {
1494 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
1495 else { movss (dst, src); return; }
1496 }
1497 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
1498 void movflt(XMMRegister dst, AddressLiteral src);
1499 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
1500
1501 void movdbl(XMMRegister dst, XMMRegister src) {
1502 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
1503 else { movsd (dst, src); return; }
1504 }
1505
1506 void movdbl(XMMRegister dst, AddressLiteral src);
1507
1508 void movdbl(XMMRegister dst, Address src) {
1509 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
1510 else { movlpd(dst, src); return; }
1511 }
1512 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
1513
1514 void incrementl(AddressLiteral dst);
1515 void incrementl(ArrayAddress dst);
1516
1517 // Alignment
1518 void align(int modulus);
1519
1520 // Misc
1521 void fat_nop(); // 5 byte nop
1522
1523 // Stack frame creation/removal
1524 void enter();
1525 void leave();
1526
1527 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
1528 // The pointer will be loaded into the thread register.
1529 void get_thread(Register thread);
1530
1531
1532 // Support for VM calls
1533 //
1534 // It is imperative that all calls into the VM are handled via the call_VM macros.
1535 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1536 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1537
1538
1539 void call_VM(Register oop_result,
1540 address entry_point,
1541 bool check_exceptions = true);
1542 void call_VM(Register oop_result,
1543 address entry_point,
1544 Register arg_1,
1545 bool check_exceptions = true);
1546 void call_VM(Register oop_result,
1547 address entry_point,
1548 Register arg_1, Register arg_2,
1549 bool check_exceptions = true);
1550 void call_VM(Register oop_result,
1551 address entry_point,
1552 Register arg_1, Register arg_2, Register arg_3,
1553 bool check_exceptions = true);
1554
1555 // Overloadings with last_Java_sp
1556 void call_VM(Register oop_result,
1557 Register last_java_sp,
1558 address entry_point,
1559 int number_of_arguments = 0,
1560 bool check_exceptions = true);
1561 void call_VM(Register oop_result,
1562 Register last_java_sp,
1563 address entry_point,
1564 Register arg_1, bool
1565 check_exceptions = true);
1566 void call_VM(Register oop_result,
1567 Register last_java_sp,
1568 address entry_point,
1569 Register arg_1, Register arg_2,
1570 bool check_exceptions = true);
1571 void call_VM(Register oop_result,
1572 Register last_java_sp,
1573 address entry_point,
1574 Register arg_1, Register arg_2, Register arg_3,
1575 bool check_exceptions = true);
1576
1577 void call_VM_leaf(address entry_point,
1578 int number_of_arguments = 0);
1579 void call_VM_leaf(address entry_point,
1580 Register arg_1);
1581 void call_VM_leaf(address entry_point,
1582 Register arg_1, Register arg_2);
1583 void call_VM_leaf(address entry_point,
1584 Register arg_1, Register arg_2, Register arg_3);
1585
1586 // last Java Frame (fills frame anchor)
1587 void set_last_Java_frame(Register thread,
1588 Register last_java_sp,
1589 Register last_java_fp,
1590 address last_java_pc);
1591
1592 // thread in the default location (r15_thread on 64bit)
1593 void set_last_Java_frame(Register last_java_sp,
1594 Register last_java_fp,
1595 address last_java_pc);
1596
1597 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
1598
1599 // thread in the default location (r15_thread on 64bit)
1600 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
1601
1602 // Stores
1603 void store_check(Register obj); // store check for obj - register is destroyed afterwards
1604 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
1605
1606 void g1_write_barrier_pre(Register obj,
1607 #ifndef _LP64
1608 Register thread,
1609 #endif
1610 Register tmp,
1611 Register tmp2,
1612 bool tosca_live);
1613 void g1_write_barrier_post(Register store_addr,
1614 Register new_val,
1615 #ifndef _LP64
1616 Register thread,
1617 #endif
1618 Register tmp,
1619 Register tmp2);
1620
1621
1622 // split store_check(Register obj) to enhance instruction interleaving
1623 void store_check_part_1(Register obj);
1624 void store_check_part_2(Register obj);
1625
1626 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
1627 void c2bool(Register x);
1628
1629 // C++ bool manipulation
1630
1631 void movbool(Register dst, Address src);
1632 void movbool(Address dst, bool boolconst);
1633 void movbool(Address dst, Register src);
1634 void testbool(Register dst);
1635
1636 // oop manipulations
1637 void load_klass(Register dst, Register src);
1638 void store_klass(Register dst, Register src);
1639
1640 void load_prototype_header(Register dst, Register src);
1641
1642 #ifdef _LP64
1643 void store_klass_gap(Register dst, Register src);
1644
1645 void load_heap_oop(Register dst, Address src);
1646 void store_heap_oop(Address dst, Register src);
1647 void encode_heap_oop(Register r);
1648 void decode_heap_oop(Register r);
1649 void encode_heap_oop_not_null(Register r);
1650 void decode_heap_oop_not_null(Register r);
1651 void encode_heap_oop_not_null(Register dst, Register src);
1652 void decode_heap_oop_not_null(Register dst, Register src);
1653
1654 void set_narrow_oop(Register dst, jobject obj);
1655
1656 // if heap base register is used - reinit it with the correct value
1657 void reinit_heapbase();
1658 #endif // _LP64
1659
1660 // Int division/remainder for Java
1661 // (as idivl, but checks for special case as described in JVM spec.)
1662 // returns idivl instruction offset for implicit exception handling
1663 int corrected_idivl(Register reg);
1664
1665 // Long division/remainder for Java
1666 // (as idivq, but checks for special case as described in JVM spec.)
1667 // returns idivq instruction offset for implicit exception handling
1668 int corrected_idivq(Register reg);
1669
1670 void int3();
1671
1672 // Long operation macros for a 32bit cpu
1673 // Long negation for Java
1674 void lneg(Register hi, Register lo);
1675
1676 // Long multiplication for Java
1677 // (destroys contents of eax, ebx, ecx and edx)
1678 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
1679
1680 // Long shifts for Java
1681 // (semantics as described in JVM spec.)
1682 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
1683 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
1684
1685 // Long compare for Java
1686 // (semantics as described in JVM spec.)
1687 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
1688
1689
1690 // misc
1691
1692 // Sign extension
1693 void sign_extend_short(Register reg);
1694 void sign_extend_byte(Register reg);
1695
1696 // Division by power of 2, rounding towards 0
1697 void division_with_shift(Register reg, int shift_value);
1698
1699 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
1700 //
1701 // CF (corresponds to C0) if x < y
1702 // PF (corresponds to C2) if unordered
1703 // ZF (corresponds to C3) if x = y
1704 //
1705 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1706 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
1707 void fcmp(Register tmp);
1708 // Variant of the above which allows y to be further down the stack
1709 // and which only pops x and y if specified. If pop_right is
1710 // specified then pop_left must also be specified.
1711 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
1712
1713 // Floating-point comparison for Java
1714 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
1715 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
1716 // (semantics as described in JVM spec.)
1717 void fcmp2int(Register dst, bool unordered_is_less);
1718 // Variant of the above which allows y to be further down the stack
1719 // and which only pops x and y if specified. If pop_right is
1720 // specified then pop_left must also be specified.
1721 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
1722
1723 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
1724 // tmp is a temporary register, if none is available use noreg
1725 void fremr(Register tmp);
1726
1727
1728 // same as fcmp2int, but using SSE2
1729 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1730 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
1731
1732 // Inlined sin/cos generator for Java; must not use CPU instruction
1733 // directly on Intel as it does not have high enough precision
1734 // outside of the range [-pi/4, pi/4]. Extra argument indicate the
1735 // number of FPU stack slots in use; all but the topmost will
1736 // require saving if a slow case is necessary. Assumes argument is
1737 // on FP TOS; result is on FP TOS. No cpu registers are changed by
1738 // this code.
1739 void trigfunc(char trig, int num_fpu_regs_in_use = 1);
1740
1741 // branch to L if FPU flag C2 is set/not set
1742 // tmp is a temporary register, if none is available use noreg
1743 void jC2 (Register tmp, Label& L);
1744 void jnC2(Register tmp, Label& L);
1745
1746 // Pop ST (ffree & fincstp combined)
1747 void fpop();
1748
1749 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
1750 void push_fTOS();
1751
1752 // pops double TOS element from CPU stack and pushes on FPU stack
1753 void pop_fTOS();
1754
1755 void empty_FPU_stack();
1756
1757 void push_IU_state();
1758 void pop_IU_state();
1759
1760 void push_FPU_state();
1761 void pop_FPU_state();
1762
1763 void push_CPU_state();
1764 void pop_CPU_state();
1765
1766 // Round up to a power of two
1767 void round_to(Register reg, int modulus);
1768
1769 // Callee saved registers handling
1770 void push_callee_saved_registers();
1771 void pop_callee_saved_registers();
1772
1773 // allocation
1774 void eden_allocate(
1775 Register obj, // result: pointer to object after successful allocation
1776 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1777 int con_size_in_bytes, // object size in bytes if known at compile time
1778 Register t1, // temp register
1779 Label& slow_case // continuation point if fast allocation fails
1780 );
1781 void tlab_allocate(
1782 Register obj, // result: pointer to object after successful allocation
1783 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1784 int con_size_in_bytes, // object size in bytes if known at compile time
1785 Register t1, // temp register
1786 Register t2, // temp register
1787 Label& slow_case // continuation point if fast allocation fails
1788 );
1789 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
1790
1791 // small bootstrap problems
1792 RegisterConstant delayed_value(intptr_t* delayed_value_addr, Register tmp);
1793 RegisterConstant delayed_value(int(*value_fn)(), Register tmp) {
1794 return delayed_value(delayed_value_addr(value_fn), tmp);
1795 }
1796 RegisterConstant delayed_value(address(*value_fn)(), Register tmp) {
1797 return delayed_value((intptr_t*) delayed_value_addr(value_fn), tmp);
1798 }
1799
1800 // interface method calling
1801 void lookup_interface_method(Register recv_klass,
1802 Register intf_klass,
1803 RegisterConstant itable_index,
1804 Register method_result,
1805 Register scan_temp,
1806 Label& no_such_interface);
1807
1808 // method handles (JSR 292)
1809 void check_method_handle_type(Register mtype_reg, Register mh_reg,
1810 Register temp_reg,
1811 Label& wrong_method_type);
1812 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg,
1813 Register temp_reg);
1814 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
1815 Address argument_address(RegisterConstant arg_slot, int extra_slot_offset = 0);
1816
1817
1818 // klass type checking (falls through on failure)
1819 void check_klass_subtype(Register sub_klass,
1820 Register super_klass,
1821 Register temp_reg,
1822 Label& L_success);
1823
1824 //----
1825 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
1826
1827 // Debugging
1828
1829 // only if +VerifyOops
1830 void verify_oop(Register reg, const char* s = "broken oop");
1831 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
1832
1833 // only if +VerifyFPU
1834 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
1835
1836 // prints msg, dumps registers and stops execution
1837 void stop(const char* msg);
1838
1839 // prints msg and continues
1840 void warn(const char* msg);
1841
1842 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
1843 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1844
1845 void os_breakpoint();
1846
1847 void untested() { stop("untested"); }
1848
1849 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); }
1850
1851 void should_not_reach_here() { stop("should not reach here"); }
1852
1853 void print_CPU_state();
1854
1855 // Stack overflow checking
1856 void bang_stack_with_offset(int offset) {
1857 // stack grows down, caller passes positive offset
1858 assert(offset > 0, "must bang with negative offset");
1859 movl(Address(rsp, (-offset)), rax);
1860 }
1861
1862 // Writes to stack successive pages until offset reached to check for
1863 // stack overflow + shadow pages. Also, clobbers tmp
1864 void bang_stack_size(Register size, Register tmp);
1865
1866 // Support for serializing memory accesses between threads
1867 void serialize_memory(Register thread, Register tmp);
1868
1869 void verify_tlab();
1870
1871 // Biased locking support
1872 // lock_reg and obj_reg must be loaded up with the appropriate values.
1873 // swap_reg must be rax, and is killed.
1874 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
1875 // be killed; if not supplied, push/pop will be used internally to
1876 // allocate a temporary (inefficient, avoid if possible).
1877 // Optional slow case is for implementations (interpreter and C1) which branch to
1878 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
1879 // Returns offset of first potentially-faulting instruction for null
1880 // check info (currently consumed only by C1). If
1881 // swap_reg_contains_mark is true then returns -1 as it is assumed
1882 // the calling code has already passed any potential faults.
1883 int biased_locking_enter(Register lock_reg, Register obj_reg,
1884 Register swap_reg, Register tmp_reg,
1885 bool swap_reg_contains_mark,
1886 Label& done, Label* slow_case = NULL,
1887 BiasedLockingCounters* counters = NULL);
1888 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
1889
1890
1891 Condition negate_condition(Condition cond);
1892
1893 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
1894 // operands. In general the names are modified to avoid hiding the instruction in Assembler
1895 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
1896 // here in MacroAssembler. The major exception to this rule is call
1897
1898 // Arithmetics
1899
1900
1901 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
1902 void addptr(Address dst, Register src);
1903
1904 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
1905 void addptr(Register dst, int32_t src);
1906 void addptr(Register dst, Register src);
1907
1908 void andptr(Register dst, int32_t src);
1909 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
1910
1911 void cmp8(AddressLiteral src1, int imm);
1912
1913 // renamed to drag out the casting of address to int32_t/intptr_t
1914 void cmp32(Register src1, int32_t imm);
1915
1916 void cmp32(AddressLiteral src1, int32_t imm);
1917 // compare reg - mem, or reg - &mem
1918 void cmp32(Register src1, AddressLiteral src2);
1919
1920 void cmp32(Register src1, Address src2);
1921
1922 #ifndef _LP64
1923 void cmpoop(Address dst, jobject obj);
1924 void cmpoop(Register dst, jobject obj);
1925 #endif // _LP64
1926
1927 // NOTE src2 must be the lval. This is NOT an mem-mem compare
1928 void cmpptr(Address src1, AddressLiteral src2);
1929
1930 void cmpptr(Register src1, AddressLiteral src2);
1931
1932 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1933 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1934 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1935
1936 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1937 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
1938
1939 // cmp64 to avoild hiding cmpq
1940 void cmp64(Register src1, AddressLiteral src);
1941
1942 void cmpxchgptr(Register reg, Address adr);
1943
1944 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
1945
1946
1947 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
1948
1949
1950 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
1951
1952 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
1953
1954 void shlptr(Register dst, int32_t shift);
1955 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
1956
1957 void shrptr(Register dst, int32_t shift);
1958 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
1959
1960 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
1961 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
1962
1963 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
1964
1965 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
1966 void subptr(Register dst, int32_t src);
1967 void subptr(Register dst, Register src);
1968
1969
1970 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
1971 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
1972
1973 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
1974 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
1975
1976 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
1977
1978
1979
1980 // Helper functions for statistics gathering.
1981 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
1982 void cond_inc32(Condition cond, AddressLiteral counter_addr);
1983 // Unconditional atomic increment.
1984 void atomic_incl(AddressLiteral counter_addr);
1985
1986 void lea(Register dst, AddressLiteral adr);
1987 void lea(Address dst, AddressLiteral adr);
1988 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
1989
1990 void leal32(Register dst, Address src) { leal(dst, src); }
1991
1992 void test32(Register src1, AddressLiteral src2);
1993
1994 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1995 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1996 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1997
1998 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
1999 void testptr(Register src1, Register src2);
2000
2001 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2002 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
2003
2004 // Calls
2005
2006 void call(Label& L, relocInfo::relocType rtype);
2007 void call(Register entry);
2008
2009 // NOTE: this call tranfers to the effective address of entry NOT
2010 // the address contained by entry. This is because this is more natural
2011 // for jumps/calls.
2012 void call(AddressLiteral entry);
2013
2014 // Jumps
2015
2016 // NOTE: these jumps tranfer to the effective address of dst NOT
2017 // the address contained by dst. This is because this is more natural
2018 // for jumps/calls.
2019 void jump(AddressLiteral dst);
2020 void jump_cc(Condition cc, AddressLiteral dst);
2021
2022 // 32bit can do a case table jump in one instruction but we no longer allow the base
2023 // to be installed in the Address class. This jump will tranfers to the address
2024 // contained in the location described by entry (not the address of entry)
2025 void jump(ArrayAddress entry);
2026
2027 // Floating
2028
2029 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
2030 void andpd(XMMRegister dst, AddressLiteral src);
2031
2032 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
2033 void comiss(XMMRegister dst, AddressLiteral src);
2034
2035 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
2036 void comisd(XMMRegister dst, AddressLiteral src);
2037
2038 void fldcw(Address src) { Assembler::fldcw(src); }
2039 void fldcw(AddressLiteral src);
2040
2041 void fld_s(int index) { Assembler::fld_s(index); }
2042 void fld_s(Address src) { Assembler::fld_s(src); }
2043 void fld_s(AddressLiteral src);
2044
2045 void fld_d(Address src) { Assembler::fld_d(src); }
2046 void fld_d(AddressLiteral src);
2047
2048 void fld_x(Address src) { Assembler::fld_x(src); }
2049 void fld_x(AddressLiteral src);
2050
2051 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
2052 void ldmxcsr(AddressLiteral src);
2053
2054 private:
2055 // these are private because users should be doing movflt/movdbl
2056
2057 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
2058 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
2059 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
2060 void movss(XMMRegister dst, AddressLiteral src);
2061
2062 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
2063 void movlpd(XMMRegister dst, AddressLiteral src);
2064
2065 public:
2066
2067 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
2068 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
2069 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
2070 void movsd(XMMRegister dst, AddressLiteral src);
2071
2072 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
2073 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
2074 void ucomiss(XMMRegister dst, AddressLiteral src);
2075
2076 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
2077 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
2078 void ucomisd(XMMRegister dst, AddressLiteral src);
2079
2080 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
2081 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
2082 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
2083 void xorpd(XMMRegister dst, AddressLiteral src);
2084
2085 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
2086 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
2087 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
2088 void xorps(XMMRegister dst, AddressLiteral src);
2089
2090 // Data
2091
2092 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2093
2094 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2095 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); }
2096
2097 void movoop(Register dst, jobject obj);
2098 void movoop(Address dst, jobject obj);
2099
2100 void movptr(ArrayAddress dst, Register src);
2101 // can this do an lea?
2102 void movptr(Register dst, ArrayAddress src);
2103
2104 void movptr(Register dst, Address src);
2105
2106 void movptr(Register dst, AddressLiteral src);
2107
2108 void movptr(Register dst, intptr_t src);
2109 void movptr(Register dst, Register src);
2110 void movptr(Address dst, intptr_t src);
2111
2112 void movptr(Address dst, Register src);
2113
2114 #ifdef _LP64
2115 // Generally the next two are only used for moving NULL
2116 // Although there are situations in initializing the mark word where
2117 // they could be used. They are dangerous.
2118
2119 // They only exist on LP64 so that int32_t and intptr_t are not the same
2120 // and we have ambiguous declarations.
2121
2122 void movptr(Address dst, int32_t imm32);
2123 void movptr(Register dst, int32_t imm32);
2124 #endif // _LP64
2125
2126 // to avoid hiding movl
2127 void mov32(AddressLiteral dst, Register src);
2128 void mov32(Register dst, AddressLiteral src);
2129
2130 // to avoid hiding movb
2131 void movbyte(ArrayAddress dst, int src);
2132
2133 // Can push value or effective address
2134 void pushptr(AddressLiteral src);
2135
2136 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2137 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2138
2139 void pushoop(jobject obj);
2140
2141 // sign extend as need a l to ptr sized element
2142 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2143 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2144
2145
2146 #undef VIRTUAL
2147
2148 };
2149
2150 /**
2151 * class SkipIfEqual:
2152 *
2153 * Instantiating this class will result in assembly code being output that will
2154 * jump around any code emitted between the creation of the instance and it's
2155 * automatic destruction at the end of a scope block, depending on the value of
2156 * the flag passed to the constructor, which will be checked at run-time.
2157 */
2158 class SkipIfEqual {
2159 private:
2160 MacroAssembler* _masm;
2161 Label _label;
2162
2163 public:
2164 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2165 ~SkipIfEqual();
2166 };
2167
2168 #ifdef ASSERT
2169 inline bool AbstractAssembler::pd_check_instruction_mark() { return true; }
2170 #endif
--- EOF ---