1 /*
2 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
26 jint& stub_inst = *(jint*) branch;
27 stub_inst = patched_branch(target - branch, stub_inst, 0);
28 }
29
30 #ifndef PRODUCT
31 inline void MacroAssembler::pd_print_patched_instruction(address branch) {
32 jint stub_inst = *(jint*) branch;
33 print_instruction(stub_inst);
34 ::tty->print("%s", " (unresolved)");
35 }
36 #endif // PRODUCT
37
38 inline bool Address::is_simm13(int offset) { return Assembler::is_simm13(disp() + offset); }
39
40
41 // inlines for SPARC assembler -- dmu 5/97
42
43 inline void Assembler::check_delay() {
44 # ifdef CHECK_DELAY
45 guarantee( delay_state != at_delay_slot, "must say delayed() when filling delay slot");
46 delay_state = no_delay;
47 # endif
48 }
49
50 inline void Assembler::emit_long(int x) {
51 check_delay();
52 AbstractAssembler::emit_long(x);
53 }
54
55 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
56 relocate(rtype);
57 emit_long(x);
58 }
59
60 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
61 relocate(rspec);
62 emit_long(x);
63 }
64
65
66 inline void Assembler::add( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | rs2(s2) ); }
67 inline void Assembler::add( Register s1, int simm13a, Register d, relocInfo::relocType rtype ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rtype ); }
68 inline void Assembler::add( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(add_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec ); }
69 inline void Assembler::add( const Address& a, Register d, int offset) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); }
70
71 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bpr_op2) | wdisp16(intptr_t(d), intptr_t(pc())) | predict(p) | rs1(s1), rt); has_delay_slot(); }
72 inline void Assembler::bpr( RCondition c, bool a, Predict p, Register s1, Label& L) { bpr( c, a, p, s1, target(L)); }
73
74 inline void Assembler::fb( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
75 inline void Assembler::fb( Condition c, bool a, Label& L ) { fb(c, a, target(L)); }
76
77 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(fbp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
78 inline void Assembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) { fbp(c, a, cc, p, target(L)); }
79
80 inline void Assembler::cb( Condition c, bool a, address d, relocInfo::relocType rt ) { v8_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(cb_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
81 inline void Assembler::cb( Condition c, bool a, Label& L ) { cb(c, a, target(L)); }
82
83 inline void Assembler::br( Condition c, bool a, address d, relocInfo::relocType rt ) { v9_dep(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(br_op2) | wdisp(intptr_t(d), intptr_t(pc()), 22), rt); has_delay_slot(); }
84 inline void Assembler::br( Condition c, bool a, Label& L ) { br(c, a, target(L)); }
85
86 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) { v9_only(); emit_data( op(branch_op) | annul(a) | cond(c) | op2(bp_op2) | branchcc(cc) | predict(p) | wdisp(intptr_t(d), intptr_t(pc()), 19), rt); has_delay_slot(); }
87 inline void Assembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) { bp(c, a, cc, p, target(L)); }
88
89 inline void Assembler::call( address d, relocInfo::relocType rt ) { emit_data( op(call_op) | wdisp(intptr_t(d), intptr_t(pc()), 30), rt); has_delay_slot(); assert(rt != relocInfo::virtual_call_type, "must use virtual_call_Relocation::spec"); }
90 inline void Assembler::call( Label& L, relocInfo::relocType rt ) { call( target(L), rt); }
91
92 inline void Assembler::flush( Register s1, Register s2) { emit_long( op(arith_op) | op3(flush_op3) | rs1(s1) | rs2(s2)); }
93 inline void Assembler::flush( Register s1, int simm13a) { emit_data( op(arith_op) | op3(flush_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
94
95 inline void Assembler::jmpl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
96 inline void Assembler::jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec ) { emit_data( op(arith_op) | rd(d) | op3(jmpl_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rspec); has_delay_slot(); }
97
98 inline void Assembler::jmpl( Address& a, Register d, int offset) { jmpl( a.base(), a.disp() + offset, d, a.rspec(offset)); }
99
100
101 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | rs2(s2) ); }
102 inline void Assembler::ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
103
104 inline void Assembler::ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset) { relocate(a.rspec(offset)); ldf( w, a.base(), a.disp() + offset, d); }
105
106 inline void Assembler::ldfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
107 inline void Assembler::ldfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
108 inline void Assembler::ldxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | rs2(s2) ); }
109 inline void Assembler::ldxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(ldfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
110
111 inline void Assembler::ldc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | rs2(s2) ); }
112 inline void Assembler::ldc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
113 inline void Assembler::lddc( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | rs2(s2) ); }
114 inline void Assembler::lddc( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(lddc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
115 inline void Assembler::ldcsr( Register s1, Register s2, int crd) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | rs2(s2) ); }
116 inline void Assembler::ldcsr( Register s1, int simm13a, int crd) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(ldcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
117
118 inline void Assembler::ldsb( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | rs2(s2) ); }
119 inline void Assembler::ldsb( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
120
121 inline void Assembler::ldsh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | rs2(s2) ); }
122 inline void Assembler::ldsh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
123 inline void Assembler::ldsw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | rs2(s2) ); }
124 inline void Assembler::ldsw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldsw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
125 inline void Assembler::ldub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | rs2(s2) ); }
126 inline void Assembler::ldub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
127 inline void Assembler::lduh( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | rs2(s2) ); }
128 inline void Assembler::lduh( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduh_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
129 inline void Assembler::lduw( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | rs2(s2) ); }
130 inline void Assembler::lduw( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(lduw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
131
132 inline void Assembler::ldx( Register s1, Register s2, Register d) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | rs2(s2) ); }
133 inline void Assembler::ldx( Register s1, int simm13a, Register d) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(ldx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
134 inline void Assembler::ldd( Register s1, Register s2, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | rs2(s2) ); }
135 inline void Assembler::ldd( Register s1, int simm13a, Register d) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(ldd_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
136
137 #ifdef _LP64
138 // Make all 32 bit loads signed so 64 bit registers maintain proper sign
139 inline void Assembler::ld( Register s1, Register s2, Register d) { ldsw( s1, s2, d); }
140 inline void Assembler::ld( Register s1, int simm13a, Register d) { ldsw( s1, simm13a, d); }
141 #else
142 inline void Assembler::ld( Register s1, Register s2, Register d) { lduw( s1, s2, d); }
143 inline void Assembler::ld( Register s1, int simm13a, Register d) { lduw( s1, simm13a, d); }
144 #endif
145
146 inline void Assembler::ld( Register s1, RegisterConstant s2, Register d) {
147 if (s2.is_register()) ld(s1, s2.as_register(), d);
148 else ld(s1, s2.as_constant(), d);
149 }
150 inline void Assembler::ldsw( Register s1, RegisterConstant s2, Register d) {
151 if (s2.is_register()) ldsw(s1, s2.as_register(), d);
152 else ldsw(s1, s2.as_constant(), d);
153 }
154 inline void Assembler::lduw( Register s1, RegisterConstant s2, Register d) {
155 if (s2.is_register()) ldsw(s1, s2.as_register(), d);
156 else ldsw(s1, s2.as_constant(), d);
157 }
158 inline void Assembler::ldx( Register s1, RegisterConstant s2, Register d) {
159 if (s2.is_register()) ldx(s1, s2.as_register(), d);
160 else ldx(s1, s2.as_constant(), d);
161 }
162
163 // form effective addresses this way:
164 inline void Assembler::add( Register s1, RegisterConstant s2, Register d, int offset) {
165 if (s2.is_register()) add(s1, s2.as_register(), d);
166 else { add(s1, s2.as_constant() + offset, d); offset = 0; }
167 if (offset != 0) add(d, offset, d);
168 }
169
170 inline void Assembler::ld( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ld( a.base(), a.disp() + offset, d ); }
171 inline void Assembler::ldsb( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsb( a.base(), a.disp() + offset, d ); }
172 inline void Assembler::ldsh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsh( a.base(), a.disp() + offset, d ); }
173 inline void Assembler::ldsw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldsw( a.base(), a.disp() + offset, d ); }
174 inline void Assembler::ldub( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldub( a.base(), a.disp() + offset, d ); }
175 inline void Assembler::lduh( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduh( a.base(), a.disp() + offset, d ); }
176 inline void Assembler::lduw( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); lduw( a.base(), a.disp() + offset, d ); }
177 inline void Assembler::ldd( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldd( a.base(), a.disp() + offset, d ); }
178 inline void Assembler::ldx( const Address& a, Register d, int offset ) { relocate(a.rspec(offset)); ldx( a.base(), a.disp() + offset, d ); }
179
180
181 inline void Assembler::ldstub( Register s1, Register s2, Register d) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | rs2(s2) ); }
182 inline void Assembler::ldstub( Register s1, int simm13a, Register d) { emit_data( op(ldst_op) | rd(d) | op3(ldstub_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
183
184
185 inline void Assembler::prefetch(Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); }
186 inline void Assembler::prefetch(Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
187
188 inline void Assembler::prefetch(const Address& a, PrefetchFcn f, int offset) { v9_only(); relocate(a.rspec(offset)); prefetch(a.base(), a.disp() + offset, f); }
189
190
191 inline void Assembler::rett( Register s1, Register s2 ) { emit_long( op(arith_op) | op3(rett_op3) | rs1(s1) | rs2(s2)); has_delay_slot(); }
192 inline void Assembler::rett( Register s1, int simm13a, relocInfo::relocType rt) { emit_data( op(arith_op) | op3(rett_op3) | rs1(s1) | immed(true) | simm(simm13a, 13), rt); has_delay_slot(); }
193
194 inline void Assembler::sethi( int imm22a, Register d, RelocationHolder const& rspec ) { emit_data( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(imm22a), rspec); }
195
196 // pp 222
197
198 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2) { emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | rs2(s2) ); }
199 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a) { emit_data( op(ldst_op) | fd(d, w) | alt_op3(stf_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
200
201 inline void Assembler::stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset) { relocate(a.rspec(offset)); stf(w, d, a.base(), a.disp() + offset); }
202
203 inline void Assembler::stfsr( Register s1, Register s2) { v9_dep(); emit_long( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
204 inline void Assembler::stfsr( Register s1, int simm13a) { v9_dep(); emit_data( op(ldst_op) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
205 inline void Assembler::stxfsr( Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | rs2(s2) ); }
206 inline void Assembler::stxfsr( Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(G1) | op3(stfsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
207
208 // p 226
209
210 inline void Assembler::stb( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | rs2(s2) ); }
211 inline void Assembler::stb( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stb_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
212 inline void Assembler::sth( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | rs2(s2) ); }
213 inline void Assembler::sth( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(sth_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
214 inline void Assembler::stw( Register d, Register s1, Register s2) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | rs2(s2) ); }
215 inline void Assembler::stw( Register d, Register s1, int simm13a) { emit_data( op(ldst_op) | rd(d) | op3(stw_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
216
217
218 inline void Assembler::stx( Register d, Register s1, Register s2) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | rs2(s2) ); }
219 inline void Assembler::stx( Register d, Register s1, int simm13a) { v9_only(); emit_data( op(ldst_op) | rd(d) | op3(stx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
220 inline void Assembler::std( Register d, Register s1, Register s2) { v9_dep(); assert(d->is_even(), "not even"); emit_long( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | rs2(s2) ); }
221 inline void Assembler::std( Register d, Register s1, int simm13a) { v9_dep(); assert(d->is_even(), "not even"); emit_data( op(ldst_op) | rd(d) | op3(std_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
222
223 inline void Assembler::st( Register d, Register s1, Register s2) { stw(d, s1, s2); }
224 inline void Assembler::st( Register d, Register s1, int simm13a) { stw(d, s1, simm13a); }
225
226 inline void Assembler::st( Register d, Register s1, RegisterConstant s2) {
227 if (s2.is_register()) st(d, s1, s2.as_register());
228 else st(d, s1, s2.as_constant());
229 }
230 inline void Assembler::stx( Register d, Register s1, RegisterConstant s2) {
231 if (s2.is_register()) stx(d, s1, s2.as_register());
232 else stx(d, s1, s2.as_constant());
233 }
234
235 inline void Assembler::stb( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stb( d, a.base(), a.disp() + offset); }
236 inline void Assembler::sth( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); sth( d, a.base(), a.disp() + offset); }
237 inline void Assembler::stw( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stw( d, a.base(), a.disp() + offset); }
238 inline void Assembler::st( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); st( d, a.base(), a.disp() + offset); }
239 inline void Assembler::std( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); std( d, a.base(), a.disp() + offset); }
240 inline void Assembler::stx( Register d, const Address& a, int offset) { relocate(a.rspec(offset)); stx( d, a.base(), a.disp() + offset); }
241
242 // v8 p 99
243
244 inline void Assembler::stc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | rs2(s2) ); }
245 inline void Assembler::stc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
246 inline void Assembler::stdc( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | rs2(s2) ); }
247 inline void Assembler::stdc( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
248 inline void Assembler::stcsr( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | rs2(s2) ); }
249 inline void Assembler::stcsr( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stcsr_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
250 inline void Assembler::stdcq( int crd, Register s1, Register s2) { v8_only(); emit_long( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | rs2(s2) ); }
251 inline void Assembler::stdcq( int crd, Register s1, int simm13a) { v8_only(); emit_data( op(ldst_op) | fcn(crd) | op3(stdcq_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
252
253
254 // pp 231
255
256 inline void Assembler::swap( Register s1, Register s2, Register d) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | rs2(s2) ); }
257 inline void Assembler::swap( Register s1, int simm13a, Register d) { v9_dep(); emit_data( op(ldst_op) | rd(d) | op3(swap_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); }
258
259 inline void Assembler::swap( Address& a, Register d, int offset ) { relocate(a.rspec(offset)); swap( a.base(), a.disp() + offset, d ); }
260
261
262 // Use the right loads/stores for the platform
263 inline void MacroAssembler::ld_ptr( Register s1, Register s2, Register d ) {
264 #ifdef _LP64
265 Assembler::ldx( s1, s2, d);
266 #else
267 Assembler::ld( s1, s2, d);
268 #endif
269 }
270
271 inline void MacroAssembler::ld_ptr( Register s1, int simm13a, Register d ) {
272 #ifdef _LP64
273 Assembler::ldx( s1, simm13a, d);
274 #else
275 Assembler::ld( s1, simm13a, d);
276 #endif
277 }
278
279 inline void MacroAssembler::ld_ptr( Register s1, RegisterConstant s2, Register d ) {
280 #ifdef _LP64
281 Assembler::ldx( s1, s2, d);
282 #else
283 Assembler::ld( s1, s2, d);
284 #endif
285 }
286
287 inline void MacroAssembler::ld_ptr( const Address& a, Register d, int offset ) {
288 #ifdef _LP64
289 Assembler::ldx( a, d, offset );
290 #else
291 Assembler::ld( a, d, offset );
292 #endif
293 }
294
295 inline void MacroAssembler::st_ptr( Register d, Register s1, Register s2 ) {
296 #ifdef _LP64
297 Assembler::stx( d, s1, s2);
298 #else
299 Assembler::st( d, s1, s2);
300 #endif
301 }
302
303 inline void MacroAssembler::st_ptr( Register d, Register s1, int simm13a ) {
304 #ifdef _LP64
305 Assembler::stx( d, s1, simm13a);
306 #else
307 Assembler::st( d, s1, simm13a);
308 #endif
309 }
310
311 inline void MacroAssembler::st_ptr( Register d, Register s1, RegisterConstant s2 ) {
312 #ifdef _LP64
313 Assembler::stx( d, s1, s2);
314 #else
315 Assembler::st( d, s1, s2);
316 #endif
317 }
318
319 inline void MacroAssembler::st_ptr( Register d, const Address& a, int offset) {
320 #ifdef _LP64
321 Assembler::stx( d, a, offset);
322 #else
323 Assembler::st( d, a, offset);
324 #endif
325 }
326
327 // Use the right loads/stores for the platform
328 inline void MacroAssembler::ld_long( Register s1, Register s2, Register d ) {
329 #ifdef _LP64
330 Assembler::ldx(s1, s2, d);
331 #else
332 Assembler::ldd(s1, s2, d);
333 #endif
334 }
335
336 inline void MacroAssembler::ld_long( Register s1, int simm13a, Register d ) {
337 #ifdef _LP64
338 Assembler::ldx(s1, simm13a, d);
339 #else
340 Assembler::ldd(s1, simm13a, d);
341 #endif
342 }
343
344 inline void MacroAssembler::ld_long( const Address& a, Register d, int offset ) {
345 #ifdef _LP64
346 Assembler::ldx(a, d, offset );
347 #else
348 Assembler::ldd(a, d, offset );
349 #endif
350 }
351
352 inline void MacroAssembler::st_long( Register d, Register s1, Register s2 ) {
353 #ifdef _LP64
354 Assembler::stx(d, s1, s2);
355 #else
356 Assembler::std(d, s1, s2);
357 #endif
358 }
359
360 inline void MacroAssembler::st_long( Register d, Register s1, int simm13a ) {
361 #ifdef _LP64
362 Assembler::stx(d, s1, simm13a);
363 #else
364 Assembler::std(d, s1, simm13a);
365 #endif
366 }
367
368 inline void MacroAssembler::st_long( Register d, const Address& a, int offset ) {
369 #ifdef _LP64
370 Assembler::stx(d, a, offset);
371 #else
372 Assembler::std(d, a, offset);
373 #endif
374 }
375
376 // Functions for isolating 64 bit shifts for LP64
377
378 inline void MacroAssembler::sll_ptr( Register s1, Register s2, Register d ) {
379 #ifdef _LP64
380 Assembler::sllx(s1, s2, d);
381 #else
382 Assembler::sll(s1, s2, d);
383 #endif
384 }
385
386 inline void MacroAssembler::sll_ptr( Register s1, int imm6a, Register d ) {
387 #ifdef _LP64
388 Assembler::sllx(s1, imm6a, d);
389 #else
390 Assembler::sll(s1, imm6a, d);
391 #endif
392 }
393
394 inline void MacroAssembler::srl_ptr( Register s1, Register s2, Register d ) {
395 #ifdef _LP64
396 Assembler::srlx(s1, s2, d);
397 #else
398 Assembler::srl(s1, s2, d);
399 #endif
400 }
401
402 inline void MacroAssembler::srl_ptr( Register s1, int imm6a, Register d ) {
403 #ifdef _LP64
404 Assembler::srlx(s1, imm6a, d);
405 #else
406 Assembler::srl(s1, imm6a, d);
407 #endif
408 }
409
410 // Use the right branch for the platform
411
412 inline void MacroAssembler::br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
413 if (VM_Version::v9_instructions_work())
414 Assembler::bp(c, a, icc, p, d, rt);
415 else
416 Assembler::br(c, a, d, rt);
417 }
418
419 inline void MacroAssembler::br( Condition c, bool a, Predict p, Label& L ) {
420 br(c, a, p, target(L));
421 }
422
423
424 // Branch that tests either xcc or icc depending on the
425 // architecture compiled (LP64 or not)
426 inline void MacroAssembler::brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
427 #ifdef _LP64
428 Assembler::bp(c, a, xcc, p, d, rt);
429 #else
430 MacroAssembler::br(c, a, p, d, rt);
431 #endif
432 }
433
434 inline void MacroAssembler::brx( Condition c, bool a, Predict p, Label& L ) {
435 brx(c, a, p, target(L));
436 }
437
438 inline void MacroAssembler::ba( bool a, Label& L ) {
439 br(always, a, pt, L);
440 }
441
442 // Warning: V9 only functions
443 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
444 Assembler::bp(c, a, cc, p, d, rt);
445 }
446
447 inline void MacroAssembler::bp( Condition c, bool a, CC cc, Predict p, Label& L ) {
448 Assembler::bp(c, a, cc, p, L);
449 }
450
451 inline void MacroAssembler::fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt ) {
452 if (VM_Version::v9_instructions_work())
453 fbp(c, a, fcc0, p, d, rt);
454 else
455 Assembler::fb(c, a, d, rt);
456 }
457
458 inline void MacroAssembler::fb( Condition c, bool a, Predict p, Label& L ) {
459 fb(c, a, p, target(L));
460 }
461
462 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt ) {
463 Assembler::fbp(c, a, cc, p, d, rt);
464 }
465
466 inline void MacroAssembler::fbp( Condition c, bool a, CC cc, Predict p, Label& L ) {
467 Assembler::fbp(c, a, cc, p, L);
468 }
469
470 inline void MacroAssembler::jmp( Register s1, Register s2 ) { jmpl( s1, s2, G0 ); }
471 inline void MacroAssembler::jmp( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, G0, rspec); }
472
473 // Call with a check to see if we need to deal with the added
474 // expense of relocation and if we overflow the displacement
475 // of the quick call instruction./
476 // Check to see if we have to deal with relocations
477 inline void MacroAssembler::call( address d, relocInfo::relocType rt ) {
478 #ifdef _LP64
479 intptr_t disp;
480 // NULL is ok because it will be relocated later.
481 // Must change NULL to a reachable address in order to
482 // pass asserts here and in wdisp.
483 if ( d == NULL )
484 d = pc();
485
486 // Is this address within range of the call instruction?
487 // If not, use the expensive instruction sequence
488 disp = (intptr_t)d - (intptr_t)pc();
489 if ( disp != (intptr_t)(int32_t)disp ) {
490 relocate(rt);
491 Address dest(O7, (address)d);
492 sethi(dest, /*ForceRelocatable=*/ true);
493 jmpl(dest, O7);
494 }
495 else {
496 Assembler::call( d, rt );
497 }
498 #else
499 Assembler::call( d, rt );
500 #endif
501 }
502
503 inline void MacroAssembler::call( Label& L, relocInfo::relocType rt ) {
504 MacroAssembler::call( target(L), rt);
505 }
506
507
508
509 inline void MacroAssembler::callr( Register s1, Register s2 ) { jmpl( s1, s2, O7 ); }
510 inline void MacroAssembler::callr( Register s1, int simm13a, RelocationHolder const& rspec ) { jmpl( s1, simm13a, O7, rspec); }
511
512 // prefetch instruction
513 inline void MacroAssembler::iprefetch( address d, relocInfo::relocType rt ) {
514 if (VM_Version::v9_instructions_work())
515 Assembler::bp( never, true, xcc, pt, d, rt );
516 }
517 inline void MacroAssembler::iprefetch( Label& L) { iprefetch( target(L) ); }
518
519
520 // clobbers o7 on V8!!
521 // returns delta from gotten pc to addr after
522 inline int MacroAssembler::get_pc( Register d ) {
523 int x = offset();
524 if (VM_Version::v9_instructions_work())
525 rdpc(d);
526 else {
527 Label lbl;
528 Assembler::call(lbl, relocInfo::none); // No relocation as this is call to pc+0x8
529 if (d == O7) delayed()->nop();
530 else delayed()->mov(O7, d);
531 bind(lbl);
532 }
533 return offset() - x;
534 }
535
536
537 // Note: All MacroAssembler::set_foo functions are defined out-of-line.
538
539
540 // Loads the current PC of the following instruction as an immediate value in
541 // 2 instructions. All PCs in the CodeCache are within 2 Gig of each other.
542 inline intptr_t MacroAssembler::load_pc_address( Register reg, int bytes_to_skip ) {
543 intptr_t thepc = (intptr_t)pc() + 2*BytesPerInstWord + bytes_to_skip;
544 #ifdef _LP64
545 Unimplemented();
546 #else
547 Assembler::sethi( thepc & ~0x3ff, reg, internal_word_Relocation::spec((address)thepc));
548 Assembler::add(reg,thepc & 0x3ff, reg, internal_word_Relocation::spec((address)thepc));
549 #endif
550 return thepc;
551 }
552
553 inline void MacroAssembler::load_address( Address& a, int offset ) {
554 assert_not_delayed();
555 #ifdef _LP64
556 sethi(a);
557 add(a, a.base(), offset);
558 #else
559 if (a.hi() == 0 && a.rtype() == relocInfo::none) {
560 set(a.disp() + offset, a.base());
561 }
562 else {
563 sethi(a);
564 add(a, a.base(), offset);
565 }
566 #endif
567 }
568
569
570 inline void MacroAssembler::split_disp( Address& a, Register temp ) {
571 assert_not_delayed();
572 a = a.split_disp();
573 Assembler::sethi(a.hi(), temp, a.rspec());
574 add(a.base(), temp, a.base());
575 }
576
577
578 inline void MacroAssembler::load_contents( Address& a, Register d, int offset ) {
579 assert_not_delayed();
580 sethi(a);
581 ld(a, d, offset);
582 }
583
584
585 inline void MacroAssembler::load_ptr_contents( Address& a, Register d, int offset ) {
586 assert_not_delayed();
587 sethi(a);
588 ld_ptr(a, d, offset);
589 }
590
591
592 inline void MacroAssembler::store_contents( Register s, Address& a, int offset ) {
593 assert_not_delayed();
594 sethi(a);
595 st(s, a, offset);
596 }
597
598
599 inline void MacroAssembler::store_ptr_contents( Register s, Address& a, int offset ) {
600 assert_not_delayed();
601 sethi(a);
602 st_ptr(s, a, offset);
603 }
604
605
606 // This code sequence is relocatable to any address, even on LP64.
607 inline void MacroAssembler::jumpl_to( Address& a, Register d, int offset ) {
608 assert_not_delayed();
609 // Force fixed length sethi because NativeJump and NativeFarCall don't handle
610 // variable length instruction streams.
611 sethi(a, /*ForceRelocatable=*/ true);
612 jmpl(a, d, offset);
613 }
614
615
616 inline void MacroAssembler::jump_to( Address& a, int offset ) {
617 jumpl_to( a, G0, offset );
618 }
619
620
621 inline void MacroAssembler::jump_indirect_to( Address& a, Register temp,
622 int ld_offset, int jmp_offset ) {
623 assert_not_delayed();
624 //sethi(a); // sethi is caller responsibility for this one
625 ld_ptr(a, temp, ld_offset);
626 jmp(temp, jmp_offset);
627 }
628
629
630 inline void MacroAssembler::set_oop( jobject obj, Register d ) {
631 set_oop(allocate_oop_address(obj, d));
632 }
633
634
635 inline void MacroAssembler::set_oop_constant( jobject obj, Register d ) {
636 set_oop(constant_oop_address(obj, d));
637 }
638
639
640 inline void MacroAssembler::set_oop( Address obj_addr ) {
641 assert(obj_addr.rspec().type()==relocInfo::oop_type, "must be an oop reloc");
642 load_address(obj_addr);
643 }
644
645
646 inline void MacroAssembler::load_argument( Argument& a, Register d ) {
647 if (a.is_register())
648 mov(a.as_register(), d);
649 else
650 ld (a.as_address(), d);
651 }
652
653 inline void MacroAssembler::store_argument( Register s, Argument& a ) {
654 if (a.is_register())
655 mov(s, a.as_register());
656 else
657 st_ptr (s, a.as_address()); // ABI says everything is right justified.
658 }
659
660 inline void MacroAssembler::store_ptr_argument( Register s, Argument& a ) {
661 if (a.is_register())
662 mov(s, a.as_register());
663 else
664 st_ptr (s, a.as_address());
665 }
666
667
668 #ifdef _LP64
669 inline void MacroAssembler::store_float_argument( FloatRegister s, Argument& a ) {
670 if (a.is_float_register())
671 // V9 ABI has F1, F3, F5 are used to pass instead of O0, O1, O2
672 fmov(FloatRegisterImpl::S, s, a.as_float_register() );
673 else
674 // Floats are stored in the high half of the stack entry
675 // The low half is undefined per the ABI.
676 stf(FloatRegisterImpl::S, s, a.as_address(), sizeof(jfloat));
677 }
678
679 inline void MacroAssembler::store_double_argument( FloatRegister s, Argument& a ) {
680 if (a.is_float_register())
681 // V9 ABI has D0, D2, D4 are used to pass instead of O0, O1, O2
682 fmov(FloatRegisterImpl::D, s, a.as_double_register() );
683 else
684 stf(FloatRegisterImpl::D, s, a.as_address());
685 }
686
687 inline void MacroAssembler::store_long_argument( Register s, Argument& a ) {
688 if (a.is_register())
689 mov(s, a.as_register());
690 else
691 stx(s, a.as_address());
692 }
693 #endif
694
695 inline void MacroAssembler::clrb( Register s1, Register s2) { stb( G0, s1, s2 ); }
696 inline void MacroAssembler::clrh( Register s1, Register s2) { sth( G0, s1, s2 ); }
697 inline void MacroAssembler::clr( Register s1, Register s2) { stw( G0, s1, s2 ); }
698 inline void MacroAssembler::clrx( Register s1, Register s2) { stx( G0, s1, s2 ); }
699
700 inline void MacroAssembler::clrb( Register s1, int simm13a) { stb( G0, s1, simm13a); }
701 inline void MacroAssembler::clrh( Register s1, int simm13a) { sth( G0, s1, simm13a); }
702 inline void MacroAssembler::clr( Register s1, int simm13a) { stw( G0, s1, simm13a); }
703 inline void MacroAssembler::clrx( Register s1, int simm13a) { stx( G0, s1, simm13a); }
704
705 // returns if membar generates anything, obviously this code should mirror
706 // membar below.
707 inline bool MacroAssembler::membar_has_effect( Membar_mask_bits const7a ) {
708 if( !os::is_MP() ) return false; // Not needed on single CPU
709 if( VM_Version::v9_instructions_work() ) {
710 const Membar_mask_bits effective_mask =
711 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
712 return (effective_mask != 0);
713 } else {
714 return true;
715 }
716 }
717
718 inline void MacroAssembler::membar( Membar_mask_bits const7a ) {
719 // Uniprocessors do not need memory barriers
720 if (!os::is_MP()) return;
721 // Weakened for current Sparcs and TSO. See the v9 manual, sections 8.4.3,
722 // 8.4.4.3, a.31 and a.50.
723 if( VM_Version::v9_instructions_work() ) {
724 // Under TSO, setting bit 3, 2, or 0 is redundant, so the only value
725 // of the mmask subfield of const7a that does anything that isn't done
726 // implicitly is StoreLoad.
727 const Membar_mask_bits effective_mask =
728 Membar_mask_bits(const7a & ~(LoadLoad | LoadStore | StoreStore));
729 if ( effective_mask != 0 ) {
730 Assembler::membar( effective_mask );
731 }
732 } else {
733 // stbar is the closest there is on v8. Equivalent to membar(StoreStore). We
734 // do not issue the stbar because to my knowledge all v8 machines implement TSO,
735 // which guarantees that all stores behave as if an stbar were issued just after
736 // each one of them. On these machines, stbar ought to be a nop. There doesn't
737 // appear to be an equivalent of membar(StoreLoad) on v8: TSO doesn't require it,
738 // it can't be specified by stbar, nor have I come up with a way to simulate it.
739 //
740 // Addendum. Dave says that ldstub guarantees a write buffer flush to coherent
741 // space. Put one here to be on the safe side.
742 Assembler::ldstub(SP, 0, G0);
743 }
744 }