67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
68 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
69
70 // The following globals are used for the new C1 & interpreter calling convention:
71 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
72
73 // This local is used to preserve G2_thread in the interpreter and in stubs:
74 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
75
76 // These globals are used as scratch registers in the interpreter:
77
78 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
79 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
80 REGISTER_DECLARATION(Register, G3_scratch , G3);
81 REGISTER_DECLARATION(Register, G4_scratch , G4);
82
83 // These globals are used as short-lived scratch registers in the compiler:
84
85 REGISTER_DECLARATION(Register, Gtemp , G5);
86
87 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
88 // because a single patchable "set" instruction (NativeMovConstReg,
89 // or NativeMovConstPatching for compiler1) instruction
90 // serves to set up either quantity, depending on whether the compiled
91 // call site is an inline cache or is megamorphic. See the function
92 // CompiledIC::set_to_megamorphic.
93 //
94 // On the other hand, G5_inline_cache_klass must differ from G5_method,
95 // because both registers are needed for an inline cache that calls
96 // an interpreted method.
97 //
98 // Note that G5_method is only the method-self for the interpreter,
99 // and is logically unrelated to G5_megamorphic_method.
100 //
101 // Invariants on G2_thread (the JavaThread pointer):
102 // - it should not be used for any other purpose anywhere
103 // - it must be re-initialized by StubRoutines::call_stub()
104 // - it must be preserved around every use of call_VM
105
106 // We can consider using g2/g3/g4 to cache more values than the
107 // JavaThread, such as the card-marking base or perhaps pointers into
108 // Eden. It's something of a waste to use them as scratch temporaries,
109 // since they are not supposed to be volatile. (Of course, if we find
110 // that Java doesn't benefit from application globals, then we can just
111 // use them as ordinary temporaries.)
112 //
113 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
114 // it makes sense to use them routinely for procedure linkage,
115 // whenever the On registers are not applicable. Examples: G5_method,
116 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
242 #define Lmonitors AS_REGISTER(Register, Lmonitors)
243 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
244 #define Lscratch AS_REGISTER(Register, Lscratch)
245 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
246 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
247 #endif /* ! CC_INTERP */
248
249 #define Lentry_args AS_REGISTER(Register, Lentry_args)
250 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
251 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
252 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
253 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
254 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
255
256 #define Oexception AS_REGISTER(Register, Oexception)
257 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
258
259
260 #endif
261
262 // Address is an abstraction used to represent a memory location.
263 //
264 // Note: A register location is represented via a Register, not
265 // via an address for efficiency & simplicity reasons.
266
267 class Address VALUE_OBJ_CLASS_SPEC {
268 private:
269 Register _base;
270 #ifdef _LP64
271 int _hi32; // bits 63::32
272 int _low32; // bits 31::0
273 #endif
274 int _hi;
275 int _disp;
276 RelocationHolder _rspec;
277
278 RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {
279 switch (rt) {
280 case relocInfo::external_word_type:
281 return external_word_Relocation::spec(a);
1065 #endif
1066 AbstractAssembler::flush();
1067 }
1068
1069 inline void emit_long(int); // shadows AbstractAssembler::emit_long
1070 inline void emit_data(int x) { emit_long(x); }
1071 inline void emit_data(int, RelocationHolder const&);
1072 inline void emit_data(int, relocInfo::relocType rtype);
1073 // helper for above fcns
1074 inline void check_delay();
1075
1076
1077 public:
1078 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1079
1080 // pp 135 (addc was addx in v8)
1081
1082 inline void add( Register s1, Register s2, Register d );
1083 inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1084 inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1085 inline void add( const Address& a, Register d, int offset = 0);
1086
1087 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1088 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1089 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1090 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1091 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1092 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1093
1094 // pp 136
1095
1096 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1097 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1098
1099 protected: // use MacroAssembler::br instead
1100
1101 // pp 138
1102
1103 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1104 inline void fb( Condition c, bool a, Label& L );
1105
1106 // pp 141
1281 inline void lduh( Register s1, int simm13a, Register d);
1282 inline void lduw( Register s1, Register s2, Register d );
1283 inline void lduw( Register s1, int simm13a, Register d);
1284 inline void ldx( Register s1, Register s2, Register d );
1285 inline void ldx( Register s1, int simm13a, Register d);
1286 inline void ld( Register s1, Register s2, Register d );
1287 inline void ld( Register s1, int simm13a, Register d);
1288 inline void ldd( Register s1, Register s2, Register d );
1289 inline void ldd( Register s1, int simm13a, Register d);
1290
1291 inline void ldsb( const Address& a, Register d, int offset = 0 );
1292 inline void ldsh( const Address& a, Register d, int offset = 0 );
1293 inline void ldsw( const Address& a, Register d, int offset = 0 );
1294 inline void ldub( const Address& a, Register d, int offset = 0 );
1295 inline void lduh( const Address& a, Register d, int offset = 0 );
1296 inline void lduw( const Address& a, Register d, int offset = 0 );
1297 inline void ldx( const Address& a, Register d, int offset = 0 );
1298 inline void ld( const Address& a, Register d, int offset = 0 );
1299 inline void ldd( const Address& a, Register d, int offset = 0 );
1300
1301 // pp 177
1302
1303 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1304 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1305 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1306 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1307 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1308 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1309 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1310 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1311 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1312 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1313 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1314 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1315 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1316 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1317 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1318 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1319
1320 // pp 179
1501 inline void stb( Register d, Register s1, Register s2 );
1502 inline void stb( Register d, Register s1, int simm13a);
1503 inline void sth( Register d, Register s1, Register s2 );
1504 inline void sth( Register d, Register s1, int simm13a);
1505 inline void stw( Register d, Register s1, Register s2 );
1506 inline void stw( Register d, Register s1, int simm13a);
1507 inline void st( Register d, Register s1, Register s2 );
1508 inline void st( Register d, Register s1, int simm13a);
1509 inline void stx( Register d, Register s1, Register s2 );
1510 inline void stx( Register d, Register s1, int simm13a);
1511 inline void std( Register d, Register s1, Register s2 );
1512 inline void std( Register d, Register s1, int simm13a);
1513
1514 inline void stb( Register d, const Address& a, int offset = 0 );
1515 inline void sth( Register d, const Address& a, int offset = 0 );
1516 inline void stw( Register d, const Address& a, int offset = 0 );
1517 inline void stx( Register d, const Address& a, int offset = 0 );
1518 inline void st( Register d, const Address& a, int offset = 0 );
1519 inline void std( Register d, const Address& a, int offset = 0 );
1520
1521 // pp 177
1522
1523 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1524 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1525 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1526 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1527 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1528 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1529 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1530 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1531 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1532 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1533
1534 // pp 97 (v8)
1535
1536 inline void stc( int crd, Register s1, Register s2 );
1537 inline void stc( int crd, Register s1, int simm13a);
1538 inline void stdc( int crd, Register s1, Register s2 );
1539 inline void stdc( int crd, Register s1, int simm13a);
1540 inline void stcsr( int crd, Register s1, Register s2 );
1889 else assert_not_delayed(); // Put something useful in the delay slot!
1890 }
1891
1892 inline void mov_or_nop( Register s, Register d) {
1893 if ( s != d ) or3( G0, s, d);
1894 else nop();
1895 }
1896
1897 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1898
1899 // address pseudos: make these names unlike instruction names to avoid confusion
1900 inline void split_disp( Address& a, Register temp );
1901 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1902 inline void load_address( Address& a, int offset = 0 );
1903 inline void load_contents( Address& a, Register d, int offset = 0 );
1904 inline void load_ptr_contents( Address& a, Register d, int offset = 0 );
1905 inline void store_contents( Register s, Address& a, int offset = 0 );
1906 inline void store_ptr_contents( Register s, Address& a, int offset = 0 );
1907 inline void jumpl_to( Address& a, Register d, int offset = 0 );
1908 inline void jump_to( Address& a, int offset = 0 );
1909
1910 // ring buffer traceable jumps
1911
1912 void jmp2( Register r1, Register r2, const char* file, int line );
1913 void jmp ( Register r1, int offset, const char* file, int line );
1914
1915 void jumpl( Address& a, Register d, int offset, const char* file, int line );
1916 void jump ( Address& a, int offset, const char* file, int line );
1917
1918
1919 // argument pseudos:
1920
1921 inline void load_argument( Argument& a, Register d );
1922 inline void store_argument( Register s, Argument& a );
1923 inline void store_ptr_argument( Register s, Argument& a );
1924 inline void store_float_argument( FloatRegister s, Argument& a );
1925 inline void store_double_argument( FloatRegister s, Argument& a );
1926 inline void store_long_argument( Register s, Argument& a );
1927
1928 // handy macros:
1929
1930 inline void round_to( Register r, int modulus ) {
1931 assert_not_delayed();
1932 inc( r, modulus - 1 );
1933 and3( r, -modulus, r );
1934 }
1935
1936 // --------------------------------------------------
1937
1938 // Functions for isolating 64 bit loads for LP64
1939 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
1940 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
1941 inline void ld_ptr( Register s1, Register s2, Register d );
1942 inline void ld_ptr( Register s1, int simm13a, Register d);
1943 inline void ld_ptr( const Address& a, Register d, int offset = 0 );
1944 inline void st_ptr( Register d, Register s1, Register s2 );
1945 inline void st_ptr( Register d, Register s1, int simm13a);
1946 inline void st_ptr( Register d, const Address& a, int offset = 0 );
1947
1948 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
1949 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
1950 inline void ld_long( Register s1, Register s2, Register d );
1951 inline void ld_long( Register s1, int simm13a, Register d );
1952 inline void ld_long( const Address& a, Register d, int offset = 0 );
1953 inline void st_long( Register d, Register s1, Register s2 );
1954 inline void st_long( Register d, Register s1, int simm13a );
1955 inline void st_long( Register d, const Address& a, int offset = 0 );
1956
1957 // --------------------------------------------------
1958
1959 public:
1960 // traps as per trap.h (SPARC ABI?)
1961
1962 void breakpoint_trap();
1963 void breakpoint_trap(Condition c, CC cc = icc);
1964 void flush_windows_trap();
1965 void clean_windows_trap();
2250 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2251
2252 // allocation
2253 void eden_allocate(
2254 Register obj, // result: pointer to object after successful allocation
2255 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2256 int con_size_in_bytes, // object size in bytes if known at compile time
2257 Register t1, // temp register
2258 Register t2, // temp register
2259 Label& slow_case // continuation point if fast allocation fails
2260 );
2261 void tlab_allocate(
2262 Register obj, // result: pointer to object after successful allocation
2263 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2264 int con_size_in_bytes, // object size in bytes if known at compile time
2265 Register t1, // temp register
2266 Label& slow_case // continuation point if fast allocation fails
2267 );
2268 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2269
2270 // Stack overflow checking
2271
2272 // Note: this clobbers G3_scratch
2273 void bang_stack_with_offset(int offset) {
2274 // stack grows down, caller passes positive offset
2275 assert(offset > 0, "must bang with negative offset");
2276 set((-offset)+STACK_BIAS, G3_scratch);
2277 st(G0, SP, G3_scratch);
2278 }
2279
2280 // Writes to stack successive pages until offset reached to check for
2281 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2282 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2283
2284 void verify_tlab();
2285
2286 Condition negate_condition(Condition cond);
2287
2288 // Helper functions for statistics gathering.
2289 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
|
67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
68 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
69
70 // The following globals are used for the new C1 & interpreter calling convention:
71 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
72
73 // This local is used to preserve G2_thread in the interpreter and in stubs:
74 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
75
76 // These globals are used as scratch registers in the interpreter:
77
78 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
79 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
80 REGISTER_DECLARATION(Register, G3_scratch , G3);
81 REGISTER_DECLARATION(Register, G4_scratch , G4);
82
83 // These globals are used as short-lived scratch registers in the compiler:
84
85 REGISTER_DECLARATION(Register, Gtemp , G5);
86
87 // JSR 292 fixed register usages:
88 REGISTER_DECLARATION(Register, G5_method_type , G5);
89 REGISTER_DECLARATION(Register, G3_method_handle , G3);
90
91 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
92 // because a single patchable "set" instruction (NativeMovConstReg,
93 // or NativeMovConstPatching for compiler1) instruction
94 // serves to set up either quantity, depending on whether the compiled
95 // call site is an inline cache or is megamorphic. See the function
96 // CompiledIC::set_to_megamorphic.
97 //
98 // If a inline cache targets an interpreted method, then the
99 // G5 register will be used twice during the call. First,
100 // the call site will be patched to load a compiledICHolder
101 // into G5. (This is an ordered pair of ic_klass, method.)
102 // The c2i adapter will first check the ic_klass, then load
103 // G5_method with the method part of the pair just before
104 // jumping into the interpreter.
105 //
106 // Note that G5_method is only the method-self for the interpreter,
107 // and is logically unrelated to G5_megamorphic_method.
108 //
109 // Invariants on G2_thread (the JavaThread pointer):
110 // - it should not be used for any other purpose anywhere
111 // - it must be re-initialized by StubRoutines::call_stub()
112 // - it must be preserved around every use of call_VM
113
114 // We can consider using g2/g3/g4 to cache more values than the
115 // JavaThread, such as the card-marking base or perhaps pointers into
116 // Eden. It's something of a waste to use them as scratch temporaries,
117 // since they are not supposed to be volatile. (Of course, if we find
118 // that Java doesn't benefit from application globals, then we can just
119 // use them as ordinary temporaries.)
120 //
121 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
122 // it makes sense to use them routinely for procedure linkage,
123 // whenever the On registers are not applicable. Examples: G5_method,
124 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
250 #define Lmonitors AS_REGISTER(Register, Lmonitors)
251 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
252 #define Lscratch AS_REGISTER(Register, Lscratch)
253 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
254 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
255 #endif /* ! CC_INTERP */
256
257 #define Lentry_args AS_REGISTER(Register, Lentry_args)
258 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
259 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
260 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
261 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
262 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
263
264 #define Oexception AS_REGISTER(Register, Oexception)
265 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
266
267
268 #endif
269
270 // A union type for code which has to assemble both constant and non-constant operands.
271 class RegisterConstant VALUE_OBJ_CLASS_SPEC {
272 private:
273 Register _r;
274 intptr_t _c;
275
276 public:
277 RegisterConstant(): _r(noreg), _c(0) {}
278 RegisterConstant(Register r): _r(r), _c(0) {}
279 RegisterConstant(intptr_t c): _r(noreg), _c(c) {}
280
281 Register as_register() const { assert(is_register(),""); return _r; }
282 intptr_t as_constant() const { assert(is_constant(),""); return _c; }
283
284 Register register_or_noreg() const { return _r; }
285 intptr_t constant_or_zero() const { return _c; }
286
287 bool is_register() const { return _r != noreg; }
288 bool is_constant() const { return _r == noreg; }
289 };
290
291 // Address is an abstraction used to represent a memory location.
292 //
293 // Note: A register location is represented via a Register, not
294 // via an address for efficiency & simplicity reasons.
295
296 class Address VALUE_OBJ_CLASS_SPEC {
297 private:
298 Register _base;
299 #ifdef _LP64
300 int _hi32; // bits 63::32
301 int _low32; // bits 31::0
302 #endif
303 int _hi;
304 int _disp;
305 RelocationHolder _rspec;
306
307 RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {
308 switch (rt) {
309 case relocInfo::external_word_type:
310 return external_word_Relocation::spec(a);
1094 #endif
1095 AbstractAssembler::flush();
1096 }
1097
1098 inline void emit_long(int); // shadows AbstractAssembler::emit_long
1099 inline void emit_data(int x) { emit_long(x); }
1100 inline void emit_data(int, RelocationHolder const&);
1101 inline void emit_data(int, relocInfo::relocType rtype);
1102 // helper for above fcns
1103 inline void check_delay();
1104
1105
1106 public:
1107 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1108
1109 // pp 135 (addc was addx in v8)
1110
1111 inline void add( Register s1, Register s2, Register d );
1112 inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1113 inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1114 inline void add( Register s1, RegisterConstant s2, Register d, int offset = 0);
1115 inline void add( const Address& a, Register d, int offset = 0);
1116
1117
1118 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1119 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1120 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1121 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1122 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1123 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1124
1125 // pp 136
1126
1127 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1128 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1129
1130 protected: // use MacroAssembler::br instead
1131
1132 // pp 138
1133
1134 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1135 inline void fb( Condition c, bool a, Label& L );
1136
1137 // pp 141
1312 inline void lduh( Register s1, int simm13a, Register d);
1313 inline void lduw( Register s1, Register s2, Register d );
1314 inline void lduw( Register s1, int simm13a, Register d);
1315 inline void ldx( Register s1, Register s2, Register d );
1316 inline void ldx( Register s1, int simm13a, Register d);
1317 inline void ld( Register s1, Register s2, Register d );
1318 inline void ld( Register s1, int simm13a, Register d);
1319 inline void ldd( Register s1, Register s2, Register d );
1320 inline void ldd( Register s1, int simm13a, Register d);
1321
1322 inline void ldsb( const Address& a, Register d, int offset = 0 );
1323 inline void ldsh( const Address& a, Register d, int offset = 0 );
1324 inline void ldsw( const Address& a, Register d, int offset = 0 );
1325 inline void ldub( const Address& a, Register d, int offset = 0 );
1326 inline void lduh( const Address& a, Register d, int offset = 0 );
1327 inline void lduw( const Address& a, Register d, int offset = 0 );
1328 inline void ldx( const Address& a, Register d, int offset = 0 );
1329 inline void ld( const Address& a, Register d, int offset = 0 );
1330 inline void ldd( const Address& a, Register d, int offset = 0 );
1331
1332 inline void ld( Register s1, RegisterConstant s2, Register d );
1333 inline void lduw( Register s1, RegisterConstant s2, Register d );
1334 inline void ldsw( Register s1, RegisterConstant s2, Register d );
1335 inline void ldx( Register s1, RegisterConstant s2, Register d );
1336
1337 // pp 177
1338
1339 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1340 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1341 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1342 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1343 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1344 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1345 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1346 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1347 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1348 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1349 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1350 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1351 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1352 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1353 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1354 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1355
1356 // pp 179
1537 inline void stb( Register d, Register s1, Register s2 );
1538 inline void stb( Register d, Register s1, int simm13a);
1539 inline void sth( Register d, Register s1, Register s2 );
1540 inline void sth( Register d, Register s1, int simm13a);
1541 inline void stw( Register d, Register s1, Register s2 );
1542 inline void stw( Register d, Register s1, int simm13a);
1543 inline void st( Register d, Register s1, Register s2 );
1544 inline void st( Register d, Register s1, int simm13a);
1545 inline void stx( Register d, Register s1, Register s2 );
1546 inline void stx( Register d, Register s1, int simm13a);
1547 inline void std( Register d, Register s1, Register s2 );
1548 inline void std( Register d, Register s1, int simm13a);
1549
1550 inline void stb( Register d, const Address& a, int offset = 0 );
1551 inline void sth( Register d, const Address& a, int offset = 0 );
1552 inline void stw( Register d, const Address& a, int offset = 0 );
1553 inline void stx( Register d, const Address& a, int offset = 0 );
1554 inline void st( Register d, const Address& a, int offset = 0 );
1555 inline void std( Register d, const Address& a, int offset = 0 );
1556
1557 inline void st( Register d, Register s1, RegisterConstant s2 );
1558 inline void stx( Register d, Register s1, RegisterConstant s2 );
1559
1560 // pp 177
1561
1562 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1563 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1564 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1565 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1566 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1567 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1568 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1569 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1570 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1571 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1572
1573 // pp 97 (v8)
1574
1575 inline void stc( int crd, Register s1, Register s2 );
1576 inline void stc( int crd, Register s1, int simm13a);
1577 inline void stdc( int crd, Register s1, Register s2 );
1578 inline void stdc( int crd, Register s1, int simm13a);
1579 inline void stcsr( int crd, Register s1, Register s2 );
1928 else assert_not_delayed(); // Put something useful in the delay slot!
1929 }
1930
1931 inline void mov_or_nop( Register s, Register d) {
1932 if ( s != d ) or3( G0, s, d);
1933 else nop();
1934 }
1935
1936 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1937
1938 // address pseudos: make these names unlike instruction names to avoid confusion
1939 inline void split_disp( Address& a, Register temp );
1940 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1941 inline void load_address( Address& a, int offset = 0 );
1942 inline void load_contents( Address& a, Register d, int offset = 0 );
1943 inline void load_ptr_contents( Address& a, Register d, int offset = 0 );
1944 inline void store_contents( Register s, Address& a, int offset = 0 );
1945 inline void store_ptr_contents( Register s, Address& a, int offset = 0 );
1946 inline void jumpl_to( Address& a, Register d, int offset = 0 );
1947 inline void jump_to( Address& a, int offset = 0 );
1948 inline void jump_indirect_to( Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0 );
1949
1950 // ring buffer traceable jumps
1951
1952 void jmp2( Register r1, Register r2, const char* file, int line );
1953 void jmp ( Register r1, int offset, const char* file, int line );
1954
1955 void jumpl( Address& a, Register d, int offset, const char* file, int line );
1956 void jump ( Address& a, int offset, const char* file, int line );
1957
1958
1959 // argument pseudos:
1960
1961 inline void load_argument( Argument& a, Register d );
1962 inline void store_argument( Register s, Argument& a );
1963 inline void store_ptr_argument( Register s, Argument& a );
1964 inline void store_float_argument( FloatRegister s, Argument& a );
1965 inline void store_double_argument( FloatRegister s, Argument& a );
1966 inline void store_long_argument( Register s, Argument& a );
1967
1968 // handy macros:
1969
1970 inline void round_to( Register r, int modulus ) {
1971 assert_not_delayed();
1972 inc( r, modulus - 1 );
1973 and3( r, -modulus, r );
1974 }
1975
1976 // --------------------------------------------------
1977
1978 // Functions for isolating 64 bit loads for LP64
1979 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
1980 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
1981 inline void ld_ptr( Register s1, Register s2, Register d );
1982 inline void ld_ptr( Register s1, int simm13a, Register d);
1983 inline void ld_ptr( Register s1, RegisterConstant s2, Register d );
1984 inline void ld_ptr( const Address& a, Register d, int offset = 0 );
1985 inline void st_ptr( Register d, Register s1, Register s2 );
1986 inline void st_ptr( Register d, Register s1, int simm13a);
1987 inline void st_ptr( Register d, Register s1, RegisterConstant s2 );
1988 inline void st_ptr( Register d, const Address& a, int offset = 0 );
1989
1990 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
1991 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
1992 inline void ld_long( Register s1, Register s2, Register d );
1993 inline void ld_long( Register s1, int simm13a, Register d );
1994 inline void ld_long( const Address& a, Register d, int offset = 0 );
1995 inline void st_long( Register d, Register s1, Register s2 );
1996 inline void st_long( Register d, Register s1, int simm13a );
1997 inline void st_long( Register d, const Address& a, int offset = 0 );
1998
1999 // --------------------------------------------------
2000
2001 public:
2002 // traps as per trap.h (SPARC ABI?)
2003
2004 void breakpoint_trap();
2005 void breakpoint_trap(Condition c, CC cc = icc);
2006 void flush_windows_trap();
2007 void clean_windows_trap();
2292 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2293
2294 // allocation
2295 void eden_allocate(
2296 Register obj, // result: pointer to object after successful allocation
2297 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2298 int con_size_in_bytes, // object size in bytes if known at compile time
2299 Register t1, // temp register
2300 Register t2, // temp register
2301 Label& slow_case // continuation point if fast allocation fails
2302 );
2303 void tlab_allocate(
2304 Register obj, // result: pointer to object after successful allocation
2305 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2306 int con_size_in_bytes, // object size in bytes if known at compile time
2307 Register t1, // temp register
2308 Label& slow_case // continuation point if fast allocation fails
2309 );
2310 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2311
2312 // small bootstrap problems
2313 RegisterConstant delayed_value(intptr_t* delayed_value_addr, Register tmp,
2314 int offset = 0);
2315 RegisterConstant delayed_value(int(*value_fn)(), Register tmp,
2316 int offset = 0) {
2317 return delayed_value(delayed_value_addr(value_fn), tmp, offset);
2318 }
2319 RegisterConstant delayed_value(address(*value_fn)(), Register tmp,
2320 int offset = 0) {
2321 return delayed_value((intptr_t*) delayed_value_addr(value_fn), tmp, offset);
2322 }
2323
2324 // interface method calling
2325 void lookup_interface_method(Register recv_klass,
2326 Register intf_klass,
2327 RegisterConstant itable_index,
2328 Register method_result,
2329 Register scan_temp,
2330 Label& no_such_interface);
2331
2332 // method handles (JSR 292)
2333 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2334 Register temp_reg,
2335 Label& wrong_method_type);
2336 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2337 // offset relative to Gargs of argument at tos[arg_slot].
2338 // (arg_slot == 0 means the last argument, not the first).
2339 RegisterConstant argument_offset(RegisterConstant arg_slot,
2340 int extra_slot_offset = 0);
2341
2342 // klass type checking (falls through on failure)
2343 void check_klass_subtype(Register sub_klass,
2344 Register super_klass,
2345 Register temp_reg,
2346 Label& L_success);
2347
2348
2349 // Stack overflow checking
2350
2351 // Note: this clobbers G3_scratch
2352 void bang_stack_with_offset(int offset) {
2353 // stack grows down, caller passes positive offset
2354 assert(offset > 0, "must bang with negative offset");
2355 set((-offset)+STACK_BIAS, G3_scratch);
2356 st(G0, SP, G3_scratch);
2357 }
2358
2359 // Writes to stack successive pages until offset reached to check for
2360 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2361 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2362
2363 void verify_tlab();
2364
2365 Condition negate_condition(Condition cond);
2366
2367 // Helper functions for statistics gathering.
2368 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
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