1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // <sys/trap.h> promises that the system will not use traps 16-31
28 #define ST_RESERVED_FOR_USER_0 0x10
29
30 /* Written: David Ungar 4/19/97 */
31
32 // Contains all the definitions needed for sparc assembly code generation.
33
34 // Register aliases for parts of the system:
35
36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
37 // across context switches in V8+ ABI. Of course, there are no 64 bit regs
38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
39
40 // g2-g4 are scratch registers called "application globals". Their
41 // meaning is reserved to the "compilation system"--which means us!
42 // They are are not supposed to be touched by ordinary C code, although
43 // highly-optimized C code might steal them for temps. They are safe
44 // across thread switches, and the ABI requires that they be safe
45 // across function calls.
46 //
47 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
48 // across func calls, and V8+ also allows g5 to be clobbered across
49 // func calls. Also, g1 and g5 can get touched while doing shared
50 // library loading.
51 //
52 // We must not touch g7 (it is the thread-self register) and g6 is
53 // reserved for certain tools. g0, of course, is always zero.
54 //
55 // (Sources: SunSoft Compilers Group, thread library engineers.)
56
57 // %%%% The interpreter should be revisited to reduce global scratch regs.
58
59 // This global always holds the current JavaThread pointer:
60
61 REGISTER_DECLARATION(Register, G2_thread , G2);
62 REGISTER_DECLARATION(Register, G6_heapbase , G6);
63
64 // The following globals are part of the Java calling convention:
65
66 REGISTER_DECLARATION(Register, G5_method , G5);
67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
68 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
69
70 // The following globals are used for the new C1 & interpreter calling convention:
71 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
72
73 // This local is used to preserve G2_thread in the interpreter and in stubs:
74 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
75
76 // These globals are used as scratch registers in the interpreter:
77
78 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
79 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
80 REGISTER_DECLARATION(Register, G3_scratch , G3);
81 REGISTER_DECLARATION(Register, G4_scratch , G4);
82
83 // These globals are used as short-lived scratch registers in the compiler:
84
85 REGISTER_DECLARATION(Register, Gtemp , G5);
86
87 // JSR 292 fixed register usages:
88 REGISTER_DECLARATION(Register, G5_method_type , G5);
89 REGISTER_DECLARATION(Register, G3_method_handle , G3);
90
91 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
92 // because a single patchable "set" instruction (NativeMovConstReg,
93 // or NativeMovConstPatching for compiler1) instruction
94 // serves to set up either quantity, depending on whether the compiled
95 // call site is an inline cache or is megamorphic. See the function
96 // CompiledIC::set_to_megamorphic.
97 //
98 // If a inline cache targets an interpreted method, then the
99 // G5 register will be used twice during the call. First,
100 // the call site will be patched to load a compiledICHolder
101 // into G5. (This is an ordered pair of ic_klass, method.)
102 // The c2i adapter will first check the ic_klass, then load
103 // G5_method with the method part of the pair just before
104 // jumping into the interpreter.
105 //
106 // Note that G5_method is only the method-self for the interpreter,
107 // and is logically unrelated to G5_megamorphic_method.
108 //
109 // Invariants on G2_thread (the JavaThread pointer):
110 // - it should not be used for any other purpose anywhere
111 // - it must be re-initialized by StubRoutines::call_stub()
112 // - it must be preserved around every use of call_VM
113
114 // We can consider using g2/g3/g4 to cache more values than the
115 // JavaThread, such as the card-marking base or perhaps pointers into
116 // Eden. It's something of a waste to use them as scratch temporaries,
117 // since they are not supposed to be volatile. (Of course, if we find
118 // that Java doesn't benefit from application globals, then we can just
119 // use them as ordinary temporaries.)
120 //
121 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
122 // it makes sense to use them routinely for procedure linkage,
123 // whenever the On registers are not applicable. Examples: G5_method,
124 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
125 // stubs. This means that compiler stubs, etc., should be kept to a
126 // maximum of two or three G-register arguments.
127
128
129 // stub frames
130
131 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
132
133 // Interpreter frames
134
135 #ifdef CC_INTERP
136 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
137 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
138 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
139 REGISTER_DECLARATION(Register, L2_scratch , L2);
140 REGISTER_DECLARATION(Register, L3_scratch , L3);
141 REGISTER_DECLARATION(Register, L4_scratch , L4);
142 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
143 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
144 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
145 REGISTER_DECLARATION(Register, O5_savedSP , O5);
146 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
147 // a copy SP, so in 64-bit it's a biased value. The bias
148 // is added and removed as needed in the frame code.
149 // Interface to signature handler
150 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
151 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
152
153 #else
154 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
155 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
156 REGISTER_DECLARATION(Register, Lmethod , L2);
157 REGISTER_DECLARATION(Register, Llocals , L3);
158 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
159 // must match Llocals in asm interpreter
160 REGISTER_DECLARATION(Register, Lmonitors , L4);
161 REGISTER_DECLARATION(Register, Lbyte_code , L5);
162 // When calling out from the interpreter we record SP so that we can remove any extra stack
163 // space allocated during adapter transitions. This register is only live from the point
164 // of the call until we return.
165 REGISTER_DECLARATION(Register, Llast_SP , L5);
166 REGISTER_DECLARATION(Register, Lscratch , L5);
167 REGISTER_DECLARATION(Register, Lscratch2 , L6);
168 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
169
170 REGISTER_DECLARATION(Register, O5_savedSP , O5);
171 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
172 // a copy SP, so in 64-bit it's a biased value. The bias
173 // is added and removed as needed in the frame code.
174 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
175 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
176 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
177 #endif /* CC_INTERP */
178
179 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
180 // the interpreter code. If Lscratch2 needs to be used for some
181 // purpose than LcpoolCache should be restore after that for
182 // the interpreter to work right
183 // (These assignments must be compatible with L7_thread_cache; see above.)
184
185 // Since Lbcp points into the middle of the method object,
186 // it is temporarily converted into a "bcx" during GC.
187
188 // Exception processing
189 // These registers are passed into exception handlers.
190 // All exception handlers require the exception object being thrown.
191 // In addition, an nmethod's exception handler must be passed
192 // the address of the call site within the nmethod, to allow
193 // proper selection of the applicable catch block.
194 // (Interpreter frames use their own bcp() for this purpose.)
195 //
196 // The Oissuing_pc value is not always needed. When jumping to a
197 // handler that is known to be interpreted, the Oissuing_pc value can be
198 // omitted. An actual catch block in compiled code receives (from its
199 // nmethod's exception handler) the thrown exception in the Oexception,
200 // but it doesn't need the Oissuing_pc.
201 //
202 // If an exception handler (either interpreted or compiled)
203 // discovers there is no applicable catch block, it updates
204 // the Oissuing_pc to the continuation PC of its own caller,
205 // pops back to that caller's stack frame, and executes that
206 // caller's exception handler. Obviously, this process will
207 // iterate until the control stack is popped back to a method
208 // containing an applicable catch block. A key invariant is
209 // that the Oissuing_pc value is always a value local to
210 // the method whose exception handler is currently executing.
211 //
212 // Note: The issuing PC value is __not__ a raw return address (I7 value).
213 // It is a "return pc", the address __following__ the call.
214 // Raw return addresses are converted to issuing PCs by frame::pc(),
215 // or by stubs. Issuing PCs can be used directly with PC range tables.
216 //
217 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
218 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
219
220
221 // These must occur after the declarations above
222 #ifndef DONT_USE_REGISTER_DEFINES
223
224 #define Gthread AS_REGISTER(Register, Gthread)
225 #define Gmethod AS_REGISTER(Register, Gmethod)
226 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
227 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
228 #define Gargs AS_REGISTER(Register, Gargs)
229 #define Lthread_cache AS_REGISTER(Register, Lthread_cache)
230 #define Gframe_size AS_REGISTER(Register, Gframe_size)
231 #define Gtemp AS_REGISTER(Register, Gtemp)
232
233 #ifdef CC_INTERP
234 #define Lstate AS_REGISTER(Register, Lstate)
235 #define Lesp AS_REGISTER(Register, Lesp)
236 #define L1_scratch AS_REGISTER(Register, L1_scratch)
237 #define Lmirror AS_REGISTER(Register, Lmirror)
238 #define L2_scratch AS_REGISTER(Register, L2_scratch)
239 #define L3_scratch AS_REGISTER(Register, L3_scratch)
240 #define L4_scratch AS_REGISTER(Register, L4_scratch)
241 #define Lscratch AS_REGISTER(Register, Lscratch)
242 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
243 #define L7_scratch AS_REGISTER(Register, L7_scratch)
244 #define Ostate AS_REGISTER(Register, Ostate)
245 #else
246 #define Lesp AS_REGISTER(Register, Lesp)
247 #define Lbcp AS_REGISTER(Register, Lbcp)
248 #define Lmethod AS_REGISTER(Register, Lmethod)
249 #define Llocals AS_REGISTER(Register, Llocals)
250 #define Lmonitors AS_REGISTER(Register, Lmonitors)
251 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
252 #define Lscratch AS_REGISTER(Register, Lscratch)
253 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
254 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
255 #endif /* ! CC_INTERP */
256
257 #define Lentry_args AS_REGISTER(Register, Lentry_args)
258 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
259 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
260 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
261 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
262 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
263
264 #define Oexception AS_REGISTER(Register, Oexception)
265 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
266
267
268 #endif
269
270 // A union type for code which has to assemble both constant and non-constant operands.
271 class RegisterConstant VALUE_OBJ_CLASS_SPEC {
272 private:
273 Register _r;
274 intptr_t _c;
275
276 public:
277 RegisterConstant(): _r(noreg), _c(0) {}
278 RegisterConstant(Register r): _r(r), _c(0) {}
279 RegisterConstant(intptr_t c): _r(noreg), _c(c) {}
280
281 Register as_register() const { assert(is_register(),""); return _r; }
282 intptr_t as_constant() const { assert(is_constant(),""); return _c; }
283
284 Register register_or_noreg() const { return _r; }
285 intptr_t constant_or_zero() const { return _c; }
286
287 bool is_register() const { return _r != noreg; }
288 bool is_constant() const { return _r == noreg; }
289 };
290
291 // Address is an abstraction used to represent a memory location.
292 //
293 // Note: A register location is represented via a Register, not
294 // via an address for efficiency & simplicity reasons.
295
296 class Address VALUE_OBJ_CLASS_SPEC {
297 private:
298 Register _base;
299 #ifdef _LP64
300 int _hi32; // bits 63::32
301 int _low32; // bits 31::0
302 #endif
303 int _hi;
304 int _disp;
305 RelocationHolder _rspec;
306
307 RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {
308 switch (rt) {
309 case relocInfo::external_word_type:
310 return external_word_Relocation::spec(a);
311 case relocInfo::internal_word_type:
312 return internal_word_Relocation::spec(a);
313 #ifdef _LP64
314 case relocInfo::opt_virtual_call_type:
315 return opt_virtual_call_Relocation::spec();
316 case relocInfo::static_call_type:
317 return static_call_Relocation::spec();
318 case relocInfo::runtime_call_type:
319 return runtime_call_Relocation::spec();
320 #endif
321 case relocInfo::none:
322 return RelocationHolder();
323 default:
324 ShouldNotReachHere();
325 return RelocationHolder();
326 }
327 }
328
329 public:
330 Address(Register b, address a, relocInfo::relocType rt = relocInfo::none)
331 : _rspec(rspec_from_rtype(rt, a))
332 {
333 _base = b;
334 #ifdef _LP64
335 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word
336 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word
337 #endif
338 _hi = (intptr_t)a & ~0x3ff; // top 22 bits in low word
339 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits
340 }
341
342 Address(Register b, address a, RelocationHolder const& rspec)
343 : _rspec(rspec)
344 {
345 _base = b;
346 #ifdef _LP64
347 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word
348 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word
349 #endif
350 _hi = (intptr_t)a & ~0x3ff; // top 22 bits
351 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits
352 }
353
354 Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder())
355 : _rspec(rspec)
356 {
357 _base = b;
358 #ifdef _LP64
359 // [RGV] Put in Assert to force me to check usage of this constructor
360 assert( h == 0, "Check usage of this constructor" );
361 _hi32 = h;
362 _low32 = d;
363 _hi = h;
364 _disp = d;
365 #else
366 _hi = h;
367 _disp = d;
368 #endif
369 }
370
371 Address()
372 : _rspec(RelocationHolder())
373 {
374 _base = G0;
375 #ifdef _LP64
376 _hi32 = 0;
377 _low32 = 0;
378 #endif
379 _hi = 0;
380 _disp = 0;
381 }
382
383 // fancier constructors
384
385 enum addr_type {
386 extra_in_argument, // in the In registers
387 extra_out_argument // in the Outs
388 };
389
390 Address( addr_type, int );
391
392 // accessors
393
394 Register base() const { return _base; }
395 #ifdef _LP64
396 int hi32() const { return _hi32; }
397 int low32() const { return _low32; }
398 #endif
399 int hi() const { return _hi; }
400 int disp() const { return _disp; }
401 #ifdef _LP64
402 intptr_t value() const { return ((intptr_t)_hi32 << 32) |
403 (intptr_t)(uint32_t)_low32; }
404 #else
405 int value() const { return _hi | _disp; }
406 #endif
407 const relocInfo::relocType rtype() { return _rspec.type(); }
408 const RelocationHolder& rspec() { return _rspec; }
409
410 RelocationHolder rspec(int offset) const {
411 return offset == 0 ? _rspec : _rspec.plus(offset);
412 }
413
414 inline bool is_simm13(int offset = 0); // check disp+offset for overflow
415
416 Address split_disp() const { // deal with disp overflow
417 Address a = (*this);
418 int hi_disp = _disp & ~0x3ff;
419 if (hi_disp != 0) {
420 a._disp -= hi_disp;
421 a._hi += hi_disp;
422 }
423 return a;
424 }
425
426 Address after_save() const {
427 Address a = (*this);
428 a._base = a._base->after_save();
429 return a;
430 }
431
432 Address after_restore() const {
433 Address a = (*this);
434 a._base = a._base->after_restore();
435 return a;
436 }
437
438 friend class Assembler;
439 };
440
441
442 inline Address RegisterImpl::address_in_saved_window() const {
443 return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
444 }
445
446
447
448 // Argument is an abstraction used to represent an outgoing
449 // actual argument or an incoming formal parameter, whether
450 // it resides in memory or in a register, in a manner consistent
451 // with the SPARC Application Binary Interface, or ABI. This is
452 // often referred to as the native or C calling convention.
453
454 class Argument VALUE_OBJ_CLASS_SPEC {
455 private:
456 int _number;
457 bool _is_in;
458
459 public:
460 #ifdef _LP64
461 enum {
462 n_register_parameters = 6, // only 6 registers may contain integer parameters
463 n_float_register_parameters = 16 // Can have up to 16 floating registers
464 };
465 #else
466 enum {
467 n_register_parameters = 6 // only 6 registers may contain integer parameters
468 };
469 #endif
470
471 // creation
472 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
473
474 int number() const { return _number; }
475 bool is_in() const { return _is_in; }
476 bool is_out() const { return !is_in(); }
477
478 Argument successor() const { return Argument(number() + 1, is_in()); }
479 Argument as_in() const { return Argument(number(), true ); }
480 Argument as_out() const { return Argument(number(), false); }
481
482 // locating register-based arguments:
483 bool is_register() const { return _number < n_register_parameters; }
484
485 #ifdef _LP64
486 // locating Floating Point register-based arguments:
487 bool is_float_register() const { return _number < n_float_register_parameters; }
488
489 FloatRegister as_float_register() const {
490 assert(is_float_register(), "must be a register argument");
491 return as_FloatRegister(( number() *2 ) + 1);
492 }
493 FloatRegister as_double_register() const {
494 assert(is_float_register(), "must be a register argument");
495 return as_FloatRegister(( number() *2 ));
496 }
497 #endif
498
499 Register as_register() const {
500 assert(is_register(), "must be a register argument");
501 return is_in() ? as_iRegister(number()) : as_oRegister(number());
502 }
503
504 // locating memory-based arguments
505 Address as_address() const {
506 assert(!is_register(), "must be a memory argument");
507 return address_in_frame();
508 }
509
510 // When applied to a register-based argument, give the corresponding address
511 // into the 6-word area "into which callee may store register arguments"
512 // (This is a different place than the corresponding register-save area location.)
513 Address address_in_frame() const {
514 return Address( is_in() ? Address::extra_in_argument
515 : Address::extra_out_argument,
516 _number );
517 }
518
519 // debugging
520 const char* name() const;
521
522 friend class Assembler;
523 };
524
525
526 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
527 // level; i.e., what you write
528 // is what you get. The Assembler is generating code into a CodeBuffer.
529
530 class Assembler : public AbstractAssembler {
531 protected:
532
533 static void print_instruction(int inst);
534 static int patched_branch(int dest_pos, int inst, int inst_pos);
535 static int branch_destination(int inst, int pos);
536
537
538 friend class AbstractAssembler;
539
540 // code patchers need various routines like inv_wdisp()
541 friend class NativeInstruction;
542 friend class NativeGeneralJump;
543 friend class Relocation;
544 friend class Label;
545
546 public:
547 // op carries format info; see page 62 & 267
548
549 enum ops {
550 call_op = 1, // fmt 1
551 branch_op = 0, // also sethi (fmt2)
552 arith_op = 2, // fmt 3, arith & misc
553 ldst_op = 3 // fmt 3, load/store
554 };
555
556 enum op2s {
557 bpr_op2 = 3,
558 fb_op2 = 6,
559 fbp_op2 = 5,
560 br_op2 = 2,
561 bp_op2 = 1,
562 cb_op2 = 7, // V8
563 sethi_op2 = 4
564 };
565
566 enum op3s {
567 // selected op3s
568 add_op3 = 0x00,
569 and_op3 = 0x01,
570 or_op3 = 0x02,
571 xor_op3 = 0x03,
572 sub_op3 = 0x04,
573 andn_op3 = 0x05,
574 orn_op3 = 0x06,
575 xnor_op3 = 0x07,
576 addc_op3 = 0x08,
577 mulx_op3 = 0x09,
578 umul_op3 = 0x0a,
579 smul_op3 = 0x0b,
580 subc_op3 = 0x0c,
581 udivx_op3 = 0x0d,
582 udiv_op3 = 0x0e,
583 sdiv_op3 = 0x0f,
584
585 addcc_op3 = 0x10,
586 andcc_op3 = 0x11,
587 orcc_op3 = 0x12,
588 xorcc_op3 = 0x13,
589 subcc_op3 = 0x14,
590 andncc_op3 = 0x15,
591 orncc_op3 = 0x16,
592 xnorcc_op3 = 0x17,
593 addccc_op3 = 0x18,
594 umulcc_op3 = 0x1a,
595 smulcc_op3 = 0x1b,
596 subccc_op3 = 0x1c,
597 udivcc_op3 = 0x1e,
598 sdivcc_op3 = 0x1f,
599
600 taddcc_op3 = 0x20,
601 tsubcc_op3 = 0x21,
602 taddcctv_op3 = 0x22,
603 tsubcctv_op3 = 0x23,
604 mulscc_op3 = 0x24,
605 sll_op3 = 0x25,
606 sllx_op3 = 0x25,
607 srl_op3 = 0x26,
608 srlx_op3 = 0x26,
609 sra_op3 = 0x27,
610 srax_op3 = 0x27,
611 rdreg_op3 = 0x28,
612 membar_op3 = 0x28,
613
614 flushw_op3 = 0x2b,
615 movcc_op3 = 0x2c,
616 sdivx_op3 = 0x2d,
617 popc_op3 = 0x2e,
618 movr_op3 = 0x2f,
619
620 sir_op3 = 0x30,
621 wrreg_op3 = 0x30,
622 saved_op3 = 0x31,
623
624 fpop1_op3 = 0x34,
625 fpop2_op3 = 0x35,
626 impdep1_op3 = 0x36,
627 impdep2_op3 = 0x37,
628 jmpl_op3 = 0x38,
629 rett_op3 = 0x39,
630 trap_op3 = 0x3a,
631 flush_op3 = 0x3b,
632 save_op3 = 0x3c,
633 restore_op3 = 0x3d,
634 done_op3 = 0x3e,
635 retry_op3 = 0x3e,
636
637 lduw_op3 = 0x00,
638 ldub_op3 = 0x01,
639 lduh_op3 = 0x02,
640 ldd_op3 = 0x03,
641 stw_op3 = 0x04,
642 stb_op3 = 0x05,
643 sth_op3 = 0x06,
644 std_op3 = 0x07,
645 ldsw_op3 = 0x08,
646 ldsb_op3 = 0x09,
647 ldsh_op3 = 0x0a,
648 ldx_op3 = 0x0b,
649
650 ldstub_op3 = 0x0d,
651 stx_op3 = 0x0e,
652 swap_op3 = 0x0f,
653
654 lduwa_op3 = 0x10,
655 ldxa_op3 = 0x1b,
656
657 stwa_op3 = 0x14,
658 stxa_op3 = 0x1e,
659
660 ldf_op3 = 0x20,
661 ldfsr_op3 = 0x21,
662 ldqf_op3 = 0x22,
663 lddf_op3 = 0x23,
664 stf_op3 = 0x24,
665 stfsr_op3 = 0x25,
666 stqf_op3 = 0x26,
667 stdf_op3 = 0x27,
668
669 prefetch_op3 = 0x2d,
670
671
672 ldc_op3 = 0x30,
673 ldcsr_op3 = 0x31,
674 lddc_op3 = 0x33,
675 stc_op3 = 0x34,
676 stcsr_op3 = 0x35,
677 stdcq_op3 = 0x36,
678 stdc_op3 = 0x37,
679
680 casa_op3 = 0x3c,
681 casxa_op3 = 0x3e,
682
683 alt_bit_op3 = 0x10,
684 cc_bit_op3 = 0x10
685 };
686
687 enum opfs {
688 // selected opfs
689 fmovs_opf = 0x01,
690 fmovd_opf = 0x02,
691
692 fnegs_opf = 0x05,
693 fnegd_opf = 0x06,
694
695 fadds_opf = 0x41,
696 faddd_opf = 0x42,
697 fsubs_opf = 0x45,
698 fsubd_opf = 0x46,
699
700 fmuls_opf = 0x49,
701 fmuld_opf = 0x4a,
702 fdivs_opf = 0x4d,
703 fdivd_opf = 0x4e,
704
705 fcmps_opf = 0x51,
706 fcmpd_opf = 0x52,
707
708 fstox_opf = 0x81,
709 fdtox_opf = 0x82,
710 fxtos_opf = 0x84,
711 fxtod_opf = 0x88,
712 fitos_opf = 0xc4,
713 fdtos_opf = 0xc6,
714 fitod_opf = 0xc8,
715 fstod_opf = 0xc9,
716 fstoi_opf = 0xd1,
717 fdtoi_opf = 0xd2
718 };
719
720 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
721
722 enum Condition {
723 // for FBfcc & FBPfcc instruction
724 f_never = 0,
725 f_notEqual = 1,
726 f_notZero = 1,
727 f_lessOrGreater = 2,
728 f_unorderedOrLess = 3,
729 f_less = 4,
730 f_unorderedOrGreater = 5,
731 f_greater = 6,
732 f_unordered = 7,
733 f_always = 8,
734 f_equal = 9,
735 f_zero = 9,
736 f_unorderedOrEqual = 10,
737 f_greaterOrEqual = 11,
738 f_unorderedOrGreaterOrEqual = 12,
739 f_lessOrEqual = 13,
740 f_unorderedOrLessOrEqual = 14,
741 f_ordered = 15,
742
743 // V8 coproc, pp 123 v8 manual
744
745 cp_always = 8,
746 cp_never = 0,
747 cp_3 = 7,
748 cp_2 = 6,
749 cp_2or3 = 5,
750 cp_1 = 4,
751 cp_1or3 = 3,
752 cp_1or2 = 2,
753 cp_1or2or3 = 1,
754 cp_0 = 9,
755 cp_0or3 = 10,
756 cp_0or2 = 11,
757 cp_0or2or3 = 12,
758 cp_0or1 = 13,
759 cp_0or1or3 = 14,
760 cp_0or1or2 = 15,
761
762
763 // for integers
764
765 never = 0,
766 equal = 1,
767 zero = 1,
768 lessEqual = 2,
769 less = 3,
770 lessEqualUnsigned = 4,
771 lessUnsigned = 5,
772 carrySet = 5,
773 negative = 6,
774 overflowSet = 7,
775 always = 8,
776 notEqual = 9,
777 notZero = 9,
778 greater = 10,
779 greaterEqual = 11,
780 greaterUnsigned = 12,
781 greaterEqualUnsigned = 13,
782 carryClear = 13,
783 positive = 14,
784 overflowClear = 15
785 };
786
787 enum CC {
788 icc = 0, xcc = 2,
789 // ptr_cc is the correct condition code for a pointer or intptr_t:
790 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
791 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
792 };
793
794 enum PrefetchFcn {
795 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
796 };
797
798 public:
799 // Helper functions for groups of instructions
800
801 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
802
803 enum Membar_mask_bits { // page 184, v9
804 StoreStore = 1 << 3,
805 LoadStore = 1 << 2,
806 StoreLoad = 1 << 1,
807 LoadLoad = 1 << 0,
808
809 Sync = 1 << 6,
810 MemIssue = 1 << 5,
811 Lookaside = 1 << 4
812 };
813
814 // test if x is within signed immediate range for nbits
815 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
816
817 // test if -4096 <= x <= 4095
818 static bool is_simm13(int x) { return is_simm(x, 13); }
819
820 enum ASIs { // page 72, v9
821 ASI_PRIMARY = 0x80,
822 ASI_PRIMARY_LITTLE = 0x88
823 // add more from book as needed
824 };
825
826 protected:
827 // helpers
828
829 // x is supposed to fit in a field "nbits" wide
830 // and be sign-extended. Check the range.
831
832 static void assert_signed_range(intptr_t x, int nbits) {
833 assert( nbits == 32
834 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
835 "value out of range");
836 }
837
838 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
839 assert( (x & 3) == 0, "not word aligned");
840 assert_signed_range(x, nbits + 2);
841 }
842
843 static void assert_unsigned_const(int x, int nbits) {
844 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
845 }
846
847 // fields: note bits numbered from LSB = 0,
848 // fields known by inclusive bit range
849
850 static int fmask(juint hi_bit, juint lo_bit) {
851 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
852 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
853 }
854
855 // inverse of u_field
856
857 static int inv_u_field(int x, int hi_bit, int lo_bit) {
858 juint r = juint(x) >> lo_bit;
859 r &= fmask( hi_bit, lo_bit);
860 return int(r);
861 }
862
863
864 // signed version: extract from field and sign-extend
865
866 static int inv_s_field(int x, int hi_bit, int lo_bit) {
867 int sign_shift = 31 - hi_bit;
868 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
869 }
870
871 // given a field that ranges from hi_bit to lo_bit (inclusive,
872 // LSB = 0), and an unsigned value for the field,
873 // shift it into the field
874
875 #ifdef ASSERT
876 static int u_field(int x, int hi_bit, int lo_bit) {
877 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
878 "value out of range");
879 int r = x << lo_bit;
880 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
881 return r;
882 }
883 #else
884 // make sure this is inlined as it will reduce code size significantly
885 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
886 #endif
887
888 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
889 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
890 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
891 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
892
893 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
894
895 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
896 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
897 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
898
899 static int op( int x) { return u_field(x, 31, 30); }
900 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
901 static int fcn( int x) { return u_field(x, 29, 25); }
902 static int op3( int x) { return u_field(x, 24, 19); }
903 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
904 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
905 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
906 static int cond( int x) { return u_field(x, 28, 25); }
907 static int cond_mov( int x) { return u_field(x, 17, 14); }
908 static int rcond( RCondition x) { return u_field(x, 12, 10); }
909 static int op2( int x) { return u_field(x, 24, 22); }
910 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
911 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
912 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
913 static int imm_asi( int x) { return u_field(x, 12, 5); }
914 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
915 static int opf_low6( int w) { return u_field(w, 10, 5); }
916 static int opf_low5( int w) { return u_field(w, 9, 5); }
917 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
918 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
919 static int opf( int x) { return u_field(x, 13, 5); }
920
921 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
922 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
923
924 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
925 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
926 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
927
928 // some float instructions use this encoding on the op3 field
929 static int alt_op3(int op, FloatRegisterImpl::Width w) {
930 int r;
931 switch(w) {
932 case FloatRegisterImpl::S: r = op + 0; break;
933 case FloatRegisterImpl::D: r = op + 3; break;
934 case FloatRegisterImpl::Q: r = op + 2; break;
935 default: ShouldNotReachHere(); break;
936 }
937 return op3(r);
938 }
939
940
941 // compute inverse of simm
942 static int inv_simm(int x, int nbits) {
943 return (int)(x << (32 - nbits)) >> (32 - nbits);
944 }
945
946 static int inv_simm13( int x ) { return inv_simm(x, 13); }
947
948 // signed immediate, in low bits, nbits long
949 static int simm(int x, int nbits) {
950 assert_signed_range(x, nbits);
951 return x & (( 1 << nbits ) - 1);
952 }
953
954 // compute inverse of wdisp16
955 static intptr_t inv_wdisp16(int x, intptr_t pos) {
956 int lo = x & (( 1 << 14 ) - 1);
957 int hi = (x >> 20) & 3;
958 if (hi >= 2) hi |= ~1;
959 return (((hi << 14) | lo) << 2) + pos;
960 }
961
962 // word offset, 14 bits at LSend, 2 bits at B21, B20
963 static int wdisp16(intptr_t x, intptr_t off) {
964 intptr_t xx = x - off;
965 assert_signed_word_disp_range(xx, 16);
966 int r = (xx >> 2) & ((1 << 14) - 1)
967 | ( ( (xx>>(2+14)) & 3 ) << 20 );
968 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
969 return r;
970 }
971
972
973 // word displacement in low-order nbits bits
974
975 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
976 int pre_sign_extend = x & (( 1 << nbits ) - 1);
977 int r = pre_sign_extend >= ( 1 << (nbits-1) )
978 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
979 : pre_sign_extend;
980 return (r << 2) + pos;
981 }
982
983 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
984 intptr_t xx = x - off;
985 assert_signed_word_disp_range(xx, nbits);
986 int r = (xx >> 2) & (( 1 << nbits ) - 1);
987 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
988 return r;
989 }
990
991
992 // Extract the top 32 bits in a 64 bit word
993 static int32_t hi32( int64_t x ) {
994 int32_t r = int32_t( (uint64_t)x >> 32 );
995 return r;
996 }
997
998 // given a sethi instruction, extract the constant, left-justified
999 static int inv_hi22( int x ) {
1000 return x << 10;
1001 }
1002
1003 // create an imm22 field, given a 32-bit left-justified constant
1004 static int hi22( int x ) {
1005 int r = int( juint(x) >> 10 );
1006 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
1007 return r;
1008 }
1009
1010 // create a low10 __value__ (not a field) for a given a 32-bit constant
1011 static int low10( int x ) {
1012 return x & ((1 << 10) - 1);
1013 }
1014
1015 // instruction only in v9
1016 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
1017
1018 // instruction only in v8
1019 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
1020
1021 // instruction deprecated in v9
1022 static void v9_dep() { } // do nothing for now
1023
1024 // some float instructions only exist for single prec. on v8
1025 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
1026
1027 // v8 has no CC field
1028 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
1029
1030 protected:
1031 // Simple delay-slot scheme:
1032 // In order to check the programmer, the assembler keeps track of deley slots.
1033 // It forbids CTIs in delay slots (conservative, but should be OK).
1034 // Also, when putting an instruction into a delay slot, you must say
1035 // asm->delayed()->add(...), in order to check that you don't omit
1036 // delay-slot instructions.
1037 // To implement this, we use a simple FSA
1038
1039 #ifdef ASSERT
1040 #define CHECK_DELAY
1041 #endif
1042 #ifdef CHECK_DELAY
1043 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
1044 #endif
1045
1046 public:
1047 // Tells assembler next instruction must NOT be in delay slot.
1048 // Use at start of multinstruction macros.
1049 void assert_not_delayed() {
1050 // This is a separate overloading to avoid creation of string constants
1051 // in non-asserted code--with some compilers this pollutes the object code.
1052 #ifdef CHECK_DELAY
1053 assert_not_delayed("next instruction should not be a delay slot");
1054 #endif
1055 }
1056 void assert_not_delayed(const char* msg) {
1057 #ifdef CHECK_DELAY
1058 assert_msg ( delay_state == no_delay, msg);
1059 #endif
1060 }
1061
1062 protected:
1063 // Delay slot helpers
1064 // cti is called when emitting control-transfer instruction,
1065 // BEFORE doing the emitting.
1066 // Only effective when assertion-checking is enabled.
1067 void cti() {
1068 #ifdef CHECK_DELAY
1069 assert_not_delayed("cti should not be in delay slot");
1070 #endif
1071 }
1072
1073 // called when emitting cti with a delay slot, AFTER emitting
1074 void has_delay_slot() {
1075 #ifdef CHECK_DELAY
1076 assert_not_delayed("just checking");
1077 delay_state = at_delay_slot;
1078 #endif
1079 }
1080
1081 public:
1082 // Tells assembler you know that next instruction is delayed
1083 Assembler* delayed() {
1084 #ifdef CHECK_DELAY
1085 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1086 delay_state = filling_delay_slot;
1087 #endif
1088 return this;
1089 }
1090
1091 void flush() {
1092 #ifdef CHECK_DELAY
1093 assert ( delay_state == no_delay, "ending code with a delay slot");
1094 #endif
1095 AbstractAssembler::flush();
1096 }
1097
1098 inline void emit_long(int); // shadows AbstractAssembler::emit_long
1099 inline void emit_data(int x) { emit_long(x); }
1100 inline void emit_data(int, RelocationHolder const&);
1101 inline void emit_data(int, relocInfo::relocType rtype);
1102 // helper for above fcns
1103 inline void check_delay();
1104
1105
1106 public:
1107 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1108
1109 // pp 135 (addc was addx in v8)
1110
1111 inline void add( Register s1, Register s2, Register d );
1112 inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1113 inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1114 inline void add( Register s1, RegisterConstant s2, Register d, int offset = 0);
1115 inline void add( const Address& a, Register d, int offset = 0);
1116
1117
1118 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1119 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1120 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1121 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1122 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1123 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1124
1125 // pp 136
1126
1127 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1128 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1129
1130 protected: // use MacroAssembler::br instead
1131
1132 // pp 138
1133
1134 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1135 inline void fb( Condition c, bool a, Label& L );
1136
1137 // pp 141
1138
1139 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1140 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1141
1142 public:
1143
1144 // pp 144
1145
1146 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1147 inline void br( Condition c, bool a, Label& L );
1148
1149 // pp 146
1150
1151 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1152 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1153
1154 // pp 121 (V8)
1155
1156 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1157 inline void cb( Condition c, bool a, Label& L );
1158
1159 // pp 149
1160
1161 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1162 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1163
1164 // pp 150
1165
1166 // These instructions compare the contents of s2 with the contents of
1167 // memory at address in s1. If the values are equal, the contents of memory
1168 // at address s1 is swapped with the data in d. If the values are not equal,
1169 // the the contents of memory at s1 is loaded into d, without the swap.
1170
1171 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1172 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1173
1174 // pp 152
1175
1176 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
1177 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1178 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
1179 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1180 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1181 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1182 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1183 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1184
1185 // pp 155
1186
1187 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
1188 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
1189
1190 // pp 156
1191
1192 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
1193 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
1194
1195 // pp 157
1196
1197 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1198 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1199
1200 // pp 159
1201
1202 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1203 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1204
1205 // pp 160
1206
1207 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
1208
1209 // pp 161
1210
1211 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
1212 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
1213
1214 // pp 162
1215
1216 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1217
1218 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1219
1220 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
1221 // on v8 to do negation of single, double and quad precision floats.
1222
1223 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
1224
1225 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1226
1227 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
1228 // on v8 to do abs operation on single/double/quad precision floats.
1229
1230 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
1231
1232 // pp 163
1233
1234 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
1235 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
1236 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
1237
1238 // pp 164
1239
1240 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
1241
1242 // pp 165
1243
1244 inline void flush( Register s1, Register s2 );
1245 inline void flush( Register s1, int simm13a);
1246
1247 // pp 167
1248
1249 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); }
1250
1251 // pp 168
1252
1253 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
1254 // v8 unimp == illtrap(0)
1255
1256 // pp 169
1257
1258 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
1259 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
1260
1261 // pp 149 (v8)
1262
1263 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1264 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1265
1266 // pp 170
1267
1268 void jmpl( Register s1, Register s2, Register d );
1269 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1270
1271 inline void jmpl( Address& a, Register d, int offset = 0);
1272
1273 // 171
1274
1275 inline void ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d );
1276 inline void ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
1277
1278 inline void ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
1279
1280
1281 inline void ldfsr( Register s1, Register s2 );
1282 inline void ldfsr( Register s1, int simm13a);
1283 inline void ldxfsr( Register s1, Register s2 );
1284 inline void ldxfsr( Register s1, int simm13a);
1285
1286 // pp 94 (v8)
1287
1288 inline void ldc( Register s1, Register s2, int crd );
1289 inline void ldc( Register s1, int simm13a, int crd);
1290 inline void lddc( Register s1, Register s2, int crd );
1291 inline void lddc( Register s1, int simm13a, int crd);
1292 inline void ldcsr( Register s1, Register s2, int crd );
1293 inline void ldcsr( Register s1, int simm13a, int crd);
1294
1295
1296 // 173
1297
1298 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1299 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1300
1301 // pp 175, lduw is ld on v8
1302
1303 inline void ldsb( Register s1, Register s2, Register d );
1304 inline void ldsb( Register s1, int simm13a, Register d);
1305 inline void ldsh( Register s1, Register s2, Register d );
1306 inline void ldsh( Register s1, int simm13a, Register d);
1307 inline void ldsw( Register s1, Register s2, Register d );
1308 inline void ldsw( Register s1, int simm13a, Register d);
1309 inline void ldub( Register s1, Register s2, Register d );
1310 inline void ldub( Register s1, int simm13a, Register d);
1311 inline void lduh( Register s1, Register s2, Register d );
1312 inline void lduh( Register s1, int simm13a, Register d);
1313 inline void lduw( Register s1, Register s2, Register d );
1314 inline void lduw( Register s1, int simm13a, Register d);
1315 inline void ldx( Register s1, Register s2, Register d );
1316 inline void ldx( Register s1, int simm13a, Register d);
1317 inline void ld( Register s1, Register s2, Register d );
1318 inline void ld( Register s1, int simm13a, Register d);
1319 inline void ldd( Register s1, Register s2, Register d );
1320 inline void ldd( Register s1, int simm13a, Register d);
1321
1322 inline void ldsb( const Address& a, Register d, int offset = 0 );
1323 inline void ldsh( const Address& a, Register d, int offset = 0 );
1324 inline void ldsw( const Address& a, Register d, int offset = 0 );
1325 inline void ldub( const Address& a, Register d, int offset = 0 );
1326 inline void lduh( const Address& a, Register d, int offset = 0 );
1327 inline void lduw( const Address& a, Register d, int offset = 0 );
1328 inline void ldx( const Address& a, Register d, int offset = 0 );
1329 inline void ld( const Address& a, Register d, int offset = 0 );
1330 inline void ldd( const Address& a, Register d, int offset = 0 );
1331
1332 inline void ld( Register s1, RegisterConstant s2, Register d );
1333 inline void lduw( Register s1, RegisterConstant s2, Register d );
1334 inline void ldsw( Register s1, RegisterConstant s2, Register d );
1335 inline void ldx( Register s1, RegisterConstant s2, Register d );
1336
1337 // pp 177
1338
1339 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1340 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1341 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1342 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1343 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1344 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1345 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1346 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1347 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1348 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1349 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1350 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1351 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1352 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1353 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1354 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1355
1356 // pp 179
1357
1358 inline void ldstub( Register s1, Register s2, Register d );
1359 inline void ldstub( Register s1, int simm13a, Register d);
1360
1361 // pp 180
1362
1363 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1364 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1365
1366 // pp 181
1367
1368 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1369 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1370 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1371 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1372 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1373 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1374 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1375 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1376 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1377 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1378 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1379 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1380 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1381 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1382 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1383 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1384 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1385 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1386 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1387 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1388 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1389 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1390 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1391 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1392
1393 // pp 183
1394
1395 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
1396
1397 // pp 185
1398
1399 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
1400
1401 // pp 189
1402
1403 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1404
1405 // pp 191
1406
1407 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
1408 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
1409
1410 // pp 195
1411
1412 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1413 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1414
1415 // pp 196
1416
1417 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1418 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1419 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1420 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1421 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1422 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1423
1424 // pp 197
1425
1426 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1427 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1428 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1429 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1430 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1431 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1432 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1433 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1434
1435 // pp 199
1436
1437 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1438 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1439
1440 // pp 201
1441
1442 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
1443
1444
1445 // pp 202
1446
1447 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1448 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1449
1450 // pp 203
1451
1452 void prefetch( Register s1, Register s2, PrefetchFcn f);
1453 void prefetch( Register s1, int simm13a, PrefetchFcn f);
1454 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1455 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1456
1457 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
1458
1459 // pp 208
1460
1461 // not implementing read privileged register
1462
1463 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1464 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1465 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1466 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1467 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1468 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1469
1470 // pp 213
1471
1472 inline void rett( Register s1, Register s2);
1473 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1474
1475 // pp 214
1476
1477 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1478 void save( Register s1, int simm13a, Register d ) {
1479 // make sure frame is at least large enough for the register save area
1480 assert(-simm13a >= 16 * wordSize, "frame too small");
1481 emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1482 }
1483
1484 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1485 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1486
1487 // pp 216
1488
1489 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
1490 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
1491
1492 // pp 217
1493
1494 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1495 // pp 218
1496
1497 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1498 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1499 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1500 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1501 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1502 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1503
1504 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1505 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1506 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1507 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1508 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1509 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1510
1511 // pp 220
1512
1513 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1514
1515 // pp 221
1516
1517 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1518
1519 // pp 222
1520
1521 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2 );
1522 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1523 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
1524
1525 inline void stfsr( Register s1, Register s2 );
1526 inline void stfsr( Register s1, int simm13a);
1527 inline void stxfsr( Register s1, Register s2 );
1528 inline void stxfsr( Register s1, int simm13a);
1529
1530 // pp 224
1531
1532 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1533 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1534
1535 // p 226
1536
1537 inline void stb( Register d, Register s1, Register s2 );
1538 inline void stb( Register d, Register s1, int simm13a);
1539 inline void sth( Register d, Register s1, Register s2 );
1540 inline void sth( Register d, Register s1, int simm13a);
1541 inline void stw( Register d, Register s1, Register s2 );
1542 inline void stw( Register d, Register s1, int simm13a);
1543 inline void st( Register d, Register s1, Register s2 );
1544 inline void st( Register d, Register s1, int simm13a);
1545 inline void stx( Register d, Register s1, Register s2 );
1546 inline void stx( Register d, Register s1, int simm13a);
1547 inline void std( Register d, Register s1, Register s2 );
1548 inline void std( Register d, Register s1, int simm13a);
1549
1550 inline void stb( Register d, const Address& a, int offset = 0 );
1551 inline void sth( Register d, const Address& a, int offset = 0 );
1552 inline void stw( Register d, const Address& a, int offset = 0 );
1553 inline void stx( Register d, const Address& a, int offset = 0 );
1554 inline void st( Register d, const Address& a, int offset = 0 );
1555 inline void std( Register d, const Address& a, int offset = 0 );
1556
1557 inline void st( Register d, Register s1, RegisterConstant s2 );
1558 inline void stx( Register d, Register s1, RegisterConstant s2 );
1559
1560 // pp 177
1561
1562 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1563 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1564 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1565 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1566 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1567 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1568 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1569 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1570 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1571 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1572
1573 // pp 97 (v8)
1574
1575 inline void stc( int crd, Register s1, Register s2 );
1576 inline void stc( int crd, Register s1, int simm13a);
1577 inline void stdc( int crd, Register s1, Register s2 );
1578 inline void stdc( int crd, Register s1, int simm13a);
1579 inline void stcsr( int crd, Register s1, Register s2 );
1580 inline void stcsr( int crd, Register s1, int simm13a);
1581 inline void stdcq( int crd, Register s1, Register s2 );
1582 inline void stdcq( int crd, Register s1, int simm13a);
1583
1584 // pp 230
1585
1586 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1587 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1588 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1589 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1590 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1591 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1592 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1593 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1594
1595 // pp 231
1596
1597 inline void swap( Register s1, Register s2, Register d );
1598 inline void swap( Register s1, int simm13a, Register d);
1599 inline void swap( Address& a, Register d, int offset = 0 );
1600
1601 // pp 232
1602
1603 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1604 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1605
1606 // pp 234, note op in book is wrong, see pp 268
1607
1608 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1609 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1610 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1611 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1612
1613 // pp 235
1614
1615 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1616 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1617 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1618 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1619
1620 // pp 237
1621
1622 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1623 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1624 // simple uncond. trap
1625 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1626
1627 // pp 239 omit write priv register for now
1628
1629 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1630 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1631 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
1632 rs1(s) |
1633 op3(wrreg_op3) |
1634 u_field(2, 29, 25) |
1635 u_field(1, 13, 13) |
1636 simm(simm13a, 13)); }
1637 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1638 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1639
1640 // For a given register condition, return the appropriate condition code
1641 // Condition (the one you would use to get the same effect after "tst" on
1642 // the target register.)
1643 Assembler::Condition reg_cond_to_cc_cond(RCondition in);
1644
1645
1646 // Creation
1647 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1648 #ifdef CHECK_DELAY
1649 delay_state = no_delay;
1650 #endif
1651 }
1652
1653 // Testing
1654 #ifndef PRODUCT
1655 void test_v9();
1656 void test_v8_onlys();
1657 #endif
1658 };
1659
1660
1661 class RegistersForDebugging : public StackObj {
1662 public:
1663 intptr_t i[8], l[8], o[8], g[8];
1664 float f[32];
1665 double d[32];
1666
1667 void print(outputStream* s);
1668
1669 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
1670 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
1671 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
1672 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
1673 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
1674 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
1675
1676 // gen asm code to save regs
1677 static void save_registers(MacroAssembler* a);
1678
1679 // restore global registers in case C code disturbed them
1680 static void restore_registers(MacroAssembler* a, Register r);
1681
1682
1683 };
1684
1685
1686 // MacroAssembler extends Assembler by a few frequently used macros.
1687 //
1688 // Most of the standard SPARC synthetic ops are defined here.
1689 // Instructions for which a 'better' code sequence exists depending
1690 // on arguments should also go in here.
1691
1692 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
1693 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
1694 #define JUMP(a, off) jump(a, off, __FILE__, __LINE__)
1695 #define JUMPL(a, d, off) jumpl(a, d, off, __FILE__, __LINE__)
1696
1697
1698 class MacroAssembler: public Assembler {
1699 protected:
1700 // Support for VM calls
1701 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1702 // may customize this version by overriding it for its purposes (e.g., to save/restore
1703 // additional registers when doing a VM call).
1704 #ifdef CC_INTERP
1705 #define VIRTUAL
1706 #else
1707 #define VIRTUAL virtual
1708 #endif
1709
1710 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1711
1712 //
1713 // It is imperative that all calls into the VM are handled via the call_VM macros.
1714 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1715 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1716 //
1717 // This is the base routine called by the different versions of call_VM. The interpreter
1718 // may customize this version by overriding it for its purposes (e.g., to save/restore
1719 // additional registers when doing a VM call).
1720 //
1721 // A non-volatile java_thread_cache register should be specified so
1722 // that the G2_thread value can be preserved across the call.
1723 // (If java_thread_cache is noreg, then a slow get_thread call
1724 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
1725 // thread.
1726 //
1727 // If no last_java_sp is specified (noreg) than SP will be used instead.
1728
1729 virtual void call_VM_base(
1730 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1731 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
1732 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1733 address entry_point, // the entry point
1734 int number_of_arguments, // the number of arguments (w/o thread) to pop after call
1735 bool check_exception=true // flag which indicates if exception should be checked
1736 );
1737
1738 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1739 // The implementation is only non-empty for the InterpreterMacroAssembler,
1740 // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
1741 virtual void check_and_handle_popframe(Register scratch_reg);
1742 virtual void check_and_handle_earlyret(Register scratch_reg);
1743
1744 public:
1745 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1746
1747 // Support for NULL-checks
1748 //
1749 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1750 // If the accessed location is M[reg + offset] and the offset is known, provide the
1751 // offset. No explicit code generation is needed if the offset is within a certain
1752 // range (0 <= offset <= page_size).
1753 //
1754 // %%%%%% Currently not done for SPARC
1755
1756 void null_check(Register reg, int offset = -1);
1757 static bool needs_explicit_null_check(intptr_t offset);
1758
1759 // support for delayed instructions
1760 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1761
1762 // branches that use right instruction for v8 vs. v9
1763 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1764 inline void br( Condition c, bool a, Predict p, Label& L );
1765 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1766 inline void fb( Condition c, bool a, Predict p, Label& L );
1767
1768 // compares register with zero and branches (V9 and V8 instructions)
1769 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1770 // Compares a pointer register with zero and branches on (not)null.
1771 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1772 void br_null ( Register s1, bool a, Predict p, Label& L );
1773 void br_notnull( Register s1, bool a, Predict p, Label& L );
1774
1775 // These versions will do the most efficient thing on v8 and v9. Perhaps
1776 // this is what the routine above was meant to do, but it didn't (and
1777 // didn't cover both target address kinds.)
1778 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1779 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1780
1781 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1782 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1783
1784 // Branch that tests xcc in LP64 and icc in !LP64
1785 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1786 inline void brx( Condition c, bool a, Predict p, Label& L );
1787
1788 // unconditional short branch
1789 inline void ba( bool a, Label& L );
1790
1791 // Branch that tests fp condition codes
1792 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1793 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1794
1795 // get PC the best way
1796 inline int get_pc( Register d );
1797
1798 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1799 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1800 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1801
1802 inline void jmp( Register s1, Register s2 );
1803 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1804
1805 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1806 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1807 inline void callr( Register s1, Register s2 );
1808 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1809
1810 // Emits nothing on V8
1811 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
1812 inline void iprefetch( Label& L);
1813
1814 inline void tst( Register s ) { orcc( G0, s, G0 ); }
1815
1816 #ifdef PRODUCT
1817 inline void ret( bool trace = TraceJumps ) { if (trace) {
1818 mov(I7, O7); // traceable register
1819 JMP(O7, 2 * BytesPerInstWord);
1820 } else {
1821 jmpl( I7, 2 * BytesPerInstWord, G0 );
1822 }
1823 }
1824
1825 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
1826 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
1827 #else
1828 void ret( bool trace = TraceJumps );
1829 void retl( bool trace = TraceJumps );
1830 #endif /* PRODUCT */
1831
1832 // Required platform-specific helpers for Label::patch_instructions.
1833 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1834 void pd_patch_instruction(address branch, address target);
1835 #ifndef PRODUCT
1836 static void pd_print_patched_instruction(address branch);
1837 #endif
1838
1839 // sethi Macro handles optimizations and relocations
1840 void sethi( Address& a, bool ForceRelocatable = false );
1841 void sethi( intptr_t imm22a, Register d, bool ForceRelocatable = false, RelocationHolder const& rspec = RelocationHolder());
1842
1843 // compute the size of a sethi/set
1844 static int size_of_sethi( address a, bool worst_case = false );
1845 static int worst_case_size_of_set();
1846
1847 // set may be either setsw or setuw (high 32 bits may be zero or sign)
1848 void set( intptr_t value, Register d, RelocationHolder const& rspec = RelocationHolder() );
1849 void setsw( int value, Register d, RelocationHolder const& rspec = RelocationHolder() );
1850 void set64( jlong value, Register d, Register tmp);
1851
1852 // sign-extend 32 to 64
1853 inline void signx( Register s, Register d ) { sra( s, G0, d); }
1854 inline void signx( Register d ) { sra( d, G0, d); }
1855
1856 inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1857 inline void not1( Register d ) { xnor( d, G0, d ); }
1858
1859 inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1860 inline void neg( Register d ) { sub( G0, d, d ); }
1861
1862 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1863 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1864 // Functions for isolating 64 bit atomic swaps for LP64
1865 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1866 inline void cas_ptr( Register s1, Register s2, Register d) {
1867 #ifdef _LP64
1868 casx( s1, s2, d );
1869 #else
1870 cas( s1, s2, d );
1871 #endif
1872 }
1873
1874 // Functions for isolating 64 bit shifts for LP64
1875 inline void sll_ptr( Register s1, Register s2, Register d );
1876 inline void sll_ptr( Register s1, int imm6a, Register d );
1877 inline void srl_ptr( Register s1, Register s2, Register d );
1878 inline void srl_ptr( Register s1, int imm6a, Register d );
1879
1880 // little-endian
1881 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
1882 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
1883
1884 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
1885 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
1886
1887 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
1888 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
1889
1890 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
1891 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
1892
1893 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
1894 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
1895
1896 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
1897 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
1898
1899 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
1900 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
1901
1902 inline void clr( Register d ) { or3( G0, G0, d ); }
1903
1904 inline void clrb( Register s1, Register s2);
1905 inline void clrh( Register s1, Register s2);
1906 inline void clr( Register s1, Register s2);
1907 inline void clrx( Register s1, Register s2);
1908
1909 inline void clrb( Register s1, int simm13a);
1910 inline void clrh( Register s1, int simm13a);
1911 inline void clr( Register s1, int simm13a);
1912 inline void clrx( Register s1, int simm13a);
1913
1914 // copy & clear upper word
1915 inline void clruw( Register s, Register d ) { srl( s, G0, d); }
1916 // clear upper word
1917 inline void clruwu( Register d ) { srl( d, G0, d); }
1918
1919 // membar psuedo instruction. takes into account target memory model.
1920 inline void membar( Assembler::Membar_mask_bits const7a );
1921
1922 // returns if membar generates anything.
1923 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
1924
1925 // mov pseudo instructions
1926 inline void mov( Register s, Register d) {
1927 if ( s != d ) or3( G0, s, d);
1928 else assert_not_delayed(); // Put something useful in the delay slot!
1929 }
1930
1931 inline void mov_or_nop( Register s, Register d) {
1932 if ( s != d ) or3( G0, s, d);
1933 else nop();
1934 }
1935
1936 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1937
1938 // address pseudos: make these names unlike instruction names to avoid confusion
1939 inline void split_disp( Address& a, Register temp );
1940 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1941 inline void load_address( Address& a, int offset = 0 );
1942 inline void load_contents( Address& a, Register d, int offset = 0 );
1943 inline void load_ptr_contents( Address& a, Register d, int offset = 0 );
1944 inline void store_contents( Register s, Address& a, int offset = 0 );
1945 inline void store_ptr_contents( Register s, Address& a, int offset = 0 );
1946 inline void jumpl_to( Address& a, Register d, int offset = 0 );
1947 inline void jump_to( Address& a, int offset = 0 );
1948 inline void jump_indirect_to( Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0 );
1949
1950 // ring buffer traceable jumps
1951
1952 void jmp2( Register r1, Register r2, const char* file, int line );
1953 void jmp ( Register r1, int offset, const char* file, int line );
1954
1955 void jumpl( Address& a, Register d, int offset, const char* file, int line );
1956 void jump ( Address& a, int offset, const char* file, int line );
1957
1958
1959 // argument pseudos:
1960
1961 inline void load_argument( Argument& a, Register d );
1962 inline void store_argument( Register s, Argument& a );
1963 inline void store_ptr_argument( Register s, Argument& a );
1964 inline void store_float_argument( FloatRegister s, Argument& a );
1965 inline void store_double_argument( FloatRegister s, Argument& a );
1966 inline void store_long_argument( Register s, Argument& a );
1967
1968 // handy macros:
1969
1970 inline void round_to( Register r, int modulus ) {
1971 assert_not_delayed();
1972 inc( r, modulus - 1 );
1973 and3( r, -modulus, r );
1974 }
1975
1976 // --------------------------------------------------
1977
1978 // Functions for isolating 64 bit loads for LP64
1979 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
1980 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
1981 inline void ld_ptr( Register s1, Register s2, Register d );
1982 inline void ld_ptr( Register s1, int simm13a, Register d);
1983 inline void ld_ptr( Register s1, RegisterConstant s2, Register d );
1984 inline void ld_ptr( const Address& a, Register d, int offset = 0 );
1985 inline void st_ptr( Register d, Register s1, Register s2 );
1986 inline void st_ptr( Register d, Register s1, int simm13a);
1987 inline void st_ptr( Register d, Register s1, RegisterConstant s2 );
1988 inline void st_ptr( Register d, const Address& a, int offset = 0 );
1989
1990 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
1991 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
1992 inline void ld_long( Register s1, Register s2, Register d );
1993 inline void ld_long( Register s1, int simm13a, Register d );
1994 inline void ld_long( const Address& a, Register d, int offset = 0 );
1995 inline void st_long( Register d, Register s1, Register s2 );
1996 inline void st_long( Register d, Register s1, int simm13a );
1997 inline void st_long( Register d, const Address& a, int offset = 0 );
1998
1999 // --------------------------------------------------
2000
2001 public:
2002 // traps as per trap.h (SPARC ABI?)
2003
2004 void breakpoint_trap();
2005 void breakpoint_trap(Condition c, CC cc = icc);
2006 void flush_windows_trap();
2007 void clean_windows_trap();
2008 void get_psr_trap();
2009 void set_psr_trap();
2010
2011 // V8/V9 flush_windows
2012 void flush_windows();
2013
2014 // Support for serializing memory accesses between threads
2015 void serialize_memory(Register thread, Register tmp1, Register tmp2);
2016
2017 // Stack frame creation/removal
2018 void enter();
2019 void leave();
2020
2021 // V8/V9 integer multiply
2022 void mult(Register s1, Register s2, Register d);
2023 void mult(Register s1, int simm13a, Register d);
2024
2025 // V8/V9 read and write of condition codes.
2026 void read_ccr(Register d);
2027 void write_ccr(Register s);
2028
2029 // Manipulation of C++ bools
2030 // These are idioms to flag the need for care with accessing bools but on
2031 // this platform we assume byte size
2032
2033 inline void stbool( Register d, const Address& a, int offset = 0 ) { stb(d, a, offset); }
2034 inline void ldbool( const Address& a, Register d, int offset = 0 ) { ldsb( a, d, offset ); }
2035 inline void tstbool( Register s ) { tst(s); }
2036 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
2037
2038 // klass oop manipulations if compressed
2039 void load_klass(Register src_oop, Register klass);
2040 void store_klass(Register klass, Register dst_oop);
2041 void store_klass_gap(Register s, Register dst_oop);
2042
2043 // oop manipulations
2044 void load_heap_oop(const Address& s, Register d, int offset = 0);
2045 void load_heap_oop(Register s1, Register s2, Register d);
2046 void load_heap_oop(Register s1, int simm13a, Register d);
2047 void store_heap_oop(Register d, Register s1, Register s2);
2048 void store_heap_oop(Register d, Register s1, int simm13a);
2049 void store_heap_oop(Register d, const Address& a, int offset = 0);
2050
2051 void encode_heap_oop(Register src, Register dst);
2052 void encode_heap_oop(Register r) {
2053 encode_heap_oop(r, r);
2054 }
2055 void decode_heap_oop(Register src, Register dst);
2056 void decode_heap_oop(Register r) {
2057 decode_heap_oop(r, r);
2058 }
2059 void encode_heap_oop_not_null(Register r);
2060 void decode_heap_oop_not_null(Register r);
2061 void encode_heap_oop_not_null(Register src, Register dst);
2062 void decode_heap_oop_not_null(Register src, Register dst);
2063
2064 // Support for managing the JavaThread pointer (i.e.; the reference to
2065 // thread-local information).
2066 void get_thread(); // load G2_thread
2067 void verify_thread(); // verify G2_thread contents
2068 void save_thread (const Register threache); // save to cache
2069 void restore_thread(const Register thread_cache); // restore from cache
2070
2071 // Support for last Java frame (but use call_VM instead where possible)
2072 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
2073 void reset_last_Java_frame(void);
2074
2075 // Call into the VM.
2076 // Passes the thread pointer (in O0) as a prepended argument.
2077 // Makes sure oop return values are visible to the GC.
2078 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2079 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
2080 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2081 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2082
2083 // these overloadings are not presently used on SPARC:
2084 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2085 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
2086 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2087 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2088
2089 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
2090 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
2091 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
2092 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
2093
2094 void get_vm_result (Register oop_result);
2095 void get_vm_result_2(Register oop_result);
2096
2097 // vm result is currently getting hijacked to for oop preservation
2098 void set_vm_result(Register oop_result);
2099
2100 // if call_VM_base was called with check_exceptions=false, then call
2101 // check_and_forward_exception to handle exceptions when it is safe
2102 void check_and_forward_exception(Register scratch_reg);
2103
2104 private:
2105 // For V8
2106 void read_ccr_trap(Register ccr_save);
2107 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2108
2109 #ifdef ASSERT
2110 // For V8 debugging. Uses V8 instruction sequence and checks
2111 // result with V9 insturctions rdccr and wrccr.
2112 // Uses Gscatch and Gscatch2
2113 void read_ccr_v8_assert(Register ccr_save);
2114 void write_ccr_v8_assert(Register ccr_save);
2115 #endif // ASSERT
2116
2117 public:
2118
2119 // Write to card table for - register is destroyed afterwards.
2120 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2121
2122 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2123
2124 #ifndef SERIALGC
2125 // Array store and offset
2126 void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs);
2127
2128 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2129
2130 // May do filtering, depending on the boolean arguments.
2131 void g1_card_table_write(jbyte* byte_map_base,
2132 Register tmp, Register obj, Register new_val,
2133 bool region_filter, bool null_filter);
2134 #endif // SERIALGC
2135
2136 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2137 void push_fTOS();
2138
2139 // pops double TOS element from CPU stack and pushes on FPU stack
2140 void pop_fTOS();
2141
2142 void empty_FPU_stack();
2143
2144 void push_IU_state();
2145 void pop_IU_state();
2146
2147 void push_FPU_state();
2148 void pop_FPU_state();
2149
2150 void push_CPU_state();
2151 void pop_CPU_state();
2152
2153 // if heap base register is used - reinit it with the correct value
2154 void reinit_heapbase();
2155
2156 // Debugging
2157 void _verify_oop(Register reg, const char * msg, const char * file, int line);
2158 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
2159
2160 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
2161 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
2162
2163 // only if +VerifyOops
2164 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2165 // only if +VerifyFPU
2166 void stop(const char* msg); // prints msg, dumps registers and stops execution
2167 void warn(const char* msg); // prints msg, but don't stop
2168 void untested(const char* what = "");
2169 void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); }
2170 void should_not_reach_here() { stop("should not reach here"); }
2171 void print_CPU_state();
2172
2173 // oops in code
2174 Address allocate_oop_address( jobject obj, Register d ); // allocate_index
2175 Address constant_oop_address( jobject obj, Register d ); // find_index
2176 inline void set_oop ( jobject obj, Register d ); // uses allocate_oop_address
2177 inline void set_oop_constant( jobject obj, Register d ); // uses constant_oop_address
2178 inline void set_oop ( Address obj_addr ); // same as load_address
2179
2180 void set_narrow_oop( jobject obj, Register d );
2181
2182 // nop padding
2183 void align(int modulus);
2184
2185 // declare a safepoint
2186 void safepoint();
2187
2188 // factor out part of stop into subroutine to save space
2189 void stop_subroutine();
2190 // factor out part of verify_oop into subroutine to save space
2191 void verify_oop_subroutine();
2192
2193 // side-door communication with signalHandler in os_solaris.cpp
2194 static address _verify_oop_implicit_branch[3];
2195
2196 #ifndef PRODUCT
2197 static void test();
2198 #endif
2199
2200 // convert an incoming arglist to varargs format; put the pointer in d
2201 void set_varargs( Argument a, Register d );
2202
2203 int total_frame_size_in_bytes(int extraWords);
2204
2205 // used when extraWords known statically
2206 void save_frame(int extraWords);
2207 void save_frame_c1(int size_in_bytes);
2208 // make a frame, and simultaneously pass up one or two register value
2209 // into the new register window
2210 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
2211
2212 // give no. (outgoing) params, calc # of words will need on frame
2213 void calc_mem_param_words(Register Rparam_words, Register Rresult);
2214
2215 // used to calculate frame size dynamically
2216 // result is in bytes and must be negated for save inst
2217 void calc_frame_size(Register extraWords, Register resultReg);
2218
2219 // calc and also save
2220 void calc_frame_size_and_save(Register extraWords, Register resultReg);
2221
2222 static void debug(char* msg, RegistersForDebugging* outWindow);
2223
2224 // implementations of bytecodes used by both interpreter and compiler
2225
2226 void lcmp( Register Ra_hi, Register Ra_low,
2227 Register Rb_hi, Register Rb_low,
2228 Register Rresult);
2229
2230 void lneg( Register Rhi, Register Rlow );
2231
2232 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
2233 Register Rout_high, Register Rout_low, Register Rtemp );
2234
2235 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
2236 Register Rout_high, Register Rout_low, Register Rtemp );
2237
2238 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
2239 Register Rout_high, Register Rout_low, Register Rtemp );
2240
2241 #ifdef _LP64
2242 void lcmp( Register Ra, Register Rb, Register Rresult);
2243 #endif
2244
2245 void float_cmp( bool is_float, int unordered_result,
2246 FloatRegister Fa, FloatRegister Fb,
2247 Register Rresult);
2248
2249 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2250 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2251 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2252 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2253
2254 void save_all_globals_into_locals();
2255 void restore_globals_from_locals();
2256
2257 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2258 address lock_addr=0, bool use_call_vm=false);
2259 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2260 address lock_addr=0, bool use_call_vm=false);
2261 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2262
2263 // These set the icc condition code to equal if the lock succeeded
2264 // and notEqual if it failed and requires a slow case
2265 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
2266 Register Rscratch,
2267 BiasedLockingCounters* counters = NULL,
2268 bool try_bias = UseBiasedLocking);
2269 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
2270 Register Rscratch,
2271 bool try_bias = UseBiasedLocking);
2272
2273 // Biased locking support
2274 // Upon entry, lock_reg must point to the lock record on the stack,
2275 // obj_reg must contain the target object, and mark_reg must contain
2276 // the target object's header.
2277 // Destroys mark_reg if an attempt is made to bias an anonymously
2278 // biased lock. In this case a failure will go either to the slow
2279 // case or fall through with the notEqual condition code set with
2280 // the expectation that the slow case in the runtime will be called.
2281 // In the fall-through case where the CAS-based lock is done,
2282 // mark_reg is not destroyed.
2283 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
2284 Label& done, Label* slow_case = NULL,
2285 BiasedLockingCounters* counters = NULL);
2286 // Upon entry, the base register of mark_addr must contain the oop.
2287 // Destroys temp_reg.
2288
2289 // If allow_delay_slot_filling is set to true, the next instruction
2290 // emitted after this one will go in an annulled delay slot if the
2291 // biased locking exit case failed.
2292 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2293
2294 // allocation
2295 void eden_allocate(
2296 Register obj, // result: pointer to object after successful allocation
2297 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2298 int con_size_in_bytes, // object size in bytes if known at compile time
2299 Register t1, // temp register
2300 Register t2, // temp register
2301 Label& slow_case // continuation point if fast allocation fails
2302 );
2303 void tlab_allocate(
2304 Register obj, // result: pointer to object after successful allocation
2305 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2306 int con_size_in_bytes, // object size in bytes if known at compile time
2307 Register t1, // temp register
2308 Label& slow_case // continuation point if fast allocation fails
2309 );
2310 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2311
2312 // small bootstrap problems
2313 RegisterConstant delayed_value(intptr_t* delayed_value_addr, Register tmp,
2314 int offset = 0);
2315 RegisterConstant delayed_value(int(*value_fn)(), Register tmp,
2316 int offset = 0) {
2317 return delayed_value(delayed_value_addr(value_fn), tmp, offset);
2318 }
2319 RegisterConstant delayed_value(address(*value_fn)(), Register tmp,
2320 int offset = 0) {
2321 return delayed_value((intptr_t*) delayed_value_addr(value_fn), tmp, offset);
2322 }
2323
2324 // interface method calling
2325 void lookup_interface_method(Register recv_klass,
2326 Register intf_klass,
2327 RegisterConstant itable_index,
2328 Register method_result,
2329 Register scan_temp,
2330 Label& no_such_interface);
2331
2332 // method handles (JSR 292)
2333 void check_method_handle_type(Register mtype_reg, Register mh_reg,
2334 Register temp_reg,
2335 Label& wrong_method_type);
2336 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg);
2337 // offset relative to Gargs of argument at tos[arg_slot].
2338 // (arg_slot == 0 means the last argument, not the first).
2339 RegisterConstant argument_offset(RegisterConstant arg_slot,
2340 int extra_slot_offset = 0);
2341
2342 // klass type checking (falls through on failure)
2343 void check_klass_subtype(Register sub_klass,
2344 Register super_klass,
2345 Register temp_reg,
2346 Label& L_success);
2347
2348
2349 // Stack overflow checking
2350
2351 // Note: this clobbers G3_scratch
2352 void bang_stack_with_offset(int offset) {
2353 // stack grows down, caller passes positive offset
2354 assert(offset > 0, "must bang with negative offset");
2355 set((-offset)+STACK_BIAS, G3_scratch);
2356 st(G0, SP, G3_scratch);
2357 }
2358
2359 // Writes to stack successive pages until offset reached to check for
2360 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2361 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2362
2363 void verify_tlab();
2364
2365 Condition negate_condition(Condition cond);
2366
2367 // Helper functions for statistics gathering.
2368 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
2369 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
2370 // Unconditional increment.
2371 void inc_counter(address counter_addr, Register Rtemp1, Register Rtemp2);
2372
2373 #undef VIRTUAL
2374
2375 };
2376
2377 /**
2378 * class SkipIfEqual:
2379 *
2380 * Instantiating this class will result in assembly code being output that will
2381 * jump around any code emitted between the creation of the instance and it's
2382 * automatic destruction at the end of a scope block, depending on the value of
2383 * the flag passed to the constructor, which will be checked at run-time.
2384 */
2385 class SkipIfEqual : public StackObj {
2386 private:
2387 MacroAssembler* _masm;
2388 Label _label;
2389
2390 public:
2391 // 'temp' is a temp register that this object can use (and trash)
2392 SkipIfEqual(MacroAssembler*, Register temp,
2393 const bool* flag_addr, Assembler::Condition condition);
2394 ~SkipIfEqual();
2395 };
2396
2397 #ifdef ASSERT
2398 // On RISC, there's no benefit to verifying instruction boundaries.
2399 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
2400 #endif