1 //
2 // Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d.
135 // Word a in each register holds a Float, words ab hold a Double. We
136 // currently do not use the SIMD capabilities, so registers cd are
137 // unused at the moment.
138 // XMM8-XMM15 must be encoded with REX.
139 // Linux ABI: No register preserved across function calls
140 // XMM0-XMM7 might hold parameters
141 // Windows ABI: XMM6-XMM15 preserved across function calls
142 // XMM0-XMM3 might hold parameters
143
144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
146
147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
149
150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
152
153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
155
156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
158
159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
161
162 #ifdef _WIN64
163
164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg());
165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next());
166
167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg());
168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next());
169
170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg());
171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next());
172
173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg());
174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next());
175
176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg());
177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next());
178
179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg());
180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next());
181
182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg());
183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next());
184
185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg());
186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next());
187
188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg());
189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next());
190
191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg());
192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next());
193
194 #else
195
196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
198
199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
201
202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg());
203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next());
204
205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg());
206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next());
207
208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg());
209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next());
210
211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg());
212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next());
213
214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg());
215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next());
216
217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg());
218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next());
219
220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg());
221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next());
222
223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg());
224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next());
225
226 #endif // _WIN64
227
228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad());
229
230 // Specify priority of register selection within phases of register
231 // allocation. Highest priority is first. A useful heuristic is to
232 // give registers a low priority when they are required by machine
233 // instructions, like EAX and EDX on I486, and choose no-save registers
234 // before save-on-call, & save-on-call before save-on-entry. Registers
235 // which participate in fixed calling sequences should come last.
236 // Registers which are used as pairs must fall on an even boundary.
237
238 alloc_class chunk0(R10, R10_H,
239 R11, R11_H,
240 R8, R8_H,
241 R9, R9_H,
242 R12, R12_H,
243 RCX, RCX_H,
244 RBX, RBX_H,
245 RDI, RDI_H,
246 RDX, RDX_H,
247 RSI, RSI_H,
248 RAX, RAX_H,
249 RBP, RBP_H,
250 R13, R13_H,
251 R14, R14_H,
252 R15, R15_H,
253 RSP, RSP_H);
254
255 // XXX probably use 8-15 first on Linux
256 alloc_class chunk1(XMM0, XMM0_H,
257 XMM1, XMM1_H,
258 XMM2, XMM2_H,
259 XMM3, XMM3_H,
260 XMM4, XMM4_H,
261 XMM5, XMM5_H,
262 XMM6, XMM6_H,
263 XMM7, XMM7_H,
264 XMM8, XMM8_H,
265 XMM9, XMM9_H,
266 XMM10, XMM10_H,
267 XMM11, XMM11_H,
268 XMM12, XMM12_H,
269 XMM13, XMM13_H,
270 XMM14, XMM14_H,
271 XMM15, XMM15_H);
272
273 alloc_class chunk2(RFLAGS);
274
275
276 //----------Architecture Description Register Classes--------------------------
277 // Several register classes are automatically defined based upon information in
278 // this architecture description.
279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // Class for all pointer registers (including RSP)
286 reg_class any_reg(RAX, RAX_H,
287 RDX, RDX_H,
288 RBP, RBP_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 RBX, RBX_H,
293 RSP, RSP_H,
294 R8, R8_H,
295 R9, R9_H,
296 R10, R10_H,
297 R11, R11_H,
298 R12, R12_H,
299 R13, R13_H,
300 R14, R14_H,
301 R15, R15_H);
302
303 // Class for all pointer registers except RSP
304 reg_class ptr_reg(RAX, RAX_H,
305 RDX, RDX_H,
306 RBP, RBP_H,
307 RDI, RDI_H,
308 RSI, RSI_H,
309 RCX, RCX_H,
310 RBX, RBX_H,
311 R8, R8_H,
312 R9, R9_H,
313 R10, R10_H,
314 R11, R11_H,
315 R13, R13_H,
316 R14, R14_H);
317
318 // Class for all pointer registers except RAX and RSP
319 reg_class ptr_no_rax_reg(RDX, RDX_H,
320 RBP, RBP_H,
321 RDI, RDI_H,
322 RSI, RSI_H,
323 RCX, RCX_H,
324 RBX, RBX_H,
325 R8, R8_H,
326 R9, R9_H,
327 R10, R10_H,
328 R11, R11_H,
329 R12, R12_H,
330 R13, R13_H,
331 R14, R14_H);
332
333 reg_class ptr_no_rbp_reg(RDX, RDX_H,
334 RAX, RAX_H,
335 RDI, RDI_H,
336 RSI, RSI_H,
337 RCX, RCX_H,
338 RBX, RBX_H,
339 R8, R8_H,
340 R9, R9_H,
341 R10, R10_H,
342 R11, R11_H,
343 R12, R12_H,
344 R13, R13_H,
345 R14, R14_H);
346
347 // Class for all pointer registers except RAX, RBX and RSP
348 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H,
349 RBP, RBP_H,
350 RDI, RDI_H,
351 RSI, RSI_H,
352 RCX, RCX_H,
353 R8, R8_H,
354 R9, R9_H,
355 R10, R10_H,
356 R11, R11_H,
357 R12, R12_H,
358 R13, R13_H,
359 R14, R14_H);
360
361 // Singleton class for RAX pointer register
362 reg_class ptr_rax_reg(RAX, RAX_H);
363
364 // Singleton class for RBX pointer register
365 reg_class ptr_rbx_reg(RBX, RBX_H);
366
367 // Singleton class for RSI pointer register
368 reg_class ptr_rsi_reg(RSI, RSI_H);
369
370 // Singleton class for RDI pointer register
371 reg_class ptr_rdi_reg(RDI, RDI_H);
372
373 // Singleton class for RBP pointer register
374 reg_class ptr_rbp_reg(RBP, RBP_H);
375
376 // Singleton class for stack pointer
377 reg_class ptr_rsp_reg(RSP, RSP_H);
378
379 // Singleton class for TLS pointer
380 reg_class ptr_r15_reg(R15, R15_H);
381
382 // Class for all long registers (except RSP)
383 reg_class long_reg(RAX, RAX_H,
384 RDX, RDX_H,
385 RBP, RBP_H,
386 RDI, RDI_H,
387 RSI, RSI_H,
388 RCX, RCX_H,
389 RBX, RBX_H,
390 R8, R8_H,
391 R9, R9_H,
392 R10, R10_H,
393 R11, R11_H,
394 R13, R13_H,
395 R14, R14_H);
396
397 // Class for all long registers except RAX, RDX (and RSP)
398 reg_class long_no_rax_rdx_reg(RBP, RBP_H,
399 RDI, RDI_H,
400 RSI, RSI_H,
401 RCX, RCX_H,
402 RBX, RBX_H,
403 R8, R8_H,
404 R9, R9_H,
405 R10, R10_H,
406 R11, R11_H,
407 R13, R13_H,
408 R14, R14_H);
409
410 // Class for all long registers except RCX (and RSP)
411 reg_class long_no_rcx_reg(RBP, RBP_H,
412 RDI, RDI_H,
413 RSI, RSI_H,
414 RAX, RAX_H,
415 RDX, RDX_H,
416 RBX, RBX_H,
417 R8, R8_H,
418 R9, R9_H,
419 R10, R10_H,
420 R11, R11_H,
421 R13, R13_H,
422 R14, R14_H);
423
424 // Class for all long registers except RAX (and RSP)
425 reg_class long_no_rax_reg(RBP, RBP_H,
426 RDX, RDX_H,
427 RDI, RDI_H,
428 RSI, RSI_H,
429 RCX, RCX_H,
430 RBX, RBX_H,
431 R8, R8_H,
432 R9, R9_H,
433 R10, R10_H,
434 R11, R11_H,
435 R13, R13_H,
436 R14, R14_H);
437
438 // Singleton class for RAX long register
439 reg_class long_rax_reg(RAX, RAX_H);
440
441 // Singleton class for RCX long register
442 reg_class long_rcx_reg(RCX, RCX_H);
443
444 // Singleton class for RDX long register
445 reg_class long_rdx_reg(RDX, RDX_H);
446
447 // Singleton class for R12 long register
448 reg_class long_r12_reg(R12, R12_H);
449
450 // Class for all int registers (except RSP)
451 reg_class int_reg(RAX,
452 RDX,
453 RBP,
454 RDI,
455 RSI,
456 RCX,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers except RCX (and RSP)
466 reg_class int_no_rcx_reg(RAX,
467 RDX,
468 RBP,
469 RDI,
470 RSI,
471 RBX,
472 R8,
473 R9,
474 R10,
475 R11,
476 R13,
477 R14);
478
479 // Class for all int registers except RAX, RDX (and RSP)
480 reg_class int_no_rax_rdx_reg(RBP,
481 RDI,
482 RSI,
483 RCX,
484 RBX,
485 R8,
486 R9,
487 R10,
488 R11,
489 R13,
490 R14);
491
492 // Singleton class for RAX int register
493 reg_class int_rax_reg(RAX);
494
495 // Singleton class for RBX int register
496 reg_class int_rbx_reg(RBX);
497
498 // Singleton class for RCX int register
499 reg_class int_rcx_reg(RCX);
500
501 // Singleton class for RCX int register
502 reg_class int_rdx_reg(RDX);
503
504 // Singleton class for RCX int register
505 reg_class int_rdi_reg(RDI);
506
507 // Singleton class for instruction pointer
508 // reg_class ip_reg(RIP);
509
510 // Singleton class for condition codes
511 reg_class int_flags(RFLAGS);
512
513 // Class for all float registers
514 reg_class float_reg(XMM0,
515 XMM1,
516 XMM2,
517 XMM3,
518 XMM4,
519 XMM5,
520 XMM6,
521 XMM7,
522 XMM8,
523 XMM9,
524 XMM10,
525 XMM11,
526 XMM12,
527 XMM13,
528 XMM14,
529 XMM15);
530
531 // Class for all double registers
532 reg_class double_reg(XMM0, XMM0_H,
533 XMM1, XMM1_H,
534 XMM2, XMM2_H,
535 XMM3, XMM3_H,
536 XMM4, XMM4_H,
537 XMM5, XMM5_H,
538 XMM6, XMM6_H,
539 XMM7, XMM7_H,
540 XMM8, XMM8_H,
541 XMM9, XMM9_H,
542 XMM10, XMM10_H,
543 XMM11, XMM11_H,
544 XMM12, XMM12_H,
545 XMM13, XMM13_H,
546 XMM14, XMM14_H,
547 XMM15, XMM15_H);
548
549 // XMM6 and XMM7 could be used as temporary registers for long, float and
550 // double values for SSE2.
551 reg_class double_reg6( XMM6,XMM6_H );
552 reg_class double_reg7( XMM7,XMM7_H );
553 %}
554
555
556 //----------SOURCE BLOCK-------------------------------------------------------
557 // This is a block of C++ code which provides values, functions, and
558 // definitions necessary in the rest of the architecture description
559 source %{
560 #define RELOC_IMM64 Assembler::imm_operand
561 #define RELOC_DISP32 Assembler::disp32_operand
562
563 #define __ _masm.
564
565 // !!!!! Special hack to get all types of calls to specify the byte offset
566 // from the start of the call to the point where the return address
567 // will point.
568 int MachCallStaticJavaNode::ret_addr_offset()
569 {
570 return 5; // 5 bytes from start of call to where return address points
571 }
572
573 int MachCallDynamicJavaNode::ret_addr_offset()
574 {
575 return 15; // 15 bytes from start of call to where return address points
576 }
577
578 // In os_cpu .ad file
579 // int MachCallRuntimeNode::ret_addr_offset()
580
581 // Indicate if the safepoint node needs the polling page as an input.
582 // Since amd64 does not have absolute addressing but RIP-relative
583 // addressing and the polling page is within 2G, it doesn't.
584 bool SafePointNode::needs_polling_address_input()
585 {
586 return false;
587 }
588
589 //
590 // Compute padding required for nodes which need alignment
591 //
592
593 // The address of the call instruction needs to be 4-byte aligned to
594 // ensure that it does not span a cache line so that it can be patched.
595 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
596 {
597 current_offset += 1; // skip call opcode byte
598 return round_to(current_offset, alignment_required()) - current_offset;
599 }
600
601 // The address of the call instruction needs to be 4-byte aligned to
602 // ensure that it does not span a cache line so that it can be patched.
603 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
604 {
605 current_offset += 11; // skip movq instruction + call opcode byte
606 return round_to(current_offset, alignment_required()) - current_offset;
607 }
608
609 #ifndef PRODUCT
610 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const
611 {
612 st->print("INT3");
613 }
614 #endif
615
616 // EMIT_RM()
617 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3)
618 {
619 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
620 *(cbuf.code_end()) = c;
621 cbuf.set_code_end(cbuf.code_end() + 1);
622 }
623
624 // EMIT_CC()
625 void emit_cc(CodeBuffer &cbuf, int f1, int f2)
626 {
627 unsigned char c = (unsigned char) (f1 | f2);
628 *(cbuf.code_end()) = c;
629 cbuf.set_code_end(cbuf.code_end() + 1);
630 }
631
632 // EMIT_OPCODE()
633 void emit_opcode(CodeBuffer &cbuf, int code)
634 {
635 *(cbuf.code_end()) = (unsigned char) code;
636 cbuf.set_code_end(cbuf.code_end() + 1);
637 }
638
639 // EMIT_OPCODE() w/ relocation information
640 void emit_opcode(CodeBuffer &cbuf,
641 int code, relocInfo::relocType reloc, int offset, int format)
642 {
643 cbuf.relocate(cbuf.inst_mark() + offset, reloc, format);
644 emit_opcode(cbuf, code);
645 }
646
647 // EMIT_D8()
648 void emit_d8(CodeBuffer &cbuf, int d8)
649 {
650 *(cbuf.code_end()) = (unsigned char) d8;
651 cbuf.set_code_end(cbuf.code_end() + 1);
652 }
653
654 // EMIT_D16()
655 void emit_d16(CodeBuffer &cbuf, int d16)
656 {
657 *((short *)(cbuf.code_end())) = d16;
658 cbuf.set_code_end(cbuf.code_end() + 2);
659 }
660
661 // EMIT_D32()
662 void emit_d32(CodeBuffer &cbuf, int d32)
663 {
664 *((int *)(cbuf.code_end())) = d32;
665 cbuf.set_code_end(cbuf.code_end() + 4);
666 }
667
668 // EMIT_D64()
669 void emit_d64(CodeBuffer &cbuf, int64_t d64)
670 {
671 *((int64_t*) (cbuf.code_end())) = d64;
672 cbuf.set_code_end(cbuf.code_end() + 8);
673 }
674
675 // emit 32 bit value and construct relocation entry from relocInfo::relocType
676 void emit_d32_reloc(CodeBuffer& cbuf,
677 int d32,
678 relocInfo::relocType reloc,
679 int format)
680 {
681 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
682 cbuf.relocate(cbuf.inst_mark(), reloc, format);
683
684 *((int*) (cbuf.code_end())) = d32;
685 cbuf.set_code_end(cbuf.code_end() + 4);
686 }
687
688 // emit 32 bit value and construct relocation entry from RelocationHolder
689 void emit_d32_reloc(CodeBuffer& cbuf,
690 int d32,
691 RelocationHolder const& rspec,
692 int format)
693 {
694 #ifdef ASSERT
695 if (rspec.reloc()->type() == relocInfo::oop_type &&
696 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
697 assert(oop((intptr_t)d32)->is_oop() && oop((intptr_t)d32)->is_perm(), "cannot embed non-perm oops in code");
698 }
699 #endif
700 cbuf.relocate(cbuf.inst_mark(), rspec, format);
701
702 *((int* )(cbuf.code_end())) = d32;
703 cbuf.set_code_end(cbuf.code_end() + 4);
704 }
705
706 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
707 address next_ip = cbuf.code_end() + 4;
708 emit_d32_reloc(cbuf, (int) (addr - next_ip),
709 external_word_Relocation::spec(addr),
710 RELOC_DISP32);
711 }
712
713
714 // emit 64 bit value and construct relocation entry from relocInfo::relocType
715 void emit_d64_reloc(CodeBuffer& cbuf,
716 int64_t d64,
717 relocInfo::relocType reloc,
718 int format)
719 {
720 cbuf.relocate(cbuf.inst_mark(), reloc, format);
721
722 *((int64_t*) (cbuf.code_end())) = d64;
723 cbuf.set_code_end(cbuf.code_end() + 8);
724 }
725
726 // emit 64 bit value and construct relocation entry from RelocationHolder
727 void emit_d64_reloc(CodeBuffer& cbuf,
728 int64_t d64,
729 RelocationHolder const& rspec,
730 int format)
731 {
732 #ifdef ASSERT
733 if (rspec.reloc()->type() == relocInfo::oop_type &&
734 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
735 assert(oop(d64)->is_oop() && oop(d64)->is_perm(),
736 "cannot embed non-perm oops in code");
737 }
738 #endif
739 cbuf.relocate(cbuf.inst_mark(), rspec, format);
740
741 *((int64_t*) (cbuf.code_end())) = d64;
742 cbuf.set_code_end(cbuf.code_end() + 8);
743 }
744
745 // Access stack slot for load or store
746 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
747 {
748 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
749 if (-0x80 <= disp && disp < 0x80) {
750 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
751 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
752 emit_d8(cbuf, disp); // Displacement // R/M byte
753 } else {
754 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
755 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
756 emit_d32(cbuf, disp); // Displacement // R/M byte
757 }
758 }
759
760 // rRegI ereg, memory mem) %{ // emit_reg_mem
761 void encode_RegMem(CodeBuffer &cbuf,
762 int reg,
763 int base, int index, int scale, int disp, bool disp_is_oop)
764 {
765 assert(!disp_is_oop, "cannot have disp");
766 int regenc = reg & 7;
767 int baseenc = base & 7;
768 int indexenc = index & 7;
769
770 // There is no index & no scale, use form without SIB byte
771 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
772 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
773 if (disp == 0 && base != RBP_enc && base != R13_enc) {
774 emit_rm(cbuf, 0x0, regenc, baseenc); // *
775 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
776 // If 8-bit displacement, mode 0x1
777 emit_rm(cbuf, 0x1, regenc, baseenc); // *
778 emit_d8(cbuf, disp);
779 } else {
780 // If 32-bit displacement
781 if (base == -1) { // Special flag for absolute address
782 emit_rm(cbuf, 0x0, regenc, 0x5); // *
783 if (disp_is_oop) {
784 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
785 } else {
786 emit_d32(cbuf, disp);
787 }
788 } else {
789 // Normal base + offset
790 emit_rm(cbuf, 0x2, regenc, baseenc); // *
791 if (disp_is_oop) {
792 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
793 } else {
794 emit_d32(cbuf, disp);
795 }
796 }
797 }
798 } else {
799 // Else, encode with the SIB byte
800 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
801 if (disp == 0 && base != RBP_enc && base != R13_enc) {
802 // If no displacement
803 emit_rm(cbuf, 0x0, regenc, 0x4); // *
804 emit_rm(cbuf, scale, indexenc, baseenc);
805 } else {
806 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) {
807 // If 8-bit displacement, mode 0x1
808 emit_rm(cbuf, 0x1, regenc, 0x4); // *
809 emit_rm(cbuf, scale, indexenc, baseenc);
810 emit_d8(cbuf, disp);
811 } else {
812 // If 32-bit displacement
813 if (base == 0x04 ) {
814 emit_rm(cbuf, 0x2, regenc, 0x4);
815 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
816 } else {
817 emit_rm(cbuf, 0x2, regenc, 0x4);
818 emit_rm(cbuf, scale, indexenc, baseenc); // *
819 }
820 if (disp_is_oop) {
821 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
822 } else {
823 emit_d32(cbuf, disp);
824 }
825 }
826 }
827 }
828 }
829
830 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc)
831 {
832 if (dstenc != srcenc) {
833 if (dstenc < 8) {
834 if (srcenc >= 8) {
835 emit_opcode(cbuf, Assembler::REX_B);
836 srcenc -= 8;
837 }
838 } else {
839 if (srcenc < 8) {
840 emit_opcode(cbuf, Assembler::REX_R);
841 } else {
842 emit_opcode(cbuf, Assembler::REX_RB);
843 srcenc -= 8;
844 }
845 dstenc -= 8;
846 }
847
848 emit_opcode(cbuf, 0x8B);
849 emit_rm(cbuf, 0x3, dstenc, srcenc);
850 }
851 }
852
853 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
854 if( dst_encoding == src_encoding ) {
855 // reg-reg copy, use an empty encoding
856 } else {
857 MacroAssembler _masm(&cbuf);
858
859 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
860 }
861 }
862
863
864 //=============================================================================
865 #ifndef PRODUCT
866 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const
867 {
868 Compile* C = ra_->C;
869
870 int framesize = C->frame_slots() << LogBytesPerInt;
871 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
872 // Remove wordSize for return adr already pushed
873 // and another for the RBP we are going to save
874 framesize -= 2*wordSize;
875 bool need_nop = true;
876
877 // Calls to C2R adapters often do not accept exceptional returns.
878 // We require that their callers must bang for them. But be
879 // careful, because some VM calls (such as call site linkage) can
880 // use several kilobytes of stack. But the stack safety zone should
881 // account for that. See bugs 4446381, 4468289, 4497237.
882 if (C->need_stack_bang(framesize)) {
883 st->print_cr("# stack bang"); st->print("\t");
884 need_nop = false;
885 }
886 st->print_cr("pushq rbp"); st->print("\t");
887
888 if (VerifyStackAtCalls) {
889 // Majik cookie to verify stack depth
890 st->print_cr("pushq 0xffffffffbadb100d"
891 "\t# Majik cookie for stack depth check");
892 st->print("\t");
893 framesize -= wordSize; // Remove 2 for cookie
894 need_nop = false;
895 }
896
897 if (framesize) {
898 st->print("subq rsp, #%d\t# Create frame", framesize);
899 if (framesize < 0x80 && need_nop) {
900 st->print("\n\tnop\t# nop for patch_verified_entry");
901 }
902 }
903 }
904 #endif
905
906 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
907 {
908 Compile* C = ra_->C;
909
910 // WARNING: Initial instruction MUST be 5 bytes or longer so that
911 // NativeJump::patch_verified_entry will be able to patch out the entry
912 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
913 // depth is ok at 5 bytes, the frame allocation can be either 3 or
914 // 6 bytes. So if we don't do the fldcw or the push then we must
915 // use the 6 byte frame allocation even if we have no frame. :-(
916 // If method sets FPU control word do it now
917
918 int framesize = C->frame_slots() << LogBytesPerInt;
919 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
920 // Remove wordSize for return adr already pushed
921 // and another for the RBP we are going to save
922 framesize -= 2*wordSize;
923 bool need_nop = true;
924
925 // Calls to C2R adapters often do not accept exceptional returns.
926 // We require that their callers must bang for them. But be
927 // careful, because some VM calls (such as call site linkage) can
928 // use several kilobytes of stack. But the stack safety zone should
929 // account for that. See bugs 4446381, 4468289, 4497237.
930 if (C->need_stack_bang(framesize)) {
931 MacroAssembler masm(&cbuf);
932 masm.generate_stack_overflow_check(framesize);
933 need_nop = false;
934 }
935
936 // We always push rbp so that on return to interpreter rbp will be
937 // restored correctly and we can correct the stack.
938 emit_opcode(cbuf, 0x50 | RBP_enc);
939
940 if (VerifyStackAtCalls) {
941 // Majik cookie to verify stack depth
942 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d
943 emit_d32(cbuf, 0xbadb100d);
944 framesize -= wordSize; // Remove 2 for cookie
945 need_nop = false;
946 }
947
948 if (framesize) {
949 emit_opcode(cbuf, Assembler::REX_W);
950 if (framesize < 0x80) {
951 emit_opcode(cbuf, 0x83); // sub SP,#framesize
952 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
953 emit_d8(cbuf, framesize);
954 if (need_nop) {
955 emit_opcode(cbuf, 0x90); // nop
956 }
957 } else {
958 emit_opcode(cbuf, 0x81); // sub SP,#framesize
959 emit_rm(cbuf, 0x3, 0x05, RSP_enc);
960 emit_d32(cbuf, framesize);
961 }
962 }
963
964 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
965
966 #ifdef ASSERT
967 if (VerifyStackAtCalls) {
968 Label L;
969 MacroAssembler masm(&cbuf);
970 masm.push(rax);
971 masm.mov(rax, rsp);
972 masm.andptr(rax, StackAlignmentInBytes-1);
973 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
974 masm.pop(rax);
975 masm.jcc(Assembler::equal, L);
976 masm.stop("Stack is not properly aligned!");
977 masm.bind(L);
978 }
979 #endif
980 }
981
982 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
983 {
984 return MachNode::size(ra_); // too many variables; just compute it
985 // the hard way
986 }
987
988 int MachPrologNode::reloc() const
989 {
990 return 0; // a large enough number
991 }
992
993 //=============================================================================
994 #ifndef PRODUCT
995 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
996 {
997 Compile* C = ra_->C;
998 int framesize = C->frame_slots() << LogBytesPerInt;
999 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1000 // Remove word for return adr already pushed
1001 // and RBP
1002 framesize -= 2*wordSize;
1003
1004 if (framesize) {
1005 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize);
1006 st->print("\t");
1007 }
1008
1009 st->print_cr("popq\trbp");
1010 if (do_polling() && C->is_method_compilation()) {
1011 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t"
1012 "# Safepoint: poll for GC");
1013 st->print("\t");
1014 }
1015 }
1016 #endif
1017
1018 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1019 {
1020 Compile* C = ra_->C;
1021 int framesize = C->frame_slots() << LogBytesPerInt;
1022 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1023 // Remove word for return adr already pushed
1024 // and RBP
1025 framesize -= 2*wordSize;
1026
1027 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
1028
1029 if (framesize) {
1030 emit_opcode(cbuf, Assembler::REX_W);
1031 if (framesize < 0x80) {
1032 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
1033 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1034 emit_d8(cbuf, framesize);
1035 } else {
1036 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
1037 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
1038 emit_d32(cbuf, framesize);
1039 }
1040 }
1041
1042 // popq rbp
1043 emit_opcode(cbuf, 0x58 | RBP_enc);
1044
1045 if (do_polling() && C->is_method_compilation()) {
1046 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
1047 // XXX reg_mem doesn't support RIP-relative addressing yet
1048 cbuf.set_inst_mark();
1049 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_return_type, 0); // XXX
1050 emit_opcode(cbuf, 0x85); // testl
1051 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
1052 // cbuf.inst_mark() is beginning of instruction
1053 emit_d32_reloc(cbuf, os::get_polling_page());
1054 // relocInfo::poll_return_type,
1055 }
1056 }
1057
1058 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1059 {
1060 Compile* C = ra_->C;
1061 int framesize = C->frame_slots() << LogBytesPerInt;
1062 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
1063 // Remove word for return adr already pushed
1064 // and RBP
1065 framesize -= 2*wordSize;
1066
1067 uint size = 0;
1068
1069 if (do_polling() && C->is_method_compilation()) {
1070 size += 6;
1071 }
1072
1073 // count popq rbp
1074 size++;
1075
1076 if (framesize) {
1077 if (framesize < 0x80) {
1078 size += 4;
1079 } else if (framesize) {
1080 size += 7;
1081 }
1082 }
1083
1084 return size;
1085 }
1086
1087 int MachEpilogNode::reloc() const
1088 {
1089 return 2; // a large enough number
1090 }
1091
1092 const Pipeline* MachEpilogNode::pipeline() const
1093 {
1094 return MachNode::pipeline_class();
1095 }
1096
1097 int MachEpilogNode::safepoint_offset() const
1098 {
1099 return 0;
1100 }
1101
1102 //=============================================================================
1103
1104 enum RC {
1105 rc_bad,
1106 rc_int,
1107 rc_float,
1108 rc_stack
1109 };
1110
1111 static enum RC rc_class(OptoReg::Name reg)
1112 {
1113 if( !OptoReg::is_valid(reg) ) return rc_bad;
1114
1115 if (OptoReg::is_stack(reg)) return rc_stack;
1116
1117 VMReg r = OptoReg::as_VMReg(reg);
1118
1119 if (r->is_Register()) return rc_int;
1120
1121 assert(r->is_XMMRegister(), "must be");
1122 return rc_float;
1123 }
1124
1125 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1126 PhaseRegAlloc* ra_,
1127 bool do_size,
1128 outputStream* st) const
1129 {
1130
1131 // Get registers to move
1132 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1133 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1134 OptoReg::Name dst_second = ra_->get_reg_second(this);
1135 OptoReg::Name dst_first = ra_->get_reg_first(this);
1136
1137 enum RC src_second_rc = rc_class(src_second);
1138 enum RC src_first_rc = rc_class(src_first);
1139 enum RC dst_second_rc = rc_class(dst_second);
1140 enum RC dst_first_rc = rc_class(dst_first);
1141
1142 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1143 "must move at least 1 register" );
1144
1145 if (src_first == dst_first && src_second == dst_second) {
1146 // Self copy, no move
1147 return 0;
1148 } else if (src_first_rc == rc_stack) {
1149 // mem ->
1150 if (dst_first_rc == rc_stack) {
1151 // mem -> mem
1152 assert(src_second != dst_first, "overlap");
1153 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1154 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1155 // 64-bit
1156 int src_offset = ra_->reg2offset(src_first);
1157 int dst_offset = ra_->reg2offset(dst_first);
1158 if (cbuf) {
1159 emit_opcode(*cbuf, 0xFF);
1160 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false);
1161
1162 emit_opcode(*cbuf, 0x8F);
1163 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false);
1164
1165 #ifndef PRODUCT
1166 } else if (!do_size) {
1167 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1168 "popq [rsp + #%d]",
1169 src_offset,
1170 dst_offset);
1171 #endif
1172 }
1173 return
1174 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) +
1175 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4));
1176 } else {
1177 // 32-bit
1178 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1179 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1180 // No pushl/popl, so:
1181 int src_offset = ra_->reg2offset(src_first);
1182 int dst_offset = ra_->reg2offset(dst_first);
1183 if (cbuf) {
1184 emit_opcode(*cbuf, Assembler::REX_W);
1185 emit_opcode(*cbuf, 0x89);
1186 emit_opcode(*cbuf, 0x44);
1187 emit_opcode(*cbuf, 0x24);
1188 emit_opcode(*cbuf, 0xF8);
1189
1190 emit_opcode(*cbuf, 0x8B);
1191 encode_RegMem(*cbuf,
1192 RAX_enc,
1193 RSP_enc, 0x4, 0, src_offset,
1194 false);
1195
1196 emit_opcode(*cbuf, 0x89);
1197 encode_RegMem(*cbuf,
1198 RAX_enc,
1199 RSP_enc, 0x4, 0, dst_offset,
1200 false);
1201
1202 emit_opcode(*cbuf, Assembler::REX_W);
1203 emit_opcode(*cbuf, 0x8B);
1204 emit_opcode(*cbuf, 0x44);
1205 emit_opcode(*cbuf, 0x24);
1206 emit_opcode(*cbuf, 0xF8);
1207
1208 #ifndef PRODUCT
1209 } else if (!do_size) {
1210 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1211 "movl rax, [rsp + #%d]\n\t"
1212 "movl [rsp + #%d], rax\n\t"
1213 "movq rax, [rsp - #8]",
1214 src_offset,
1215 dst_offset);
1216 #endif
1217 }
1218 return
1219 5 + // movq
1220 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl
1221 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl
1222 5; // movq
1223 }
1224 } else if (dst_first_rc == rc_int) {
1225 // mem -> gpr
1226 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1227 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1228 // 64-bit
1229 int offset = ra_->reg2offset(src_first);
1230 if (cbuf) {
1231 if (Matcher::_regEncode[dst_first] < 8) {
1232 emit_opcode(*cbuf, Assembler::REX_W);
1233 } else {
1234 emit_opcode(*cbuf, Assembler::REX_WR);
1235 }
1236 emit_opcode(*cbuf, 0x8B);
1237 encode_RegMem(*cbuf,
1238 Matcher::_regEncode[dst_first],
1239 RSP_enc, 0x4, 0, offset,
1240 false);
1241 #ifndef PRODUCT
1242 } else if (!do_size) {
1243 st->print("movq %s, [rsp + #%d]\t# spill",
1244 Matcher::regName[dst_first],
1245 offset);
1246 #endif
1247 }
1248 return
1249 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1250 } else {
1251 // 32-bit
1252 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1253 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1254 int offset = ra_->reg2offset(src_first);
1255 if (cbuf) {
1256 if (Matcher::_regEncode[dst_first] >= 8) {
1257 emit_opcode(*cbuf, Assembler::REX_R);
1258 }
1259 emit_opcode(*cbuf, 0x8B);
1260 encode_RegMem(*cbuf,
1261 Matcher::_regEncode[dst_first],
1262 RSP_enc, 0x4, 0, offset,
1263 false);
1264 #ifndef PRODUCT
1265 } else if (!do_size) {
1266 st->print("movl %s, [rsp + #%d]\t# spill",
1267 Matcher::regName[dst_first],
1268 offset);
1269 #endif
1270 }
1271 return
1272 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1273 ((Matcher::_regEncode[dst_first] < 8)
1274 ? 3
1275 : 4); // REX
1276 }
1277 } else if (dst_first_rc == rc_float) {
1278 // mem-> xmm
1279 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1280 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1281 // 64-bit
1282 int offset = ra_->reg2offset(src_first);
1283 if (cbuf) {
1284 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1285 if (Matcher::_regEncode[dst_first] >= 8) {
1286 emit_opcode(*cbuf, Assembler::REX_R);
1287 }
1288 emit_opcode(*cbuf, 0x0F);
1289 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1290 encode_RegMem(*cbuf,
1291 Matcher::_regEncode[dst_first],
1292 RSP_enc, 0x4, 0, offset,
1293 false);
1294 #ifndef PRODUCT
1295 } else if (!do_size) {
1296 st->print("%s %s, [rsp + #%d]\t# spill",
1297 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1298 Matcher::regName[dst_first],
1299 offset);
1300 #endif
1301 }
1302 return
1303 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1304 ((Matcher::_regEncode[dst_first] < 8)
1305 ? 5
1306 : 6); // REX
1307 } else {
1308 // 32-bit
1309 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1310 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1311 int offset = ra_->reg2offset(src_first);
1312 if (cbuf) {
1313 emit_opcode(*cbuf, 0xF3);
1314 if (Matcher::_regEncode[dst_first] >= 8) {
1315 emit_opcode(*cbuf, Assembler::REX_R);
1316 }
1317 emit_opcode(*cbuf, 0x0F);
1318 emit_opcode(*cbuf, 0x10);
1319 encode_RegMem(*cbuf,
1320 Matcher::_regEncode[dst_first],
1321 RSP_enc, 0x4, 0, offset,
1322 false);
1323 #ifndef PRODUCT
1324 } else if (!do_size) {
1325 st->print("movss %s, [rsp + #%d]\t# spill",
1326 Matcher::regName[dst_first],
1327 offset);
1328 #endif
1329 }
1330 return
1331 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1332 ((Matcher::_regEncode[dst_first] < 8)
1333 ? 5
1334 : 6); // REX
1335 }
1336 }
1337 } else if (src_first_rc == rc_int) {
1338 // gpr ->
1339 if (dst_first_rc == rc_stack) {
1340 // gpr -> mem
1341 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1342 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1343 // 64-bit
1344 int offset = ra_->reg2offset(dst_first);
1345 if (cbuf) {
1346 if (Matcher::_regEncode[src_first] < 8) {
1347 emit_opcode(*cbuf, Assembler::REX_W);
1348 } else {
1349 emit_opcode(*cbuf, Assembler::REX_WR);
1350 }
1351 emit_opcode(*cbuf, 0x89);
1352 encode_RegMem(*cbuf,
1353 Matcher::_regEncode[src_first],
1354 RSP_enc, 0x4, 0, offset,
1355 false);
1356 #ifndef PRODUCT
1357 } else if (!do_size) {
1358 st->print("movq [rsp + #%d], %s\t# spill",
1359 offset,
1360 Matcher::regName[src_first]);
1361 #endif
1362 }
1363 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX
1364 } else {
1365 // 32-bit
1366 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1367 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1368 int offset = ra_->reg2offset(dst_first);
1369 if (cbuf) {
1370 if (Matcher::_regEncode[src_first] >= 8) {
1371 emit_opcode(*cbuf, Assembler::REX_R);
1372 }
1373 emit_opcode(*cbuf, 0x89);
1374 encode_RegMem(*cbuf,
1375 Matcher::_regEncode[src_first],
1376 RSP_enc, 0x4, 0, offset,
1377 false);
1378 #ifndef PRODUCT
1379 } else if (!do_size) {
1380 st->print("movl [rsp + #%d], %s\t# spill",
1381 offset,
1382 Matcher::regName[src_first]);
1383 #endif
1384 }
1385 return
1386 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1387 ((Matcher::_regEncode[src_first] < 8)
1388 ? 3
1389 : 4); // REX
1390 }
1391 } else if (dst_first_rc == rc_int) {
1392 // gpr -> gpr
1393 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1394 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1395 // 64-bit
1396 if (cbuf) {
1397 if (Matcher::_regEncode[dst_first] < 8) {
1398 if (Matcher::_regEncode[src_first] < 8) {
1399 emit_opcode(*cbuf, Assembler::REX_W);
1400 } else {
1401 emit_opcode(*cbuf, Assembler::REX_WB);
1402 }
1403 } else {
1404 if (Matcher::_regEncode[src_first] < 8) {
1405 emit_opcode(*cbuf, Assembler::REX_WR);
1406 } else {
1407 emit_opcode(*cbuf, Assembler::REX_WRB);
1408 }
1409 }
1410 emit_opcode(*cbuf, 0x8B);
1411 emit_rm(*cbuf, 0x3,
1412 Matcher::_regEncode[dst_first] & 7,
1413 Matcher::_regEncode[src_first] & 7);
1414 #ifndef PRODUCT
1415 } else if (!do_size) {
1416 st->print("movq %s, %s\t# spill",
1417 Matcher::regName[dst_first],
1418 Matcher::regName[src_first]);
1419 #endif
1420 }
1421 return 3; // REX
1422 } else {
1423 // 32-bit
1424 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1425 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1426 if (cbuf) {
1427 if (Matcher::_regEncode[dst_first] < 8) {
1428 if (Matcher::_regEncode[src_first] >= 8) {
1429 emit_opcode(*cbuf, Assembler::REX_B);
1430 }
1431 } else {
1432 if (Matcher::_regEncode[src_first] < 8) {
1433 emit_opcode(*cbuf, Assembler::REX_R);
1434 } else {
1435 emit_opcode(*cbuf, Assembler::REX_RB);
1436 }
1437 }
1438 emit_opcode(*cbuf, 0x8B);
1439 emit_rm(*cbuf, 0x3,
1440 Matcher::_regEncode[dst_first] & 7,
1441 Matcher::_regEncode[src_first] & 7);
1442 #ifndef PRODUCT
1443 } else if (!do_size) {
1444 st->print("movl %s, %s\t# spill",
1445 Matcher::regName[dst_first],
1446 Matcher::regName[src_first]);
1447 #endif
1448 }
1449 return
1450 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1451 ? 2
1452 : 3; // REX
1453 }
1454 } else if (dst_first_rc == rc_float) {
1455 // gpr -> xmm
1456 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1457 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1458 // 64-bit
1459 if (cbuf) {
1460 emit_opcode(*cbuf, 0x66);
1461 if (Matcher::_regEncode[dst_first] < 8) {
1462 if (Matcher::_regEncode[src_first] < 8) {
1463 emit_opcode(*cbuf, Assembler::REX_W);
1464 } else {
1465 emit_opcode(*cbuf, Assembler::REX_WB);
1466 }
1467 } else {
1468 if (Matcher::_regEncode[src_first] < 8) {
1469 emit_opcode(*cbuf, Assembler::REX_WR);
1470 } else {
1471 emit_opcode(*cbuf, Assembler::REX_WRB);
1472 }
1473 }
1474 emit_opcode(*cbuf, 0x0F);
1475 emit_opcode(*cbuf, 0x6E);
1476 emit_rm(*cbuf, 0x3,
1477 Matcher::_regEncode[dst_first] & 7,
1478 Matcher::_regEncode[src_first] & 7);
1479 #ifndef PRODUCT
1480 } else if (!do_size) {
1481 st->print("movdq %s, %s\t# spill",
1482 Matcher::regName[dst_first],
1483 Matcher::regName[src_first]);
1484 #endif
1485 }
1486 return 5; // REX
1487 } else {
1488 // 32-bit
1489 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1490 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1491 if (cbuf) {
1492 emit_opcode(*cbuf, 0x66);
1493 if (Matcher::_regEncode[dst_first] < 8) {
1494 if (Matcher::_regEncode[src_first] >= 8) {
1495 emit_opcode(*cbuf, Assembler::REX_B);
1496 }
1497 } else {
1498 if (Matcher::_regEncode[src_first] < 8) {
1499 emit_opcode(*cbuf, Assembler::REX_R);
1500 } else {
1501 emit_opcode(*cbuf, Assembler::REX_RB);
1502 }
1503 }
1504 emit_opcode(*cbuf, 0x0F);
1505 emit_opcode(*cbuf, 0x6E);
1506 emit_rm(*cbuf, 0x3,
1507 Matcher::_regEncode[dst_first] & 7,
1508 Matcher::_regEncode[src_first] & 7);
1509 #ifndef PRODUCT
1510 } else if (!do_size) {
1511 st->print("movdl %s, %s\t# spill",
1512 Matcher::regName[dst_first],
1513 Matcher::regName[src_first]);
1514 #endif
1515 }
1516 return
1517 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1518 ? 4
1519 : 5; // REX
1520 }
1521 }
1522 } else if (src_first_rc == rc_float) {
1523 // xmm ->
1524 if (dst_first_rc == rc_stack) {
1525 // xmm -> mem
1526 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1527 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1528 // 64-bit
1529 int offset = ra_->reg2offset(dst_first);
1530 if (cbuf) {
1531 emit_opcode(*cbuf, 0xF2);
1532 if (Matcher::_regEncode[src_first] >= 8) {
1533 emit_opcode(*cbuf, Assembler::REX_R);
1534 }
1535 emit_opcode(*cbuf, 0x0F);
1536 emit_opcode(*cbuf, 0x11);
1537 encode_RegMem(*cbuf,
1538 Matcher::_regEncode[src_first],
1539 RSP_enc, 0x4, 0, offset,
1540 false);
1541 #ifndef PRODUCT
1542 } else if (!do_size) {
1543 st->print("movsd [rsp + #%d], %s\t# spill",
1544 offset,
1545 Matcher::regName[src_first]);
1546 #endif
1547 }
1548 return
1549 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1550 ((Matcher::_regEncode[src_first] < 8)
1551 ? 5
1552 : 6); // REX
1553 } else {
1554 // 32-bit
1555 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1556 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1557 int offset = ra_->reg2offset(dst_first);
1558 if (cbuf) {
1559 emit_opcode(*cbuf, 0xF3);
1560 if (Matcher::_regEncode[src_first] >= 8) {
1561 emit_opcode(*cbuf, Assembler::REX_R);
1562 }
1563 emit_opcode(*cbuf, 0x0F);
1564 emit_opcode(*cbuf, 0x11);
1565 encode_RegMem(*cbuf,
1566 Matcher::_regEncode[src_first],
1567 RSP_enc, 0x4, 0, offset,
1568 false);
1569 #ifndef PRODUCT
1570 } else if (!do_size) {
1571 st->print("movss [rsp + #%d], %s\t# spill",
1572 offset,
1573 Matcher::regName[src_first]);
1574 #endif
1575 }
1576 return
1577 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) +
1578 ((Matcher::_regEncode[src_first] < 8)
1579 ? 5
1580 : 6); // REX
1581 }
1582 } else if (dst_first_rc == rc_int) {
1583 // xmm -> gpr
1584 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1585 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1586 // 64-bit
1587 if (cbuf) {
1588 emit_opcode(*cbuf, 0x66);
1589 if (Matcher::_regEncode[dst_first] < 8) {
1590 if (Matcher::_regEncode[src_first] < 8) {
1591 emit_opcode(*cbuf, Assembler::REX_W);
1592 } else {
1593 emit_opcode(*cbuf, Assembler::REX_WR); // attention!
1594 }
1595 } else {
1596 if (Matcher::_regEncode[src_first] < 8) {
1597 emit_opcode(*cbuf, Assembler::REX_WB); // attention!
1598 } else {
1599 emit_opcode(*cbuf, Assembler::REX_WRB);
1600 }
1601 }
1602 emit_opcode(*cbuf, 0x0F);
1603 emit_opcode(*cbuf, 0x7E);
1604 emit_rm(*cbuf, 0x3,
1605 Matcher::_regEncode[dst_first] & 7,
1606 Matcher::_regEncode[src_first] & 7);
1607 #ifndef PRODUCT
1608 } else if (!do_size) {
1609 st->print("movdq %s, %s\t# spill",
1610 Matcher::regName[dst_first],
1611 Matcher::regName[src_first]);
1612 #endif
1613 }
1614 return 5; // REX
1615 } else {
1616 // 32-bit
1617 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1618 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1619 if (cbuf) {
1620 emit_opcode(*cbuf, 0x66);
1621 if (Matcher::_regEncode[dst_first] < 8) {
1622 if (Matcher::_regEncode[src_first] >= 8) {
1623 emit_opcode(*cbuf, Assembler::REX_R); // attention!
1624 }
1625 } else {
1626 if (Matcher::_regEncode[src_first] < 8) {
1627 emit_opcode(*cbuf, Assembler::REX_B); // attention!
1628 } else {
1629 emit_opcode(*cbuf, Assembler::REX_RB);
1630 }
1631 }
1632 emit_opcode(*cbuf, 0x0F);
1633 emit_opcode(*cbuf, 0x7E);
1634 emit_rm(*cbuf, 0x3,
1635 Matcher::_regEncode[dst_first] & 7,
1636 Matcher::_regEncode[src_first] & 7);
1637 #ifndef PRODUCT
1638 } else if (!do_size) {
1639 st->print("movdl %s, %s\t# spill",
1640 Matcher::regName[dst_first],
1641 Matcher::regName[src_first]);
1642 #endif
1643 }
1644 return
1645 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1646 ? 4
1647 : 5; // REX
1648 }
1649 } else if (dst_first_rc == rc_float) {
1650 // xmm -> xmm
1651 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1652 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1653 // 64-bit
1654 if (cbuf) {
1655 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
1656 if (Matcher::_regEncode[dst_first] < 8) {
1657 if (Matcher::_regEncode[src_first] >= 8) {
1658 emit_opcode(*cbuf, Assembler::REX_B);
1659 }
1660 } else {
1661 if (Matcher::_regEncode[src_first] < 8) {
1662 emit_opcode(*cbuf, Assembler::REX_R);
1663 } else {
1664 emit_opcode(*cbuf, Assembler::REX_RB);
1665 }
1666 }
1667 emit_opcode(*cbuf, 0x0F);
1668 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1669 emit_rm(*cbuf, 0x3,
1670 Matcher::_regEncode[dst_first] & 7,
1671 Matcher::_regEncode[src_first] & 7);
1672 #ifndef PRODUCT
1673 } else if (!do_size) {
1674 st->print("%s %s, %s\t# spill",
1675 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1676 Matcher::regName[dst_first],
1677 Matcher::regName[src_first]);
1678 #endif
1679 }
1680 return
1681 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1682 ? 4
1683 : 5; // REX
1684 } else {
1685 // 32-bit
1686 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1687 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1688 if (cbuf) {
1689 if (!UseXmmRegToRegMoveAll)
1690 emit_opcode(*cbuf, 0xF3);
1691 if (Matcher::_regEncode[dst_first] < 8) {
1692 if (Matcher::_regEncode[src_first] >= 8) {
1693 emit_opcode(*cbuf, Assembler::REX_B);
1694 }
1695 } else {
1696 if (Matcher::_regEncode[src_first] < 8) {
1697 emit_opcode(*cbuf, Assembler::REX_R);
1698 } else {
1699 emit_opcode(*cbuf, Assembler::REX_RB);
1700 }
1701 }
1702 emit_opcode(*cbuf, 0x0F);
1703 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
1704 emit_rm(*cbuf, 0x3,
1705 Matcher::_regEncode[dst_first] & 7,
1706 Matcher::_regEncode[src_first] & 7);
1707 #ifndef PRODUCT
1708 } else if (!do_size) {
1709 st->print("%s %s, %s\t# spill",
1710 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1711 Matcher::regName[dst_first],
1712 Matcher::regName[src_first]);
1713 #endif
1714 }
1715 return
1716 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8)
1717 ? (UseXmmRegToRegMoveAll ? 3 : 4)
1718 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX
1719 }
1720 }
1721 }
1722
1723 assert(0," foo ");
1724 Unimplemented();
1725
1726 return 0;
1727 }
1728
1729 #ifndef PRODUCT
1730 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const
1731 {
1732 implementation(NULL, ra_, false, st);
1733 }
1734 #endif
1735
1736 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const
1737 {
1738 implementation(&cbuf, ra_, false, NULL);
1739 }
1740
1741 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const
1742 {
1743 return implementation(NULL, ra_, true, NULL);
1744 }
1745
1746 //=============================================================================
1747 #ifndef PRODUCT
1748 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const
1749 {
1750 st->print("nop \t# %d bytes pad for loops and calls", _count);
1751 }
1752 #endif
1753
1754 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const
1755 {
1756 MacroAssembler _masm(&cbuf);
1757 __ nop(_count);
1758 }
1759
1760 uint MachNopNode::size(PhaseRegAlloc*) const
1761 {
1762 return _count;
1763 }
1764
1765
1766 //=============================================================================
1767 #ifndef PRODUCT
1768 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1769 {
1770 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1771 int reg = ra_->get_reg_first(this);
1772 st->print("leaq %s, [rsp + #%d]\t# box lock",
1773 Matcher::regName[reg], offset);
1774 }
1775 #endif
1776
1777 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1778 {
1779 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1780 int reg = ra_->get_encode(this);
1781 if (offset >= 0x80) {
1782 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1783 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1784 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1785 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1786 emit_d32(cbuf, offset);
1787 } else {
1788 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1789 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1790 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1791 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1792 emit_d8(cbuf, offset);
1793 }
1794 }
1795
1796 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1797 {
1798 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1799 return (offset < 0x80) ? 5 : 8; // REX
1800 }
1801
1802 //=============================================================================
1803
1804 // emit call stub, compiled java to interpreter
1805 void emit_java_to_interp(CodeBuffer& cbuf)
1806 {
1807 // Stub is fixed up when the corresponding call is converted from
1808 // calling compiled code to calling interpreted code.
1809 // movq rbx, 0
1810 // jmp -5 # to self
1811
1812 address mark = cbuf.inst_mark(); // get mark within main instrs section
1813
1814 // Note that the code buffer's inst_mark is always relative to insts.
1815 // That's why we must use the macroassembler to generate a stub.
1816 MacroAssembler _masm(&cbuf);
1817
1818 address base =
1819 __ start_a_stub(Compile::MAX_stubs_size);
1820 if (base == NULL) return; // CodeBuffer::expand failed
1821 // static stub relocation stores the instruction address of the call
1822 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64);
1823 // static stub relocation also tags the methodOop in the code-stream.
1824 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time
1825 // This is recognized as unresolved by relocs/nativeinst/ic code
1826 __ jump(RuntimeAddress(__ pc()));
1827
1828 // Update current stubs pointer and restore code_end.
1829 __ end_a_stub();
1830 }
1831
1832 // size of call stub, compiled java to interpretor
1833 uint size_java_to_interp()
1834 {
1835 return 15; // movq (1+1+8); jmp (1+4)
1836 }
1837
1838 // relocation entries for call stub, compiled java to interpretor
1839 uint reloc_java_to_interp()
1840 {
1841 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1842 }
1843
1844 //=============================================================================
1845 #ifndef PRODUCT
1846 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1847 {
1848 if (UseCompressedOops) {
1849 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t", oopDesc::klass_offset_in_bytes());
1850 st->print_cr("leaq rscratch1, [r12_heapbase, r, Address::times_8, 0]");
1851 st->print_cr("cmpq rax, rscratch1\t # Inline cache check");
1852 } else {
1853 st->print_cr("cmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes() #%d]\t"
1854 "# Inline cache check", oopDesc::klass_offset_in_bytes());
1855 }
1856 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1857 st->print_cr("\tnop");
1858 if (!OptoBreakpoint) {
1859 st->print_cr("\tnop");
1860 }
1861 }
1862 #endif
1863
1864 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1865 {
1866 MacroAssembler masm(&cbuf);
1867 #ifdef ASSERT
1868 uint code_size = cbuf.code_size();
1869 #endif
1870 if (UseCompressedOops) {
1871 masm.load_klass(rscratch1, j_rarg0);
1872 masm.cmpptr(rax, rscratch1);
1873 } else {
1874 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1875 }
1876
1877 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1878
1879 /* WARNING these NOPs are critical so that verified entry point is properly
1880 aligned for patching by NativeJump::patch_verified_entry() */
1881 int nops_cnt = 1;
1882 if (!OptoBreakpoint) {
1883 // Leave space for int3
1884 nops_cnt += 1;
1885 }
1886 if (UseCompressedOops) {
1887 // ??? divisible by 4 is aligned?
1888 nops_cnt += 1;
1889 }
1890 masm.nop(nops_cnt);
1891
1892 assert(cbuf.code_size() - code_size == size(ra_),
1893 "checking code size of inline cache node");
1894 }
1895
1896 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1897 {
1898 if (UseCompressedOops) {
1899 return OptoBreakpoint ? 19 : 20;
1900 } else {
1901 return OptoBreakpoint ? 11 : 12;
1902 }
1903 }
1904
1905
1906 //=============================================================================
1907 uint size_exception_handler()
1908 {
1909 // NativeCall instruction size is the same as NativeJump.
1910 // Note that this value is also credited (in output.cpp) to
1911 // the size of the code section.
1912 return NativeJump::instruction_size;
1913 }
1914
1915 // Emit exception handler code.
1916 int emit_exception_handler(CodeBuffer& cbuf)
1917 {
1918
1919 // Note that the code buffer's inst_mark is always relative to insts.
1920 // That's why we must use the macroassembler to generate a handler.
1921 MacroAssembler _masm(&cbuf);
1922 address base =
1923 __ start_a_stub(size_exception_handler());
1924 if (base == NULL) return 0; // CodeBuffer::expand failed
1925 int offset = __ offset();
1926 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1927 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1928 __ end_a_stub();
1929 return offset;
1930 }
1931
1932 uint size_deopt_handler()
1933 {
1934 // three 5 byte instructions
1935 return 15;
1936 }
1937
1938 // Emit deopt handler code.
1939 int emit_deopt_handler(CodeBuffer& cbuf)
1940 {
1941
1942 // Note that the code buffer's inst_mark is always relative to insts.
1943 // That's why we must use the macroassembler to generate a handler.
1944 MacroAssembler _masm(&cbuf);
1945 address base =
1946 __ start_a_stub(size_deopt_handler());
1947 if (base == NULL) return 0; // CodeBuffer::expand failed
1948 int offset = __ offset();
1949 address the_pc = (address) __ pc();
1950 Label next;
1951 // push a "the_pc" on the stack without destroying any registers
1952 // as they all may be live.
1953
1954 // push address of "next"
1955 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32
1956 __ bind(next);
1957 // adjust it so it matches "the_pc"
1958 __ subptr(Address(rsp, 0), __ offset() - offset);
1959 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1960 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1961 __ end_a_stub();
1962 return offset;
1963 }
1964
1965 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1966 int mark = cbuf.insts()->mark_off();
1967 MacroAssembler _masm(&cbuf);
1968 address double_address = __ double_constant(x);
1969 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1970 emit_d32_reloc(cbuf,
1971 (int) (double_address - cbuf.code_end() - 4),
1972 internal_word_Relocation::spec(double_address),
1973 RELOC_DISP32);
1974 }
1975
1976 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1977 int mark = cbuf.insts()->mark_off();
1978 MacroAssembler _masm(&cbuf);
1979 address float_address = __ float_constant(x);
1980 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1981 emit_d32_reloc(cbuf,
1982 (int) (float_address - cbuf.code_end() - 4),
1983 internal_word_Relocation::spec(float_address),
1984 RELOC_DISP32);
1985 }
1986
1987
1988 int Matcher::regnum_to_fpu_offset(int regnum)
1989 {
1990 return regnum - 32; // The FP registers are in the second chunk
1991 }
1992
1993 // This is UltraSparc specific, true just means we have fast l2f conversion
1994 const bool Matcher::convL2FSupported(void) {
1995 return true;
1996 }
1997
1998 // Vector width in bytes
1999 const uint Matcher::vector_width_in_bytes(void) {
2000 return 8;
2001 }
2002
2003 // Vector ideal reg
2004 const uint Matcher::vector_ideal_reg(void) {
2005 return Op_RegD;
2006 }
2007
2008 // Is this branch offset short enough that a short branch can be used?
2009 //
2010 // NOTE: If the platform does not provide any short branch variants, then
2011 // this method should return false for offset 0.
2012 bool Matcher::is_short_branch_offset(int rule, int offset) {
2013 // the short version of jmpConUCF2 contains multiple branches,
2014 // making the reach slightly less
2015 if (rule == jmpConUCF2_rule)
2016 return (-126 <= offset && offset <= 125);
2017 return (-128 <= offset && offset <= 127);
2018 }
2019
2020 const bool Matcher::isSimpleConstant64(jlong value) {
2021 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
2022 //return value == (int) value; // Cf. storeImmL and immL32.
2023
2024 // Probably always true, even if a temp register is required.
2025 return true;
2026 }
2027
2028 // The ecx parameter to rep stosq for the ClearArray node is in words.
2029 const bool Matcher::init_array_count_is_in_bytes = false;
2030
2031 // Threshold size for cleararray.
2032 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2033
2034 // Should the Matcher clone shifts on addressing modes, expecting them
2035 // to be subsumed into complex addressing expressions or compute them
2036 // into registers? True for Intel but false for most RISCs
2037 const bool Matcher::clone_shift_expressions = true;
2038
2039 // Is it better to copy float constants, or load them directly from
2040 // memory? Intel can load a float constant from a direct address,
2041 // requiring no extra registers. Most RISCs will have to materialize
2042 // an address into a register first, so they would do better to copy
2043 // the constant from stack.
2044 const bool Matcher::rematerialize_float_constants = true; // XXX
2045
2046 // If CPU can load and store mis-aligned doubles directly then no
2047 // fixup is needed. Else we split the double into 2 integer pieces
2048 // and move it piece-by-piece. Only happens when passing doubles into
2049 // C code as the Java calling convention forces doubles to be aligned.
2050 const bool Matcher::misaligned_doubles_ok = true;
2051
2052 // No-op on amd64
2053 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
2054
2055 // Advertise here if the CPU requires explicit rounding operations to
2056 // implement the UseStrictFP mode.
2057 const bool Matcher::strict_fp_requires_explicit_rounding = true;
2058
2059 // Do floats take an entire double register or just half?
2060 const bool Matcher::float_in_double = true;
2061 // Do ints take an entire long register or just half?
2062 const bool Matcher::int_in_long = true;
2063
2064 // Return whether or not this register is ever used as an argument.
2065 // This function is used on startup to build the trampoline stubs in
2066 // generateOptoStub. Registers not mentioned will be killed by the VM
2067 // call in the trampoline, and arguments in those registers not be
2068 // available to the callee.
2069 bool Matcher::can_be_java_arg(int reg)
2070 {
2071 return
2072 reg == RDI_num || reg == RDI_H_num ||
2073 reg == RSI_num || reg == RSI_H_num ||
2074 reg == RDX_num || reg == RDX_H_num ||
2075 reg == RCX_num || reg == RCX_H_num ||
2076 reg == R8_num || reg == R8_H_num ||
2077 reg == R9_num || reg == R9_H_num ||
2078 reg == R12_num || reg == R12_H_num ||
2079 reg == XMM0_num || reg == XMM0_H_num ||
2080 reg == XMM1_num || reg == XMM1_H_num ||
2081 reg == XMM2_num || reg == XMM2_H_num ||
2082 reg == XMM3_num || reg == XMM3_H_num ||
2083 reg == XMM4_num || reg == XMM4_H_num ||
2084 reg == XMM5_num || reg == XMM5_H_num ||
2085 reg == XMM6_num || reg == XMM6_H_num ||
2086 reg == XMM7_num || reg == XMM7_H_num;
2087 }
2088
2089 bool Matcher::is_spillable_arg(int reg)
2090 {
2091 return can_be_java_arg(reg);
2092 }
2093
2094 // Register for DIVI projection of divmodI
2095 RegMask Matcher::divI_proj_mask() {
2096 return INT_RAX_REG_mask;
2097 }
2098
2099 // Register for MODI projection of divmodI
2100 RegMask Matcher::modI_proj_mask() {
2101 return INT_RDX_REG_mask;
2102 }
2103
2104 // Register for DIVL projection of divmodL
2105 RegMask Matcher::divL_proj_mask() {
2106 return LONG_RAX_REG_mask;
2107 }
2108
2109 // Register for MODL projection of divmodL
2110 RegMask Matcher::modL_proj_mask() {
2111 return LONG_RDX_REG_mask;
2112 }
2113
2114 static Address build_address(int b, int i, int s, int d) {
2115 Register index = as_Register(i);
2116 Address::ScaleFactor scale = (Address::ScaleFactor)s;
2117 if (index == rsp) {
2118 index = noreg;
2119 scale = Address::no_scale;
2120 }
2121 Address addr(as_Register(b), index, scale, d);
2122 return addr;
2123 }
2124
2125 %}
2126
2127 //----------ENCODING BLOCK-----------------------------------------------------
2128 // This block specifies the encoding classes used by the compiler to
2129 // output byte streams. Encoding classes are parameterized macros
2130 // used by Machine Instruction Nodes in order to generate the bit
2131 // encoding of the instruction. Operands specify their base encoding
2132 // interface with the interface keyword. There are currently
2133 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
2134 // COND_INTER. REG_INTER causes an operand to generate a function
2135 // which returns its register number when queried. CONST_INTER causes
2136 // an operand to generate a function which returns the value of the
2137 // constant when queried. MEMORY_INTER causes an operand to generate
2138 // four functions which return the Base Register, the Index Register,
2139 // the Scale Value, and the Offset Value of the operand when queried.
2140 // COND_INTER causes an operand to generate six functions which return
2141 // the encoding code (ie - encoding bits for the instruction)
2142 // associated with each basic boolean condition for a conditional
2143 // instruction.
2144 //
2145 // Instructions specify two basic values for encoding. Again, a
2146 // function is available to check if the constant displacement is an
2147 // oop. They use the ins_encode keyword to specify their encoding
2148 // classes (which must be a sequence of enc_class names, and their
2149 // parameters, specified in the encoding block), and they use the
2150 // opcode keyword to specify, in order, their primary, secondary, and
2151 // tertiary opcode. Only the opcode sections which a particular
2152 // instruction needs for encoding need to be specified.
2153 encode %{
2154 // Build emit functions for each basic byte or larger field in the
2155 // intel encoding scheme (opcode, rm, sib, immediate), and call them
2156 // from C++ code in the enc_class source block. Emit functions will
2157 // live in the main source block for now. In future, we can
2158 // generalize this by adding a syntax that specifies the sizes of
2159 // fields in an order, so that the adlc can build the emit functions
2160 // automagically
2161
2162 // Emit primary opcode
2163 enc_class OpcP
2164 %{
2165 emit_opcode(cbuf, $primary);
2166 %}
2167
2168 // Emit secondary opcode
2169 enc_class OpcS
2170 %{
2171 emit_opcode(cbuf, $secondary);
2172 %}
2173
2174 // Emit tertiary opcode
2175 enc_class OpcT
2176 %{
2177 emit_opcode(cbuf, $tertiary);
2178 %}
2179
2180 // Emit opcode directly
2181 enc_class Opcode(immI d8)
2182 %{
2183 emit_opcode(cbuf, $d8$$constant);
2184 %}
2185
2186 // Emit size prefix
2187 enc_class SizePrefix
2188 %{
2189 emit_opcode(cbuf, 0x66);
2190 %}
2191
2192 enc_class reg(rRegI reg)
2193 %{
2194 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
2195 %}
2196
2197 enc_class reg_reg(rRegI dst, rRegI src)
2198 %{
2199 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2200 %}
2201
2202 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
2203 %{
2204 emit_opcode(cbuf, $opcode$$constant);
2205 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2206 %}
2207
2208 enc_class cmpfp_fixup()
2209 %{
2210 // jnp,s exit
2211 emit_opcode(cbuf, 0x7B);
2212 emit_d8(cbuf, 0x0A);
2213
2214 // pushfq
2215 emit_opcode(cbuf, 0x9C);
2216
2217 // andq $0xffffff2b, (%rsp)
2218 emit_opcode(cbuf, Assembler::REX_W);
2219 emit_opcode(cbuf, 0x81);
2220 emit_opcode(cbuf, 0x24);
2221 emit_opcode(cbuf, 0x24);
2222 emit_d32(cbuf, 0xffffff2b);
2223
2224 // popfq
2225 emit_opcode(cbuf, 0x9D);
2226
2227 // nop (target for branch to avoid branch to branch)
2228 emit_opcode(cbuf, 0x90);
2229 %}
2230
2231 enc_class cmpfp3(rRegI dst)
2232 %{
2233 int dstenc = $dst$$reg;
2234
2235 // movl $dst, -1
2236 if (dstenc >= 8) {
2237 emit_opcode(cbuf, Assembler::REX_B);
2238 }
2239 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2240 emit_d32(cbuf, -1);
2241
2242 // jp,s done
2243 emit_opcode(cbuf, 0x7A);
2244 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A);
2245
2246 // jb,s done
2247 emit_opcode(cbuf, 0x72);
2248 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2249
2250 // setne $dst
2251 if (dstenc >= 4) {
2252 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2253 }
2254 emit_opcode(cbuf, 0x0F);
2255 emit_opcode(cbuf, 0x95);
2256 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2257
2258 // movzbl $dst, $dst
2259 if (dstenc >= 4) {
2260 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2261 }
2262 emit_opcode(cbuf, 0x0F);
2263 emit_opcode(cbuf, 0xB6);
2264 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2265 %}
2266
2267 enc_class cdql_enc(no_rax_rdx_RegI div)
2268 %{
2269 // Full implementation of Java idiv and irem; checks for
2270 // special case as described in JVM spec., p.243 & p.271.
2271 //
2272 // normal case special case
2273 //
2274 // input : rax: dividend min_int
2275 // reg: divisor -1
2276 //
2277 // output: rax: quotient (= rax idiv reg) min_int
2278 // rdx: remainder (= rax irem reg) 0
2279 //
2280 // Code sequnce:
2281 //
2282 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
2283 // 5: 75 07/08 jne e <normal>
2284 // 7: 33 d2 xor %edx,%edx
2285 // [div >= 8 -> offset + 1]
2286 // [REX_B]
2287 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
2288 // c: 74 03/04 je 11 <done>
2289 // 000000000000000e <normal>:
2290 // e: 99 cltd
2291 // [div >= 8 -> offset + 1]
2292 // [REX_B]
2293 // f: f7 f9 idiv $div
2294 // 0000000000000011 <done>:
2295
2296 // cmp $0x80000000,%eax
2297 emit_opcode(cbuf, 0x3d);
2298 emit_d8(cbuf, 0x00);
2299 emit_d8(cbuf, 0x00);
2300 emit_d8(cbuf, 0x00);
2301 emit_d8(cbuf, 0x80);
2302
2303 // jne e <normal>
2304 emit_opcode(cbuf, 0x75);
2305 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
2306
2307 // xor %edx,%edx
2308 emit_opcode(cbuf, 0x33);
2309 emit_d8(cbuf, 0xD2);
2310
2311 // cmp $0xffffffffffffffff,%ecx
2312 if ($div$$reg >= 8) {
2313 emit_opcode(cbuf, Assembler::REX_B);
2314 }
2315 emit_opcode(cbuf, 0x83);
2316 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2317 emit_d8(cbuf, 0xFF);
2318
2319 // je 11 <done>
2320 emit_opcode(cbuf, 0x74);
2321 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
2322
2323 // <normal>
2324 // cltd
2325 emit_opcode(cbuf, 0x99);
2326
2327 // idivl (note: must be emitted by the user of this rule)
2328 // <done>
2329 %}
2330
2331 enc_class cdqq_enc(no_rax_rdx_RegL div)
2332 %{
2333 // Full implementation of Java ldiv and lrem; checks for
2334 // special case as described in JVM spec., p.243 & p.271.
2335 //
2336 // normal case special case
2337 //
2338 // input : rax: dividend min_long
2339 // reg: divisor -1
2340 //
2341 // output: rax: quotient (= rax idiv reg) min_long
2342 // rdx: remainder (= rax irem reg) 0
2343 //
2344 // Code sequnce:
2345 //
2346 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
2347 // 7: 00 00 80
2348 // a: 48 39 d0 cmp %rdx,%rax
2349 // d: 75 08 jne 17 <normal>
2350 // f: 33 d2 xor %edx,%edx
2351 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
2352 // 15: 74 05 je 1c <done>
2353 // 0000000000000017 <normal>:
2354 // 17: 48 99 cqto
2355 // 19: 48 f7 f9 idiv $div
2356 // 000000000000001c <done>:
2357
2358 // mov $0x8000000000000000,%rdx
2359 emit_opcode(cbuf, Assembler::REX_W);
2360 emit_opcode(cbuf, 0xBA);
2361 emit_d8(cbuf, 0x00);
2362 emit_d8(cbuf, 0x00);
2363 emit_d8(cbuf, 0x00);
2364 emit_d8(cbuf, 0x00);
2365 emit_d8(cbuf, 0x00);
2366 emit_d8(cbuf, 0x00);
2367 emit_d8(cbuf, 0x00);
2368 emit_d8(cbuf, 0x80);
2369
2370 // cmp %rdx,%rax
2371 emit_opcode(cbuf, Assembler::REX_W);
2372 emit_opcode(cbuf, 0x39);
2373 emit_d8(cbuf, 0xD0);
2374
2375 // jne 17 <normal>
2376 emit_opcode(cbuf, 0x75);
2377 emit_d8(cbuf, 0x08);
2378
2379 // xor %edx,%edx
2380 emit_opcode(cbuf, 0x33);
2381 emit_d8(cbuf, 0xD2);
2382
2383 // cmp $0xffffffffffffffff,$div
2384 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
2385 emit_opcode(cbuf, 0x83);
2386 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
2387 emit_d8(cbuf, 0xFF);
2388
2389 // je 1e <done>
2390 emit_opcode(cbuf, 0x74);
2391 emit_d8(cbuf, 0x05);
2392
2393 // <normal>
2394 // cqto
2395 emit_opcode(cbuf, Assembler::REX_W);
2396 emit_opcode(cbuf, 0x99);
2397
2398 // idivq (note: must be emitted by the user of this rule)
2399 // <done>
2400 %}
2401
2402 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2403 enc_class OpcSE(immI imm)
2404 %{
2405 // Emit primary opcode and set sign-extend bit
2406 // Check for 8-bit immediate, and set sign extend bit in opcode
2407 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2408 emit_opcode(cbuf, $primary | 0x02);
2409 } else {
2410 // 32-bit immediate
2411 emit_opcode(cbuf, $primary);
2412 }
2413 %}
2414
2415 enc_class OpcSErm(rRegI dst, immI imm)
2416 %{
2417 // OpcSEr/m
2418 int dstenc = $dst$$reg;
2419 if (dstenc >= 8) {
2420 emit_opcode(cbuf, Assembler::REX_B);
2421 dstenc -= 8;
2422 }
2423 // Emit primary opcode and set sign-extend bit
2424 // Check for 8-bit immediate, and set sign extend bit in opcode
2425 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2426 emit_opcode(cbuf, $primary | 0x02);
2427 } else {
2428 // 32-bit immediate
2429 emit_opcode(cbuf, $primary);
2430 }
2431 // Emit r/m byte with secondary opcode, after primary opcode.
2432 emit_rm(cbuf, 0x3, $secondary, dstenc);
2433 %}
2434
2435 enc_class OpcSErm_wide(rRegL dst, immI imm)
2436 %{
2437 // OpcSEr/m
2438 int dstenc = $dst$$reg;
2439 if (dstenc < 8) {
2440 emit_opcode(cbuf, Assembler::REX_W);
2441 } else {
2442 emit_opcode(cbuf, Assembler::REX_WB);
2443 dstenc -= 8;
2444 }
2445 // Emit primary opcode and set sign-extend bit
2446 // Check for 8-bit immediate, and set sign extend bit in opcode
2447 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2448 emit_opcode(cbuf, $primary | 0x02);
2449 } else {
2450 // 32-bit immediate
2451 emit_opcode(cbuf, $primary);
2452 }
2453 // Emit r/m byte with secondary opcode, after primary opcode.
2454 emit_rm(cbuf, 0x3, $secondary, dstenc);
2455 %}
2456
2457 enc_class Con8or32(immI imm)
2458 %{
2459 // Check for 8-bit immediate, and set sign extend bit in opcode
2460 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2461 $$$emit8$imm$$constant;
2462 } else {
2463 // 32-bit immediate
2464 $$$emit32$imm$$constant;
2465 }
2466 %}
2467
2468 enc_class Lbl(label labl)
2469 %{
2470 // JMP, CALL
2471 Label* l = $labl$$label;
2472 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2473 %}
2474
2475 enc_class LblShort(label labl)
2476 %{
2477 // JMP, CALL
2478 Label* l = $labl$$label;
2479 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2480 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2481 emit_d8(cbuf, disp);
2482 %}
2483
2484 enc_class opc2_reg(rRegI dst)
2485 %{
2486 // BSWAP
2487 emit_cc(cbuf, $secondary, $dst$$reg);
2488 %}
2489
2490 enc_class opc3_reg(rRegI dst)
2491 %{
2492 // BSWAP
2493 emit_cc(cbuf, $tertiary, $dst$$reg);
2494 %}
2495
2496 enc_class reg_opc(rRegI div)
2497 %{
2498 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2499 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2500 %}
2501
2502 enc_class Jcc(cmpOp cop, label labl)
2503 %{
2504 // JCC
2505 Label* l = $labl$$label;
2506 $$$emit8$primary;
2507 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2508 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0);
2509 %}
2510
2511 enc_class JccShort (cmpOp cop, label labl)
2512 %{
2513 // JCC
2514 Label *l = $labl$$label;
2515 emit_cc(cbuf, $primary, $cop$$cmpcode);
2516 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
2517 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
2518 emit_d8(cbuf, disp);
2519 %}
2520
2521 enc_class enc_cmov(cmpOp cop)
2522 %{
2523 // CMOV
2524 $$$emit8$primary;
2525 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2526 %}
2527
2528 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src)
2529 %{
2530 // Invert sense of branch from sense of cmov
2531 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2532 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8)
2533 ? (UseXmmRegToRegMoveAll ? 3 : 4)
2534 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX
2535 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src)
2536 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3);
2537 if ($dst$$reg < 8) {
2538 if ($src$$reg >= 8) {
2539 emit_opcode(cbuf, Assembler::REX_B);
2540 }
2541 } else {
2542 if ($src$$reg < 8) {
2543 emit_opcode(cbuf, Assembler::REX_R);
2544 } else {
2545 emit_opcode(cbuf, Assembler::REX_RB);
2546 }
2547 }
2548 emit_opcode(cbuf, 0x0F);
2549 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2550 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2551 %}
2552
2553 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src)
2554 %{
2555 // Invert sense of branch from sense of cmov
2556 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1);
2557 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX
2558
2559 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src)
2560 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2);
2561 if ($dst$$reg < 8) {
2562 if ($src$$reg >= 8) {
2563 emit_opcode(cbuf, Assembler::REX_B);
2564 }
2565 } else {
2566 if ($src$$reg < 8) {
2567 emit_opcode(cbuf, Assembler::REX_R);
2568 } else {
2569 emit_opcode(cbuf, Assembler::REX_RB);
2570 }
2571 }
2572 emit_opcode(cbuf, 0x0F);
2573 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10);
2574 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
2575 %}
2576
2577 enc_class enc_PartialSubtypeCheck()
2578 %{
2579 Register Rrdi = as_Register(RDI_enc); // result register
2580 Register Rrax = as_Register(RAX_enc); // super class
2581 Register Rrcx = as_Register(RCX_enc); // killed
2582 Register Rrsi = as_Register(RSI_enc); // sub class
2583 Label hit, miss, cmiss;
2584
2585 MacroAssembler _masm(&cbuf);
2586 // Compare super with sub directly, since super is not in its own SSA.
2587 // The compiler used to emit this test, but we fold it in here,
2588 // to allow platform-specific tweaking on sparc.
2589 __ cmpptr(Rrax, Rrsi);
2590 __ jcc(Assembler::equal, hit);
2591 #ifndef PRODUCT
2592 __ lea(Rrcx, ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
2593 __ incrementl(Address(Rrcx, 0));
2594 #endif //PRODUCT
2595 __ movptr(Rrdi, Address(Rrsi,
2596 sizeof(oopDesc) +
2597 Klass::secondary_supers_offset_in_bytes()));
2598 __ movl(Rrcx, Address(Rrdi, arrayOopDesc::length_offset_in_bytes()));
2599 __ addptr(Rrdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT));
2600 if (UseCompressedOops) {
2601 __ encode_heap_oop(Rrax);
2602 __ repne_scanl();
2603 __ jcc(Assembler::notEqual, cmiss);
2604 __ decode_heap_oop(Rrax);
2605 __ movptr(Address(Rrsi,
2606 sizeof(oopDesc) +
2607 Klass::secondary_super_cache_offset_in_bytes()),
2608 Rrax);
2609 __ jmp(hit);
2610 __ bind(cmiss);
2611 __ decode_heap_oop(Rrax);
2612 __ jmp(miss);
2613 } else {
2614 __ repne_scan();
2615 __ jcc(Assembler::notEqual, miss);
2616 __ movptr(Address(Rrsi,
2617 sizeof(oopDesc) +
2618 Klass::secondary_super_cache_offset_in_bytes()),
2619 Rrax);
2620 }
2621 __ bind(hit);
2622 if ($primary) {
2623 __ xorptr(Rrdi, Rrdi);
2624 }
2625 __ bind(miss);
2626 %}
2627
2628 enc_class Java_To_Interpreter(method meth)
2629 %{
2630 // CALL Java_To_Interpreter
2631 // This is the instruction starting address for relocation info.
2632 cbuf.set_inst_mark();
2633 $$$emit8$primary;
2634 // CALL directly to the runtime
2635 emit_d32_reloc(cbuf,
2636 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2637 runtime_call_Relocation::spec(),
2638 RELOC_DISP32);
2639 %}
2640
2641 enc_class Java_Static_Call(method meth)
2642 %{
2643 // JAVA STATIC CALL
2644 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2645 // determine who we intended to call.
2646 cbuf.set_inst_mark();
2647 $$$emit8$primary;
2648
2649 if (!_method) {
2650 emit_d32_reloc(cbuf,
2651 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2652 runtime_call_Relocation::spec(),
2653 RELOC_DISP32);
2654 } else if (_optimized_virtual) {
2655 emit_d32_reloc(cbuf,
2656 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2657 opt_virtual_call_Relocation::spec(),
2658 RELOC_DISP32);
2659 } else {
2660 emit_d32_reloc(cbuf,
2661 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2662 static_call_Relocation::spec(),
2663 RELOC_DISP32);
2664 }
2665 if (_method) {
2666 // Emit stub for static call
2667 emit_java_to_interp(cbuf);
2668 }
2669 %}
2670
2671 enc_class Java_Dynamic_Call(method meth)
2672 %{
2673 // JAVA DYNAMIC CALL
2674 // !!!!!
2675 // Generate "movq rax, -1", placeholder instruction to load oop-info
2676 // emit_call_dynamic_prologue( cbuf );
2677 cbuf.set_inst_mark();
2678
2679 // movq rax, -1
2680 emit_opcode(cbuf, Assembler::REX_W);
2681 emit_opcode(cbuf, 0xB8 | RAX_enc);
2682 emit_d64_reloc(cbuf,
2683 (int64_t) Universe::non_oop_word(),
2684 oop_Relocation::spec_for_immediate(), RELOC_IMM64);
2685 address virtual_call_oop_addr = cbuf.inst_mark();
2686 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2687 // who we intended to call.
2688 cbuf.set_inst_mark();
2689 $$$emit8$primary;
2690 emit_d32_reloc(cbuf,
2691 (int) ($meth$$method - ((intptr_t) cbuf.code_end()) - 4),
2692 virtual_call_Relocation::spec(virtual_call_oop_addr),
2693 RELOC_DISP32);
2694 %}
2695
2696 enc_class Java_Compiled_Call(method meth)
2697 %{
2698 // JAVA COMPILED CALL
2699 int disp = in_bytes(methodOopDesc:: from_compiled_offset());
2700
2701 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2702 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2703
2704 // callq *disp(%rax)
2705 cbuf.set_inst_mark();
2706 $$$emit8$primary;
2707 if (disp < 0x80) {
2708 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2709 emit_d8(cbuf, disp); // Displacement
2710 } else {
2711 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2712 emit_d32(cbuf, disp); // Displacement
2713 }
2714 %}
2715
2716 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2717 %{
2718 // SAL, SAR, SHR
2719 int dstenc = $dst$$reg;
2720 if (dstenc >= 8) {
2721 emit_opcode(cbuf, Assembler::REX_B);
2722 dstenc -= 8;
2723 }
2724 $$$emit8$primary;
2725 emit_rm(cbuf, 0x3, $secondary, dstenc);
2726 $$$emit8$shift$$constant;
2727 %}
2728
2729 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2730 %{
2731 // SAL, SAR, SHR
2732 int dstenc = $dst$$reg;
2733 if (dstenc < 8) {
2734 emit_opcode(cbuf, Assembler::REX_W);
2735 } else {
2736 emit_opcode(cbuf, Assembler::REX_WB);
2737 dstenc -= 8;
2738 }
2739 $$$emit8$primary;
2740 emit_rm(cbuf, 0x3, $secondary, dstenc);
2741 $$$emit8$shift$$constant;
2742 %}
2743
2744 enc_class load_immI(rRegI dst, immI src)
2745 %{
2746 int dstenc = $dst$$reg;
2747 if (dstenc >= 8) {
2748 emit_opcode(cbuf, Assembler::REX_B);
2749 dstenc -= 8;
2750 }
2751 emit_opcode(cbuf, 0xB8 | dstenc);
2752 $$$emit32$src$$constant;
2753 %}
2754
2755 enc_class load_immL(rRegL dst, immL src)
2756 %{
2757 int dstenc = $dst$$reg;
2758 if (dstenc < 8) {
2759 emit_opcode(cbuf, Assembler::REX_W);
2760 } else {
2761 emit_opcode(cbuf, Assembler::REX_WB);
2762 dstenc -= 8;
2763 }
2764 emit_opcode(cbuf, 0xB8 | dstenc);
2765 emit_d64(cbuf, $src$$constant);
2766 %}
2767
2768 enc_class load_immUL32(rRegL dst, immUL32 src)
2769 %{
2770 // same as load_immI, but this time we care about zeroes in the high word
2771 int dstenc = $dst$$reg;
2772 if (dstenc >= 8) {
2773 emit_opcode(cbuf, Assembler::REX_B);
2774 dstenc -= 8;
2775 }
2776 emit_opcode(cbuf, 0xB8 | dstenc);
2777 $$$emit32$src$$constant;
2778 %}
2779
2780 enc_class load_immL32(rRegL dst, immL32 src)
2781 %{
2782 int dstenc = $dst$$reg;
2783 if (dstenc < 8) {
2784 emit_opcode(cbuf, Assembler::REX_W);
2785 } else {
2786 emit_opcode(cbuf, Assembler::REX_WB);
2787 dstenc -= 8;
2788 }
2789 emit_opcode(cbuf, 0xC7);
2790 emit_rm(cbuf, 0x03, 0x00, dstenc);
2791 $$$emit32$src$$constant;
2792 %}
2793
2794 enc_class load_immP31(rRegP dst, immP32 src)
2795 %{
2796 // same as load_immI, but this time we care about zeroes in the high word
2797 int dstenc = $dst$$reg;
2798 if (dstenc >= 8) {
2799 emit_opcode(cbuf, Assembler::REX_B);
2800 dstenc -= 8;
2801 }
2802 emit_opcode(cbuf, 0xB8 | dstenc);
2803 $$$emit32$src$$constant;
2804 %}
2805
2806 enc_class load_immP(rRegP dst, immP src)
2807 %{
2808 int dstenc = $dst$$reg;
2809 if (dstenc < 8) {
2810 emit_opcode(cbuf, Assembler::REX_W);
2811 } else {
2812 emit_opcode(cbuf, Assembler::REX_WB);
2813 dstenc -= 8;
2814 }
2815 emit_opcode(cbuf, 0xB8 | dstenc);
2816 // This next line should be generated from ADLC
2817 if ($src->constant_is_oop()) {
2818 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64);
2819 } else {
2820 emit_d64(cbuf, $src$$constant);
2821 }
2822 %}
2823
2824 enc_class load_immF(regF dst, immF con)
2825 %{
2826 // XXX reg_mem doesn't support RIP-relative addressing yet
2827 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2828 emit_float_constant(cbuf, $con$$constant);
2829 %}
2830
2831 enc_class load_immD(regD dst, immD con)
2832 %{
2833 // XXX reg_mem doesn't support RIP-relative addressing yet
2834 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2835 emit_double_constant(cbuf, $con$$constant);
2836 %}
2837
2838 enc_class load_conF (regF dst, immF con) %{ // Load float constant
2839 emit_opcode(cbuf, 0xF3);
2840 if ($dst$$reg >= 8) {
2841 emit_opcode(cbuf, Assembler::REX_R);
2842 }
2843 emit_opcode(cbuf, 0x0F);
2844 emit_opcode(cbuf, 0x10);
2845 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2846 emit_float_constant(cbuf, $con$$constant);
2847 %}
2848
2849 enc_class load_conD (regD dst, immD con) %{ // Load double constant
2850 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
2851 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2852 if ($dst$$reg >= 8) {
2853 emit_opcode(cbuf, Assembler::REX_R);
2854 }
2855 emit_opcode(cbuf, 0x0F);
2856 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2857 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101
2858 emit_double_constant(cbuf, $con$$constant);
2859 %}
2860
2861 // Encode a reg-reg copy. If it is useless, then empty encoding.
2862 enc_class enc_copy(rRegI dst, rRegI src)
2863 %{
2864 encode_copy(cbuf, $dst$$reg, $src$$reg);
2865 %}
2866
2867 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2868 enc_class enc_CopyXD( RegD dst, RegD src ) %{
2869 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2870 %}
2871
2872 enc_class enc_copy_always(rRegI dst, rRegI src)
2873 %{
2874 int srcenc = $src$$reg;
2875 int dstenc = $dst$$reg;
2876
2877 if (dstenc < 8) {
2878 if (srcenc >= 8) {
2879 emit_opcode(cbuf, Assembler::REX_B);
2880 srcenc -= 8;
2881 }
2882 } else {
2883 if (srcenc < 8) {
2884 emit_opcode(cbuf, Assembler::REX_R);
2885 } else {
2886 emit_opcode(cbuf, Assembler::REX_RB);
2887 srcenc -= 8;
2888 }
2889 dstenc -= 8;
2890 }
2891
2892 emit_opcode(cbuf, 0x8B);
2893 emit_rm(cbuf, 0x3, dstenc, srcenc);
2894 %}
2895
2896 enc_class enc_copy_wide(rRegL dst, rRegL src)
2897 %{
2898 int srcenc = $src$$reg;
2899 int dstenc = $dst$$reg;
2900
2901 if (dstenc != srcenc) {
2902 if (dstenc < 8) {
2903 if (srcenc < 8) {
2904 emit_opcode(cbuf, Assembler::REX_W);
2905 } else {
2906 emit_opcode(cbuf, Assembler::REX_WB);
2907 srcenc -= 8;
2908 }
2909 } else {
2910 if (srcenc < 8) {
2911 emit_opcode(cbuf, Assembler::REX_WR);
2912 } else {
2913 emit_opcode(cbuf, Assembler::REX_WRB);
2914 srcenc -= 8;
2915 }
2916 dstenc -= 8;
2917 }
2918 emit_opcode(cbuf, 0x8B);
2919 emit_rm(cbuf, 0x3, dstenc, srcenc);
2920 }
2921 %}
2922
2923 enc_class Con32(immI src)
2924 %{
2925 // Output immediate
2926 $$$emit32$src$$constant;
2927 %}
2928
2929 enc_class Con64(immL src)
2930 %{
2931 // Output immediate
2932 emit_d64($src$$constant);
2933 %}
2934
2935 enc_class Con32F_as_bits(immF src)
2936 %{
2937 // Output Float immediate bits
2938 jfloat jf = $src$$constant;
2939 jint jf_as_bits = jint_cast(jf);
2940 emit_d32(cbuf, jf_as_bits);
2941 %}
2942
2943 enc_class Con16(immI src)
2944 %{
2945 // Output immediate
2946 $$$emit16$src$$constant;
2947 %}
2948
2949 // How is this different from Con32??? XXX
2950 enc_class Con_d32(immI src)
2951 %{
2952 emit_d32(cbuf,$src$$constant);
2953 %}
2954
2955 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2956 // Output immediate memory reference
2957 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2958 emit_d32(cbuf, 0x00);
2959 %}
2960
2961 enc_class jump_enc(rRegL switch_val, rRegI dest) %{
2962 MacroAssembler masm(&cbuf);
2963
2964 Register switch_reg = as_Register($switch_val$$reg);
2965 Register dest_reg = as_Register($dest$$reg);
2966 address table_base = masm.address_table_constant(_index2label);
2967
2968 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2969 // to do that and the compiler is using that register as one it can allocate.
2970 // So we build it all by hand.
2971 // Address index(noreg, switch_reg, Address::times_1);
2972 // ArrayAddress dispatch(table, index);
2973
2974 Address dispatch(dest_reg, switch_reg, Address::times_1);
2975
2976 masm.lea(dest_reg, InternalAddress(table_base));
2977 masm.jmp(dispatch);
2978 %}
2979
2980 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
2981 MacroAssembler masm(&cbuf);
2982
2983 Register switch_reg = as_Register($switch_val$$reg);
2984 Register dest_reg = as_Register($dest$$reg);
2985 address table_base = masm.address_table_constant(_index2label);
2986
2987 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
2988 // to do that and the compiler is using that register as one it can allocate.
2989 // So we build it all by hand.
2990 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2991 // ArrayAddress dispatch(table, index);
2992
2993 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant);
2994
2995 masm.lea(dest_reg, InternalAddress(table_base));
2996 masm.jmp(dispatch);
2997 %}
2998
2999 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
3000 MacroAssembler masm(&cbuf);
3001
3002 Register switch_reg = as_Register($switch_val$$reg);
3003 Register dest_reg = as_Register($dest$$reg);
3004 address table_base = masm.address_table_constant(_index2label);
3005
3006 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
3007 // to do that and the compiler is using that register as one it can allocate.
3008 // So we build it all by hand.
3009 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3010 // ArrayAddress dispatch(table, index);
3011
3012 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant);
3013 masm.lea(dest_reg, InternalAddress(table_base));
3014 masm.jmp(dispatch);
3015
3016 %}
3017
3018 enc_class lock_prefix()
3019 %{
3020 if (os::is_MP()) {
3021 emit_opcode(cbuf, 0xF0); // lock
3022 }
3023 %}
3024
3025 enc_class REX_mem(memory mem)
3026 %{
3027 if ($mem$$base >= 8) {
3028 if ($mem$$index < 8) {
3029 emit_opcode(cbuf, Assembler::REX_B);
3030 } else {
3031 emit_opcode(cbuf, Assembler::REX_XB);
3032 }
3033 } else {
3034 if ($mem$$index >= 8) {
3035 emit_opcode(cbuf, Assembler::REX_X);
3036 }
3037 }
3038 %}
3039
3040 enc_class REX_mem_wide(memory mem)
3041 %{
3042 if ($mem$$base >= 8) {
3043 if ($mem$$index < 8) {
3044 emit_opcode(cbuf, Assembler::REX_WB);
3045 } else {
3046 emit_opcode(cbuf, Assembler::REX_WXB);
3047 }
3048 } else {
3049 if ($mem$$index < 8) {
3050 emit_opcode(cbuf, Assembler::REX_W);
3051 } else {
3052 emit_opcode(cbuf, Assembler::REX_WX);
3053 }
3054 }
3055 %}
3056
3057 // for byte regs
3058 enc_class REX_breg(rRegI reg)
3059 %{
3060 if ($reg$$reg >= 4) {
3061 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3062 }
3063 %}
3064
3065 // for byte regs
3066 enc_class REX_reg_breg(rRegI dst, rRegI src)
3067 %{
3068 if ($dst$$reg < 8) {
3069 if ($src$$reg >= 4) {
3070 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
3071 }
3072 } else {
3073 if ($src$$reg < 8) {
3074 emit_opcode(cbuf, Assembler::REX_R);
3075 } else {
3076 emit_opcode(cbuf, Assembler::REX_RB);
3077 }
3078 }
3079 %}
3080
3081 // for byte regs
3082 enc_class REX_breg_mem(rRegI reg, memory mem)
3083 %{
3084 if ($reg$$reg < 8) {
3085 if ($mem$$base < 8) {
3086 if ($mem$$index >= 8) {
3087 emit_opcode(cbuf, Assembler::REX_X);
3088 } else if ($reg$$reg >= 4) {
3089 emit_opcode(cbuf, Assembler::REX);
3090 }
3091 } else {
3092 if ($mem$$index < 8) {
3093 emit_opcode(cbuf, Assembler::REX_B);
3094 } else {
3095 emit_opcode(cbuf, Assembler::REX_XB);
3096 }
3097 }
3098 } else {
3099 if ($mem$$base < 8) {
3100 if ($mem$$index < 8) {
3101 emit_opcode(cbuf, Assembler::REX_R);
3102 } else {
3103 emit_opcode(cbuf, Assembler::REX_RX);
3104 }
3105 } else {
3106 if ($mem$$index < 8) {
3107 emit_opcode(cbuf, Assembler::REX_RB);
3108 } else {
3109 emit_opcode(cbuf, Assembler::REX_RXB);
3110 }
3111 }
3112 }
3113 %}
3114
3115 enc_class REX_reg(rRegI reg)
3116 %{
3117 if ($reg$$reg >= 8) {
3118 emit_opcode(cbuf, Assembler::REX_B);
3119 }
3120 %}
3121
3122 enc_class REX_reg_wide(rRegI reg)
3123 %{
3124 if ($reg$$reg < 8) {
3125 emit_opcode(cbuf, Assembler::REX_W);
3126 } else {
3127 emit_opcode(cbuf, Assembler::REX_WB);
3128 }
3129 %}
3130
3131 enc_class REX_reg_reg(rRegI dst, rRegI src)
3132 %{
3133 if ($dst$$reg < 8) {
3134 if ($src$$reg >= 8) {
3135 emit_opcode(cbuf, Assembler::REX_B);
3136 }
3137 } else {
3138 if ($src$$reg < 8) {
3139 emit_opcode(cbuf, Assembler::REX_R);
3140 } else {
3141 emit_opcode(cbuf, Assembler::REX_RB);
3142 }
3143 }
3144 %}
3145
3146 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
3147 %{
3148 if ($dst$$reg < 8) {
3149 if ($src$$reg < 8) {
3150 emit_opcode(cbuf, Assembler::REX_W);
3151 } else {
3152 emit_opcode(cbuf, Assembler::REX_WB);
3153 }
3154 } else {
3155 if ($src$$reg < 8) {
3156 emit_opcode(cbuf, Assembler::REX_WR);
3157 } else {
3158 emit_opcode(cbuf, Assembler::REX_WRB);
3159 }
3160 }
3161 %}
3162
3163 enc_class REX_reg_mem(rRegI reg, memory mem)
3164 %{
3165 if ($reg$$reg < 8) {
3166 if ($mem$$base < 8) {
3167 if ($mem$$index >= 8) {
3168 emit_opcode(cbuf, Assembler::REX_X);
3169 }
3170 } else {
3171 if ($mem$$index < 8) {
3172 emit_opcode(cbuf, Assembler::REX_B);
3173 } else {
3174 emit_opcode(cbuf, Assembler::REX_XB);
3175 }
3176 }
3177 } else {
3178 if ($mem$$base < 8) {
3179 if ($mem$$index < 8) {
3180 emit_opcode(cbuf, Assembler::REX_R);
3181 } else {
3182 emit_opcode(cbuf, Assembler::REX_RX);
3183 }
3184 } else {
3185 if ($mem$$index < 8) {
3186 emit_opcode(cbuf, Assembler::REX_RB);
3187 } else {
3188 emit_opcode(cbuf, Assembler::REX_RXB);
3189 }
3190 }
3191 }
3192 %}
3193
3194 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
3195 %{
3196 if ($reg$$reg < 8) {
3197 if ($mem$$base < 8) {
3198 if ($mem$$index < 8) {
3199 emit_opcode(cbuf, Assembler::REX_W);
3200 } else {
3201 emit_opcode(cbuf, Assembler::REX_WX);
3202 }
3203 } else {
3204 if ($mem$$index < 8) {
3205 emit_opcode(cbuf, Assembler::REX_WB);
3206 } else {
3207 emit_opcode(cbuf, Assembler::REX_WXB);
3208 }
3209 }
3210 } else {
3211 if ($mem$$base < 8) {
3212 if ($mem$$index < 8) {
3213 emit_opcode(cbuf, Assembler::REX_WR);
3214 } else {
3215 emit_opcode(cbuf, Assembler::REX_WRX);
3216 }
3217 } else {
3218 if ($mem$$index < 8) {
3219 emit_opcode(cbuf, Assembler::REX_WRB);
3220 } else {
3221 emit_opcode(cbuf, Assembler::REX_WRXB);
3222 }
3223 }
3224 }
3225 %}
3226
3227 enc_class reg_mem(rRegI ereg, memory mem)
3228 %{
3229 // High registers handle in encode_RegMem
3230 int reg = $ereg$$reg;
3231 int base = $mem$$base;
3232 int index = $mem$$index;
3233 int scale = $mem$$scale;
3234 int disp = $mem$$disp;
3235 bool disp_is_oop = $mem->disp_is_oop();
3236
3237 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop);
3238 %}
3239
3240 enc_class RM_opc_mem(immI rm_opcode, memory mem)
3241 %{
3242 int rm_byte_opcode = $rm_opcode$$constant;
3243
3244 // High registers handle in encode_RegMem
3245 int base = $mem$$base;
3246 int index = $mem$$index;
3247 int scale = $mem$$scale;
3248 int displace = $mem$$disp;
3249
3250 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when
3251 // working with static
3252 // globals
3253 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
3254 disp_is_oop);
3255 %}
3256
3257 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
3258 %{
3259 int reg_encoding = $dst$$reg;
3260 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
3261 int index = 0x04; // 0x04 indicates no index
3262 int scale = 0x00; // 0x00 indicates no scale
3263 int displace = $src1$$constant; // 0x00 indicates no displacement
3264 bool disp_is_oop = false;
3265 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
3266 disp_is_oop);
3267 %}
3268
3269 enc_class neg_reg(rRegI dst)
3270 %{
3271 int dstenc = $dst$$reg;
3272 if (dstenc >= 8) {
3273 emit_opcode(cbuf, Assembler::REX_B);
3274 dstenc -= 8;
3275 }
3276 // NEG $dst
3277 emit_opcode(cbuf, 0xF7);
3278 emit_rm(cbuf, 0x3, 0x03, dstenc);
3279 %}
3280
3281 enc_class neg_reg_wide(rRegI dst)
3282 %{
3283 int dstenc = $dst$$reg;
3284 if (dstenc < 8) {
3285 emit_opcode(cbuf, Assembler::REX_W);
3286 } else {
3287 emit_opcode(cbuf, Assembler::REX_WB);
3288 dstenc -= 8;
3289 }
3290 // NEG $dst
3291 emit_opcode(cbuf, 0xF7);
3292 emit_rm(cbuf, 0x3, 0x03, dstenc);
3293 %}
3294
3295 enc_class setLT_reg(rRegI dst)
3296 %{
3297 int dstenc = $dst$$reg;
3298 if (dstenc >= 8) {
3299 emit_opcode(cbuf, Assembler::REX_B);
3300 dstenc -= 8;
3301 } else if (dstenc >= 4) {
3302 emit_opcode(cbuf, Assembler::REX);
3303 }
3304 // SETLT $dst
3305 emit_opcode(cbuf, 0x0F);
3306 emit_opcode(cbuf, 0x9C);
3307 emit_rm(cbuf, 0x3, 0x0, dstenc);
3308 %}
3309
3310 enc_class setNZ_reg(rRegI dst)
3311 %{
3312 int dstenc = $dst$$reg;
3313 if (dstenc >= 8) {
3314 emit_opcode(cbuf, Assembler::REX_B);
3315 dstenc -= 8;
3316 } else if (dstenc >= 4) {
3317 emit_opcode(cbuf, Assembler::REX);
3318 }
3319 // SETNZ $dst
3320 emit_opcode(cbuf, 0x0F);
3321 emit_opcode(cbuf, 0x95);
3322 emit_rm(cbuf, 0x3, 0x0, dstenc);
3323 %}
3324
3325 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y,
3326 rcx_RegI tmp)
3327 %{
3328 // cadd_cmpLT
3329
3330 int tmpReg = $tmp$$reg;
3331
3332 int penc = $p$$reg;
3333 int qenc = $q$$reg;
3334 int yenc = $y$$reg;
3335
3336 // subl $p,$q
3337 if (penc < 8) {
3338 if (qenc >= 8) {
3339 emit_opcode(cbuf, Assembler::REX_B);
3340 }
3341 } else {
3342 if (qenc < 8) {
3343 emit_opcode(cbuf, Assembler::REX_R);
3344 } else {
3345 emit_opcode(cbuf, Assembler::REX_RB);
3346 }
3347 }
3348 emit_opcode(cbuf, 0x2B);
3349 emit_rm(cbuf, 0x3, penc & 7, qenc & 7);
3350
3351 // sbbl $tmp, $tmp
3352 emit_opcode(cbuf, 0x1B);
3353 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
3354
3355 // andl $tmp, $y
3356 if (yenc >= 8) {
3357 emit_opcode(cbuf, Assembler::REX_B);
3358 }
3359 emit_opcode(cbuf, 0x23);
3360 emit_rm(cbuf, 0x3, tmpReg, yenc & 7);
3361
3362 // addl $p,$tmp
3363 if (penc >= 8) {
3364 emit_opcode(cbuf, Assembler::REX_R);
3365 }
3366 emit_opcode(cbuf, 0x03);
3367 emit_rm(cbuf, 0x3, penc & 7, tmpReg);
3368 %}
3369
3370 // Compare the lonogs and set -1, 0, or 1 into dst
3371 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
3372 %{
3373 int src1enc = $src1$$reg;
3374 int src2enc = $src2$$reg;
3375 int dstenc = $dst$$reg;
3376
3377 // cmpq $src1, $src2
3378 if (src1enc < 8) {
3379 if (src2enc < 8) {
3380 emit_opcode(cbuf, Assembler::REX_W);
3381 } else {
3382 emit_opcode(cbuf, Assembler::REX_WB);
3383 }
3384 } else {
3385 if (src2enc < 8) {
3386 emit_opcode(cbuf, Assembler::REX_WR);
3387 } else {
3388 emit_opcode(cbuf, Assembler::REX_WRB);
3389 }
3390 }
3391 emit_opcode(cbuf, 0x3B);
3392 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
3393
3394 // movl $dst, -1
3395 if (dstenc >= 8) {
3396 emit_opcode(cbuf, Assembler::REX_B);
3397 }
3398 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
3399 emit_d32(cbuf, -1);
3400
3401 // jl,s done
3402 emit_opcode(cbuf, 0x7C);
3403 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
3404
3405 // setne $dst
3406 if (dstenc >= 4) {
3407 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
3408 }
3409 emit_opcode(cbuf, 0x0F);
3410 emit_opcode(cbuf, 0x95);
3411 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
3412
3413 // movzbl $dst, $dst
3414 if (dstenc >= 4) {
3415 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
3416 }
3417 emit_opcode(cbuf, 0x0F);
3418 emit_opcode(cbuf, 0xB6);
3419 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
3420 %}
3421
3422 enc_class Push_ResultXD(regD dst) %{
3423 int dstenc = $dst$$reg;
3424
3425 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP]
3426
3427 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp]
3428 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
3429 if (dstenc >= 8) {
3430 emit_opcode(cbuf, Assembler::REX_R);
3431 }
3432 emit_opcode (cbuf, 0x0F );
3433 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 );
3434 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false);
3435
3436 // add rsp,8
3437 emit_opcode(cbuf, Assembler::REX_W);
3438 emit_opcode(cbuf,0x83);
3439 emit_rm(cbuf,0x3, 0x0, RSP_enc);
3440 emit_d8(cbuf,0x08);
3441 %}
3442
3443 enc_class Push_SrcXD(regD src) %{
3444 int srcenc = $src$$reg;
3445
3446 // subq rsp,#8
3447 emit_opcode(cbuf, Assembler::REX_W);
3448 emit_opcode(cbuf, 0x83);
3449 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
3450 emit_d8(cbuf, 0x8);
3451
3452 // movsd [rsp],src
3453 emit_opcode(cbuf, 0xF2);
3454 if (srcenc >= 8) {
3455 emit_opcode(cbuf, Assembler::REX_R);
3456 }
3457 emit_opcode(cbuf, 0x0F);
3458 emit_opcode(cbuf, 0x11);
3459 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false);
3460
3461 // fldd [rsp]
3462 emit_opcode(cbuf, 0x66);
3463 emit_opcode(cbuf, 0xDD);
3464 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false);
3465 %}
3466
3467
3468 enc_class movq_ld(regD dst, memory mem) %{
3469 MacroAssembler _masm(&cbuf);
3470 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3471 __ movq(as_XMMRegister($dst$$reg), madr);
3472 %}
3473
3474 enc_class movq_st(memory mem, regD src) %{
3475 MacroAssembler _masm(&cbuf);
3476 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3477 __ movq(madr, as_XMMRegister($src$$reg));
3478 %}
3479
3480 enc_class pshufd_8x8(regF dst, regF src) %{
3481 MacroAssembler _masm(&cbuf);
3482
3483 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3484 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3485 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3486 %}
3487
3488 enc_class pshufd_4x16(regF dst, regF src) %{
3489 MacroAssembler _masm(&cbuf);
3490
3491 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3492 %}
3493
3494 enc_class pshufd(regD dst, regD src, int mode) %{
3495 MacroAssembler _masm(&cbuf);
3496
3497 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3498 %}
3499
3500 enc_class pxor(regD dst, regD src) %{
3501 MacroAssembler _masm(&cbuf);
3502
3503 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3504 %}
3505
3506 enc_class mov_i2x(regD dst, rRegI src) %{
3507 MacroAssembler _masm(&cbuf);
3508
3509 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3510 %}
3511
3512 // obj: object to lock
3513 // box: box address (header location) -- killed
3514 // tmp: rax -- killed
3515 // scr: rbx -- killed
3516 //
3517 // What follows is a direct transliteration of fast_lock() and fast_unlock()
3518 // from i486.ad. See that file for comments.
3519 // TODO: where possible switch from movq (r, 0) to movl(r,0) and
3520 // use the shorter encoding. (Movl clears the high-order 32-bits).
3521
3522
3523 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr)
3524 %{
3525 Register objReg = as_Register((int)$obj$$reg);
3526 Register boxReg = as_Register((int)$box$$reg);
3527 Register tmpReg = as_Register($tmp$$reg);
3528 Register scrReg = as_Register($scr$$reg);
3529 MacroAssembler masm(&cbuf);
3530
3531 // Verify uniqueness of register assignments -- necessary but not sufficient
3532 assert (objReg != boxReg && objReg != tmpReg &&
3533 objReg != scrReg && tmpReg != scrReg, "invariant") ;
3534
3535 if (_counters != NULL) {
3536 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3537 }
3538 if (EmitSync & 1) {
3539 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3540 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3541 masm.cmpptr(rsp, (int32_t)NULL_WORD) ;
3542 } else
3543 if (EmitSync & 2) {
3544 Label DONE_LABEL;
3545 if (UseBiasedLocking) {
3546 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3547 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3548 }
3549 // QQQ was movl...
3550 masm.movptr(tmpReg, 0x1);
3551 masm.orptr(tmpReg, Address(objReg, 0));
3552 masm.movptr(Address(boxReg, 0), tmpReg);
3553 if (os::is_MP()) {
3554 masm.lock();
3555 }
3556 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3557 masm.jcc(Assembler::equal, DONE_LABEL);
3558
3559 // Recursive locking
3560 masm.subptr(tmpReg, rsp);
3561 masm.andptr(tmpReg, 7 - os::vm_page_size());
3562 masm.movptr(Address(boxReg, 0), tmpReg);
3563
3564 masm.bind(DONE_LABEL);
3565 masm.nop(); // avoid branch to branch
3566 } else {
3567 Label DONE_LABEL, IsInflated, Egress;
3568
3569 masm.movptr(tmpReg, Address(objReg, 0)) ;
3570 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased
3571 masm.jcc (Assembler::notZero, IsInflated) ;
3572
3573 // it's stack-locked, biased or neutral
3574 // TODO: optimize markword triage order to reduce the number of
3575 // conditional branches in the most common cases.
3576 // Beware -- there's a subtle invariant that fetch of the markword
3577 // at [FETCH], below, will never observe a biased encoding (*101b).
3578 // If this invariant is not held we'll suffer exclusion (safety) failure.
3579
3580 if (UseBiasedLocking && !UseOptoBiasInlining) {
3581 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters);
3582 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3583 }
3584
3585 // was q will it destroy high?
3586 masm.orl (tmpReg, 1) ;
3587 masm.movptr(Address(boxReg, 0), tmpReg) ;
3588 if (os::is_MP()) { masm.lock(); }
3589 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3590 if (_counters != NULL) {
3591 masm.cond_inc32(Assembler::equal,
3592 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3593 }
3594 masm.jcc (Assembler::equal, DONE_LABEL);
3595
3596 // Recursive locking
3597 masm.subptr(tmpReg, rsp);
3598 masm.andptr(tmpReg, 7 - os::vm_page_size());
3599 masm.movptr(Address(boxReg, 0), tmpReg);
3600 if (_counters != NULL) {
3601 masm.cond_inc32(Assembler::equal,
3602 ExternalAddress((address) _counters->fast_path_entry_count_addr()));
3603 }
3604 masm.jmp (DONE_LABEL) ;
3605
3606 masm.bind (IsInflated) ;
3607 // It's inflated
3608
3609 // TODO: someday avoid the ST-before-CAS penalty by
3610 // relocating (deferring) the following ST.
3611 // We should also think about trying a CAS without having
3612 // fetched _owner. If the CAS is successful we may
3613 // avoid an RTO->RTS upgrade on the $line.
3614 // Without cast to int32_t a movptr will destroy r10 which is typically obj
3615 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ;
3616
3617 masm.mov (boxReg, tmpReg) ;
3618 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3619 masm.testptr(tmpReg, tmpReg) ;
3620 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3621
3622 // It's inflated and appears unlocked
3623 if (os::is_MP()) { masm.lock(); }
3624 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3625 // Intentional fall-through into DONE_LABEL ...
3626
3627 masm.bind (DONE_LABEL) ;
3628 masm.nop () ; // avoid jmp to jmp
3629 }
3630 %}
3631
3632 // obj: object to unlock
3633 // box: box address (displaced header location), killed
3634 // RBX: killed tmp; cannot be obj nor box
3635 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp)
3636 %{
3637
3638 Register objReg = as_Register($obj$$reg);
3639 Register boxReg = as_Register($box$$reg);
3640 Register tmpReg = as_Register($tmp$$reg);
3641 MacroAssembler masm(&cbuf);
3642
3643 if (EmitSync & 4) {
3644 masm.cmpptr(rsp, 0) ;
3645 } else
3646 if (EmitSync & 8) {
3647 Label DONE_LABEL;
3648 if (UseBiasedLocking) {
3649 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3650 }
3651
3652 // Check whether the displaced header is 0
3653 //(=> recursive unlock)
3654 masm.movptr(tmpReg, Address(boxReg, 0));
3655 masm.testptr(tmpReg, tmpReg);
3656 masm.jcc(Assembler::zero, DONE_LABEL);
3657
3658 // If not recursive lock, reset the header to displaced header
3659 if (os::is_MP()) {
3660 masm.lock();
3661 }
3662 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3663 masm.bind(DONE_LABEL);
3664 masm.nop(); // avoid branch to branch
3665 } else {
3666 Label DONE_LABEL, Stacked, CheckSucc ;
3667
3668 if (UseBiasedLocking && !UseOptoBiasInlining) {
3669 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3670 }
3671
3672 masm.movptr(tmpReg, Address(objReg, 0)) ;
3673 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ;
3674 masm.jcc (Assembler::zero, DONE_LABEL) ;
3675 masm.testl (tmpReg, 0x02) ;
3676 masm.jcc (Assembler::zero, Stacked) ;
3677
3678 // It's inflated
3679 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3680 masm.xorptr(boxReg, r15_thread) ;
3681 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3682 masm.jcc (Assembler::notZero, DONE_LABEL) ;
3683 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3684 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3685 masm.jcc (Assembler::notZero, CheckSucc) ;
3686 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3687 masm.jmp (DONE_LABEL) ;
3688
3689 if ((EmitSync & 65536) == 0) {
3690 Label LSuccess, LGoSlowPath ;
3691 masm.bind (CheckSucc) ;
3692 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3693 masm.jcc (Assembler::zero, LGoSlowPath) ;
3694
3695 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the
3696 // the explicit ST;MEMBAR combination, but masm doesn't currently support
3697 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc
3698 // are all faster when the write buffer is populated.
3699 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3700 if (os::is_MP()) {
3701 masm.lock () ; masm.addl (Address(rsp, 0), 0) ;
3702 }
3703 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ;
3704 masm.jcc (Assembler::notZero, LSuccess) ;
3705
3706 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX
3707 if (os::is_MP()) { masm.lock(); }
3708 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3709 masm.jcc (Assembler::notEqual, LSuccess) ;
3710 // Intentional fall-through into slow-path
3711
3712 masm.bind (LGoSlowPath) ;
3713 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3714 masm.jmp (DONE_LABEL) ;
3715
3716 masm.bind (LSuccess) ;
3717 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success
3718 masm.jmp (DONE_LABEL) ;
3719 }
3720
3721 masm.bind (Stacked) ;
3722 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch
3723 if (os::is_MP()) { masm.lock(); }
3724 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
3725
3726 if (EmitSync & 65536) {
3727 masm.bind (CheckSucc) ;
3728 }
3729 masm.bind(DONE_LABEL);
3730 if (EmitSync & 32768) {
3731 masm.nop(); // avoid branch to branch
3732 }
3733 }
3734 %}
3735
3736 enc_class enc_String_Compare()
3737 %{
3738 Label RCX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3739 POP_LABEL, DONE_LABEL, CONT_LABEL,
3740 WHILE_HEAD_LABEL;
3741 MacroAssembler masm(&cbuf);
3742
3743 // Get the first character position in both strings
3744 // [8] char array, [12] offset, [16] count
3745 int value_offset = java_lang_String::value_offset_in_bytes();
3746 int offset_offset = java_lang_String::offset_offset_in_bytes();
3747 int count_offset = java_lang_String::count_offset_in_bytes();
3748 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3749
3750 masm.load_heap_oop(rax, Address(rsi, value_offset));
3751 masm.movl(rcx, Address(rsi, offset_offset));
3752 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3753 masm.load_heap_oop(rbx, Address(rdi, value_offset));
3754 masm.movl(rcx, Address(rdi, offset_offset));
3755 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3756
3757 // Compute the minimum of the string lengths(rsi) and the
3758 // difference of the string lengths (stack)
3759
3760 // do the conditional move stuff
3761 masm.movl(rdi, Address(rdi, count_offset));
3762 masm.movl(rsi, Address(rsi, count_offset));
3763 masm.movl(rcx, rdi);
3764 masm.subl(rdi, rsi);
3765 masm.push(rdi);
3766 masm.cmov(Assembler::lessEqual, rsi, rcx);
3767
3768 // Is the minimum length zero?
3769 masm.bind(RCX_GOOD_LABEL);
3770 masm.testl(rsi, rsi);
3771 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3772
3773 // Load first characters
3774 masm.load_unsigned_word(rcx, Address(rbx, 0));
3775 masm.load_unsigned_word(rdi, Address(rax, 0));
3776
3777 // Compare first characters
3778 masm.subl(rcx, rdi);
3779 masm.jccb(Assembler::notZero, POP_LABEL);
3780 masm.decrementl(rsi);
3781 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3782
3783 {
3784 // Check after comparing first character to see if strings are equivalent
3785 Label LSkip2;
3786 // Check if the strings start at same location
3787 masm.cmpptr(rbx, rax);
3788 masm.jccb(Assembler::notEqual, LSkip2);
3789
3790 // Check if the length difference is zero (from stack)
3791 masm.cmpl(Address(rsp, 0), 0x0);
3792 masm.jccb(Assembler::equal, LENGTH_DIFF_LABEL);
3793
3794 // Strings might not be equivalent
3795 masm.bind(LSkip2);
3796 }
3797
3798 // Advance to next character
3799 masm.addptr(rax, 2);
3800 masm.addptr(rbx, 2);
3801
3802 if (UseSSE>=4 && UseSSE42Intrinsics) {
3803 // With SSE4.2, use double quad vector compare
3804 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
3805 // Setup to compare 16-byte vectors
3806 masm.movl(rdi, rsi);
3807 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count
3808 masm.andl(rdi, 0x00000007); // rdi holds the tail count
3809 masm.testl(rsi, rsi);
3810 masm.jccb(Assembler::zero, COMPARE_TAIL);
3811
3812 masm.lea(rax, Address(rax, rsi, Address::times_2));
3813 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3814 masm.negptr(rsi);
3815
3816 masm.bind(COMPARE_VECTORS);
3817 masm.movdqu(xmm6, Address(rax, rsi, Address::times_2));
3818 masm.movdqu(xmm7, Address(rbx, rsi, Address::times_2));
3819 masm.pxor(xmm6, xmm7);
3820 masm.ptest(xmm6, xmm6);
3821 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
3822 masm.addptr(rsi, 8);
3823 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3824 masm.jmpb(COMPARE_TAIL);
3825
3826 // Mismatched characters in the vectors
3827 masm.bind(VECTOR_NOT_EQUAL);
3828 masm.lea(rax, Address(rax, rsi, Address::times_2));
3829 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3830 masm.movl(rdi, 8);
3831
3832 // Compare tail (< 8 chars), or rescan last vectors to
3833 // find 1st mismatched characters
3834 masm.bind(COMPARE_TAIL);
3835 masm.testl(rdi, rdi);
3836 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3837 masm.movl(rsi, rdi);
3838 // Fallthru to tail compare
3839 }
3840
3841 // Shift RAX and RBX to the end of the arrays, negate min
3842 masm.lea(rax, Address(rax, rsi, Address::times_2, 0));
3843 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0));
3844 masm.negptr(rsi);
3845
3846 // Compare the rest of the characters
3847 masm.bind(WHILE_HEAD_LABEL);
3848 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3849 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3850 masm.subl(rcx, rdi);
3851 masm.jccb(Assembler::notZero, POP_LABEL);
3852 masm.increment(rsi);
3853 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3854
3855 // Strings are equal up to min length. Return the length difference.
3856 masm.bind(LENGTH_DIFF_LABEL);
3857 masm.pop(rcx);
3858 masm.jmpb(DONE_LABEL);
3859
3860 // Discard the stored length difference
3861 masm.bind(POP_LABEL);
3862 masm.addptr(rsp, 8);
3863
3864 // That's it
3865 masm.bind(DONE_LABEL);
3866 %}
3867
3868 enc_class enc_String_IndexOf() %{
3869 // SSE4.2 version
3870 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
3871 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE;
3872 MacroAssembler masm(&cbuf);
3873
3874 // Get the first character position in both strings
3875 // [8] char array, [12] offset, [16] count
3876 int value_offset = java_lang_String::value_offset_in_bytes();
3877 int offset_offset = java_lang_String::offset_offset_in_bytes();
3878 int count_offset = java_lang_String::count_offset_in_bytes();
3879 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3880
3881 // Get counts for string and substr
3882 masm.movl(rdx, Address(rsi, count_offset));
3883 masm.movl(rax, Address(rdi, count_offset));
3884 // Check for substr count > string count
3885 masm.cmpl(rax, rdx);
3886 masm.jccb(Assembler::greater, RET_NEG_ONE);
3887
3888 // Start the indexOf operation
3889 // Get start addr of string
3890 masm.load_heap_oop(rbx, Address(rsi, value_offset));
3891 masm.movl(rcx, Address(rsi, offset_offset));
3892 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset));
3893 masm.push(rsi);
3894
3895 // Get start addr of substr
3896 masm.load_heap_oop(rbx, Address(rdi, value_offset));
3897 masm.movl(rcx, Address(rdi, offset_offset));
3898 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset));
3899 masm.push(rdi);
3900 masm.push(rax);
3901 masm.jmpb(PREP_FOR_SCAN);
3902
3903 // Substr count saved at sp
3904 // Substr saved at sp+8
3905 // String saved at sp+16
3906
3907 // Prep to load substr for scan
3908 masm.bind(LOAD_SUBSTR);
3909 masm.movptr(rdi, Address(rsp, 8));
3910 masm.movl(rax, Address(rsp, 0));
3911
3912 // Load substr
3913 masm.bind(PREP_FOR_SCAN);
3914 masm.movdqu(xmm6, Address(rdi, 0));
3915 masm.addq(rdx, 8); // prime the loop
3916 masm.subptr(rsi, 16);
3917
3918
3919 // Scan string for substr in 16-byte vectors
3920 masm.bind(SCAN_TO_SUBSTR);
3921 masm.subq(rdx, 8);
3922 masm.addptr(rsi, 16);
3923 masm.pcmpestri(xmm6, Address(rsi, 0), 0x0d);
3924 masm.jcc(Assembler::above, SCAN_TO_SUBSTR);
3925 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND);
3926
3927 // Fallthru: found a potential substr
3928
3929 //Make sure string is still long enough
3930 masm.subl(rdx, rcx);
3931 masm.cmpl(rdx, rax);
3932 masm.jccb(Assembler::negative, RET_NOT_FOUND);
3933 // Compute start addr of substr
3934 masm.lea(rsi, Address(rsi, rcx, Address::times_2));
3935 masm.movptr(rbx, rsi);
3936
3937 // Compare potential substr
3938 masm.addq(rdx, 8); // prime the loop
3939 masm.addq(rax, 8);
3940 masm.subptr(rsi, 16);
3941 masm.subptr(rdi, 16);
3942
3943 // Scan 16-byte vectors of string and substr
3944 masm.bind(SCAN_SUBSTR);
3945 masm.subq(rax, 8);
3946 masm.subq(rdx, 8);
3947 masm.addptr(rsi, 16);
3948 masm.addptr(rdi, 16);
3949 masm.movdqu(xmm6, Address(rdi, 0));
3950 masm.pcmpestri(xmm6, Address(rsi, 0), 0x0d);
3951 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0
3952 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
3953
3954 // Compute substr offset
3955 masm.movptr(rsi, Address(rsp, 16));
3956 masm.subptr(rbx, rsi);
3957 masm.shrl(rbx, 1);
3958 masm.jmpb(CLEANUP);
3959
3960 masm.bind(RET_NEG_ONE);
3961 masm.movl(rbx, -1);
3962 masm.jmpb(DONE);
3963
3964 masm.bind(RET_NOT_FOUND);
3965 masm.movl(rbx, -1);
3966
3967 masm.bind(CLEANUP);
3968 masm.addptr(rsp, 24);
3969
3970 masm.bind(DONE);
3971 %}
3972
3973 enc_class enc_String_Equals() %{
3974 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR;
3975 MacroAssembler masm(&cbuf);
3976
3977 int value_offset = java_lang_String::value_offset_in_bytes();
3978 int offset_offset = java_lang_String::offset_offset_in_bytes();
3979 int count_offset = java_lang_String::count_offset_in_bytes();
3980 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3981
3982 // does source == target string?
3983 masm.cmpptr(rdi, rsi);
3984 masm.jccb(Assembler::equal, RET_TRUE);
3985
3986 // get and compare counts
3987 masm.movl(rcx, Address(rdi, count_offset));
3988 masm.movl(rax, Address(rsi, count_offset));
3989 masm.cmpl(rcx, rax);
3990 masm.jccb(Assembler::notEqual, RET_FALSE);
3991 masm.testl(rax, rax);
3992 masm.jccb(Assembler::zero, RET_TRUE);
3993
3994 // get source string offset and value
3995 masm.load_heap_oop(rbx, Address(rsi, value_offset));
3996 masm.movl(rax, Address(rsi, offset_offset));
3997 masm.lea(rsi, Address(rbx, rax, Address::times_2, base_offset));
3998
3999 // get compare string offset and value
4000 masm.load_heap_oop(rbx, Address(rdi, value_offset));
4001 masm.movl(rax, Address(rdi, offset_offset));
4002 masm.lea(rdi, Address(rbx, rax, Address::times_2, base_offset));
4003
4004 // Set byte count
4005 masm.shll(rcx, 1);
4006 masm.movl(rax, rcx);
4007
4008 if (UseSSE>=4 && UseSSE42Intrinsics) {
4009 // With SSE4.2, use double quad vector compare
4010 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4011 // Compare 16-byte vectors
4012 masm.andl(rcx, 0xfffffff0); // vector count (in bytes)
4013 masm.andl(rax, 0x0000000e); // tail count (in bytes)
4014 masm.testl(rcx, rcx);
4015 masm.jccb(Assembler::zero, COMPARE_TAIL);
4016 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
4017 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
4018 masm.negptr(rcx);
4019
4020 masm.bind(COMPARE_WIDE_VECTORS);
4021 masm.movdqu(xmm6, Address(rdi, rcx, Address::times_1));
4022 masm.movdqu(xmm7, Address(rsi, rcx, Address::times_1));
4023 masm.pxor(xmm6, xmm7);
4024 masm.ptest(xmm6, xmm6);
4025 masm.jccb(Assembler::notZero, RET_FALSE);
4026 masm.addptr(rcx, 16);
4027 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4028 masm.bind(COMPARE_TAIL);
4029 masm.movl(rcx, rax);
4030 // Fallthru to tail compare
4031 }
4032
4033 // Compare 4-byte vectors
4034 masm.andl(rcx, 0xfffffffc); // vector count (in bytes)
4035 masm.andl(rax, 0x00000002); // tail char (in bytes)
4036 masm.testl(rcx, rcx);
4037 masm.jccb(Assembler::zero, COMPARE_CHAR);
4038 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
4039 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
4040 masm.negptr(rcx);
4041
4042 masm.bind(COMPARE_VECTORS);
4043 masm.movl(rbx, Address(rdi, rcx, Address::times_1));
4044 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1));
4045 masm.jccb(Assembler::notEqual, RET_FALSE);
4046 masm.addptr(rcx, 4);
4047 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4048
4049 // Compare trailing char (final 2 bytes), if any
4050 masm.bind(COMPARE_CHAR);
4051 masm.testl(rax, rax);
4052 masm.jccb(Assembler::zero, RET_TRUE);
4053 masm.load_unsigned_word(rbx, Address(rdi, 0));
4054 masm.load_unsigned_word(rcx, Address(rsi, 0));
4055 masm.cmpl(rbx, rcx);
4056 masm.jccb(Assembler::notEqual, RET_FALSE);
4057
4058 masm.bind(RET_TRUE);
4059 masm.movl(rax, 1); // return true
4060 masm.jmpb(DONE);
4061
4062 masm.bind(RET_FALSE);
4063 masm.xorl(rax, rax); // return false
4064
4065 masm.bind(DONE);
4066 %}
4067
4068
4069 enc_class enc_Array_Equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1, rbx_RegI tmp2, regD6 tmp3, regD7 tmp4, rcx_RegI result) %{
4070 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
4071 MacroAssembler masm(&cbuf);
4072
4073 Register ary1Reg = as_Register($ary1$$reg);
4074 Register ary2Reg = as_Register($ary2$$reg);
4075 Register tmp1Reg = as_Register($tmp1$$reg);
4076 Register tmp2Reg = as_Register($tmp2$$reg);
4077 Register resultReg = as_Register($result$$reg);
4078
4079 int length_offset = arrayOopDesc::length_offset_in_bytes();
4080 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4081
4082 // Check the input args
4083 masm.cmpq(ary1Reg, ary2Reg);
4084 masm.jccb(Assembler::equal, TRUE_LABEL);
4085 masm.testq(ary1Reg, ary1Reg);
4086 masm.jccb(Assembler::zero, FALSE_LABEL);
4087 masm.testq(ary2Reg, ary2Reg);
4088 masm.jccb(Assembler::zero, FALSE_LABEL);
4089
4090 // Check the lengths
4091 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
4092 masm.movl(resultReg, Address(ary2Reg, length_offset));
4093 masm.cmpl(tmp2Reg, resultReg);
4094 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4095 masm.testl(resultReg, resultReg);
4096 masm.jccb(Assembler::zero, TRUE_LABEL);
4097
4098 //load array address
4099 masm.lea(ary1Reg, Address(ary1Reg, base_offset));
4100 masm.lea(ary2Reg, Address(ary2Reg, base_offset));
4101
4102 //set byte count
4103 masm.shll(tmp2Reg, 1);
4104 masm.movl(resultReg,tmp2Reg);
4105
4106 if (UseSSE>=4 && UseSSE42Intrinsics){
4107 // With SSE4.2, use double quad vector compare
4108 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4109 // Compare 16-byte vectors
4110 masm.andl(tmp2Reg, 0xfffffff0); // vector count (in bytes)
4111 masm.andl(resultReg, 0x0000000e); // tail count (in bytes)
4112 masm.testl(tmp2Reg, tmp2Reg);
4113 masm.jccb(Assembler::zero, COMPARE_TAIL);
4114 masm.lea(ary1Reg, Address(ary1Reg, tmp2Reg, Address::times_1));
4115 masm.lea(ary2Reg, Address(ary2Reg, tmp2Reg, Address::times_1));
4116 masm.negptr(tmp2Reg);
4117
4118 masm.bind(COMPARE_WIDE_VECTORS);
4119 masm.movdqu(xmm6, Address(ary1Reg, tmp2Reg, Address::times_1));
4120 masm.movdqu(xmm7, Address(ary2Reg, tmp2Reg, Address::times_1));
4121 masm.pxor(xmm6, xmm7);
4122 masm.ptest(xmm6, xmm6);
4123
4124 masm.jccb(Assembler::notZero, FALSE_LABEL);
4125 masm.addptr(tmp2Reg, 16);
4126 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4127 masm.bind(COMPARE_TAIL);
4128 masm.movl(tmp2Reg, resultReg);
4129 // Fallthru to tail compare
4130 }
4131
4132 // Compare 4-byte vectors
4133 masm.andl(tmp2Reg, 0xfffffffc); // vector count (in bytes)
4134 masm.andl(resultReg, 0x00000002); // tail char (in bytes)
4135 masm.testl(tmp2Reg, tmp2Reg); //if tmp2 == 0, only compare char
4136 masm.jccb(Assembler::zero, COMPARE_CHAR);
4137 masm.lea(ary1Reg, Address(ary1Reg, tmp2Reg, Address::times_1));
4138 masm.lea(ary2Reg, Address(ary2Reg, tmp2Reg, Address::times_1));
4139 masm.negptr(tmp2Reg);
4140
4141 masm.bind(COMPARE_VECTORS);
4142 masm.movl(tmp1Reg, Address(ary1Reg, tmp2Reg, Address::times_1));
4143 masm.cmpl(tmp1Reg, Address(ary2Reg, tmp2Reg, Address::times_1));
4144 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4145 masm.addptr(tmp2Reg, 4);
4146 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4147
4148 // Compare trailing char (final 2 bytes), if any
4149 masm.bind(COMPARE_CHAR);
4150 masm.testl(resultReg, resultReg);
4151 masm.jccb(Assembler::zero, TRUE_LABEL);
4152 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, 0));
4153 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, 0));
4154 masm.cmpl(tmp1Reg, tmp2Reg);
4155 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4156
4157 masm.bind(TRUE_LABEL);
4158 masm.movl(resultReg, 1); // return true
4159 masm.jmpb(DONE);
4160
4161 masm.bind(FALSE_LABEL);
4162 masm.xorl(resultReg, resultReg); // return false
4163
4164 // That's it
4165 masm.bind(DONE);
4166 %}
4167
4168 enc_class enc_rethrow()
4169 %{
4170 cbuf.set_inst_mark();
4171 emit_opcode(cbuf, 0xE9); // jmp entry
4172 emit_d32_reloc(cbuf,
4173 (int) (OptoRuntime::rethrow_stub() - cbuf.code_end() - 4),
4174 runtime_call_Relocation::spec(),
4175 RELOC_DISP32);
4176 %}
4177
4178 enc_class absF_encoding(regF dst)
4179 %{
4180 int dstenc = $dst$$reg;
4181 address signmask_address = (address) StubRoutines::x86::float_sign_mask();
4182
4183 cbuf.set_inst_mark();
4184 if (dstenc >= 8) {
4185 emit_opcode(cbuf, Assembler::REX_R);
4186 dstenc -= 8;
4187 }
4188 // XXX reg_mem doesn't support RIP-relative addressing yet
4189 emit_opcode(cbuf, 0x0F);
4190 emit_opcode(cbuf, 0x54);
4191 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
4192 emit_d32_reloc(cbuf, signmask_address);
4193 %}
4194
4195 enc_class absD_encoding(regD dst)
4196 %{
4197 int dstenc = $dst$$reg;
4198 address signmask_address = (address) StubRoutines::x86::double_sign_mask();
4199
4200 cbuf.set_inst_mark();
4201 emit_opcode(cbuf, 0x66);
4202 if (dstenc >= 8) {
4203 emit_opcode(cbuf, Assembler::REX_R);
4204 dstenc -= 8;
4205 }
4206 // XXX reg_mem doesn't support RIP-relative addressing yet
4207 emit_opcode(cbuf, 0x0F);
4208 emit_opcode(cbuf, 0x54);
4209 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
4210 emit_d32_reloc(cbuf, signmask_address);
4211 %}
4212
4213 enc_class negF_encoding(regF dst)
4214 %{
4215 int dstenc = $dst$$reg;
4216 address signflip_address = (address) StubRoutines::x86::float_sign_flip();
4217
4218 cbuf.set_inst_mark();
4219 if (dstenc >= 8) {
4220 emit_opcode(cbuf, Assembler::REX_R);
4221 dstenc -= 8;
4222 }
4223 // XXX reg_mem doesn't support RIP-relative addressing yet
4224 emit_opcode(cbuf, 0x0F);
4225 emit_opcode(cbuf, 0x57);
4226 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
4227 emit_d32_reloc(cbuf, signflip_address);
4228 %}
4229
4230 enc_class negD_encoding(regD dst)
4231 %{
4232 int dstenc = $dst$$reg;
4233 address signflip_address = (address) StubRoutines::x86::double_sign_flip();
4234
4235 cbuf.set_inst_mark();
4236 emit_opcode(cbuf, 0x66);
4237 if (dstenc >= 8) {
4238 emit_opcode(cbuf, Assembler::REX_R);
4239 dstenc -= 8;
4240 }
4241 // XXX reg_mem doesn't support RIP-relative addressing yet
4242 emit_opcode(cbuf, 0x0F);
4243 emit_opcode(cbuf, 0x57);
4244 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101
4245 emit_d32_reloc(cbuf, signflip_address);
4246 %}
4247
4248 enc_class f2i_fixup(rRegI dst, regF src)
4249 %{
4250 int dstenc = $dst$$reg;
4251 int srcenc = $src$$reg;
4252
4253 // cmpl $dst, #0x80000000
4254 if (dstenc >= 8) {
4255 emit_opcode(cbuf, Assembler::REX_B);
4256 }
4257 emit_opcode(cbuf, 0x81);
4258 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
4259 emit_d32(cbuf, 0x80000000);
4260
4261 // jne,s done
4262 emit_opcode(cbuf, 0x75);
4263 if (srcenc < 8 && dstenc < 8) {
4264 emit_d8(cbuf, 0xF);
4265 } else if (srcenc >= 8 && dstenc >= 8) {
4266 emit_d8(cbuf, 0x11);
4267 } else {
4268 emit_d8(cbuf, 0x10);
4269 }
4270
4271 // subq rsp, #8
4272 emit_opcode(cbuf, Assembler::REX_W);
4273 emit_opcode(cbuf, 0x83);
4274 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4275 emit_d8(cbuf, 8);
4276
4277 // movss [rsp], $src
4278 emit_opcode(cbuf, 0xF3);
4279 if (srcenc >= 8) {
4280 emit_opcode(cbuf, Assembler::REX_R);
4281 }
4282 emit_opcode(cbuf, 0x0F);
4283 emit_opcode(cbuf, 0x11);
4284 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4285
4286 // call f2i_fixup
4287 cbuf.set_inst_mark();
4288 emit_opcode(cbuf, 0xE8);
4289 emit_d32_reloc(cbuf,
4290 (int)
4291 (StubRoutines::x86::f2i_fixup() - cbuf.code_end() - 4),
4292 runtime_call_Relocation::spec(),
4293 RELOC_DISP32);
4294
4295 // popq $dst
4296 if (dstenc >= 8) {
4297 emit_opcode(cbuf, Assembler::REX_B);
4298 }
4299 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4300
4301 // done:
4302 %}
4303
4304 enc_class f2l_fixup(rRegL dst, regF src)
4305 %{
4306 int dstenc = $dst$$reg;
4307 int srcenc = $src$$reg;
4308 address const_address = (address) StubRoutines::x86::double_sign_flip();
4309
4310 // cmpq $dst, [0x8000000000000000]
4311 cbuf.set_inst_mark();
4312 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
4313 emit_opcode(cbuf, 0x39);
4314 // XXX reg_mem doesn't support RIP-relative addressing yet
4315 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
4316 emit_d32_reloc(cbuf, const_address);
4317
4318
4319 // jne,s done
4320 emit_opcode(cbuf, 0x75);
4321 if (srcenc < 8 && dstenc < 8) {
4322 emit_d8(cbuf, 0xF);
4323 } else if (srcenc >= 8 && dstenc >= 8) {
4324 emit_d8(cbuf, 0x11);
4325 } else {
4326 emit_d8(cbuf, 0x10);
4327 }
4328
4329 // subq rsp, #8
4330 emit_opcode(cbuf, Assembler::REX_W);
4331 emit_opcode(cbuf, 0x83);
4332 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4333 emit_d8(cbuf, 8);
4334
4335 // movss [rsp], $src
4336 emit_opcode(cbuf, 0xF3);
4337 if (srcenc >= 8) {
4338 emit_opcode(cbuf, Assembler::REX_R);
4339 }
4340 emit_opcode(cbuf, 0x0F);
4341 emit_opcode(cbuf, 0x11);
4342 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4343
4344 // call f2l_fixup
4345 cbuf.set_inst_mark();
4346 emit_opcode(cbuf, 0xE8);
4347 emit_d32_reloc(cbuf,
4348 (int)
4349 (StubRoutines::x86::f2l_fixup() - cbuf.code_end() - 4),
4350 runtime_call_Relocation::spec(),
4351 RELOC_DISP32);
4352
4353 // popq $dst
4354 if (dstenc >= 8) {
4355 emit_opcode(cbuf, Assembler::REX_B);
4356 }
4357 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4358
4359 // done:
4360 %}
4361
4362 enc_class d2i_fixup(rRegI dst, regD src)
4363 %{
4364 int dstenc = $dst$$reg;
4365 int srcenc = $src$$reg;
4366
4367 // cmpl $dst, #0x80000000
4368 if (dstenc >= 8) {
4369 emit_opcode(cbuf, Assembler::REX_B);
4370 }
4371 emit_opcode(cbuf, 0x81);
4372 emit_rm(cbuf, 0x3, 0x7, dstenc & 7);
4373 emit_d32(cbuf, 0x80000000);
4374
4375 // jne,s done
4376 emit_opcode(cbuf, 0x75);
4377 if (srcenc < 8 && dstenc < 8) {
4378 emit_d8(cbuf, 0xF);
4379 } else if (srcenc >= 8 && dstenc >= 8) {
4380 emit_d8(cbuf, 0x11);
4381 } else {
4382 emit_d8(cbuf, 0x10);
4383 }
4384
4385 // subq rsp, #8
4386 emit_opcode(cbuf, Assembler::REX_W);
4387 emit_opcode(cbuf, 0x83);
4388 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4389 emit_d8(cbuf, 8);
4390
4391 // movsd [rsp], $src
4392 emit_opcode(cbuf, 0xF2);
4393 if (srcenc >= 8) {
4394 emit_opcode(cbuf, Assembler::REX_R);
4395 }
4396 emit_opcode(cbuf, 0x0F);
4397 emit_opcode(cbuf, 0x11);
4398 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4399
4400 // call d2i_fixup
4401 cbuf.set_inst_mark();
4402 emit_opcode(cbuf, 0xE8);
4403 emit_d32_reloc(cbuf,
4404 (int)
4405 (StubRoutines::x86::d2i_fixup() - cbuf.code_end() - 4),
4406 runtime_call_Relocation::spec(),
4407 RELOC_DISP32);
4408
4409 // popq $dst
4410 if (dstenc >= 8) {
4411 emit_opcode(cbuf, Assembler::REX_B);
4412 }
4413 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4414
4415 // done:
4416 %}
4417
4418 enc_class d2l_fixup(rRegL dst, regD src)
4419 %{
4420 int dstenc = $dst$$reg;
4421 int srcenc = $src$$reg;
4422 address const_address = (address) StubRoutines::x86::double_sign_flip();
4423
4424 // cmpq $dst, [0x8000000000000000]
4425 cbuf.set_inst_mark();
4426 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR);
4427 emit_opcode(cbuf, 0x39);
4428 // XXX reg_mem doesn't support RIP-relative addressing yet
4429 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101
4430 emit_d32_reloc(cbuf, const_address);
4431
4432
4433 // jne,s done
4434 emit_opcode(cbuf, 0x75);
4435 if (srcenc < 8 && dstenc < 8) {
4436 emit_d8(cbuf, 0xF);
4437 } else if (srcenc >= 8 && dstenc >= 8) {
4438 emit_d8(cbuf, 0x11);
4439 } else {
4440 emit_d8(cbuf, 0x10);
4441 }
4442
4443 // subq rsp, #8
4444 emit_opcode(cbuf, Assembler::REX_W);
4445 emit_opcode(cbuf, 0x83);
4446 emit_rm(cbuf, 0x3, 0x5, RSP_enc);
4447 emit_d8(cbuf, 8);
4448
4449 // movsd [rsp], $src
4450 emit_opcode(cbuf, 0xF2);
4451 if (srcenc >= 8) {
4452 emit_opcode(cbuf, Assembler::REX_R);
4453 }
4454 emit_opcode(cbuf, 0x0F);
4455 emit_opcode(cbuf, 0x11);
4456 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes
4457
4458 // call d2l_fixup
4459 cbuf.set_inst_mark();
4460 emit_opcode(cbuf, 0xE8);
4461 emit_d32_reloc(cbuf,
4462 (int)
4463 (StubRoutines::x86::d2l_fixup() - cbuf.code_end() - 4),
4464 runtime_call_Relocation::spec(),
4465 RELOC_DISP32);
4466
4467 // popq $dst
4468 if (dstenc >= 8) {
4469 emit_opcode(cbuf, Assembler::REX_B);
4470 }
4471 emit_opcode(cbuf, 0x58 | (dstenc & 7));
4472
4473 // done:
4474 %}
4475
4476 enc_class enc_membar_acquire
4477 %{
4478 // [jk] not needed currently, if you enable this and it really
4479 // emits code don't forget to the remove the "size(0)" line in
4480 // membar_acquire()
4481 // MacroAssembler masm(&cbuf);
4482 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore |
4483 // Assembler::LoadLoad));
4484 %}
4485
4486 enc_class enc_membar_release
4487 %{
4488 // [jk] not needed currently, if you enable this and it really
4489 // emits code don't forget to the remove the "size(0)" line in
4490 // membar_release()
4491 // MacroAssembler masm(&cbuf);
4492 // masm.membar(Assembler::Membar_mask_bits(Assembler::LoadStore |
4493 // Assembler::StoreStore));
4494 %}
4495
4496 enc_class enc_membar_volatile
4497 %{
4498 MacroAssembler masm(&cbuf);
4499 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4500 Assembler::StoreStore));
4501 %}
4502
4503 // Safepoint Poll. This polls the safepoint page, and causes an
4504 // exception if it is not readable. Unfortunately, it kills
4505 // RFLAGS in the process.
4506 enc_class enc_safepoint_poll
4507 %{
4508 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes
4509 // XXX reg_mem doesn't support RIP-relative addressing yet
4510 cbuf.set_inst_mark();
4511 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); // XXX
4512 emit_opcode(cbuf, 0x85); // testl
4513 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5
4514 // cbuf.inst_mark() is beginning of instruction
4515 emit_d32_reloc(cbuf, os::get_polling_page());
4516 // relocInfo::poll_type,
4517 %}
4518 %}
4519
4520
4521
4522 //----------FRAME--------------------------------------------------------------
4523 // Definition of frame structure and management information.
4524 //
4525 // S T A C K L A Y O U T Allocators stack-slot number
4526 // | (to get allocators register number
4527 // G Owned by | | v add OptoReg::stack0())
4528 // r CALLER | |
4529 // o | +--------+ pad to even-align allocators stack-slot
4530 // w V | pad0 | numbers; owned by CALLER
4531 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4532 // h ^ | in | 5
4533 // | | args | 4 Holes in incoming args owned by SELF
4534 // | | | | 3
4535 // | | +--------+
4536 // V | | old out| Empty on Intel, window on Sparc
4537 // | old |preserve| Must be even aligned.
4538 // | SP-+--------+----> Matcher::_old_SP, even aligned
4539 // | | in | 3 area for Intel ret address
4540 // Owned by |preserve| Empty on Sparc.
4541 // SELF +--------+
4542 // | | pad2 | 2 pad to align old SP
4543 // | +--------+ 1
4544 // | | locks | 0
4545 // | +--------+----> OptoReg::stack0(), even aligned
4546 // | | pad1 | 11 pad to align new SP
4547 // | +--------+
4548 // | | | 10
4549 // | | spills | 9 spills
4550 // V | | 8 (pad0 slot for callee)
4551 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4552 // ^ | out | 7
4553 // | | args | 6 Holes in outgoing args owned by CALLEE
4554 // Owned by +--------+
4555 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4556 // | new |preserve| Must be even-aligned.
4557 // | SP-+--------+----> Matcher::_new_SP, even aligned
4558 // | | |
4559 //
4560 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4561 // known from SELF's arguments and the Java calling convention.
4562 // Region 6-7 is determined per call site.
4563 // Note 2: If the calling convention leaves holes in the incoming argument
4564 // area, those holes are owned by SELF. Holes in the outgoing area
4565 // are owned by the CALLEE. Holes should not be nessecary in the
4566 // incoming area, as the Java calling convention is completely under
4567 // the control of the AD file. Doubles can be sorted and packed to
4568 // avoid holes. Holes in the outgoing arguments may be nessecary for
4569 // varargs C calling conventions.
4570 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4571 // even aligned with pad0 as needed.
4572 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4573 // region 6-11 is even aligned; it may be padded out more so that
4574 // the region from SP to FP meets the minimum stack alignment.
4575 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
4576 // alignment. Region 11, pad1, may be dynamically extended so that
4577 // SP meets the minimum alignment.
4578
4579 frame
4580 %{
4581 // What direction does stack grow in (assumed to be same for C & Java)
4582 stack_direction(TOWARDS_LOW);
4583
4584 // These three registers define part of the calling convention
4585 // between compiled code and the interpreter.
4586 inline_cache_reg(RAX); // Inline Cache Register
4587 interpreter_method_oop_reg(RBX); // Method Oop Register when
4588 // calling interpreter
4589
4590 // Optional: name the operand used by cisc-spilling to access
4591 // [stack_pointer + offset]
4592 cisc_spilling_operand_name(indOffset32);
4593
4594 // Number of stack slots consumed by locking an object
4595 sync_stack_slots(2);
4596
4597 // Compiled code's Frame Pointer
4598 frame_pointer(RSP);
4599
4600 // Interpreter stores its frame pointer in a register which is
4601 // stored to the stack by I2CAdaptors.
4602 // I2CAdaptors convert from interpreted java to compiled java.
4603 interpreter_frame_pointer(RBP);
4604
4605 // Stack alignment requirement
4606 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
4607
4608 // Number of stack slots between incoming argument block and the start of
4609 // a new frame. The PROLOG must add this many slots to the stack. The
4610 // EPILOG must remove this many slots. amd64 needs two slots for
4611 // return address.
4612 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
4613
4614 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4615 // for calls to C. Supports the var-args backing area for register parms.
4616 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
4617
4618 // The after-PROLOG location of the return address. Location of
4619 // return address specifies a type (REG or STACK) and a number
4620 // representing the register number (i.e. - use a register name) or
4621 // stack slot.
4622 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4623 // Otherwise, it is above the locks and verification slot and alignment word
4624 return_addr(STACK - 2 +
4625 round_to(2 + 2 * VerifyStackAtCalls +
4626 Compile::current()->fixed_slots(),
4627 WordsPerLong * 2));
4628
4629 // Body of function which returns an integer array locating
4630 // arguments either in registers or in stack slots. Passed an array
4631 // of ideal registers called "sig" and a "length" count. Stack-slot
4632 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4633 // arguments for a CALLEE. Incoming stack arguments are
4634 // automatically biased by the preserve_stack_slots field above.
4635
4636 calling_convention
4637 %{
4638 // No difference between ingoing/outgoing just pass false
4639 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4640 %}
4641
4642 c_calling_convention
4643 %{
4644 // This is obviously always outgoing
4645 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4646 %}
4647
4648 // Location of compiled Java return values. Same as C for now.
4649 return_value
4650 %{
4651 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
4652 "only return normal values");
4653
4654 static const int lo[Op_RegL + 1] = {
4655 0,
4656 0,
4657 RAX_num, // Op_RegN
4658 RAX_num, // Op_RegI
4659 RAX_num, // Op_RegP
4660 XMM0_num, // Op_RegF
4661 XMM0_num, // Op_RegD
4662 RAX_num // Op_RegL
4663 };
4664 static const int hi[Op_RegL + 1] = {
4665 0,
4666 0,
4667 OptoReg::Bad, // Op_RegN
4668 OptoReg::Bad, // Op_RegI
4669 RAX_H_num, // Op_RegP
4670 OptoReg::Bad, // Op_RegF
4671 XMM0_H_num, // Op_RegD
4672 RAX_H_num // Op_RegL
4673 };
4674 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type");
4675 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
4676 %}
4677 %}
4678
4679 //----------ATTRIBUTES---------------------------------------------------------
4680 //----------Operand Attributes-------------------------------------------------
4681 op_attrib op_cost(0); // Required cost attribute
4682
4683 //----------Instruction Attributes---------------------------------------------
4684 ins_attrib ins_cost(100); // Required cost attribute
4685 ins_attrib ins_size(8); // Required size attribute (in bits)
4686 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4687 ins_attrib ins_short_branch(0); // Required flag: is this instruction
4688 // a non-matching short branch variant
4689 // of some long branch?
4690 ins_attrib ins_alignment(1); // Required alignment attribute (must
4691 // be a power of 2) specifies the
4692 // alignment that some part of the
4693 // instruction (not necessarily the
4694 // start) requires. If > 1, a
4695 // compute_padding() function must be
4696 // provided for the instruction
4697
4698 //----------OPERANDS-----------------------------------------------------------
4699 // Operand definitions must precede instruction definitions for correct parsing
4700 // in the ADLC because operands constitute user defined types which are used in
4701 // instruction definitions.
4702
4703 //----------Simple Operands----------------------------------------------------
4704 // Immediate Operands
4705 // Integer Immediate
4706 operand immI()
4707 %{
4708 match(ConI);
4709
4710 op_cost(10);
4711 format %{ %}
4712 interface(CONST_INTER);
4713 %}
4714
4715 // Constant for test vs zero
4716 operand immI0()
4717 %{
4718 predicate(n->get_int() == 0);
4719 match(ConI);
4720
4721 op_cost(0);
4722 format %{ %}
4723 interface(CONST_INTER);
4724 %}
4725
4726 // Constant for increment
4727 operand immI1()
4728 %{
4729 predicate(n->get_int() == 1);
4730 match(ConI);
4731
4732 op_cost(0);
4733 format %{ %}
4734 interface(CONST_INTER);
4735 %}
4736
4737 // Constant for decrement
4738 operand immI_M1()
4739 %{
4740 predicate(n->get_int() == -1);
4741 match(ConI);
4742
4743 op_cost(0);
4744 format %{ %}
4745 interface(CONST_INTER);
4746 %}
4747
4748 // Valid scale values for addressing modes
4749 operand immI2()
4750 %{
4751 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4752 match(ConI);
4753
4754 format %{ %}
4755 interface(CONST_INTER);
4756 %}
4757
4758 operand immI8()
4759 %{
4760 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
4761 match(ConI);
4762
4763 op_cost(5);
4764 format %{ %}
4765 interface(CONST_INTER);
4766 %}
4767
4768 operand immI16()
4769 %{
4770 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4771 match(ConI);
4772
4773 op_cost(10);
4774 format %{ %}
4775 interface(CONST_INTER);
4776 %}
4777
4778 // Constant for long shifts
4779 operand immI_32()
4780 %{
4781 predicate( n->get_int() == 32 );
4782 match(ConI);
4783
4784 op_cost(0);
4785 format %{ %}
4786 interface(CONST_INTER);
4787 %}
4788
4789 // Constant for long shifts
4790 operand immI_64()
4791 %{
4792 predicate( n->get_int() == 64 );
4793 match(ConI);
4794
4795 op_cost(0);
4796 format %{ %}
4797 interface(CONST_INTER);
4798 %}
4799
4800 // Pointer Immediate
4801 operand immP()
4802 %{
4803 match(ConP);
4804
4805 op_cost(10);
4806 format %{ %}
4807 interface(CONST_INTER);
4808 %}
4809
4810 // NULL Pointer Immediate
4811 operand immP0()
4812 %{
4813 predicate(n->get_ptr() == 0);
4814 match(ConP);
4815
4816 op_cost(5);
4817 format %{ %}
4818 interface(CONST_INTER);
4819 %}
4820
4821 // Pointer Immediate
4822 operand immN() %{
4823 match(ConN);
4824
4825 op_cost(10);
4826 format %{ %}
4827 interface(CONST_INTER);
4828 %}
4829
4830 // NULL Pointer Immediate
4831 operand immN0() %{
4832 predicate(n->get_narrowcon() == 0);
4833 match(ConN);
4834
4835 op_cost(5);
4836 format %{ %}
4837 interface(CONST_INTER);
4838 %}
4839
4840 operand immP31()
4841 %{
4842 predicate(!n->as_Type()->type()->isa_oopptr()
4843 && (n->get_ptr() >> 31) == 0);
4844 match(ConP);
4845
4846 op_cost(5);
4847 format %{ %}
4848 interface(CONST_INTER);
4849 %}
4850
4851
4852 // Long Immediate
4853 operand immL()
4854 %{
4855 match(ConL);
4856
4857 op_cost(20);
4858 format %{ %}
4859 interface(CONST_INTER);
4860 %}
4861
4862 // Long Immediate 8-bit
4863 operand immL8()
4864 %{
4865 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
4866 match(ConL);
4867
4868 op_cost(5);
4869 format %{ %}
4870 interface(CONST_INTER);
4871 %}
4872
4873 // Long Immediate 32-bit unsigned
4874 operand immUL32()
4875 %{
4876 predicate(n->get_long() == (unsigned int) (n->get_long()));
4877 match(ConL);
4878
4879 op_cost(10);
4880 format %{ %}
4881 interface(CONST_INTER);
4882 %}
4883
4884 // Long Immediate 32-bit signed
4885 operand immL32()
4886 %{
4887 predicate(n->get_long() == (int) (n->get_long()));
4888 match(ConL);
4889
4890 op_cost(15);
4891 format %{ %}
4892 interface(CONST_INTER);
4893 %}
4894
4895 // Long Immediate zero
4896 operand immL0()
4897 %{
4898 predicate(n->get_long() == 0L);
4899 match(ConL);
4900
4901 op_cost(10);
4902 format %{ %}
4903 interface(CONST_INTER);
4904 %}
4905
4906 // Constant for increment
4907 operand immL1()
4908 %{
4909 predicate(n->get_long() == 1);
4910 match(ConL);
4911
4912 format %{ %}
4913 interface(CONST_INTER);
4914 %}
4915
4916 // Constant for decrement
4917 operand immL_M1()
4918 %{
4919 predicate(n->get_long() == -1);
4920 match(ConL);
4921
4922 format %{ %}
4923 interface(CONST_INTER);
4924 %}
4925
4926 // Long Immediate: the value 10
4927 operand immL10()
4928 %{
4929 predicate(n->get_long() == 10);
4930 match(ConL);
4931
4932 format %{ %}
4933 interface(CONST_INTER);
4934 %}
4935
4936 // Long immediate from 0 to 127.
4937 // Used for a shorter form of long mul by 10.
4938 operand immL_127()
4939 %{
4940 predicate(0 <= n->get_long() && n->get_long() < 0x80);
4941 match(ConL);
4942
4943 op_cost(10);
4944 format %{ %}
4945 interface(CONST_INTER);
4946 %}
4947
4948 // Long Immediate: low 32-bit mask
4949 operand immL_32bits()
4950 %{
4951 predicate(n->get_long() == 0xFFFFFFFFL);
4952 match(ConL);
4953 op_cost(20);
4954
4955 format %{ %}
4956 interface(CONST_INTER);
4957 %}
4958
4959 // Float Immediate zero
4960 operand immF0()
4961 %{
4962 predicate(jint_cast(n->getf()) == 0);
4963 match(ConF);
4964
4965 op_cost(5);
4966 format %{ %}
4967 interface(CONST_INTER);
4968 %}
4969
4970 // Float Immediate
4971 operand immF()
4972 %{
4973 match(ConF);
4974
4975 op_cost(15);
4976 format %{ %}
4977 interface(CONST_INTER);
4978 %}
4979
4980 // Double Immediate zero
4981 operand immD0()
4982 %{
4983 predicate(jlong_cast(n->getd()) == 0);
4984 match(ConD);
4985
4986 op_cost(5);
4987 format %{ %}
4988 interface(CONST_INTER);
4989 %}
4990
4991 // Double Immediate
4992 operand immD()
4993 %{
4994 match(ConD);
4995
4996 op_cost(15);
4997 format %{ %}
4998 interface(CONST_INTER);
4999 %}
5000
5001 // Immediates for special shifts (sign extend)
5002
5003 // Constants for increment
5004 operand immI_16()
5005 %{
5006 predicate(n->get_int() == 16);
5007 match(ConI);
5008
5009 format %{ %}
5010 interface(CONST_INTER);
5011 %}
5012
5013 operand immI_24()
5014 %{
5015 predicate(n->get_int() == 24);
5016 match(ConI);
5017
5018 format %{ %}
5019 interface(CONST_INTER);
5020 %}
5021
5022 // Constant for byte-wide masking
5023 operand immI_255()
5024 %{
5025 predicate(n->get_int() == 255);
5026 match(ConI);
5027
5028 format %{ %}
5029 interface(CONST_INTER);
5030 %}
5031
5032 // Constant for short-wide masking
5033 operand immI_65535()
5034 %{
5035 predicate(n->get_int() == 65535);
5036 match(ConI);
5037
5038 format %{ %}
5039 interface(CONST_INTER);
5040 %}
5041
5042 // Constant for byte-wide masking
5043 operand immL_255()
5044 %{
5045 predicate(n->get_long() == 255);
5046 match(ConL);
5047
5048 format %{ %}
5049 interface(CONST_INTER);
5050 %}
5051
5052 // Constant for short-wide masking
5053 operand immL_65535()
5054 %{
5055 predicate(n->get_long() == 65535);
5056 match(ConL);
5057
5058 format %{ %}
5059 interface(CONST_INTER);
5060 %}
5061
5062 // Register Operands
5063 // Integer Register
5064 operand rRegI()
5065 %{
5066 constraint(ALLOC_IN_RC(int_reg));
5067 match(RegI);
5068
5069 match(rax_RegI);
5070 match(rbx_RegI);
5071 match(rcx_RegI);
5072 match(rdx_RegI);
5073 match(rdi_RegI);
5074
5075 format %{ %}
5076 interface(REG_INTER);
5077 %}
5078
5079 // Special Registers
5080 operand rax_RegI()
5081 %{
5082 constraint(ALLOC_IN_RC(int_rax_reg));
5083 match(RegI);
5084 match(rRegI);
5085
5086 format %{ "RAX" %}
5087 interface(REG_INTER);
5088 %}
5089
5090 // Special Registers
5091 operand rbx_RegI()
5092 %{
5093 constraint(ALLOC_IN_RC(int_rbx_reg));
5094 match(RegI);
5095 match(rRegI);
5096
5097 format %{ "RBX" %}
5098 interface(REG_INTER);
5099 %}
5100
5101 operand rcx_RegI()
5102 %{
5103 constraint(ALLOC_IN_RC(int_rcx_reg));
5104 match(RegI);
5105 match(rRegI);
5106
5107 format %{ "RCX" %}
5108 interface(REG_INTER);
5109 %}
5110
5111 operand rdx_RegI()
5112 %{
5113 constraint(ALLOC_IN_RC(int_rdx_reg));
5114 match(RegI);
5115 match(rRegI);
5116
5117 format %{ "RDX" %}
5118 interface(REG_INTER);
5119 %}
5120
5121 operand rdi_RegI()
5122 %{
5123 constraint(ALLOC_IN_RC(int_rdi_reg));
5124 match(RegI);
5125 match(rRegI);
5126
5127 format %{ "RDI" %}
5128 interface(REG_INTER);
5129 %}
5130
5131 operand no_rcx_RegI()
5132 %{
5133 constraint(ALLOC_IN_RC(int_no_rcx_reg));
5134 match(RegI);
5135 match(rax_RegI);
5136 match(rbx_RegI);
5137 match(rdx_RegI);
5138 match(rdi_RegI);
5139
5140 format %{ %}
5141 interface(REG_INTER);
5142 %}
5143
5144 operand no_rax_rdx_RegI()
5145 %{
5146 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
5147 match(RegI);
5148 match(rbx_RegI);
5149 match(rcx_RegI);
5150 match(rdi_RegI);
5151
5152 format %{ %}
5153 interface(REG_INTER);
5154 %}
5155
5156 // Pointer Register
5157 operand any_RegP()
5158 %{
5159 constraint(ALLOC_IN_RC(any_reg));
5160 match(RegP);
5161 match(rax_RegP);
5162 match(rbx_RegP);
5163 match(rdi_RegP);
5164 match(rsi_RegP);
5165 match(rbp_RegP);
5166 match(r15_RegP);
5167 match(rRegP);
5168
5169 format %{ %}
5170 interface(REG_INTER);
5171 %}
5172
5173 operand rRegP()
5174 %{
5175 constraint(ALLOC_IN_RC(ptr_reg));
5176 match(RegP);
5177 match(rax_RegP);
5178 match(rbx_RegP);
5179 match(rdi_RegP);
5180 match(rsi_RegP);
5181 match(rbp_RegP);
5182 match(r15_RegP); // See Q&A below about r15_RegP.
5183
5184 format %{ %}
5185 interface(REG_INTER);
5186 %}
5187
5188
5189 operand r12RegL() %{
5190 constraint(ALLOC_IN_RC(long_r12_reg));
5191 match(RegL);
5192
5193 format %{ %}
5194 interface(REG_INTER);
5195 %}
5196
5197 operand rRegN() %{
5198 constraint(ALLOC_IN_RC(int_reg));
5199 match(RegN);
5200
5201 format %{ %}
5202 interface(REG_INTER);
5203 %}
5204
5205 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
5206 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
5207 // It's fine for an instruction input which expects rRegP to match a r15_RegP.
5208 // The output of an instruction is controlled by the allocator, which respects
5209 // register class masks, not match rules. Unless an instruction mentions
5210 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
5211 // by the allocator as an input.
5212
5213 operand no_rax_RegP()
5214 %{
5215 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
5216 match(RegP);
5217 match(rbx_RegP);
5218 match(rsi_RegP);
5219 match(rdi_RegP);
5220
5221 format %{ %}
5222 interface(REG_INTER);
5223 %}
5224
5225 operand no_rbp_RegP()
5226 %{
5227 constraint(ALLOC_IN_RC(ptr_no_rbp_reg));
5228 match(RegP);
5229 match(rbx_RegP);
5230 match(rsi_RegP);
5231 match(rdi_RegP);
5232
5233 format %{ %}
5234 interface(REG_INTER);
5235 %}
5236
5237 operand no_rax_rbx_RegP()
5238 %{
5239 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
5240 match(RegP);
5241 match(rsi_RegP);
5242 match(rdi_RegP);
5243
5244 format %{ %}
5245 interface(REG_INTER);
5246 %}
5247
5248 // Special Registers
5249 // Return a pointer value
5250 operand rax_RegP()
5251 %{
5252 constraint(ALLOC_IN_RC(ptr_rax_reg));
5253 match(RegP);
5254 match(rRegP);
5255
5256 format %{ %}
5257 interface(REG_INTER);
5258 %}
5259
5260 // Special Registers
5261 // Return a compressed pointer value
5262 operand rax_RegN()
5263 %{
5264 constraint(ALLOC_IN_RC(int_rax_reg));
5265 match(RegN);
5266 match(rRegN);
5267
5268 format %{ %}
5269 interface(REG_INTER);
5270 %}
5271
5272 // Used in AtomicAdd
5273 operand rbx_RegP()
5274 %{
5275 constraint(ALLOC_IN_RC(ptr_rbx_reg));
5276 match(RegP);
5277 match(rRegP);
5278
5279 format %{ %}
5280 interface(REG_INTER);
5281 %}
5282
5283 operand rsi_RegP()
5284 %{
5285 constraint(ALLOC_IN_RC(ptr_rsi_reg));
5286 match(RegP);
5287 match(rRegP);
5288
5289 format %{ %}
5290 interface(REG_INTER);
5291 %}
5292
5293 // Used in rep stosq
5294 operand rdi_RegP()
5295 %{
5296 constraint(ALLOC_IN_RC(ptr_rdi_reg));
5297 match(RegP);
5298 match(rRegP);
5299
5300 format %{ %}
5301 interface(REG_INTER);
5302 %}
5303
5304 operand rbp_RegP()
5305 %{
5306 constraint(ALLOC_IN_RC(ptr_rbp_reg));
5307 match(RegP);
5308 match(rRegP);
5309
5310 format %{ %}
5311 interface(REG_INTER);
5312 %}
5313
5314 operand r15_RegP()
5315 %{
5316 constraint(ALLOC_IN_RC(ptr_r15_reg));
5317 match(RegP);
5318 match(rRegP);
5319
5320 format %{ %}
5321 interface(REG_INTER);
5322 %}
5323
5324 operand rRegL()
5325 %{
5326 constraint(ALLOC_IN_RC(long_reg));
5327 match(RegL);
5328 match(rax_RegL);
5329 match(rdx_RegL);
5330
5331 format %{ %}
5332 interface(REG_INTER);
5333 %}
5334
5335 // Special Registers
5336 operand no_rax_rdx_RegL()
5337 %{
5338 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
5339 match(RegL);
5340 match(rRegL);
5341
5342 format %{ %}
5343 interface(REG_INTER);
5344 %}
5345
5346 operand no_rax_RegL()
5347 %{
5348 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
5349 match(RegL);
5350 match(rRegL);
5351 match(rdx_RegL);
5352
5353 format %{ %}
5354 interface(REG_INTER);
5355 %}
5356
5357 operand no_rcx_RegL()
5358 %{
5359 constraint(ALLOC_IN_RC(long_no_rcx_reg));
5360 match(RegL);
5361 match(rRegL);
5362
5363 format %{ %}
5364 interface(REG_INTER);
5365 %}
5366
5367 operand rax_RegL()
5368 %{
5369 constraint(ALLOC_IN_RC(long_rax_reg));
5370 match(RegL);
5371 match(rRegL);
5372
5373 format %{ "RAX" %}
5374 interface(REG_INTER);
5375 %}
5376
5377 operand rcx_RegL()
5378 %{
5379 constraint(ALLOC_IN_RC(long_rcx_reg));
5380 match(RegL);
5381 match(rRegL);
5382
5383 format %{ %}
5384 interface(REG_INTER);
5385 %}
5386
5387 operand rdx_RegL()
5388 %{
5389 constraint(ALLOC_IN_RC(long_rdx_reg));
5390 match(RegL);
5391 match(rRegL);
5392
5393 format %{ %}
5394 interface(REG_INTER);
5395 %}
5396
5397 // Flags register, used as output of compare instructions
5398 operand rFlagsReg()
5399 %{
5400 constraint(ALLOC_IN_RC(int_flags));
5401 match(RegFlags);
5402
5403 format %{ "RFLAGS" %}
5404 interface(REG_INTER);
5405 %}
5406
5407 // Flags register, used as output of FLOATING POINT compare instructions
5408 operand rFlagsRegU()
5409 %{
5410 constraint(ALLOC_IN_RC(int_flags));
5411 match(RegFlags);
5412
5413 format %{ "RFLAGS_U" %}
5414 interface(REG_INTER);
5415 %}
5416
5417 operand rFlagsRegUCF() %{
5418 constraint(ALLOC_IN_RC(int_flags));
5419 match(RegFlags);
5420 predicate(false);
5421
5422 format %{ "RFLAGS_U_CF" %}
5423 interface(REG_INTER);
5424 %}
5425
5426 // Float register operands
5427 operand regF()
5428 %{
5429 constraint(ALLOC_IN_RC(float_reg));
5430 match(RegF);
5431
5432 format %{ %}
5433 interface(REG_INTER);
5434 %}
5435
5436 // XMM Double register operands
5437 operand regD() %{
5438 constraint(ALLOC_IN_RC(double_reg));
5439 match(RegD);
5440 match(regD6);
5441 match(regD7);
5442 format %{ %}
5443 interface(REG_INTER);
5444 %}
5445
5446 // XMM6 double register operands
5447 operand regD6(regD reg) %{
5448 constraint(ALLOC_IN_RC(double_reg6));
5449 match(reg);
5450 format %{ "XMM6" %}
5451 interface(REG_INTER);
5452 %}
5453
5454 // XMM7 double register operands
5455 operand regD7(regD reg) %{
5456 constraint(ALLOC_IN_RC(double_reg7));
5457 match(reg);
5458
5459 format %{ "XMM7" %}
5460 interface(REG_INTER);
5461 %}
5462
5463 //----------Memory Operands----------------------------------------------------
5464 // Direct Memory Operand
5465 // operand direct(immP addr)
5466 // %{
5467 // match(addr);
5468
5469 // format %{ "[$addr]" %}
5470 // interface(MEMORY_INTER) %{
5471 // base(0xFFFFFFFF);
5472 // index(0x4);
5473 // scale(0x0);
5474 // disp($addr);
5475 // %}
5476 // %}
5477
5478 // Indirect Memory Operand
5479 operand indirect(any_RegP reg)
5480 %{
5481 constraint(ALLOC_IN_RC(ptr_reg));
5482 match(reg);
5483
5484 format %{ "[$reg]" %}
5485 interface(MEMORY_INTER) %{
5486 base($reg);
5487 index(0x4);
5488 scale(0x0);
5489 disp(0x0);
5490 %}
5491 %}
5492
5493 // Indirect Memory Plus Short Offset Operand
5494 operand indOffset8(any_RegP reg, immL8 off)
5495 %{
5496 constraint(ALLOC_IN_RC(ptr_reg));
5497 match(AddP reg off);
5498
5499 format %{ "[$reg + $off (8-bit)]" %}
5500 interface(MEMORY_INTER) %{
5501 base($reg);
5502 index(0x4);
5503 scale(0x0);
5504 disp($off);
5505 %}
5506 %}
5507
5508 // Indirect Memory Plus Long Offset Operand
5509 operand indOffset32(any_RegP reg, immL32 off)
5510 %{
5511 constraint(ALLOC_IN_RC(ptr_reg));
5512 match(AddP reg off);
5513
5514 format %{ "[$reg + $off (32-bit)]" %}
5515 interface(MEMORY_INTER) %{
5516 base($reg);
5517 index(0x4);
5518 scale(0x0);
5519 disp($off);
5520 %}
5521 %}
5522
5523 // Indirect Memory Plus Index Register Plus Offset Operand
5524 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
5525 %{
5526 constraint(ALLOC_IN_RC(ptr_reg));
5527 match(AddP (AddP reg lreg) off);
5528
5529 op_cost(10);
5530 format %{"[$reg + $off + $lreg]" %}
5531 interface(MEMORY_INTER) %{
5532 base($reg);
5533 index($lreg);
5534 scale(0x0);
5535 disp($off);
5536 %}
5537 %}
5538
5539 // Indirect Memory Plus Index Register Plus Offset Operand
5540 operand indIndex(any_RegP reg, rRegL lreg)
5541 %{
5542 constraint(ALLOC_IN_RC(ptr_reg));
5543 match(AddP reg lreg);
5544
5545 op_cost(10);
5546 format %{"[$reg + $lreg]" %}
5547 interface(MEMORY_INTER) %{
5548 base($reg);
5549 index($lreg);
5550 scale(0x0);
5551 disp(0x0);
5552 %}
5553 %}
5554
5555 // Indirect Memory Times Scale Plus Index Register
5556 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
5557 %{
5558 constraint(ALLOC_IN_RC(ptr_reg));
5559 match(AddP reg (LShiftL lreg scale));
5560
5561 op_cost(10);
5562 format %{"[$reg + $lreg << $scale]" %}
5563 interface(MEMORY_INTER) %{
5564 base($reg);
5565 index($lreg);
5566 scale($scale);
5567 disp(0x0);
5568 %}
5569 %}
5570
5571 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5572 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
5573 %{
5574 constraint(ALLOC_IN_RC(ptr_reg));
5575 match(AddP (AddP reg (LShiftL lreg scale)) off);
5576
5577 op_cost(10);
5578 format %{"[$reg + $off + $lreg << $scale]" %}
5579 interface(MEMORY_INTER) %{
5580 base($reg);
5581 index($lreg);
5582 scale($scale);
5583 disp($off);
5584 %}
5585 %}
5586
5587 // Indirect Narrow Oop Plus Offset Operand
5588 operand indNarrowOopOffset(rRegN src, immL32 off) %{
5589 constraint(ALLOC_IN_RC(ptr_reg));
5590 match(AddP (DecodeN src) off);
5591
5592 op_cost(10);
5593 format %{"[R12 + $src << 3 + $off] (compressed oop addressing)" %}
5594 interface(MEMORY_INTER) %{
5595 base(0xc); // R12
5596 index($src);
5597 scale(0x3);
5598 disp($off);
5599 %}
5600 %}
5601
5602 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
5603 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
5604 %{
5605 constraint(ALLOC_IN_RC(ptr_reg));
5606 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
5607 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
5608
5609 op_cost(10);
5610 format %{"[$reg + $off + $idx << $scale]" %}
5611 interface(MEMORY_INTER) %{
5612 base($reg);
5613 index($idx);
5614 scale($scale);
5615 disp($off);
5616 %}
5617 %}
5618
5619 //----------Special Memory Operands--------------------------------------------
5620 // Stack Slot Operand - This operand is used for loading and storing temporary
5621 // values on the stack where a match requires a value to
5622 // flow through memory.
5623 operand stackSlotP(sRegP reg)
5624 %{
5625 constraint(ALLOC_IN_RC(stack_slots));
5626 // No match rule because this operand is only generated in matching
5627
5628 format %{ "[$reg]" %}
5629 interface(MEMORY_INTER) %{
5630 base(0x4); // RSP
5631 index(0x4); // No Index
5632 scale(0x0); // No Scale
5633 disp($reg); // Stack Offset
5634 %}
5635 %}
5636
5637 operand stackSlotI(sRegI reg)
5638 %{
5639 constraint(ALLOC_IN_RC(stack_slots));
5640 // No match rule because this operand is only generated in matching
5641
5642 format %{ "[$reg]" %}
5643 interface(MEMORY_INTER) %{
5644 base(0x4); // RSP
5645 index(0x4); // No Index
5646 scale(0x0); // No Scale
5647 disp($reg); // Stack Offset
5648 %}
5649 %}
5650
5651 operand stackSlotF(sRegF reg)
5652 %{
5653 constraint(ALLOC_IN_RC(stack_slots));
5654 // No match rule because this operand is only generated in matching
5655
5656 format %{ "[$reg]" %}
5657 interface(MEMORY_INTER) %{
5658 base(0x4); // RSP
5659 index(0x4); // No Index
5660 scale(0x0); // No Scale
5661 disp($reg); // Stack Offset
5662 %}
5663 %}
5664
5665 operand stackSlotD(sRegD reg)
5666 %{
5667 constraint(ALLOC_IN_RC(stack_slots));
5668 // No match rule because this operand is only generated in matching
5669
5670 format %{ "[$reg]" %}
5671 interface(MEMORY_INTER) %{
5672 base(0x4); // RSP
5673 index(0x4); // No Index
5674 scale(0x0); // No Scale
5675 disp($reg); // Stack Offset
5676 %}
5677 %}
5678 operand stackSlotL(sRegL reg)
5679 %{
5680 constraint(ALLOC_IN_RC(stack_slots));
5681 // No match rule because this operand is only generated in matching
5682
5683 format %{ "[$reg]" %}
5684 interface(MEMORY_INTER) %{
5685 base(0x4); // RSP
5686 index(0x4); // No Index
5687 scale(0x0); // No Scale
5688 disp($reg); // Stack Offset
5689 %}
5690 %}
5691
5692 //----------Conditional Branch Operands----------------------------------------
5693 // Comparison Op - This is the operation of the comparison, and is limited to
5694 // the following set of codes:
5695 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
5696 //
5697 // Other attributes of the comparison, such as unsignedness, are specified
5698 // by the comparison instruction that sets a condition code flags register.
5699 // That result is represented by a flags operand whose subtype is appropriate
5700 // to the unsignedness (etc.) of the comparison.
5701 //
5702 // Later, the instruction which matches both the Comparison Op (a Bool) and
5703 // the flags (produced by the Cmp) specifies the coding of the comparison op
5704 // by matching a specific subtype of Bool operand below, such as cmpOpU.
5705
5706 // Comparision Code
5707 operand cmpOp()
5708 %{
5709 match(Bool);
5710
5711 format %{ "" %}
5712 interface(COND_INTER) %{
5713 equal(0x4, "e");
5714 not_equal(0x5, "ne");
5715 less(0xC, "l");
5716 greater_equal(0xD, "ge");
5717 less_equal(0xE, "le");
5718 greater(0xF, "g");
5719 %}
5720 %}
5721
5722 // Comparison Code, unsigned compare. Used by FP also, with
5723 // C2 (unordered) turned into GT or LT already. The other bits
5724 // C0 and C3 are turned into Carry & Zero flags.
5725 operand cmpOpU()
5726 %{
5727 match(Bool);
5728
5729 format %{ "" %}
5730 interface(COND_INTER) %{
5731 equal(0x4, "e");
5732 not_equal(0x5, "ne");
5733 less(0x2, "b");
5734 greater_equal(0x3, "nb");
5735 less_equal(0x6, "be");
5736 greater(0x7, "nbe");
5737 %}
5738 %}
5739
5740
5741 // Floating comparisons that don't require any fixup for the unordered case
5742 operand cmpOpUCF() %{
5743 match(Bool);
5744 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5745 n->as_Bool()->_test._test == BoolTest::ge ||
5746 n->as_Bool()->_test._test == BoolTest::le ||
5747 n->as_Bool()->_test._test == BoolTest::gt);
5748 format %{ "" %}
5749 interface(COND_INTER) %{
5750 equal(0x4, "e");
5751 not_equal(0x5, "ne");
5752 less(0x2, "b");
5753 greater_equal(0x3, "nb");
5754 less_equal(0x6, "be");
5755 greater(0x7, "nbe");
5756 %}
5757 %}
5758
5759
5760 // Floating comparisons that can be fixed up with extra conditional jumps
5761 operand cmpOpUCF2() %{
5762 match(Bool);
5763 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5764 n->as_Bool()->_test._test == BoolTest::eq);
5765 format %{ "" %}
5766 interface(COND_INTER) %{
5767 equal(0x4, "e");
5768 not_equal(0x5, "ne");
5769 less(0x2, "b");
5770 greater_equal(0x3, "nb");
5771 less_equal(0x6, "be");
5772 greater(0x7, "nbe");
5773 %}
5774 %}
5775
5776
5777 //----------OPERAND CLASSES----------------------------------------------------
5778 // Operand Classes are groups of operands that are used as to simplify
5779 // instruction definitions by not requiring the AD writer to specify seperate
5780 // instructions for every form of operand when the instruction accepts
5781 // multiple operand types with the same basic encoding and format. The classic
5782 // case of this is memory operands.
5783
5784 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
5785 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
5786 indNarrowOopOffset);
5787
5788 //----------PIPELINE-----------------------------------------------------------
5789 // Rules which define the behavior of the target architectures pipeline.
5790 pipeline %{
5791
5792 //----------ATTRIBUTES---------------------------------------------------------
5793 attributes %{
5794 variable_size_instructions; // Fixed size instructions
5795 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5796 instruction_unit_size = 1; // An instruction is 1 bytes long
5797 instruction_fetch_unit_size = 16; // The processor fetches one line
5798 instruction_fetch_units = 1; // of 16 bytes
5799
5800 // List of nop instructions
5801 nops( MachNop );
5802 %}
5803
5804 //----------RESOURCES----------------------------------------------------------
5805 // Resources are the functional units available to the machine
5806
5807 // Generic P2/P3 pipeline
5808 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5809 // 3 instructions decoded per cycle.
5810 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5811 // 3 ALU op, only ALU0 handles mul instructions.
5812 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5813 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
5814 BR, FPU,
5815 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
5816
5817 //----------PIPELINE DESCRIPTION-----------------------------------------------
5818 // Pipeline Description specifies the stages in the machine's pipeline
5819
5820 // Generic P2/P3 pipeline
5821 pipe_desc(S0, S1, S2, S3, S4, S5);
5822
5823 //----------PIPELINE CLASSES---------------------------------------------------
5824 // Pipeline Classes describe the stages in which input and output are
5825 // referenced by the hardware pipeline.
5826
5827 // Naming convention: ialu or fpu
5828 // Then: _reg
5829 // Then: _reg if there is a 2nd register
5830 // Then: _long if it's a pair of instructions implementing a long
5831 // Then: _fat if it requires the big decoder
5832 // Or: _mem if it requires the big decoder and a memory unit.
5833
5834 // Integer ALU reg operation
5835 pipe_class ialu_reg(rRegI dst)
5836 %{
5837 single_instruction;
5838 dst : S4(write);
5839 dst : S3(read);
5840 DECODE : S0; // any decoder
5841 ALU : S3; // any alu
5842 %}
5843
5844 // Long ALU reg operation
5845 pipe_class ialu_reg_long(rRegL dst)
5846 %{
5847 instruction_count(2);
5848 dst : S4(write);
5849 dst : S3(read);
5850 DECODE : S0(2); // any 2 decoders
5851 ALU : S3(2); // both alus
5852 %}
5853
5854 // Integer ALU reg operation using big decoder
5855 pipe_class ialu_reg_fat(rRegI dst)
5856 %{
5857 single_instruction;
5858 dst : S4(write);
5859 dst : S3(read);
5860 D0 : S0; // big decoder only
5861 ALU : S3; // any alu
5862 %}
5863
5864 // Long ALU reg operation using big decoder
5865 pipe_class ialu_reg_long_fat(rRegL dst)
5866 %{
5867 instruction_count(2);
5868 dst : S4(write);
5869 dst : S3(read);
5870 D0 : S0(2); // big decoder only; twice
5871 ALU : S3(2); // any 2 alus
5872 %}
5873
5874 // Integer ALU reg-reg operation
5875 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
5876 %{
5877 single_instruction;
5878 dst : S4(write);
5879 src : S3(read);
5880 DECODE : S0; // any decoder
5881 ALU : S3; // any alu
5882 %}
5883
5884 // Long ALU reg-reg operation
5885 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
5886 %{
5887 instruction_count(2);
5888 dst : S4(write);
5889 src : S3(read);
5890 DECODE : S0(2); // any 2 decoders
5891 ALU : S3(2); // both alus
5892 %}
5893
5894 // Integer ALU reg-reg operation
5895 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
5896 %{
5897 single_instruction;
5898 dst : S4(write);
5899 src : S3(read);
5900 D0 : S0; // big decoder only
5901 ALU : S3; // any alu
5902 %}
5903
5904 // Long ALU reg-reg operation
5905 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
5906 %{
5907 instruction_count(2);
5908 dst : S4(write);
5909 src : S3(read);
5910 D0 : S0(2); // big decoder only; twice
5911 ALU : S3(2); // both alus
5912 %}
5913
5914 // Integer ALU reg-mem operation
5915 pipe_class ialu_reg_mem(rRegI dst, memory mem)
5916 %{
5917 single_instruction;
5918 dst : S5(write);
5919 mem : S3(read);
5920 D0 : S0; // big decoder only
5921 ALU : S4; // any alu
5922 MEM : S3; // any mem
5923 %}
5924
5925 // Integer mem operation (prefetch)
5926 pipe_class ialu_mem(memory mem)
5927 %{
5928 single_instruction;
5929 mem : S3(read);
5930 D0 : S0; // big decoder only
5931 MEM : S3; // any mem
5932 %}
5933
5934 // Integer Store to Memory
5935 pipe_class ialu_mem_reg(memory mem, rRegI src)
5936 %{
5937 single_instruction;
5938 mem : S3(read);
5939 src : S5(read);
5940 D0 : S0; // big decoder only
5941 ALU : S4; // any alu
5942 MEM : S3;
5943 %}
5944
5945 // // Long Store to Memory
5946 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
5947 // %{
5948 // instruction_count(2);
5949 // mem : S3(read);
5950 // src : S5(read);
5951 // D0 : S0(2); // big decoder only; twice
5952 // ALU : S4(2); // any 2 alus
5953 // MEM : S3(2); // Both mems
5954 // %}
5955
5956 // Integer Store to Memory
5957 pipe_class ialu_mem_imm(memory mem)
5958 %{
5959 single_instruction;
5960 mem : S3(read);
5961 D0 : S0; // big decoder only
5962 ALU : S4; // any alu
5963 MEM : S3;
5964 %}
5965
5966 // Integer ALU0 reg-reg operation
5967 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
5968 %{
5969 single_instruction;
5970 dst : S4(write);
5971 src : S3(read);
5972 D0 : S0; // Big decoder only
5973 ALU0 : S3; // only alu0
5974 %}
5975
5976 // Integer ALU0 reg-mem operation
5977 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
5978 %{
5979 single_instruction;
5980 dst : S5(write);
5981 mem : S3(read);
5982 D0 : S0; // big decoder only
5983 ALU0 : S4; // ALU0 only
5984 MEM : S3; // any mem
5985 %}
5986
5987 // Integer ALU reg-reg operation
5988 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
5989 %{
5990 single_instruction;
5991 cr : S4(write);
5992 src1 : S3(read);
5993 src2 : S3(read);
5994 DECODE : S0; // any decoder
5995 ALU : S3; // any alu
5996 %}
5997
5998 // Integer ALU reg-imm operation
5999 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
6000 %{
6001 single_instruction;
6002 cr : S4(write);
6003 src1 : S3(read);
6004 DECODE : S0; // any decoder
6005 ALU : S3; // any alu
6006 %}
6007
6008 // Integer ALU reg-mem operation
6009 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
6010 %{
6011 single_instruction;
6012 cr : S4(write);
6013 src1 : S3(read);
6014 src2 : S3(read);
6015 D0 : S0; // big decoder only
6016 ALU : S4; // any alu
6017 MEM : S3;
6018 %}
6019
6020 // Conditional move reg-reg
6021 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
6022 %{
6023 instruction_count(4);
6024 y : S4(read);
6025 q : S3(read);
6026 p : S3(read);
6027 DECODE : S0(4); // any decoder
6028 %}
6029
6030 // Conditional move reg-reg
6031 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
6032 %{
6033 single_instruction;
6034 dst : S4(write);
6035 src : S3(read);
6036 cr : S3(read);
6037 DECODE : S0; // any decoder
6038 %}
6039
6040 // Conditional move reg-mem
6041 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
6042 %{
6043 single_instruction;
6044 dst : S4(write);
6045 src : S3(read);
6046 cr : S3(read);
6047 DECODE : S0; // any decoder
6048 MEM : S3;
6049 %}
6050
6051 // Conditional move reg-reg long
6052 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
6053 %{
6054 single_instruction;
6055 dst : S4(write);
6056 src : S3(read);
6057 cr : S3(read);
6058 DECODE : S0(2); // any 2 decoders
6059 %}
6060
6061 // XXX
6062 // // Conditional move double reg-reg
6063 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
6064 // %{
6065 // single_instruction;
6066 // dst : S4(write);
6067 // src : S3(read);
6068 // cr : S3(read);
6069 // DECODE : S0; // any decoder
6070 // %}
6071
6072 // Float reg-reg operation
6073 pipe_class fpu_reg(regD dst)
6074 %{
6075 instruction_count(2);
6076 dst : S3(read);
6077 DECODE : S0(2); // any 2 decoders
6078 FPU : S3;
6079 %}
6080
6081 // Float reg-reg operation
6082 pipe_class fpu_reg_reg(regD dst, regD src)
6083 %{
6084 instruction_count(2);
6085 dst : S4(write);
6086 src : S3(read);
6087 DECODE : S0(2); // any 2 decoders
6088 FPU : S3;
6089 %}
6090
6091 // Float reg-reg operation
6092 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
6093 %{
6094 instruction_count(3);
6095 dst : S4(write);
6096 src1 : S3(read);
6097 src2 : S3(read);
6098 DECODE : S0(3); // any 3 decoders
6099 FPU : S3(2);
6100 %}
6101
6102 // Float reg-reg operation
6103 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
6104 %{
6105 instruction_count(4);
6106 dst : S4(write);
6107 src1 : S3(read);
6108 src2 : S3(read);
6109 src3 : S3(read);
6110 DECODE : S0(4); // any 3 decoders
6111 FPU : S3(2);
6112 %}
6113
6114 // Float reg-reg operation
6115 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
6116 %{
6117 instruction_count(4);
6118 dst : S4(write);
6119 src1 : S3(read);
6120 src2 : S3(read);
6121 src3 : S3(read);
6122 DECODE : S1(3); // any 3 decoders
6123 D0 : S0; // Big decoder only
6124 FPU : S3(2);
6125 MEM : S3;
6126 %}
6127
6128 // Float reg-mem operation
6129 pipe_class fpu_reg_mem(regD dst, memory mem)
6130 %{
6131 instruction_count(2);
6132 dst : S5(write);
6133 mem : S3(read);
6134 D0 : S0; // big decoder only
6135 DECODE : S1; // any decoder for FPU POP
6136 FPU : S4;
6137 MEM : S3; // any mem
6138 %}
6139
6140 // Float reg-mem operation
6141 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
6142 %{
6143 instruction_count(3);
6144 dst : S5(write);
6145 src1 : S3(read);
6146 mem : S3(read);
6147 D0 : S0; // big decoder only
6148 DECODE : S1(2); // any decoder for FPU POP
6149 FPU : S4;
6150 MEM : S3; // any mem
6151 %}
6152
6153 // Float mem-reg operation
6154 pipe_class fpu_mem_reg(memory mem, regD src)
6155 %{
6156 instruction_count(2);
6157 src : S5(read);
6158 mem : S3(read);
6159 DECODE : S0; // any decoder for FPU PUSH
6160 D0 : S1; // big decoder only
6161 FPU : S4;
6162 MEM : S3; // any mem
6163 %}
6164
6165 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
6166 %{
6167 instruction_count(3);
6168 src1 : S3(read);
6169 src2 : S3(read);
6170 mem : S3(read);
6171 DECODE : S0(2); // any decoder for FPU PUSH
6172 D0 : S1; // big decoder only
6173 FPU : S4;
6174 MEM : S3; // any mem
6175 %}
6176
6177 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
6178 %{
6179 instruction_count(3);
6180 src1 : S3(read);
6181 src2 : S3(read);
6182 mem : S4(read);
6183 DECODE : S0; // any decoder for FPU PUSH
6184 D0 : S0(2); // big decoder only
6185 FPU : S4;
6186 MEM : S3(2); // any mem
6187 %}
6188
6189 pipe_class fpu_mem_mem(memory dst, memory src1)
6190 %{
6191 instruction_count(2);
6192 src1 : S3(read);
6193 dst : S4(read);
6194 D0 : S0(2); // big decoder only
6195 MEM : S3(2); // any mem
6196 %}
6197
6198 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
6199 %{
6200 instruction_count(3);
6201 src1 : S3(read);
6202 src2 : S3(read);
6203 dst : S4(read);
6204 D0 : S0(3); // big decoder only
6205 FPU : S4;
6206 MEM : S3(3); // any mem
6207 %}
6208
6209 pipe_class fpu_mem_reg_con(memory mem, regD src1)
6210 %{
6211 instruction_count(3);
6212 src1 : S4(read);
6213 mem : S4(read);
6214 DECODE : S0; // any decoder for FPU PUSH
6215 D0 : S0(2); // big decoder only
6216 FPU : S4;
6217 MEM : S3(2); // any mem
6218 %}
6219
6220 // Float load constant
6221 pipe_class fpu_reg_con(regD dst)
6222 %{
6223 instruction_count(2);
6224 dst : S5(write);
6225 D0 : S0; // big decoder only for the load
6226 DECODE : S1; // any decoder for FPU POP
6227 FPU : S4;
6228 MEM : S3; // any mem
6229 %}
6230
6231 // Float load constant
6232 pipe_class fpu_reg_reg_con(regD dst, regD src)
6233 %{
6234 instruction_count(3);
6235 dst : S5(write);
6236 src : S3(read);
6237 D0 : S0; // big decoder only for the load
6238 DECODE : S1(2); // any decoder for FPU POP
6239 FPU : S4;
6240 MEM : S3; // any mem
6241 %}
6242
6243 // UnConditional branch
6244 pipe_class pipe_jmp(label labl)
6245 %{
6246 single_instruction;
6247 BR : S3;
6248 %}
6249
6250 // Conditional branch
6251 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
6252 %{
6253 single_instruction;
6254 cr : S1(read);
6255 BR : S3;
6256 %}
6257
6258 // Allocation idiom
6259 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
6260 %{
6261 instruction_count(1); force_serialization;
6262 fixed_latency(6);
6263 heap_ptr : S3(read);
6264 DECODE : S0(3);
6265 D0 : S2;
6266 MEM : S3;
6267 ALU : S3(2);
6268 dst : S5(write);
6269 BR : S5;
6270 %}
6271
6272 // Generic big/slow expanded idiom
6273 pipe_class pipe_slow()
6274 %{
6275 instruction_count(10); multiple_bundles; force_serialization;
6276 fixed_latency(100);
6277 D0 : S0(2);
6278 MEM : S3(2);
6279 %}
6280
6281 // The real do-nothing guy
6282 pipe_class empty()
6283 %{
6284 instruction_count(0);
6285 %}
6286
6287 // Define the class for the Nop node
6288 define
6289 %{
6290 MachNop = empty;
6291 %}
6292
6293 %}
6294
6295 //----------INSTRUCTIONS-------------------------------------------------------
6296 //
6297 // match -- States which machine-independent subtree may be replaced
6298 // by this instruction.
6299 // ins_cost -- The estimated cost of this instruction is used by instruction
6300 // selection to identify a minimum cost tree of machine
6301 // instructions that matches a tree of machine-independent
6302 // instructions.
6303 // format -- A string providing the disassembly for this instruction.
6304 // The value of an instruction's operand may be inserted
6305 // by referring to it with a '$' prefix.
6306 // opcode -- Three instruction opcodes may be provided. These are referred
6307 // to within an encode class as $primary, $secondary, and $tertiary
6308 // rrspectively. The primary opcode is commonly used to
6309 // indicate the type of machine instruction, while secondary
6310 // and tertiary are often used for prefix options or addressing
6311 // modes.
6312 // ins_encode -- A list of encode classes with parameters. The encode class
6313 // name must have been defined in an 'enc_class' specification
6314 // in the encode section of the architecture description.
6315
6316
6317 //----------Load/Store/Move Instructions---------------------------------------
6318 //----------Load Instructions--------------------------------------------------
6319
6320 // Load Byte (8 bit signed)
6321 instruct loadB(rRegI dst, memory mem)
6322 %{
6323 match(Set dst (LoadB mem));
6324
6325 ins_cost(125);
6326 format %{ "movsbl $dst, $mem\t# byte" %}
6327 opcode(0x0F, 0xBE);
6328 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6329 ins_pipe(ialu_reg_mem);
6330 %}
6331
6332 // Load Byte (8 bit signed) into long
6333 // instruct loadB2L(rRegL dst, memory mem)
6334 // %{
6335 // match(Set dst (ConvI2L (LoadB mem)));
6336
6337 // ins_cost(125);
6338 // format %{ "movsbq $dst, $mem\t# byte -> long" %}
6339 // opcode(0x0F, 0xBE);
6340 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6341 // ins_pipe(ialu_reg_mem);
6342 // %}
6343
6344 // Load Byte (8 bit UNsigned)
6345 instruct loadUB(rRegI dst, memory mem, immI_255 bytemask)
6346 %{
6347 match(Set dst (AndI (LoadB mem) bytemask));
6348
6349 ins_cost(125);
6350 format %{ "movzbl $dst, $mem\t# ubyte" %}
6351 opcode(0x0F, 0xB6);
6352 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6353 ins_pipe(ialu_reg_mem);
6354 %}
6355
6356 // Load Byte (8 bit UNsigned) into long
6357 // instruct loadUB2L(rRegL dst, memory mem, immI_255 bytemask)
6358 // %{
6359 // match(Set dst (ConvI2L (AndI (LoadB mem) bytemask)));
6360
6361 // ins_cost(125);
6362 // format %{ "movzbl $dst, $mem\t# ubyte -> long" %}
6363 // opcode(0x0F, 0xB6);
6364 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6365 // ins_pipe(ialu_reg_mem);
6366 // %}
6367
6368 // Load Short (16 bit signed)
6369 instruct loadS(rRegI dst, memory mem)
6370 %{
6371 match(Set dst (LoadS mem));
6372
6373 ins_cost(125); // XXX
6374 format %{ "movswl $dst, $mem\t# short" %}
6375 opcode(0x0F, 0xBF);
6376 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6377 ins_pipe(ialu_reg_mem);
6378 %}
6379
6380 // Load Short (16 bit signed) into long
6381 // instruct loadS2L(rRegL dst, memory mem)
6382 // %{
6383 // match(Set dst (ConvI2L (LoadS mem)));
6384
6385 // ins_cost(125); // XXX
6386 // format %{ "movswq $dst, $mem\t# short -> long" %}
6387 // opcode(0x0F, 0xBF);
6388 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6389 // ins_pipe(ialu_reg_mem);
6390 // %}
6391
6392 // Load Unsigned Short/Char (16 bit UNsigned)
6393 instruct loadUS(rRegI dst, memory mem)
6394 %{
6395 match(Set dst (LoadUS mem));
6396
6397 ins_cost(125);
6398 format %{ "movzwl $dst, $mem\t# ushort/char" %}
6399 opcode(0x0F, 0xB7);
6400 ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6401 ins_pipe(ialu_reg_mem);
6402 %}
6403
6404 // Load Unsigned Short/Char (16 bit UNsigned) into long
6405 // instruct loadUS2L(rRegL dst, memory mem)
6406 // %{
6407 // match(Set dst (ConvI2L (LoadUS mem)));
6408
6409 // ins_cost(125);
6410 // format %{ "movzwl $dst, $mem\t# ushort/char -> long" %}
6411 // opcode(0x0F, 0xB7);
6412 // ins_encode(REX_reg_mem(dst, mem), OpcP, OpcS, reg_mem(dst, mem));
6413 // ins_pipe(ialu_reg_mem);
6414 // %}
6415
6416 // Load Integer
6417 instruct loadI(rRegI dst, memory mem)
6418 %{
6419 match(Set dst (LoadI mem));
6420
6421 ins_cost(125); // XXX
6422 format %{ "movl $dst, $mem\t# int" %}
6423 opcode(0x8B);
6424 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6425 ins_pipe(ialu_reg_mem);
6426 %}
6427
6428 // Load Long
6429 instruct loadL(rRegL dst, memory mem)
6430 %{
6431 match(Set dst (LoadL mem));
6432
6433 ins_cost(125); // XXX
6434 format %{ "movq $dst, $mem\t# long" %}
6435 opcode(0x8B);
6436 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6437 ins_pipe(ialu_reg_mem); // XXX
6438 %}
6439
6440 // Load Range
6441 instruct loadRange(rRegI dst, memory mem)
6442 %{
6443 match(Set dst (LoadRange mem));
6444
6445 ins_cost(125); // XXX
6446 format %{ "movl $dst, $mem\t# range" %}
6447 opcode(0x8B);
6448 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
6449 ins_pipe(ialu_reg_mem);
6450 %}
6451
6452 // Load Pointer
6453 instruct loadP(rRegP dst, memory mem)
6454 %{
6455 match(Set dst (LoadP mem));
6456
6457 ins_cost(125); // XXX
6458 format %{ "movq $dst, $mem\t# ptr" %}
6459 opcode(0x8B);
6460 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6461 ins_pipe(ialu_reg_mem); // XXX
6462 %}
6463
6464 // Load Compressed Pointer
6465 instruct loadN(rRegN dst, memory mem)
6466 %{
6467 match(Set dst (LoadN mem));
6468
6469 ins_cost(125); // XXX
6470 format %{ "movl $dst, $mem\t# compressed ptr" %}
6471 ins_encode %{
6472 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6473 Register dst = as_Register($dst$$reg);
6474 __ movl(dst, addr);
6475 %}
6476 ins_pipe(ialu_reg_mem); // XXX
6477 %}
6478
6479
6480 // Load Klass Pointer
6481 instruct loadKlass(rRegP dst, memory mem)
6482 %{
6483 match(Set dst (LoadKlass mem));
6484
6485 ins_cost(125); // XXX
6486 format %{ "movq $dst, $mem\t# class" %}
6487 opcode(0x8B);
6488 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6489 ins_pipe(ialu_reg_mem); // XXX
6490 %}
6491
6492 // Load narrow Klass Pointer
6493 instruct loadNKlass(rRegN dst, memory mem)
6494 %{
6495 match(Set dst (LoadNKlass mem));
6496
6497 ins_cost(125); // XXX
6498 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
6499 ins_encode %{
6500 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6501 Register dst = as_Register($dst$$reg);
6502 __ movl(dst, addr);
6503 %}
6504 ins_pipe(ialu_reg_mem); // XXX
6505 %}
6506
6507 // Load Float
6508 instruct loadF(regF dst, memory mem)
6509 %{
6510 match(Set dst (LoadF mem));
6511
6512 ins_cost(145); // XXX
6513 format %{ "movss $dst, $mem\t# float" %}
6514 opcode(0xF3, 0x0F, 0x10);
6515 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6516 ins_pipe(pipe_slow); // XXX
6517 %}
6518
6519 // Load Double
6520 instruct loadD_partial(regD dst, memory mem)
6521 %{
6522 predicate(!UseXmmLoadAndClearUpper);
6523 match(Set dst (LoadD mem));
6524
6525 ins_cost(145); // XXX
6526 format %{ "movlpd $dst, $mem\t# double" %}
6527 opcode(0x66, 0x0F, 0x12);
6528 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6529 ins_pipe(pipe_slow); // XXX
6530 %}
6531
6532 instruct loadD(regD dst, memory mem)
6533 %{
6534 predicate(UseXmmLoadAndClearUpper);
6535 match(Set dst (LoadD mem));
6536
6537 ins_cost(145); // XXX
6538 format %{ "movsd $dst, $mem\t# double" %}
6539 opcode(0xF2, 0x0F, 0x10);
6540 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem));
6541 ins_pipe(pipe_slow); // XXX
6542 %}
6543
6544 // Load Aligned Packed Byte to XMM register
6545 instruct loadA8B(regD dst, memory mem) %{
6546 match(Set dst (Load8B mem));
6547 ins_cost(125);
6548 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6549 ins_encode( movq_ld(dst, mem));
6550 ins_pipe( pipe_slow );
6551 %}
6552
6553 // Load Aligned Packed Short to XMM register
6554 instruct loadA4S(regD dst, memory mem) %{
6555 match(Set dst (Load4S mem));
6556 ins_cost(125);
6557 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6558 ins_encode( movq_ld(dst, mem));
6559 ins_pipe( pipe_slow );
6560 %}
6561
6562 // Load Aligned Packed Char to XMM register
6563 instruct loadA4C(regD dst, memory mem) %{
6564 match(Set dst (Load4C mem));
6565 ins_cost(125);
6566 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6567 ins_encode( movq_ld(dst, mem));
6568 ins_pipe( pipe_slow );
6569 %}
6570
6571 // Load Aligned Packed Integer to XMM register
6572 instruct load2IU(regD dst, memory mem) %{
6573 match(Set dst (Load2I mem));
6574 ins_cost(125);
6575 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6576 ins_encode( movq_ld(dst, mem));
6577 ins_pipe( pipe_slow );
6578 %}
6579
6580 // Load Aligned Packed Single to XMM
6581 instruct loadA2F(regD dst, memory mem) %{
6582 match(Set dst (Load2F mem));
6583 ins_cost(145);
6584 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6585 ins_encode( movq_ld(dst, mem));
6586 ins_pipe( pipe_slow );
6587 %}
6588
6589 // Load Effective Address
6590 instruct leaP8(rRegP dst, indOffset8 mem)
6591 %{
6592 match(Set dst mem);
6593
6594 ins_cost(110); // XXX
6595 format %{ "leaq $dst, $mem\t# ptr 8" %}
6596 opcode(0x8D);
6597 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6598 ins_pipe(ialu_reg_reg_fat);
6599 %}
6600
6601 instruct leaP32(rRegP dst, indOffset32 mem)
6602 %{
6603 match(Set dst mem);
6604
6605 ins_cost(110);
6606 format %{ "leaq $dst, $mem\t# ptr 32" %}
6607 opcode(0x8D);
6608 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6609 ins_pipe(ialu_reg_reg_fat);
6610 %}
6611
6612 // instruct leaPIdx(rRegP dst, indIndex mem)
6613 // %{
6614 // match(Set dst mem);
6615
6616 // ins_cost(110);
6617 // format %{ "leaq $dst, $mem\t# ptr idx" %}
6618 // opcode(0x8D);
6619 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6620 // ins_pipe(ialu_reg_reg_fat);
6621 // %}
6622
6623 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
6624 %{
6625 match(Set dst mem);
6626
6627 ins_cost(110);
6628 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
6629 opcode(0x8D);
6630 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6631 ins_pipe(ialu_reg_reg_fat);
6632 %}
6633
6634 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
6635 %{
6636 match(Set dst mem);
6637
6638 ins_cost(110);
6639 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
6640 opcode(0x8D);
6641 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6642 ins_pipe(ialu_reg_reg_fat);
6643 %}
6644
6645 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
6646 %{
6647 match(Set dst mem);
6648
6649 ins_cost(110);
6650 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
6651 opcode(0x8D);
6652 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6653 ins_pipe(ialu_reg_reg_fat);
6654 %}
6655
6656 instruct loadConI(rRegI dst, immI src)
6657 %{
6658 match(Set dst src);
6659
6660 format %{ "movl $dst, $src\t# int" %}
6661 ins_encode(load_immI(dst, src));
6662 ins_pipe(ialu_reg_fat); // XXX
6663 %}
6664
6665 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
6666 %{
6667 match(Set dst src);
6668 effect(KILL cr);
6669
6670 ins_cost(50);
6671 format %{ "xorl $dst, $dst\t# int" %}
6672 opcode(0x33); /* + rd */
6673 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6674 ins_pipe(ialu_reg);
6675 %}
6676
6677 instruct loadConL(rRegL dst, immL src)
6678 %{
6679 match(Set dst src);
6680
6681 ins_cost(150);
6682 format %{ "movq $dst, $src\t# long" %}
6683 ins_encode(load_immL(dst, src));
6684 ins_pipe(ialu_reg);
6685 %}
6686
6687 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
6688 %{
6689 match(Set dst src);
6690 effect(KILL cr);
6691
6692 ins_cost(50);
6693 format %{ "xorl $dst, $dst\t# long" %}
6694 opcode(0x33); /* + rd */
6695 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6696 ins_pipe(ialu_reg); // XXX
6697 %}
6698
6699 instruct loadConUL32(rRegL dst, immUL32 src)
6700 %{
6701 match(Set dst src);
6702
6703 ins_cost(60);
6704 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
6705 ins_encode(load_immUL32(dst, src));
6706 ins_pipe(ialu_reg);
6707 %}
6708
6709 instruct loadConL32(rRegL dst, immL32 src)
6710 %{
6711 match(Set dst src);
6712
6713 ins_cost(70);
6714 format %{ "movq $dst, $src\t# long (32-bit)" %}
6715 ins_encode(load_immL32(dst, src));
6716 ins_pipe(ialu_reg);
6717 %}
6718
6719 instruct loadConP(rRegP dst, immP src)
6720 %{
6721 match(Set dst src);
6722
6723 format %{ "movq $dst, $src\t# ptr" %}
6724 ins_encode(load_immP(dst, src));
6725 ins_pipe(ialu_reg_fat); // XXX
6726 %}
6727
6728 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
6729 %{
6730 match(Set dst src);
6731 effect(KILL cr);
6732
6733 ins_cost(50);
6734 format %{ "xorl $dst, $dst\t# ptr" %}
6735 opcode(0x33); /* + rd */
6736 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
6737 ins_pipe(ialu_reg);
6738 %}
6739
6740 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
6741 %{
6742 match(Set dst src);
6743 effect(KILL cr);
6744
6745 ins_cost(60);
6746 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
6747 ins_encode(load_immP31(dst, src));
6748 ins_pipe(ialu_reg);
6749 %}
6750
6751 instruct loadConF(regF dst, immF src)
6752 %{
6753 match(Set dst src);
6754 ins_cost(125);
6755
6756 format %{ "movss $dst, [$src]" %}
6757 ins_encode(load_conF(dst, src));
6758 ins_pipe(pipe_slow);
6759 %}
6760
6761 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
6762 match(Set dst src);
6763 effect(KILL cr);
6764 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
6765 ins_encode %{
6766 Register dst = $dst$$Register;
6767 __ xorq(dst, dst);
6768 %}
6769 ins_pipe(ialu_reg);
6770 %}
6771
6772 instruct loadConN(rRegN dst, immN src) %{
6773 match(Set dst src);
6774
6775 ins_cost(125);
6776 format %{ "movl $dst, $src\t# compressed ptr" %}
6777 ins_encode %{
6778 address con = (address)$src$$constant;
6779 Register dst = $dst$$Register;
6780 if (con == NULL) {
6781 ShouldNotReachHere();
6782 } else {
6783 __ set_narrow_oop(dst, (jobject)$src$$constant);
6784 }
6785 %}
6786 ins_pipe(ialu_reg_fat); // XXX
6787 %}
6788
6789 instruct loadConF0(regF dst, immF0 src)
6790 %{
6791 match(Set dst src);
6792 ins_cost(100);
6793
6794 format %{ "xorps $dst, $dst\t# float 0.0" %}
6795 opcode(0x0F, 0x57);
6796 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
6797 ins_pipe(pipe_slow);
6798 %}
6799
6800 // Use the same format since predicate() can not be used here.
6801 instruct loadConD(regD dst, immD src)
6802 %{
6803 match(Set dst src);
6804 ins_cost(125);
6805
6806 format %{ "movsd $dst, [$src]" %}
6807 ins_encode(load_conD(dst, src));
6808 ins_pipe(pipe_slow);
6809 %}
6810
6811 instruct loadConD0(regD dst, immD0 src)
6812 %{
6813 match(Set dst src);
6814 ins_cost(100);
6815
6816 format %{ "xorpd $dst, $dst\t# double 0.0" %}
6817 opcode(0x66, 0x0F, 0x57);
6818 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst));
6819 ins_pipe(pipe_slow);
6820 %}
6821
6822 instruct loadSSI(rRegI dst, stackSlotI src)
6823 %{
6824 match(Set dst src);
6825
6826 ins_cost(125);
6827 format %{ "movl $dst, $src\t# int stk" %}
6828 opcode(0x8B);
6829 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6830 ins_pipe(ialu_reg_mem);
6831 %}
6832
6833 instruct loadSSL(rRegL dst, stackSlotL src)
6834 %{
6835 match(Set dst src);
6836
6837 ins_cost(125);
6838 format %{ "movq $dst, $src\t# long stk" %}
6839 opcode(0x8B);
6840 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6841 ins_pipe(ialu_reg_mem);
6842 %}
6843
6844 instruct loadSSP(rRegP dst, stackSlotP src)
6845 %{
6846 match(Set dst src);
6847
6848 ins_cost(125);
6849 format %{ "movq $dst, $src\t# ptr stk" %}
6850 opcode(0x8B);
6851 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6852 ins_pipe(ialu_reg_mem);
6853 %}
6854
6855 instruct loadSSF(regF dst, stackSlotF src)
6856 %{
6857 match(Set dst src);
6858
6859 ins_cost(125);
6860 format %{ "movss $dst, $src\t# float stk" %}
6861 opcode(0xF3, 0x0F, 0x10);
6862 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
6863 ins_pipe(pipe_slow); // XXX
6864 %}
6865
6866 // Use the same format since predicate() can not be used here.
6867 instruct loadSSD(regD dst, stackSlotD src)
6868 %{
6869 match(Set dst src);
6870
6871 ins_cost(125);
6872 format %{ "movsd $dst, $src\t# double stk" %}
6873 ins_encode %{
6874 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
6875 %}
6876 ins_pipe(pipe_slow); // XXX
6877 %}
6878
6879 // Prefetch instructions.
6880 // Must be safe to execute with invalid address (cannot fault).
6881
6882 instruct prefetchr( memory mem ) %{
6883 predicate(ReadPrefetchInstr==3);
6884 match(PrefetchRead mem);
6885 ins_cost(125);
6886
6887 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6888 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */
6889 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6890 ins_pipe(ialu_mem);
6891 %}
6892
6893 instruct prefetchrNTA( memory mem ) %{
6894 predicate(ReadPrefetchInstr==0);
6895 match(PrefetchRead mem);
6896 ins_cost(125);
6897
6898 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6899 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6900 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6901 ins_pipe(ialu_mem);
6902 %}
6903
6904 instruct prefetchrT0( memory mem ) %{
6905 predicate(ReadPrefetchInstr==1);
6906 match(PrefetchRead mem);
6907 ins_cost(125);
6908
6909 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6910 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6911 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6912 ins_pipe(ialu_mem);
6913 %}
6914
6915 instruct prefetchrT2( memory mem ) %{
6916 predicate(ReadPrefetchInstr==2);
6917 match(PrefetchRead mem);
6918 ins_cost(125);
6919
6920 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6921 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6922 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6923 ins_pipe(ialu_mem);
6924 %}
6925
6926 instruct prefetchw( memory mem ) %{
6927 predicate(AllocatePrefetchInstr==3);
6928 match(PrefetchWrite mem);
6929 ins_cost(125);
6930
6931 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %}
6932 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
6933 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6934 ins_pipe(ialu_mem);
6935 %}
6936
6937 instruct prefetchwNTA( memory mem ) %{
6938 predicate(AllocatePrefetchInstr==0);
6939 match(PrefetchWrite mem);
6940 ins_cost(125);
6941
6942 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6943 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
6944 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem));
6945 ins_pipe(ialu_mem);
6946 %}
6947
6948 instruct prefetchwT0( memory mem ) %{
6949 predicate(AllocatePrefetchInstr==1);
6950 match(PrefetchWrite mem);
6951 ins_cost(125);
6952
6953 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %}
6954 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
6955 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem));
6956 ins_pipe(ialu_mem);
6957 %}
6958
6959 instruct prefetchwT2( memory mem ) %{
6960 predicate(AllocatePrefetchInstr==2);
6961 match(PrefetchWrite mem);
6962 ins_cost(125);
6963
6964 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %}
6965 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
6966 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem));
6967 ins_pipe(ialu_mem);
6968 %}
6969
6970 //----------Store Instructions-------------------------------------------------
6971
6972 // Store Byte
6973 instruct storeB(memory mem, rRegI src)
6974 %{
6975 match(Set mem (StoreB mem src));
6976
6977 ins_cost(125); // XXX
6978 format %{ "movb $mem, $src\t# byte" %}
6979 opcode(0x88);
6980 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
6981 ins_pipe(ialu_mem_reg);
6982 %}
6983
6984 // Store Char/Short
6985 instruct storeC(memory mem, rRegI src)
6986 %{
6987 match(Set mem (StoreC mem src));
6988
6989 ins_cost(125); // XXX
6990 format %{ "movw $mem, $src\t# char/short" %}
6991 opcode(0x89);
6992 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
6993 ins_pipe(ialu_mem_reg);
6994 %}
6995
6996 // Store Integer
6997 instruct storeI(memory mem, rRegI src)
6998 %{
6999 match(Set mem (StoreI mem src));
7000
7001 ins_cost(125); // XXX
7002 format %{ "movl $mem, $src\t# int" %}
7003 opcode(0x89);
7004 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
7005 ins_pipe(ialu_mem_reg);
7006 %}
7007
7008 // Store Long
7009 instruct storeL(memory mem, rRegL src)
7010 %{
7011 match(Set mem (StoreL mem src));
7012
7013 ins_cost(125); // XXX
7014 format %{ "movq $mem, $src\t# long" %}
7015 opcode(0x89);
7016 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
7017 ins_pipe(ialu_mem_reg); // XXX
7018 %}
7019
7020 // Store Pointer
7021 instruct storeP(memory mem, any_RegP src)
7022 %{
7023 match(Set mem (StoreP mem src));
7024
7025 ins_cost(125); // XXX
7026 format %{ "movq $mem, $src\t# ptr" %}
7027 opcode(0x89);
7028 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
7029 ins_pipe(ialu_mem_reg);
7030 %}
7031
7032 // Store NULL Pointer, mark word, or other simple pointer constant.
7033 instruct storeImmP(memory mem, immP31 src)
7034 %{
7035 match(Set mem (StoreP mem src));
7036
7037 ins_cost(125); // XXX
7038 format %{ "movq $mem, $src\t# ptr" %}
7039 opcode(0xC7); /* C7 /0 */
7040 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
7041 ins_pipe(ialu_mem_imm);
7042 %}
7043
7044 // Store Compressed Pointer
7045 instruct storeN(memory mem, rRegN src)
7046 %{
7047 match(Set mem (StoreN mem src));
7048
7049 ins_cost(125); // XXX
7050 format %{ "movl $mem, $src\t# compressed ptr" %}
7051 ins_encode %{
7052 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
7053 Register src = as_Register($src$$reg);
7054 __ movl(addr, src);
7055 %}
7056 ins_pipe(ialu_mem_reg);
7057 %}
7058
7059 // Store Integer Immediate
7060 instruct storeImmI(memory mem, immI src)
7061 %{
7062 match(Set mem (StoreI mem src));
7063
7064 ins_cost(150);
7065 format %{ "movl $mem, $src\t# int" %}
7066 opcode(0xC7); /* C7 /0 */
7067 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
7068 ins_pipe(ialu_mem_imm);
7069 %}
7070
7071 // Store Long Immediate
7072 instruct storeImmL(memory mem, immL32 src)
7073 %{
7074 match(Set mem (StoreL mem src));
7075
7076 ins_cost(150);
7077 format %{ "movq $mem, $src\t# long" %}
7078 opcode(0xC7); /* C7 /0 */
7079 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
7080 ins_pipe(ialu_mem_imm);
7081 %}
7082
7083 // Store Short/Char Immediate
7084 instruct storeImmI16(memory mem, immI16 src)
7085 %{
7086 predicate(UseStoreImmI16);
7087 match(Set mem (StoreC mem src));
7088
7089 ins_cost(150);
7090 format %{ "movw $mem, $src\t# short/char" %}
7091 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7092 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
7093 ins_pipe(ialu_mem_imm);
7094 %}
7095
7096 // Store Byte Immediate
7097 instruct storeImmB(memory mem, immI8 src)
7098 %{
7099 match(Set mem (StoreB mem src));
7100
7101 ins_cost(150); // XXX
7102 format %{ "movb $mem, $src\t# byte" %}
7103 opcode(0xC6); /* C6 /0 */
7104 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
7105 ins_pipe(ialu_mem_imm);
7106 %}
7107
7108 // Store Aligned Packed Byte XMM register to memory
7109 instruct storeA8B(memory mem, regD src) %{
7110 match(Set mem (Store8B mem src));
7111 ins_cost(145);
7112 format %{ "MOVQ $mem,$src\t! packed8B" %}
7113 ins_encode( movq_st(mem, src));
7114 ins_pipe( pipe_slow );
7115 %}
7116
7117 // Store Aligned Packed Char/Short XMM register to memory
7118 instruct storeA4C(memory mem, regD src) %{
7119 match(Set mem (Store4C mem src));
7120 ins_cost(145);
7121 format %{ "MOVQ $mem,$src\t! packed4C" %}
7122 ins_encode( movq_st(mem, src));
7123 ins_pipe( pipe_slow );
7124 %}
7125
7126 // Store Aligned Packed Integer XMM register to memory
7127 instruct storeA2I(memory mem, regD src) %{
7128 match(Set mem (Store2I mem src));
7129 ins_cost(145);
7130 format %{ "MOVQ $mem,$src\t! packed2I" %}
7131 ins_encode( movq_st(mem, src));
7132 ins_pipe( pipe_slow );
7133 %}
7134
7135 // Store CMS card-mark Immediate
7136 instruct storeImmCM0(memory mem, immI0 src)
7137 %{
7138 match(Set mem (StoreCM mem src));
7139
7140 ins_cost(150); // XXX
7141 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
7142 opcode(0xC6); /* C6 /0 */
7143 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
7144 ins_pipe(ialu_mem_imm);
7145 %}
7146
7147 // Store Aligned Packed Single Float XMM register to memory
7148 instruct storeA2F(memory mem, regD src) %{
7149 match(Set mem (Store2F mem src));
7150 ins_cost(145);
7151 format %{ "MOVQ $mem,$src\t! packed2F" %}
7152 ins_encode( movq_st(mem, src));
7153 ins_pipe( pipe_slow );
7154 %}
7155
7156 // Store Float
7157 instruct storeF(memory mem, regF src)
7158 %{
7159 match(Set mem (StoreF mem src));
7160
7161 ins_cost(95); // XXX
7162 format %{ "movss $mem, $src\t# float" %}
7163 opcode(0xF3, 0x0F, 0x11);
7164 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
7165 ins_pipe(pipe_slow); // XXX
7166 %}
7167
7168 // Store immediate Float value (it is faster than store from XMM register)
7169 instruct storeF_imm(memory mem, immF src)
7170 %{
7171 match(Set mem (StoreF mem src));
7172
7173 ins_cost(50);
7174 format %{ "movl $mem, $src\t# float" %}
7175 opcode(0xC7); /* C7 /0 */
7176 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
7177 ins_pipe(ialu_mem_imm);
7178 %}
7179
7180 // Store Double
7181 instruct storeD(memory mem, regD src)
7182 %{
7183 match(Set mem (StoreD mem src));
7184
7185 ins_cost(95); // XXX
7186 format %{ "movsd $mem, $src\t# double" %}
7187 opcode(0xF2, 0x0F, 0x11);
7188 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem));
7189 ins_pipe(pipe_slow); // XXX
7190 %}
7191
7192 // Store immediate double 0.0 (it is faster than store from XMM register)
7193 instruct storeD0_imm(memory mem, immD0 src)
7194 %{
7195 match(Set mem (StoreD mem src));
7196
7197 ins_cost(50);
7198 format %{ "movq $mem, $src\t# double 0." %}
7199 opcode(0xC7); /* C7 /0 */
7200 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
7201 ins_pipe(ialu_mem_imm);
7202 %}
7203
7204 instruct storeSSI(stackSlotI dst, rRegI src)
7205 %{
7206 match(Set dst src);
7207
7208 ins_cost(100);
7209 format %{ "movl $dst, $src\t# int stk" %}
7210 opcode(0x89);
7211 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7212 ins_pipe( ialu_mem_reg );
7213 %}
7214
7215 instruct storeSSL(stackSlotL dst, rRegL src)
7216 %{
7217 match(Set dst src);
7218
7219 ins_cost(100);
7220 format %{ "movq $dst, $src\t# long stk" %}
7221 opcode(0x89);
7222 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7223 ins_pipe(ialu_mem_reg);
7224 %}
7225
7226 instruct storeSSP(stackSlotP dst, rRegP src)
7227 %{
7228 match(Set dst src);
7229
7230 ins_cost(100);
7231 format %{ "movq $dst, $src\t# ptr stk" %}
7232 opcode(0x89);
7233 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7234 ins_pipe(ialu_mem_reg);
7235 %}
7236
7237 instruct storeSSF(stackSlotF dst, regF src)
7238 %{
7239 match(Set dst src);
7240
7241 ins_cost(95); // XXX
7242 format %{ "movss $dst, $src\t# float stk" %}
7243 opcode(0xF3, 0x0F, 0x11);
7244 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
7245 ins_pipe(pipe_slow); // XXX
7246 %}
7247
7248 instruct storeSSD(stackSlotD dst, regD src)
7249 %{
7250 match(Set dst src);
7251
7252 ins_cost(95); // XXX
7253 format %{ "movsd $dst, $src\t# double stk" %}
7254 opcode(0xF2, 0x0F, 0x11);
7255 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
7256 ins_pipe(pipe_slow); // XXX
7257 %}
7258
7259 //----------BSWAP Instructions-------------------------------------------------
7260 instruct bytes_reverse_int(rRegI dst) %{
7261 match(Set dst (ReverseBytesI dst));
7262
7263 format %{ "bswapl $dst" %}
7264 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
7265 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
7266 ins_pipe( ialu_reg );
7267 %}
7268
7269 instruct bytes_reverse_long(rRegL dst) %{
7270 match(Set dst (ReverseBytesL dst));
7271
7272 format %{ "bswapq $dst" %}
7273
7274 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
7275 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
7276 ins_pipe( ialu_reg);
7277 %}
7278
7279 instruct loadI_reversed(rRegI dst, memory src) %{
7280 match(Set dst (ReverseBytesI (LoadI src)));
7281
7282 format %{ "bswap_movl $dst, $src" %}
7283 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
7284 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst));
7285 ins_pipe( ialu_reg_mem );
7286 %}
7287
7288 instruct loadL_reversed(rRegL dst, memory src) %{
7289 match(Set dst (ReverseBytesL (LoadL src)));
7290
7291 format %{ "bswap_movq $dst, $src" %}
7292 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */
7293 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst));
7294 ins_pipe( ialu_reg_mem );
7295 %}
7296
7297 instruct storeI_reversed(memory dst, rRegI src) %{
7298 match(Set dst (StoreI dst (ReverseBytesI src)));
7299
7300 format %{ "movl_bswap $dst, $src" %}
7301 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7302 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) );
7303 ins_pipe( ialu_mem_reg );
7304 %}
7305
7306 instruct storeL_reversed(memory dst, rRegL src) %{
7307 match(Set dst (StoreL dst (ReverseBytesL src)));
7308
7309 format %{ "movq_bswap $dst, $src" %}
7310 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */
7311 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) );
7312 ins_pipe( ialu_mem_reg );
7313 %}
7314
7315 //----------MemBar Instructions-----------------------------------------------
7316 // Memory barrier flavors
7317
7318 instruct membar_acquire()
7319 %{
7320 match(MemBarAcquire);
7321 ins_cost(0);
7322
7323 size(0);
7324 format %{ "MEMBAR-acquire" %}
7325 ins_encode();
7326 ins_pipe(empty);
7327 %}
7328
7329 instruct membar_acquire_lock()
7330 %{
7331 match(MemBarAcquire);
7332 predicate(Matcher::prior_fast_lock(n));
7333 ins_cost(0);
7334
7335 size(0);
7336 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7337 ins_encode();
7338 ins_pipe(empty);
7339 %}
7340
7341 instruct membar_release()
7342 %{
7343 match(MemBarRelease);
7344 ins_cost(0);
7345
7346 size(0);
7347 format %{ "MEMBAR-release" %}
7348 ins_encode();
7349 ins_pipe(empty);
7350 %}
7351
7352 instruct membar_release_lock()
7353 %{
7354 match(MemBarRelease);
7355 predicate(Matcher::post_fast_unlock(n));
7356 ins_cost(0);
7357
7358 size(0);
7359 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7360 ins_encode();
7361 ins_pipe(empty);
7362 %}
7363
7364 instruct membar_volatile()
7365 %{
7366 match(MemBarVolatile);
7367 ins_cost(400);
7368
7369 format %{ "MEMBAR-volatile" %}
7370 ins_encode(enc_membar_volatile);
7371 ins_pipe(pipe_slow);
7372 %}
7373
7374 instruct unnecessary_membar_volatile()
7375 %{
7376 match(MemBarVolatile);
7377 predicate(Matcher::post_store_load_barrier(n));
7378 ins_cost(0);
7379
7380 size(0);
7381 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7382 ins_encode();
7383 ins_pipe(empty);
7384 %}
7385
7386 //----------Move Instructions--------------------------------------------------
7387
7388 instruct castX2P(rRegP dst, rRegL src)
7389 %{
7390 match(Set dst (CastX2P src));
7391
7392 format %{ "movq $dst, $src\t# long->ptr" %}
7393 ins_encode(enc_copy_wide(dst, src));
7394 ins_pipe(ialu_reg_reg); // XXX
7395 %}
7396
7397 instruct castP2X(rRegL dst, rRegP src)
7398 %{
7399 match(Set dst (CastP2X src));
7400
7401 format %{ "movq $dst, $src\t# ptr -> long" %}
7402 ins_encode(enc_copy_wide(dst, src));
7403 ins_pipe(ialu_reg_reg); // XXX
7404 %}
7405
7406
7407 // Convert oop pointer into compressed form
7408 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
7409 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
7410 match(Set dst (EncodeP src));
7411 effect(KILL cr);
7412 format %{ "encode_heap_oop $dst,$src" %}
7413 ins_encode %{
7414 Register s = $src$$Register;
7415 Register d = $dst$$Register;
7416 if (s != d) {
7417 __ movq(d, s);
7418 }
7419 __ encode_heap_oop(d);
7420 %}
7421 ins_pipe(ialu_reg_long);
7422 %}
7423
7424 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
7425 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7426 match(Set dst (EncodeP src));
7427 effect(KILL cr);
7428 format %{ "encode_heap_oop_not_null $dst,$src" %}
7429 ins_encode %{
7430 Register s = $src$$Register;
7431 Register d = $dst$$Register;
7432 __ encode_heap_oop_not_null(d, s);
7433 %}
7434 ins_pipe(ialu_reg_long);
7435 %}
7436
7437 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
7438 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
7439 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
7440 match(Set dst (DecodeN src));
7441 effect(KILL cr);
7442 format %{ "decode_heap_oop $dst,$src" %}
7443 ins_encode %{
7444 Register s = $src$$Register;
7445 Register d = $dst$$Register;
7446 if (s != d) {
7447 __ movq(d, s);
7448 }
7449 __ decode_heap_oop(d);
7450 %}
7451 ins_pipe(ialu_reg_long);
7452 %}
7453
7454 instruct decodeHeapOop_not_null(rRegP dst, rRegN src) %{
7455 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
7456 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
7457 match(Set dst (DecodeN src));
7458 format %{ "decode_heap_oop_not_null $dst,$src" %}
7459 ins_encode %{
7460 Register s = $src$$Register;
7461 Register d = $dst$$Register;
7462 __ decode_heap_oop_not_null(d, s);
7463 %}
7464 ins_pipe(ialu_reg_long);
7465 %}
7466
7467
7468 //----------Conditional Move---------------------------------------------------
7469 // Jump
7470 // dummy instruction for generating temp registers
7471 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
7472 match(Jump (LShiftL switch_val shift));
7473 ins_cost(350);
7474 predicate(false);
7475 effect(TEMP dest);
7476
7477 format %{ "leaq $dest, table_base\n\t"
7478 "jmp [$dest + $switch_val << $shift]\n\t" %}
7479 ins_encode(jump_enc_offset(switch_val, shift, dest));
7480 ins_pipe(pipe_jmp);
7481 ins_pc_relative(1);
7482 %}
7483
7484 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
7485 match(Jump (AddL (LShiftL switch_val shift) offset));
7486 ins_cost(350);
7487 effect(TEMP dest);
7488
7489 format %{ "leaq $dest, table_base\n\t"
7490 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
7491 ins_encode(jump_enc_addr(switch_val, shift, offset, dest));
7492 ins_pipe(pipe_jmp);
7493 ins_pc_relative(1);
7494 %}
7495
7496 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7497 match(Jump switch_val);
7498 ins_cost(350);
7499 effect(TEMP dest);
7500
7501 format %{ "leaq $dest, table_base\n\t"
7502 "jmp [$dest + $switch_val]\n\t" %}
7503 ins_encode(jump_enc(switch_val, dest));
7504 ins_pipe(pipe_jmp);
7505 ins_pc_relative(1);
7506 %}
7507
7508 // Conditional move
7509 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7510 %{
7511 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7512
7513 ins_cost(200); // XXX
7514 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7515 opcode(0x0F, 0x40);
7516 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7517 ins_pipe(pipe_cmov_reg);
7518 %}
7519
7520 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7521 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7522
7523 ins_cost(200); // XXX
7524 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7525 opcode(0x0F, 0x40);
7526 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7527 ins_pipe(pipe_cmov_reg);
7528 %}
7529
7530 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7531 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7532 ins_cost(200);
7533 expand %{
7534 cmovI_regU(cop, cr, dst, src);
7535 %}
7536 %}
7537
7538 // Conditional move
7539 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7540 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7541
7542 ins_cost(250); // XXX
7543 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7544 opcode(0x0F, 0x40);
7545 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7546 ins_pipe(pipe_cmov_mem);
7547 %}
7548
7549 // Conditional move
7550 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7551 %{
7552 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7553
7554 ins_cost(250); // XXX
7555 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7556 opcode(0x0F, 0x40);
7557 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7558 ins_pipe(pipe_cmov_mem);
7559 %}
7560
7561 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7562 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7563 ins_cost(250);
7564 expand %{
7565 cmovI_memU(cop, cr, dst, src);
7566 %}
7567 %}
7568
7569 // Conditional move
7570 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7571 %{
7572 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7573
7574 ins_cost(200); // XXX
7575 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7576 opcode(0x0F, 0x40);
7577 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7578 ins_pipe(pipe_cmov_reg);
7579 %}
7580
7581 // Conditional move
7582 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7583 %{
7584 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7585
7586 ins_cost(200); // XXX
7587 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7588 opcode(0x0F, 0x40);
7589 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7590 ins_pipe(pipe_cmov_reg);
7591 %}
7592
7593 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7594 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7595 ins_cost(200);
7596 expand %{
7597 cmovN_regU(cop, cr, dst, src);
7598 %}
7599 %}
7600
7601 // Conditional move
7602 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7603 %{
7604 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7605
7606 ins_cost(200); // XXX
7607 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7608 opcode(0x0F, 0x40);
7609 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7610 ins_pipe(pipe_cmov_reg); // XXX
7611 %}
7612
7613 // Conditional move
7614 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7615 %{
7616 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7617
7618 ins_cost(200); // XXX
7619 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7620 opcode(0x0F, 0x40);
7621 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7622 ins_pipe(pipe_cmov_reg); // XXX
7623 %}
7624
7625 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7626 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7627 ins_cost(200);
7628 expand %{
7629 cmovP_regU(cop, cr, dst, src);
7630 %}
7631 %}
7632
7633 // DISABLED: Requires the ADLC to emit a bottom_type call that
7634 // correctly meets the two pointer arguments; one is an incoming
7635 // register but the other is a memory operand. ALSO appears to
7636 // be buggy with implicit null checks.
7637 //
7638 //// Conditional move
7639 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7640 //%{
7641 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7642 // ins_cost(250);
7643 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7644 // opcode(0x0F,0x40);
7645 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7646 // ins_pipe( pipe_cmov_mem );
7647 //%}
7648 //
7649 //// Conditional move
7650 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7651 //%{
7652 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7653 // ins_cost(250);
7654 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7655 // opcode(0x0F,0x40);
7656 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7657 // ins_pipe( pipe_cmov_mem );
7658 //%}
7659
7660 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7661 %{
7662 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7663
7664 ins_cost(200); // XXX
7665 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7666 opcode(0x0F, 0x40);
7667 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7668 ins_pipe(pipe_cmov_reg); // XXX
7669 %}
7670
7671 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7672 %{
7673 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7674
7675 ins_cost(200); // XXX
7676 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7677 opcode(0x0F, 0x40);
7678 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7679 ins_pipe(pipe_cmov_mem); // XXX
7680 %}
7681
7682 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7683 %{
7684 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7685
7686 ins_cost(200); // XXX
7687 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7688 opcode(0x0F, 0x40);
7689 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
7690 ins_pipe(pipe_cmov_reg); // XXX
7691 %}
7692
7693 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7694 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7695 ins_cost(200);
7696 expand %{
7697 cmovL_regU(cop, cr, dst, src);
7698 %}
7699 %}
7700
7701 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7702 %{
7703 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7704
7705 ins_cost(200); // XXX
7706 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7707 opcode(0x0F, 0x40);
7708 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
7709 ins_pipe(pipe_cmov_mem); // XXX
7710 %}
7711
7712 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7713 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7714 ins_cost(200);
7715 expand %{
7716 cmovL_memU(cop, cr, dst, src);
7717 %}
7718 %}
7719
7720 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7721 %{
7722 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7723
7724 ins_cost(200); // XXX
7725 format %{ "jn$cop skip\t# signed cmove float\n\t"
7726 "movss $dst, $src\n"
7727 "skip:" %}
7728 ins_encode(enc_cmovf_branch(cop, dst, src));
7729 ins_pipe(pipe_slow);
7730 %}
7731
7732 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7733 // %{
7734 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7735
7736 // ins_cost(200); // XXX
7737 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7738 // "movss $dst, $src\n"
7739 // "skip:" %}
7740 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7741 // ins_pipe(pipe_slow);
7742 // %}
7743
7744 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7745 %{
7746 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7747
7748 ins_cost(200); // XXX
7749 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7750 "movss $dst, $src\n"
7751 "skip:" %}
7752 ins_encode(enc_cmovf_branch(cop, dst, src));
7753 ins_pipe(pipe_slow);
7754 %}
7755
7756 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7757 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7758 ins_cost(200);
7759 expand %{
7760 cmovF_regU(cop, cr, dst, src);
7761 %}
7762 %}
7763
7764 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7765 %{
7766 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7767
7768 ins_cost(200); // XXX
7769 format %{ "jn$cop skip\t# signed cmove double\n\t"
7770 "movsd $dst, $src\n"
7771 "skip:" %}
7772 ins_encode(enc_cmovd_branch(cop, dst, src));
7773 ins_pipe(pipe_slow);
7774 %}
7775
7776 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7777 %{
7778 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7779
7780 ins_cost(200); // XXX
7781 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7782 "movsd $dst, $src\n"
7783 "skip:" %}
7784 ins_encode(enc_cmovd_branch(cop, dst, src));
7785 ins_pipe(pipe_slow);
7786 %}
7787
7788 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7789 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7790 ins_cost(200);
7791 expand %{
7792 cmovD_regU(cop, cr, dst, src);
7793 %}
7794 %}
7795
7796 //----------Arithmetic Instructions--------------------------------------------
7797 //----------Addition Instructions----------------------------------------------
7798
7799 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7800 %{
7801 match(Set dst (AddI dst src));
7802 effect(KILL cr);
7803
7804 format %{ "addl $dst, $src\t# int" %}
7805 opcode(0x03);
7806 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7807 ins_pipe(ialu_reg_reg);
7808 %}
7809
7810 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7811 %{
7812 match(Set dst (AddI dst src));
7813 effect(KILL cr);
7814
7815 format %{ "addl $dst, $src\t# int" %}
7816 opcode(0x81, 0x00); /* /0 id */
7817 ins_encode(OpcSErm(dst, src), Con8or32(src));
7818 ins_pipe( ialu_reg );
7819 %}
7820
7821 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7822 %{
7823 match(Set dst (AddI dst (LoadI src)));
7824 effect(KILL cr);
7825
7826 ins_cost(125); // XXX
7827 format %{ "addl $dst, $src\t# int" %}
7828 opcode(0x03);
7829 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7830 ins_pipe(ialu_reg_mem);
7831 %}
7832
7833 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7834 %{
7835 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7836 effect(KILL cr);
7837
7838 ins_cost(150); // XXX
7839 format %{ "addl $dst, $src\t# int" %}
7840 opcode(0x01); /* Opcode 01 /r */
7841 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7842 ins_pipe(ialu_mem_reg);
7843 %}
7844
7845 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7846 %{
7847 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7848 effect(KILL cr);
7849
7850 ins_cost(125); // XXX
7851 format %{ "addl $dst, $src\t# int" %}
7852 opcode(0x81); /* Opcode 81 /0 id */
7853 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7854 ins_pipe(ialu_mem_imm);
7855 %}
7856
7857 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
7858 %{
7859 predicate(UseIncDec);
7860 match(Set dst (AddI dst src));
7861 effect(KILL cr);
7862
7863 format %{ "incl $dst\t# int" %}
7864 opcode(0xFF, 0x00); // FF /0
7865 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7866 ins_pipe(ialu_reg);
7867 %}
7868
7869 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
7870 %{
7871 predicate(UseIncDec);
7872 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7873 effect(KILL cr);
7874
7875 ins_cost(125); // XXX
7876 format %{ "incl $dst\t# int" %}
7877 opcode(0xFF); /* Opcode FF /0 */
7878 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
7879 ins_pipe(ialu_mem_imm);
7880 %}
7881
7882 // XXX why does that use AddI
7883 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7884 %{
7885 predicate(UseIncDec);
7886 match(Set dst (AddI dst src));
7887 effect(KILL cr);
7888
7889 format %{ "decl $dst\t# int" %}
7890 opcode(0xFF, 0x01); // FF /1
7891 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7892 ins_pipe(ialu_reg);
7893 %}
7894
7895 // XXX why does that use AddI
7896 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7897 %{
7898 predicate(UseIncDec);
7899 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7900 effect(KILL cr);
7901
7902 ins_cost(125); // XXX
7903 format %{ "decl $dst\t# int" %}
7904 opcode(0xFF); /* Opcode FF /1 */
7905 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7906 ins_pipe(ialu_mem_imm);
7907 %}
7908
7909 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7910 %{
7911 match(Set dst (AddI src0 src1));
7912
7913 ins_cost(110);
7914 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7915 opcode(0x8D); /* 0x8D /r */
7916 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7917 ins_pipe(ialu_reg_reg);
7918 %}
7919
7920 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7921 %{
7922 match(Set dst (AddL dst src));
7923 effect(KILL cr);
7924
7925 format %{ "addq $dst, $src\t# long" %}
7926 opcode(0x03);
7927 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7928 ins_pipe(ialu_reg_reg);
7929 %}
7930
7931 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7932 %{
7933 match(Set dst (AddL dst src));
7934 effect(KILL cr);
7935
7936 format %{ "addq $dst, $src\t# long" %}
7937 opcode(0x81, 0x00); /* /0 id */
7938 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7939 ins_pipe( ialu_reg );
7940 %}
7941
7942 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7943 %{
7944 match(Set dst (AddL dst (LoadL src)));
7945 effect(KILL cr);
7946
7947 ins_cost(125); // XXX
7948 format %{ "addq $dst, $src\t# long" %}
7949 opcode(0x03);
7950 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7951 ins_pipe(ialu_reg_mem);
7952 %}
7953
7954 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7955 %{
7956 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7957 effect(KILL cr);
7958
7959 ins_cost(150); // XXX
7960 format %{ "addq $dst, $src\t# long" %}
7961 opcode(0x01); /* Opcode 01 /r */
7962 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7963 ins_pipe(ialu_mem_reg);
7964 %}
7965
7966 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7967 %{
7968 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7969 effect(KILL cr);
7970
7971 ins_cost(125); // XXX
7972 format %{ "addq $dst, $src\t# long" %}
7973 opcode(0x81); /* Opcode 81 /0 id */
7974 ins_encode(REX_mem_wide(dst),
7975 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7976 ins_pipe(ialu_mem_imm);
7977 %}
7978
7979 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7980 %{
7981 predicate(UseIncDec);
7982 match(Set dst (AddL dst src));
7983 effect(KILL cr);
7984
7985 format %{ "incq $dst\t# long" %}
7986 opcode(0xFF, 0x00); // FF /0
7987 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7988 ins_pipe(ialu_reg);
7989 %}
7990
7991 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7992 %{
7993 predicate(UseIncDec);
7994 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7995 effect(KILL cr);
7996
7997 ins_cost(125); // XXX
7998 format %{ "incq $dst\t# long" %}
7999 opcode(0xFF); /* Opcode FF /0 */
8000 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
8001 ins_pipe(ialu_mem_imm);
8002 %}
8003
8004 // XXX why does that use AddL
8005 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
8006 %{
8007 predicate(UseIncDec);
8008 match(Set dst (AddL dst src));
8009 effect(KILL cr);
8010
8011 format %{ "decq $dst\t# long" %}
8012 opcode(0xFF, 0x01); // FF /1
8013 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8014 ins_pipe(ialu_reg);
8015 %}
8016
8017 // XXX why does that use AddL
8018 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
8019 %{
8020 predicate(UseIncDec);
8021 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
8022 effect(KILL cr);
8023
8024 ins_cost(125); // XXX
8025 format %{ "decq $dst\t# long" %}
8026 opcode(0xFF); /* Opcode FF /1 */
8027 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
8028 ins_pipe(ialu_mem_imm);
8029 %}
8030
8031 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
8032 %{
8033 match(Set dst (AddL src0 src1));
8034
8035 ins_cost(110);
8036 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
8037 opcode(0x8D); /* 0x8D /r */
8038 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
8039 ins_pipe(ialu_reg_reg);
8040 %}
8041
8042 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
8043 %{
8044 match(Set dst (AddP dst src));
8045 effect(KILL cr);
8046
8047 format %{ "addq $dst, $src\t# ptr" %}
8048 opcode(0x03);
8049 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8050 ins_pipe(ialu_reg_reg);
8051 %}
8052
8053 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
8054 %{
8055 match(Set dst (AddP dst src));
8056 effect(KILL cr);
8057
8058 format %{ "addq $dst, $src\t# ptr" %}
8059 opcode(0x81, 0x00); /* /0 id */
8060 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8061 ins_pipe( ialu_reg );
8062 %}
8063
8064 // XXX addP mem ops ????
8065
8066 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
8067 %{
8068 match(Set dst (AddP src0 src1));
8069
8070 ins_cost(110);
8071 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
8072 opcode(0x8D); /* 0x8D /r */
8073 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
8074 ins_pipe(ialu_reg_reg);
8075 %}
8076
8077 instruct checkCastPP(rRegP dst)
8078 %{
8079 match(Set dst (CheckCastPP dst));
8080
8081 size(0);
8082 format %{ "# checkcastPP of $dst" %}
8083 ins_encode(/* empty encoding */);
8084 ins_pipe(empty);
8085 %}
8086
8087 instruct castPP(rRegP dst)
8088 %{
8089 match(Set dst (CastPP dst));
8090
8091 size(0);
8092 format %{ "# castPP of $dst" %}
8093 ins_encode(/* empty encoding */);
8094 ins_pipe(empty);
8095 %}
8096
8097 instruct castII(rRegI dst)
8098 %{
8099 match(Set dst (CastII dst));
8100
8101 size(0);
8102 format %{ "# castII of $dst" %}
8103 ins_encode(/* empty encoding */);
8104 ins_cost(0);
8105 ins_pipe(empty);
8106 %}
8107
8108 // LoadP-locked same as a regular LoadP when used with compare-swap
8109 instruct loadPLocked(rRegP dst, memory mem)
8110 %{
8111 match(Set dst (LoadPLocked mem));
8112
8113 ins_cost(125); // XXX
8114 format %{ "movq $dst, $mem\t# ptr locked" %}
8115 opcode(0x8B);
8116 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
8117 ins_pipe(ialu_reg_mem); // XXX
8118 %}
8119
8120 // LoadL-locked - same as a regular LoadL when used with compare-swap
8121 instruct loadLLocked(rRegL dst, memory mem)
8122 %{
8123 match(Set dst (LoadLLocked mem));
8124
8125 ins_cost(125); // XXX
8126 format %{ "movq $dst, $mem\t# long locked" %}
8127 opcode(0x8B);
8128 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
8129 ins_pipe(ialu_reg_mem); // XXX
8130 %}
8131
8132 // Conditional-store of the updated heap-top.
8133 // Used during allocation of the shared heap.
8134 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8135
8136 instruct storePConditional(memory heap_top_ptr,
8137 rax_RegP oldval, rRegP newval,
8138 rFlagsReg cr)
8139 %{
8140 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8141
8142 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
8143 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
8144 opcode(0x0F, 0xB1);
8145 ins_encode(lock_prefix,
8146 REX_reg_mem_wide(newval, heap_top_ptr),
8147 OpcP, OpcS,
8148 reg_mem(newval, heap_top_ptr));
8149 ins_pipe(pipe_cmpxchg);
8150 %}
8151
8152 // Conditional-store of an int value.
8153 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
8154 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
8155 %{
8156 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8157 effect(KILL oldval);
8158
8159 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
8160 opcode(0x0F, 0xB1);
8161 ins_encode(lock_prefix,
8162 REX_reg_mem(newval, mem),
8163 OpcP, OpcS,
8164 reg_mem(newval, mem));
8165 ins_pipe(pipe_cmpxchg);
8166 %}
8167
8168 // Conditional-store of a long value.
8169 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
8170 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
8171 %{
8172 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8173 effect(KILL oldval);
8174
8175 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
8176 opcode(0x0F, 0xB1);
8177 ins_encode(lock_prefix,
8178 REX_reg_mem_wide(newval, mem),
8179 OpcP, OpcS,
8180 reg_mem(newval, mem));
8181 ins_pipe(pipe_cmpxchg);
8182 %}
8183
8184
8185 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8186 instruct compareAndSwapP(rRegI res,
8187 memory mem_ptr,
8188 rax_RegP oldval, rRegP newval,
8189 rFlagsReg cr)
8190 %{
8191 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8192 effect(KILL cr, KILL oldval);
8193
8194 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8195 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8196 "sete $res\n\t"
8197 "movzbl $res, $res" %}
8198 opcode(0x0F, 0xB1);
8199 ins_encode(lock_prefix,
8200 REX_reg_mem_wide(newval, mem_ptr),
8201 OpcP, OpcS,
8202 reg_mem(newval, mem_ptr),
8203 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8204 REX_reg_breg(res, res), // movzbl
8205 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8206 ins_pipe( pipe_cmpxchg );
8207 %}
8208
8209 instruct compareAndSwapL(rRegI res,
8210 memory mem_ptr,
8211 rax_RegL oldval, rRegL newval,
8212 rFlagsReg cr)
8213 %{
8214 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8215 effect(KILL cr, KILL oldval);
8216
8217 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8218 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8219 "sete $res\n\t"
8220 "movzbl $res, $res" %}
8221 opcode(0x0F, 0xB1);
8222 ins_encode(lock_prefix,
8223 REX_reg_mem_wide(newval, mem_ptr),
8224 OpcP, OpcS,
8225 reg_mem(newval, mem_ptr),
8226 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8227 REX_reg_breg(res, res), // movzbl
8228 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8229 ins_pipe( pipe_cmpxchg );
8230 %}
8231
8232 instruct compareAndSwapI(rRegI res,
8233 memory mem_ptr,
8234 rax_RegI oldval, rRegI newval,
8235 rFlagsReg cr)
8236 %{
8237 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8238 effect(KILL cr, KILL oldval);
8239
8240 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8241 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8242 "sete $res\n\t"
8243 "movzbl $res, $res" %}
8244 opcode(0x0F, 0xB1);
8245 ins_encode(lock_prefix,
8246 REX_reg_mem(newval, mem_ptr),
8247 OpcP, OpcS,
8248 reg_mem(newval, mem_ptr),
8249 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8250 REX_reg_breg(res, res), // movzbl
8251 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8252 ins_pipe( pipe_cmpxchg );
8253 %}
8254
8255
8256 instruct compareAndSwapN(rRegI res,
8257 memory mem_ptr,
8258 rax_RegN oldval, rRegN newval,
8259 rFlagsReg cr) %{
8260 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
8261 effect(KILL cr, KILL oldval);
8262
8263 format %{ "cmpxchgl $mem_ptr,$newval\t# "
8264 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
8265 "sete $res\n\t"
8266 "movzbl $res, $res" %}
8267 opcode(0x0F, 0xB1);
8268 ins_encode(lock_prefix,
8269 REX_reg_mem(newval, mem_ptr),
8270 OpcP, OpcS,
8271 reg_mem(newval, mem_ptr),
8272 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
8273 REX_reg_breg(res, res), // movzbl
8274 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
8275 ins_pipe( pipe_cmpxchg );
8276 %}
8277
8278 //----------Subtraction Instructions-------------------------------------------
8279
8280 // Integer Subtraction Instructions
8281 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8282 %{
8283 match(Set dst (SubI dst src));
8284 effect(KILL cr);
8285
8286 format %{ "subl $dst, $src\t# int" %}
8287 opcode(0x2B);
8288 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8289 ins_pipe(ialu_reg_reg);
8290 %}
8291
8292 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8293 %{
8294 match(Set dst (SubI dst src));
8295 effect(KILL cr);
8296
8297 format %{ "subl $dst, $src\t# int" %}
8298 opcode(0x81, 0x05); /* Opcode 81 /5 */
8299 ins_encode(OpcSErm(dst, src), Con8or32(src));
8300 ins_pipe(ialu_reg);
8301 %}
8302
8303 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8304 %{
8305 match(Set dst (SubI dst (LoadI src)));
8306 effect(KILL cr);
8307
8308 ins_cost(125);
8309 format %{ "subl $dst, $src\t# int" %}
8310 opcode(0x2B);
8311 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8312 ins_pipe(ialu_reg_mem);
8313 %}
8314
8315 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8316 %{
8317 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8318 effect(KILL cr);
8319
8320 ins_cost(150);
8321 format %{ "subl $dst, $src\t# int" %}
8322 opcode(0x29); /* Opcode 29 /r */
8323 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8324 ins_pipe(ialu_mem_reg);
8325 %}
8326
8327 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8328 %{
8329 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8330 effect(KILL cr);
8331
8332 ins_cost(125); // XXX
8333 format %{ "subl $dst, $src\t# int" %}
8334 opcode(0x81); /* Opcode 81 /5 id */
8335 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8336 ins_pipe(ialu_mem_imm);
8337 %}
8338
8339 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8340 %{
8341 match(Set dst (SubL dst src));
8342 effect(KILL cr);
8343
8344 format %{ "subq $dst, $src\t# long" %}
8345 opcode(0x2B);
8346 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8347 ins_pipe(ialu_reg_reg);
8348 %}
8349
8350 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8351 %{
8352 match(Set dst (SubL dst src));
8353 effect(KILL cr);
8354
8355 format %{ "subq $dst, $src\t# long" %}
8356 opcode(0x81, 0x05); /* Opcode 81 /5 */
8357 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
8358 ins_pipe(ialu_reg);
8359 %}
8360
8361 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8362 %{
8363 match(Set dst (SubL dst (LoadL src)));
8364 effect(KILL cr);
8365
8366 ins_cost(125);
8367 format %{ "subq $dst, $src\t# long" %}
8368 opcode(0x2B);
8369 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
8370 ins_pipe(ialu_reg_mem);
8371 %}
8372
8373 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8374 %{
8375 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8376 effect(KILL cr);
8377
8378 ins_cost(150);
8379 format %{ "subq $dst, $src\t# long" %}
8380 opcode(0x29); /* Opcode 29 /r */
8381 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
8382 ins_pipe(ialu_mem_reg);
8383 %}
8384
8385 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8386 %{
8387 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8388 effect(KILL cr);
8389
8390 ins_cost(125); // XXX
8391 format %{ "subq $dst, $src\t# long" %}
8392 opcode(0x81); /* Opcode 81 /5 id */
8393 ins_encode(REX_mem_wide(dst),
8394 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
8395 ins_pipe(ialu_mem_imm);
8396 %}
8397
8398 // Subtract from a pointer
8399 // XXX hmpf???
8400 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
8401 %{
8402 match(Set dst (AddP dst (SubI zero src)));
8403 effect(KILL cr);
8404
8405 format %{ "subq $dst, $src\t# ptr - int" %}
8406 opcode(0x2B);
8407 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8408 ins_pipe(ialu_reg_reg);
8409 %}
8410
8411 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
8412 %{
8413 match(Set dst (SubI zero dst));
8414 effect(KILL cr);
8415
8416 format %{ "negl $dst\t# int" %}
8417 opcode(0xF7, 0x03); // Opcode F7 /3
8418 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8419 ins_pipe(ialu_reg);
8420 %}
8421
8422 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
8423 %{
8424 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8425 effect(KILL cr);
8426
8427 format %{ "negl $dst\t# int" %}
8428 opcode(0xF7, 0x03); // Opcode F7 /3
8429 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8430 ins_pipe(ialu_reg);
8431 %}
8432
8433 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8434 %{
8435 match(Set dst (SubL zero dst));
8436 effect(KILL cr);
8437
8438 format %{ "negq $dst\t# long" %}
8439 opcode(0xF7, 0x03); // Opcode F7 /3
8440 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8441 ins_pipe(ialu_reg);
8442 %}
8443
8444 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8445 %{
8446 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8447 effect(KILL cr);
8448
8449 format %{ "negq $dst\t# long" %}
8450 opcode(0xF7, 0x03); // Opcode F7 /3
8451 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8452 ins_pipe(ialu_reg);
8453 %}
8454
8455
8456 //----------Multiplication/Division Instructions-------------------------------
8457 // Integer Multiplication Instructions
8458 // Multiply Register
8459
8460 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8461 %{
8462 match(Set dst (MulI dst src));
8463 effect(KILL cr);
8464
8465 ins_cost(300);
8466 format %{ "imull $dst, $src\t# int" %}
8467 opcode(0x0F, 0xAF);
8468 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8469 ins_pipe(ialu_reg_reg_alu0);
8470 %}
8471
8472 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8473 %{
8474 match(Set dst (MulI src imm));
8475 effect(KILL cr);
8476
8477 ins_cost(300);
8478 format %{ "imull $dst, $src, $imm\t# int" %}
8479 opcode(0x69); /* 69 /r id */
8480 ins_encode(REX_reg_reg(dst, src),
8481 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8482 ins_pipe(ialu_reg_reg_alu0);
8483 %}
8484
8485 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8486 %{
8487 match(Set dst (MulI dst (LoadI src)));
8488 effect(KILL cr);
8489
8490 ins_cost(350);
8491 format %{ "imull $dst, $src\t# int" %}
8492 opcode(0x0F, 0xAF);
8493 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
8494 ins_pipe(ialu_reg_mem_alu0);
8495 %}
8496
8497 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8498 %{
8499 match(Set dst (MulI (LoadI src) imm));
8500 effect(KILL cr);
8501
8502 ins_cost(300);
8503 format %{ "imull $dst, $src, $imm\t# int" %}
8504 opcode(0x69); /* 69 /r id */
8505 ins_encode(REX_reg_mem(dst, src),
8506 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8507 ins_pipe(ialu_reg_mem_alu0);
8508 %}
8509
8510 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8511 %{
8512 match(Set dst (MulL dst src));
8513 effect(KILL cr);
8514
8515 ins_cost(300);
8516 format %{ "imulq $dst, $src\t# long" %}
8517 opcode(0x0F, 0xAF);
8518 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
8519 ins_pipe(ialu_reg_reg_alu0);
8520 %}
8521
8522 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8523 %{
8524 match(Set dst (MulL src imm));
8525 effect(KILL cr);
8526
8527 ins_cost(300);
8528 format %{ "imulq $dst, $src, $imm\t# long" %}
8529 opcode(0x69); /* 69 /r id */
8530 ins_encode(REX_reg_reg_wide(dst, src),
8531 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
8532 ins_pipe(ialu_reg_reg_alu0);
8533 %}
8534
8535 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8536 %{
8537 match(Set dst (MulL dst (LoadL src)));
8538 effect(KILL cr);
8539
8540 ins_cost(350);
8541 format %{ "imulq $dst, $src\t# long" %}
8542 opcode(0x0F, 0xAF);
8543 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
8544 ins_pipe(ialu_reg_mem_alu0);
8545 %}
8546
8547 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8548 %{
8549 match(Set dst (MulL (LoadL src) imm));
8550 effect(KILL cr);
8551
8552 ins_cost(300);
8553 format %{ "imulq $dst, $src, $imm\t# long" %}
8554 opcode(0x69); /* 69 /r id */
8555 ins_encode(REX_reg_mem_wide(dst, src),
8556 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
8557 ins_pipe(ialu_reg_mem_alu0);
8558 %}
8559
8560 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8561 %{
8562 match(Set dst (MulHiL src rax));
8563 effect(USE_KILL rax, KILL cr);
8564
8565 ins_cost(300);
8566 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8567 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8568 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8569 ins_pipe(ialu_reg_reg_alu0);
8570 %}
8571
8572 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8573 rFlagsReg cr)
8574 %{
8575 match(Set rax (DivI rax div));
8576 effect(KILL rdx, KILL cr);
8577
8578 ins_cost(30*100+10*100); // XXX
8579 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8580 "jne,s normal\n\t"
8581 "xorl rdx, rdx\n\t"
8582 "cmpl $div, -1\n\t"
8583 "je,s done\n"
8584 "normal: cdql\n\t"
8585 "idivl $div\n"
8586 "done:" %}
8587 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8588 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8589 ins_pipe(ialu_reg_reg_alu0);
8590 %}
8591
8592 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8593 rFlagsReg cr)
8594 %{
8595 match(Set rax (DivL rax div));
8596 effect(KILL rdx, KILL cr);
8597
8598 ins_cost(30*100+10*100); // XXX
8599 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8600 "cmpq rax, rdx\n\t"
8601 "jne,s normal\n\t"
8602 "xorl rdx, rdx\n\t"
8603 "cmpq $div, -1\n\t"
8604 "je,s done\n"
8605 "normal: cdqq\n\t"
8606 "idivq $div\n"
8607 "done:" %}
8608 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8609 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8610 ins_pipe(ialu_reg_reg_alu0);
8611 %}
8612
8613 // Integer DIVMOD with Register, both quotient and mod results
8614 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8615 rFlagsReg cr)
8616 %{
8617 match(DivModI rax div);
8618 effect(KILL cr);
8619
8620 ins_cost(30*100+10*100); // XXX
8621 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8622 "jne,s normal\n\t"
8623 "xorl rdx, rdx\n\t"
8624 "cmpl $div, -1\n\t"
8625 "je,s done\n"
8626 "normal: cdql\n\t"
8627 "idivl $div\n"
8628 "done:" %}
8629 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8630 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8631 ins_pipe(pipe_slow);
8632 %}
8633
8634 // Long DIVMOD with Register, both quotient and mod results
8635 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8636 rFlagsReg cr)
8637 %{
8638 match(DivModL rax div);
8639 effect(KILL cr);
8640
8641 ins_cost(30*100+10*100); // XXX
8642 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8643 "cmpq rax, rdx\n\t"
8644 "jne,s normal\n\t"
8645 "xorl rdx, rdx\n\t"
8646 "cmpq $div, -1\n\t"
8647 "je,s done\n"
8648 "normal: cdqq\n\t"
8649 "idivq $div\n"
8650 "done:" %}
8651 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8652 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8653 ins_pipe(pipe_slow);
8654 %}
8655
8656 //----------- DivL-By-Constant-Expansions--------------------------------------
8657 // DivI cases are handled by the compiler
8658
8659 // Magic constant, reciprical of 10
8660 instruct loadConL_0x6666666666666667(rRegL dst)
8661 %{
8662 effect(DEF dst);
8663
8664 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8665 ins_encode(load_immL(dst, 0x6666666666666667));
8666 ins_pipe(ialu_reg);
8667 %}
8668
8669 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8670 %{
8671 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8672
8673 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8674 opcode(0xF7, 0x5); /* Opcode F7 /5 */
8675 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
8676 ins_pipe(ialu_reg_reg_alu0);
8677 %}
8678
8679 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8680 %{
8681 effect(USE_DEF dst, KILL cr);
8682
8683 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8684 opcode(0xC1, 0x7); /* C1 /7 ib */
8685 ins_encode(reg_opc_imm_wide(dst, 0x3F));
8686 ins_pipe(ialu_reg);
8687 %}
8688
8689 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8690 %{
8691 effect(USE_DEF dst, KILL cr);
8692
8693 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8694 opcode(0xC1, 0x7); /* C1 /7 ib */
8695 ins_encode(reg_opc_imm_wide(dst, 0x2));
8696 ins_pipe(ialu_reg);
8697 %}
8698
8699 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8700 %{
8701 match(Set dst (DivL src div));
8702
8703 ins_cost((5+8)*100);
8704 expand %{
8705 rax_RegL rax; // Killed temp
8706 rFlagsReg cr; // Killed
8707 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8708 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8709 sarL_rReg_63(src, cr); // sarq src, 63
8710 sarL_rReg_2(dst, cr); // sarq rdx, 2
8711 subL_rReg(dst, src, cr); // subl rdx, src
8712 %}
8713 %}
8714
8715 //-----------------------------------------------------------------------------
8716
8717 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8718 rFlagsReg cr)
8719 %{
8720 match(Set rdx (ModI rax div));
8721 effect(KILL rax, KILL cr);
8722
8723 ins_cost(300); // XXX
8724 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8725 "jne,s normal\n\t"
8726 "xorl rdx, rdx\n\t"
8727 "cmpl $div, -1\n\t"
8728 "je,s done\n"
8729 "normal: cdql\n\t"
8730 "idivl $div\n"
8731 "done:" %}
8732 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8733 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
8734 ins_pipe(ialu_reg_reg_alu0);
8735 %}
8736
8737 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8738 rFlagsReg cr)
8739 %{
8740 match(Set rdx (ModL rax div));
8741 effect(KILL rax, KILL cr);
8742
8743 ins_cost(300); // XXX
8744 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8745 "cmpq rax, rdx\n\t"
8746 "jne,s normal\n\t"
8747 "xorl rdx, rdx\n\t"
8748 "cmpq $div, -1\n\t"
8749 "je,s done\n"
8750 "normal: cdqq\n\t"
8751 "idivq $div\n"
8752 "done:" %}
8753 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8754 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8755 ins_pipe(ialu_reg_reg_alu0);
8756 %}
8757
8758 // Integer Shift Instructions
8759 // Shift Left by one
8760 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8761 %{
8762 match(Set dst (LShiftI dst shift));
8763 effect(KILL cr);
8764
8765 format %{ "sall $dst, $shift" %}
8766 opcode(0xD1, 0x4); /* D1 /4 */
8767 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8768 ins_pipe(ialu_reg);
8769 %}
8770
8771 // Shift Left by one
8772 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8773 %{
8774 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8775 effect(KILL cr);
8776
8777 format %{ "sall $dst, $shift\t" %}
8778 opcode(0xD1, 0x4); /* D1 /4 */
8779 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8780 ins_pipe(ialu_mem_imm);
8781 %}
8782
8783 // Shift Left by 8-bit immediate
8784 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8785 %{
8786 match(Set dst (LShiftI dst shift));
8787 effect(KILL cr);
8788
8789 format %{ "sall $dst, $shift" %}
8790 opcode(0xC1, 0x4); /* C1 /4 ib */
8791 ins_encode(reg_opc_imm(dst, shift));
8792 ins_pipe(ialu_reg);
8793 %}
8794
8795 // Shift Left by 8-bit immediate
8796 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8797 %{
8798 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8799 effect(KILL cr);
8800
8801 format %{ "sall $dst, $shift" %}
8802 opcode(0xC1, 0x4); /* C1 /4 ib */
8803 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8804 ins_pipe(ialu_mem_imm);
8805 %}
8806
8807 // Shift Left by variable
8808 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8809 %{
8810 match(Set dst (LShiftI dst shift));
8811 effect(KILL cr);
8812
8813 format %{ "sall $dst, $shift" %}
8814 opcode(0xD3, 0x4); /* D3 /4 */
8815 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8816 ins_pipe(ialu_reg_reg);
8817 %}
8818
8819 // Shift Left by variable
8820 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8821 %{
8822 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8823 effect(KILL cr);
8824
8825 format %{ "sall $dst, $shift" %}
8826 opcode(0xD3, 0x4); /* D3 /4 */
8827 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8828 ins_pipe(ialu_mem_reg);
8829 %}
8830
8831 // Arithmetic shift right by one
8832 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8833 %{
8834 match(Set dst (RShiftI dst shift));
8835 effect(KILL cr);
8836
8837 format %{ "sarl $dst, $shift" %}
8838 opcode(0xD1, 0x7); /* D1 /7 */
8839 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8840 ins_pipe(ialu_reg);
8841 %}
8842
8843 // Arithmetic shift right by one
8844 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8845 %{
8846 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8847 effect(KILL cr);
8848
8849 format %{ "sarl $dst, $shift" %}
8850 opcode(0xD1, 0x7); /* D1 /7 */
8851 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8852 ins_pipe(ialu_mem_imm);
8853 %}
8854
8855 // Arithmetic Shift Right by 8-bit immediate
8856 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8857 %{
8858 match(Set dst (RShiftI dst shift));
8859 effect(KILL cr);
8860
8861 format %{ "sarl $dst, $shift" %}
8862 opcode(0xC1, 0x7); /* C1 /7 ib */
8863 ins_encode(reg_opc_imm(dst, shift));
8864 ins_pipe(ialu_mem_imm);
8865 %}
8866
8867 // Arithmetic Shift Right by 8-bit immediate
8868 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8869 %{
8870 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8871 effect(KILL cr);
8872
8873 format %{ "sarl $dst, $shift" %}
8874 opcode(0xC1, 0x7); /* C1 /7 ib */
8875 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8876 ins_pipe(ialu_mem_imm);
8877 %}
8878
8879 // Arithmetic Shift Right by variable
8880 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8881 %{
8882 match(Set dst (RShiftI dst shift));
8883 effect(KILL cr);
8884
8885 format %{ "sarl $dst, $shift" %}
8886 opcode(0xD3, 0x7); /* D3 /7 */
8887 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8888 ins_pipe(ialu_reg_reg);
8889 %}
8890
8891 // Arithmetic Shift Right by variable
8892 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8893 %{
8894 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8895 effect(KILL cr);
8896
8897 format %{ "sarl $dst, $shift" %}
8898 opcode(0xD3, 0x7); /* D3 /7 */
8899 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8900 ins_pipe(ialu_mem_reg);
8901 %}
8902
8903 // Logical shift right by one
8904 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8905 %{
8906 match(Set dst (URShiftI dst shift));
8907 effect(KILL cr);
8908
8909 format %{ "shrl $dst, $shift" %}
8910 opcode(0xD1, 0x5); /* D1 /5 */
8911 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8912 ins_pipe(ialu_reg);
8913 %}
8914
8915 // Logical shift right by one
8916 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8917 %{
8918 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8919 effect(KILL cr);
8920
8921 format %{ "shrl $dst, $shift" %}
8922 opcode(0xD1, 0x5); /* D1 /5 */
8923 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8924 ins_pipe(ialu_mem_imm);
8925 %}
8926
8927 // Logical Shift Right by 8-bit immediate
8928 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8929 %{
8930 match(Set dst (URShiftI dst shift));
8931 effect(KILL cr);
8932
8933 format %{ "shrl $dst, $shift" %}
8934 opcode(0xC1, 0x5); /* C1 /5 ib */
8935 ins_encode(reg_opc_imm(dst, shift));
8936 ins_pipe(ialu_reg);
8937 %}
8938
8939 // Logical Shift Right by 8-bit immediate
8940 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8941 %{
8942 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8943 effect(KILL cr);
8944
8945 format %{ "shrl $dst, $shift" %}
8946 opcode(0xC1, 0x5); /* C1 /5 ib */
8947 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8948 ins_pipe(ialu_mem_imm);
8949 %}
8950
8951 // Logical Shift Right by variable
8952 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8953 %{
8954 match(Set dst (URShiftI dst shift));
8955 effect(KILL cr);
8956
8957 format %{ "shrl $dst, $shift" %}
8958 opcode(0xD3, 0x5); /* D3 /5 */
8959 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8960 ins_pipe(ialu_reg_reg);
8961 %}
8962
8963 // Logical Shift Right by variable
8964 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8965 %{
8966 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8967 effect(KILL cr);
8968
8969 format %{ "shrl $dst, $shift" %}
8970 opcode(0xD3, 0x5); /* D3 /5 */
8971 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8972 ins_pipe(ialu_mem_reg);
8973 %}
8974
8975 // Long Shift Instructions
8976 // Shift Left by one
8977 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8978 %{
8979 match(Set dst (LShiftL dst shift));
8980 effect(KILL cr);
8981
8982 format %{ "salq $dst, $shift" %}
8983 opcode(0xD1, 0x4); /* D1 /4 */
8984 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8985 ins_pipe(ialu_reg);
8986 %}
8987
8988 // Shift Left by one
8989 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8990 %{
8991 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8992 effect(KILL cr);
8993
8994 format %{ "salq $dst, $shift" %}
8995 opcode(0xD1, 0x4); /* D1 /4 */
8996 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8997 ins_pipe(ialu_mem_imm);
8998 %}
8999
9000 // Shift Left by 8-bit immediate
9001 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9002 %{
9003 match(Set dst (LShiftL dst shift));
9004 effect(KILL cr);
9005
9006 format %{ "salq $dst, $shift" %}
9007 opcode(0xC1, 0x4); /* C1 /4 ib */
9008 ins_encode(reg_opc_imm_wide(dst, shift));
9009 ins_pipe(ialu_reg);
9010 %}
9011
9012 // Shift Left by 8-bit immediate
9013 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9014 %{
9015 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9016 effect(KILL cr);
9017
9018 format %{ "salq $dst, $shift" %}
9019 opcode(0xC1, 0x4); /* C1 /4 ib */
9020 ins_encode(REX_mem_wide(dst), OpcP,
9021 RM_opc_mem(secondary, dst), Con8or32(shift));
9022 ins_pipe(ialu_mem_imm);
9023 %}
9024
9025 // Shift Left by variable
9026 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9027 %{
9028 match(Set dst (LShiftL dst shift));
9029 effect(KILL cr);
9030
9031 format %{ "salq $dst, $shift" %}
9032 opcode(0xD3, 0x4); /* D3 /4 */
9033 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9034 ins_pipe(ialu_reg_reg);
9035 %}
9036
9037 // Shift Left by variable
9038 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9039 %{
9040 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9041 effect(KILL cr);
9042
9043 format %{ "salq $dst, $shift" %}
9044 opcode(0xD3, 0x4); /* D3 /4 */
9045 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9046 ins_pipe(ialu_mem_reg);
9047 %}
9048
9049 // Arithmetic shift right by one
9050 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9051 %{
9052 match(Set dst (RShiftL dst shift));
9053 effect(KILL cr);
9054
9055 format %{ "sarq $dst, $shift" %}
9056 opcode(0xD1, 0x7); /* D1 /7 */
9057 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9058 ins_pipe(ialu_reg);
9059 %}
9060
9061 // Arithmetic shift right by one
9062 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9063 %{
9064 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9065 effect(KILL cr);
9066
9067 format %{ "sarq $dst, $shift" %}
9068 opcode(0xD1, 0x7); /* D1 /7 */
9069 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9070 ins_pipe(ialu_mem_imm);
9071 %}
9072
9073 // Arithmetic Shift Right by 8-bit immediate
9074 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9075 %{
9076 match(Set dst (RShiftL dst shift));
9077 effect(KILL cr);
9078
9079 format %{ "sarq $dst, $shift" %}
9080 opcode(0xC1, 0x7); /* C1 /7 ib */
9081 ins_encode(reg_opc_imm_wide(dst, shift));
9082 ins_pipe(ialu_mem_imm);
9083 %}
9084
9085 // Arithmetic Shift Right by 8-bit immediate
9086 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9087 %{
9088 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9089 effect(KILL cr);
9090
9091 format %{ "sarq $dst, $shift" %}
9092 opcode(0xC1, 0x7); /* C1 /7 ib */
9093 ins_encode(REX_mem_wide(dst), OpcP,
9094 RM_opc_mem(secondary, dst), Con8or32(shift));
9095 ins_pipe(ialu_mem_imm);
9096 %}
9097
9098 // Arithmetic Shift Right by variable
9099 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9100 %{
9101 match(Set dst (RShiftL dst shift));
9102 effect(KILL cr);
9103
9104 format %{ "sarq $dst, $shift" %}
9105 opcode(0xD3, 0x7); /* D3 /7 */
9106 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9107 ins_pipe(ialu_reg_reg);
9108 %}
9109
9110 // Arithmetic Shift Right by variable
9111 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9112 %{
9113 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9114 effect(KILL cr);
9115
9116 format %{ "sarq $dst, $shift" %}
9117 opcode(0xD3, 0x7); /* D3 /7 */
9118 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9119 ins_pipe(ialu_mem_reg);
9120 %}
9121
9122 // Logical shift right by one
9123 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
9124 %{
9125 match(Set dst (URShiftL dst shift));
9126 effect(KILL cr);
9127
9128 format %{ "shrq $dst, $shift" %}
9129 opcode(0xD1, 0x5); /* D1 /5 */
9130 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
9131 ins_pipe(ialu_reg);
9132 %}
9133
9134 // Logical shift right by one
9135 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
9136 %{
9137 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9138 effect(KILL cr);
9139
9140 format %{ "shrq $dst, $shift" %}
9141 opcode(0xD1, 0x5); /* D1 /5 */
9142 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9143 ins_pipe(ialu_mem_imm);
9144 %}
9145
9146 // Logical Shift Right by 8-bit immediate
9147 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9148 %{
9149 match(Set dst (URShiftL dst shift));
9150 effect(KILL cr);
9151
9152 format %{ "shrq $dst, $shift" %}
9153 opcode(0xC1, 0x5); /* C1 /5 ib */
9154 ins_encode(reg_opc_imm_wide(dst, shift));
9155 ins_pipe(ialu_reg);
9156 %}
9157
9158
9159 // Logical Shift Right by 8-bit immediate
9160 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9161 %{
9162 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9163 effect(KILL cr);
9164
9165 format %{ "shrq $dst, $shift" %}
9166 opcode(0xC1, 0x5); /* C1 /5 ib */
9167 ins_encode(REX_mem_wide(dst), OpcP,
9168 RM_opc_mem(secondary, dst), Con8or32(shift));
9169 ins_pipe(ialu_mem_imm);
9170 %}
9171
9172 // Logical Shift Right by variable
9173 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9174 %{
9175 match(Set dst (URShiftL dst shift));
9176 effect(KILL cr);
9177
9178 format %{ "shrq $dst, $shift" %}
9179 opcode(0xD3, 0x5); /* D3 /5 */
9180 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9181 ins_pipe(ialu_reg_reg);
9182 %}
9183
9184 // Logical Shift Right by variable
9185 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9186 %{
9187 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9188 effect(KILL cr);
9189
9190 format %{ "shrq $dst, $shift" %}
9191 opcode(0xD3, 0x5); /* D3 /5 */
9192 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
9193 ins_pipe(ialu_mem_reg);
9194 %}
9195
9196 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9197 // This idiom is used by the compiler for the i2b bytecode.
9198 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9199 %{
9200 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9201
9202 format %{ "movsbl $dst, $src\t# i2b" %}
9203 opcode(0x0F, 0xBE);
9204 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9205 ins_pipe(ialu_reg_reg);
9206 %}
9207
9208 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9209 // This idiom is used by the compiler the i2s bytecode.
9210 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9211 %{
9212 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9213
9214 format %{ "movswl $dst, $src\t# i2s" %}
9215 opcode(0x0F, 0xBF);
9216 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9217 ins_pipe(ialu_reg_reg);
9218 %}
9219
9220 // ROL/ROR instructions
9221
9222 // ROL expand
9223 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
9224 effect(KILL cr, USE_DEF dst);
9225
9226 format %{ "roll $dst" %}
9227 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9228 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9229 ins_pipe(ialu_reg);
9230 %}
9231
9232 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
9233 effect(USE_DEF dst, USE shift, KILL cr);
9234
9235 format %{ "roll $dst, $shift" %}
9236 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9237 ins_encode( reg_opc_imm(dst, shift) );
9238 ins_pipe(ialu_reg);
9239 %}
9240
9241 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9242 %{
9243 effect(USE_DEF dst, USE shift, KILL cr);
9244
9245 format %{ "roll $dst, $shift" %}
9246 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9247 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9248 ins_pipe(ialu_reg_reg);
9249 %}
9250 // end of ROL expand
9251
9252 // Rotate Left by one
9253 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9254 %{
9255 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9256
9257 expand %{
9258 rolI_rReg_imm1(dst, cr);
9259 %}
9260 %}
9261
9262 // Rotate Left by 8-bit immediate
9263 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9264 %{
9265 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9266 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
9267
9268 expand %{
9269 rolI_rReg_imm8(dst, lshift, cr);
9270 %}
9271 %}
9272
9273 // Rotate Left by variable
9274 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9275 %{
9276 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
9277
9278 expand %{
9279 rolI_rReg_CL(dst, shift, cr);
9280 %}
9281 %}
9282
9283 // Rotate Left by variable
9284 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9285 %{
9286 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
9287
9288 expand %{
9289 rolI_rReg_CL(dst, shift, cr);
9290 %}
9291 %}
9292
9293 // ROR expand
9294 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
9295 %{
9296 effect(USE_DEF dst, KILL cr);
9297
9298 format %{ "rorl $dst" %}
9299 opcode(0xD1, 0x1); /* D1 /1 */
9300 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9301 ins_pipe(ialu_reg);
9302 %}
9303
9304 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
9305 %{
9306 effect(USE_DEF dst, USE shift, KILL cr);
9307
9308 format %{ "rorl $dst, $shift" %}
9309 opcode(0xC1, 0x1); /* C1 /1 ib */
9310 ins_encode(reg_opc_imm(dst, shift));
9311 ins_pipe(ialu_reg);
9312 %}
9313
9314 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
9315 %{
9316 effect(USE_DEF dst, USE shift, KILL cr);
9317
9318 format %{ "rorl $dst, $shift" %}
9319 opcode(0xD3, 0x1); /* D3 /1 */
9320 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
9321 ins_pipe(ialu_reg_reg);
9322 %}
9323 // end of ROR expand
9324
9325 // Rotate Right by one
9326 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9327 %{
9328 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9329
9330 expand %{
9331 rorI_rReg_imm1(dst, cr);
9332 %}
9333 %}
9334
9335 // Rotate Right by 8-bit immediate
9336 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9337 %{
9338 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9339 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
9340
9341 expand %{
9342 rorI_rReg_imm8(dst, rshift, cr);
9343 %}
9344 %}
9345
9346 // Rotate Right by variable
9347 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9348 %{
9349 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
9350
9351 expand %{
9352 rorI_rReg_CL(dst, shift, cr);
9353 %}
9354 %}
9355
9356 // Rotate Right by variable
9357 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
9358 %{
9359 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9360
9361 expand %{
9362 rorI_rReg_CL(dst, shift, cr);
9363 %}
9364 %}
9365
9366 // for long rotate
9367 // ROL expand
9368 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
9369 effect(USE_DEF dst, KILL cr);
9370
9371 format %{ "rolq $dst" %}
9372 opcode(0xD1, 0x0); /* Opcode D1 /0 */
9373 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9374 ins_pipe(ialu_reg);
9375 %}
9376
9377 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
9378 effect(USE_DEF dst, USE shift, KILL cr);
9379
9380 format %{ "rolq $dst, $shift" %}
9381 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
9382 ins_encode( reg_opc_imm_wide(dst, shift) );
9383 ins_pipe(ialu_reg);
9384 %}
9385
9386 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9387 %{
9388 effect(USE_DEF dst, USE shift, KILL cr);
9389
9390 format %{ "rolq $dst, $shift" %}
9391 opcode(0xD3, 0x0); /* Opcode D3 /0 */
9392 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9393 ins_pipe(ialu_reg_reg);
9394 %}
9395 // end of ROL expand
9396
9397 // Rotate Left by one
9398 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
9399 %{
9400 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9401
9402 expand %{
9403 rolL_rReg_imm1(dst, cr);
9404 %}
9405 %}
9406
9407 // Rotate Left by 8-bit immediate
9408 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
9409 %{
9410 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9411 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
9412
9413 expand %{
9414 rolL_rReg_imm8(dst, lshift, cr);
9415 %}
9416 %}
9417
9418 // Rotate Left by variable
9419 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9420 %{
9421 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
9422
9423 expand %{
9424 rolL_rReg_CL(dst, shift, cr);
9425 %}
9426 %}
9427
9428 // Rotate Left by variable
9429 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9430 %{
9431 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
9432
9433 expand %{
9434 rolL_rReg_CL(dst, shift, cr);
9435 %}
9436 %}
9437
9438 // ROR expand
9439 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
9440 %{
9441 effect(USE_DEF dst, KILL cr);
9442
9443 format %{ "rorq $dst" %}
9444 opcode(0xD1, 0x1); /* D1 /1 */
9445 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9446 ins_pipe(ialu_reg);
9447 %}
9448
9449 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
9450 %{
9451 effect(USE_DEF dst, USE shift, KILL cr);
9452
9453 format %{ "rorq $dst, $shift" %}
9454 opcode(0xC1, 0x1); /* C1 /1 ib */
9455 ins_encode(reg_opc_imm_wide(dst, shift));
9456 ins_pipe(ialu_reg);
9457 %}
9458
9459 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
9460 %{
9461 effect(USE_DEF dst, USE shift, KILL cr);
9462
9463 format %{ "rorq $dst, $shift" %}
9464 opcode(0xD3, 0x1); /* D3 /1 */
9465 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
9466 ins_pipe(ialu_reg_reg);
9467 %}
9468 // end of ROR expand
9469
9470 // Rotate Right by one
9471 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
9472 %{
9473 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9474
9475 expand %{
9476 rorL_rReg_imm1(dst, cr);
9477 %}
9478 %}
9479
9480 // Rotate Right by 8-bit immediate
9481 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
9482 %{
9483 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
9484 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
9485
9486 expand %{
9487 rorL_rReg_imm8(dst, rshift, cr);
9488 %}
9489 %}
9490
9491 // Rotate Right by variable
9492 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
9493 %{
9494 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
9495
9496 expand %{
9497 rorL_rReg_CL(dst, shift, cr);
9498 %}
9499 %}
9500
9501 // Rotate Right by variable
9502 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
9503 %{
9504 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
9505
9506 expand %{
9507 rorL_rReg_CL(dst, shift, cr);
9508 %}
9509 %}
9510
9511 // Logical Instructions
9512
9513 // Integer Logical Instructions
9514
9515 // And Instructions
9516 // And Register with Register
9517 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9518 %{
9519 match(Set dst (AndI dst src));
9520 effect(KILL cr);
9521
9522 format %{ "andl $dst, $src\t# int" %}
9523 opcode(0x23);
9524 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9525 ins_pipe(ialu_reg_reg);
9526 %}
9527
9528 // And Register with Immediate 255
9529 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9530 %{
9531 match(Set dst (AndI dst src));
9532
9533 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9534 opcode(0x0F, 0xB6);
9535 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9536 ins_pipe(ialu_reg);
9537 %}
9538
9539 // And Register with Immediate 255 and promote to long
9540 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9541 %{
9542 match(Set dst (ConvI2L (AndI src mask)));
9543
9544 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9545 opcode(0x0F, 0xB6);
9546 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9547 ins_pipe(ialu_reg);
9548 %}
9549
9550 // And Register with Immediate 65535
9551 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9552 %{
9553 match(Set dst (AndI dst src));
9554
9555 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9556 opcode(0x0F, 0xB7);
9557 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9558 ins_pipe(ialu_reg);
9559 %}
9560
9561 // And Register with Immediate 65535 and promote to long
9562 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9563 %{
9564 match(Set dst (ConvI2L (AndI src mask)));
9565
9566 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9567 opcode(0x0F, 0xB7);
9568 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
9569 ins_pipe(ialu_reg);
9570 %}
9571
9572 // And Register with Immediate
9573 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9574 %{
9575 match(Set dst (AndI dst src));
9576 effect(KILL cr);
9577
9578 format %{ "andl $dst, $src\t# int" %}
9579 opcode(0x81, 0x04); /* Opcode 81 /4 */
9580 ins_encode(OpcSErm(dst, src), Con8or32(src));
9581 ins_pipe(ialu_reg);
9582 %}
9583
9584 // And Register with Memory
9585 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9586 %{
9587 match(Set dst (AndI dst (LoadI src)));
9588 effect(KILL cr);
9589
9590 ins_cost(125);
9591 format %{ "andl $dst, $src\t# int" %}
9592 opcode(0x23);
9593 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9594 ins_pipe(ialu_reg_mem);
9595 %}
9596
9597 // And Memory with Register
9598 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9599 %{
9600 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9601 effect(KILL cr);
9602
9603 ins_cost(150);
9604 format %{ "andl $dst, $src\t# int" %}
9605 opcode(0x21); /* Opcode 21 /r */
9606 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9607 ins_pipe(ialu_mem_reg);
9608 %}
9609
9610 // And Memory with Immediate
9611 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9612 %{
9613 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9614 effect(KILL cr);
9615
9616 ins_cost(125);
9617 format %{ "andl $dst, $src\t# int" %}
9618 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9619 ins_encode(REX_mem(dst), OpcSE(src),
9620 RM_opc_mem(secondary, dst), Con8or32(src));
9621 ins_pipe(ialu_mem_imm);
9622 %}
9623
9624 // Or Instructions
9625 // Or Register with Register
9626 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9627 %{
9628 match(Set dst (OrI dst src));
9629 effect(KILL cr);
9630
9631 format %{ "orl $dst, $src\t# int" %}
9632 opcode(0x0B);
9633 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9634 ins_pipe(ialu_reg_reg);
9635 %}
9636
9637 // Or Register with Immediate
9638 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9639 %{
9640 match(Set dst (OrI dst src));
9641 effect(KILL cr);
9642
9643 format %{ "orl $dst, $src\t# int" %}
9644 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9645 ins_encode(OpcSErm(dst, src), Con8or32(src));
9646 ins_pipe(ialu_reg);
9647 %}
9648
9649 // Or Register with Memory
9650 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9651 %{
9652 match(Set dst (OrI dst (LoadI src)));
9653 effect(KILL cr);
9654
9655 ins_cost(125);
9656 format %{ "orl $dst, $src\t# int" %}
9657 opcode(0x0B);
9658 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9659 ins_pipe(ialu_reg_mem);
9660 %}
9661
9662 // Or Memory with Register
9663 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9664 %{
9665 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9666 effect(KILL cr);
9667
9668 ins_cost(150);
9669 format %{ "orl $dst, $src\t# int" %}
9670 opcode(0x09); /* Opcode 09 /r */
9671 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9672 ins_pipe(ialu_mem_reg);
9673 %}
9674
9675 // Or Memory with Immediate
9676 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9677 %{
9678 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9679 effect(KILL cr);
9680
9681 ins_cost(125);
9682 format %{ "orl $dst, $src\t# int" %}
9683 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9684 ins_encode(REX_mem(dst), OpcSE(src),
9685 RM_opc_mem(secondary, dst), Con8or32(src));
9686 ins_pipe(ialu_mem_imm);
9687 %}
9688
9689 // Xor Instructions
9690 // Xor Register with Register
9691 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9692 %{
9693 match(Set dst (XorI dst src));
9694 effect(KILL cr);
9695
9696 format %{ "xorl $dst, $src\t# int" %}
9697 opcode(0x33);
9698 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9699 ins_pipe(ialu_reg_reg);
9700 %}
9701
9702 // Xor Register with Immediate -1
9703 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9704 match(Set dst (XorI dst imm));
9705
9706 format %{ "not $dst" %}
9707 ins_encode %{
9708 __ notl($dst$$Register);
9709 %}
9710 ins_pipe(ialu_reg);
9711 %}
9712
9713 // Xor Register with Immediate
9714 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9715 %{
9716 match(Set dst (XorI dst src));
9717 effect(KILL cr);
9718
9719 format %{ "xorl $dst, $src\t# int" %}
9720 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9721 ins_encode(OpcSErm(dst, src), Con8or32(src));
9722 ins_pipe(ialu_reg);
9723 %}
9724
9725 // Xor Register with Memory
9726 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9727 %{
9728 match(Set dst (XorI dst (LoadI src)));
9729 effect(KILL cr);
9730
9731 ins_cost(125);
9732 format %{ "xorl $dst, $src\t# int" %}
9733 opcode(0x33);
9734 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9735 ins_pipe(ialu_reg_mem);
9736 %}
9737
9738 // Xor Memory with Register
9739 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9740 %{
9741 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9742 effect(KILL cr);
9743
9744 ins_cost(150);
9745 format %{ "xorl $dst, $src\t# int" %}
9746 opcode(0x31); /* Opcode 31 /r */
9747 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9748 ins_pipe(ialu_mem_reg);
9749 %}
9750
9751 // Xor Memory with Immediate
9752 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9753 %{
9754 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9755 effect(KILL cr);
9756
9757 ins_cost(125);
9758 format %{ "xorl $dst, $src\t# int" %}
9759 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9760 ins_encode(REX_mem(dst), OpcSE(src),
9761 RM_opc_mem(secondary, dst), Con8or32(src));
9762 ins_pipe(ialu_mem_imm);
9763 %}
9764
9765
9766 // Long Logical Instructions
9767
9768 // And Instructions
9769 // And Register with Register
9770 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9771 %{
9772 match(Set dst (AndL dst src));
9773 effect(KILL cr);
9774
9775 format %{ "andq $dst, $src\t# long" %}
9776 opcode(0x23);
9777 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9778 ins_pipe(ialu_reg_reg);
9779 %}
9780
9781 // And Register with Immediate 255
9782 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9783 %{
9784 match(Set dst (AndL dst src));
9785
9786 format %{ "movzbq $dst, $src\t# long & 0xFF" %}
9787 opcode(0x0F, 0xB6);
9788 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9789 ins_pipe(ialu_reg);
9790 %}
9791
9792 // And Register with Immediate 65535
9793 instruct andL_rReg_imm65535(rRegI dst, immL_65535 src)
9794 %{
9795 match(Set dst (AndL dst src));
9796
9797 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9798 opcode(0x0F, 0xB7);
9799 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9800 ins_pipe(ialu_reg);
9801 %}
9802
9803 // And Register with Immediate
9804 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9805 %{
9806 match(Set dst (AndL dst src));
9807 effect(KILL cr);
9808
9809 format %{ "andq $dst, $src\t# long" %}
9810 opcode(0x81, 0x04); /* Opcode 81 /4 */
9811 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9812 ins_pipe(ialu_reg);
9813 %}
9814
9815 // And Register with Memory
9816 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9817 %{
9818 match(Set dst (AndL dst (LoadL src)));
9819 effect(KILL cr);
9820
9821 ins_cost(125);
9822 format %{ "andq $dst, $src\t# long" %}
9823 opcode(0x23);
9824 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9825 ins_pipe(ialu_reg_mem);
9826 %}
9827
9828 // And Memory with Register
9829 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9830 %{
9831 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9832 effect(KILL cr);
9833
9834 ins_cost(150);
9835 format %{ "andq $dst, $src\t# long" %}
9836 opcode(0x21); /* Opcode 21 /r */
9837 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9838 ins_pipe(ialu_mem_reg);
9839 %}
9840
9841 // And Memory with Immediate
9842 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9843 %{
9844 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9845 effect(KILL cr);
9846
9847 ins_cost(125);
9848 format %{ "andq $dst, $src\t# long" %}
9849 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9850 ins_encode(REX_mem_wide(dst), OpcSE(src),
9851 RM_opc_mem(secondary, dst), Con8or32(src));
9852 ins_pipe(ialu_mem_imm);
9853 %}
9854
9855 // Or Instructions
9856 // Or Register with Register
9857 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9858 %{
9859 match(Set dst (OrL dst src));
9860 effect(KILL cr);
9861
9862 format %{ "orq $dst, $src\t# long" %}
9863 opcode(0x0B);
9864 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9865 ins_pipe(ialu_reg_reg);
9866 %}
9867
9868 // Use any_RegP to match R15 (TLS register) without spilling.
9869 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9870 match(Set dst (OrL dst (CastP2X src)));
9871 effect(KILL cr);
9872
9873 format %{ "orq $dst, $src\t# long" %}
9874 opcode(0x0B);
9875 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9876 ins_pipe(ialu_reg_reg);
9877 %}
9878
9879
9880 // Or Register with Immediate
9881 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9882 %{
9883 match(Set dst (OrL dst src));
9884 effect(KILL cr);
9885
9886 format %{ "orq $dst, $src\t# long" %}
9887 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9888 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9889 ins_pipe(ialu_reg);
9890 %}
9891
9892 // Or Register with Memory
9893 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9894 %{
9895 match(Set dst (OrL dst (LoadL src)));
9896 effect(KILL cr);
9897
9898 ins_cost(125);
9899 format %{ "orq $dst, $src\t# long" %}
9900 opcode(0x0B);
9901 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9902 ins_pipe(ialu_reg_mem);
9903 %}
9904
9905 // Or Memory with Register
9906 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9907 %{
9908 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9909 effect(KILL cr);
9910
9911 ins_cost(150);
9912 format %{ "orq $dst, $src\t# long" %}
9913 opcode(0x09); /* Opcode 09 /r */
9914 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9915 ins_pipe(ialu_mem_reg);
9916 %}
9917
9918 // Or Memory with Immediate
9919 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9920 %{
9921 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9922 effect(KILL cr);
9923
9924 ins_cost(125);
9925 format %{ "orq $dst, $src\t# long" %}
9926 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9927 ins_encode(REX_mem_wide(dst), OpcSE(src),
9928 RM_opc_mem(secondary, dst), Con8or32(src));
9929 ins_pipe(ialu_mem_imm);
9930 %}
9931
9932 // Xor Instructions
9933 // Xor Register with Register
9934 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9935 %{
9936 match(Set dst (XorL dst src));
9937 effect(KILL cr);
9938
9939 format %{ "xorq $dst, $src\t# long" %}
9940 opcode(0x33);
9941 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9942 ins_pipe(ialu_reg_reg);
9943 %}
9944
9945 // Xor Register with Immediate -1
9946 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9947 match(Set dst (XorL dst imm));
9948
9949 format %{ "notq $dst" %}
9950 ins_encode %{
9951 __ notq($dst$$Register);
9952 %}
9953 ins_pipe(ialu_reg);
9954 %}
9955
9956 // Xor Register with Immediate
9957 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9958 %{
9959 match(Set dst (XorL dst src));
9960 effect(KILL cr);
9961
9962 format %{ "xorq $dst, $src\t# long" %}
9963 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9964 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9965 ins_pipe(ialu_reg);
9966 %}
9967
9968 // Xor Register with Memory
9969 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9970 %{
9971 match(Set dst (XorL dst (LoadL src)));
9972 effect(KILL cr);
9973
9974 ins_cost(125);
9975 format %{ "xorq $dst, $src\t# long" %}
9976 opcode(0x33);
9977 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9978 ins_pipe(ialu_reg_mem);
9979 %}
9980
9981 // Xor Memory with Register
9982 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9983 %{
9984 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9985 effect(KILL cr);
9986
9987 ins_cost(150);
9988 format %{ "xorq $dst, $src\t# long" %}
9989 opcode(0x31); /* Opcode 31 /r */
9990 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9991 ins_pipe(ialu_mem_reg);
9992 %}
9993
9994 // Xor Memory with Immediate
9995 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9996 %{
9997 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9998 effect(KILL cr);
9999
10000 ins_cost(125);
10001 format %{ "xorq $dst, $src\t# long" %}
10002 opcode(0x81, 0x6); /* Opcode 81 /6 id */
10003 ins_encode(REX_mem_wide(dst), OpcSE(src),
10004 RM_opc_mem(secondary, dst), Con8or32(src));
10005 ins_pipe(ialu_mem_imm);
10006 %}
10007
10008 // Convert Int to Boolean
10009 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10010 %{
10011 match(Set dst (Conv2B src));
10012 effect(KILL cr);
10013
10014 format %{ "testl $src, $src\t# ci2b\n\t"
10015 "setnz $dst\n\t"
10016 "movzbl $dst, $dst" %}
10017 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
10018 setNZ_reg(dst),
10019 REX_reg_breg(dst, dst), // movzbl
10020 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10021 ins_pipe(pipe_slow); // XXX
10022 %}
10023
10024 // Convert Pointer to Boolean
10025 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10026 %{
10027 match(Set dst (Conv2B src));
10028 effect(KILL cr);
10029
10030 format %{ "testq $src, $src\t# cp2b\n\t"
10031 "setnz $dst\n\t"
10032 "movzbl $dst, $dst" %}
10033 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
10034 setNZ_reg(dst),
10035 REX_reg_breg(dst, dst), // movzbl
10036 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
10037 ins_pipe(pipe_slow); // XXX
10038 %}
10039
10040 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10041 %{
10042 match(Set dst (CmpLTMask p q));
10043 effect(KILL cr);
10044
10045 ins_cost(400); // XXX
10046 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10047 "setlt $dst\n\t"
10048 "movzbl $dst, $dst\n\t"
10049 "negl $dst" %}
10050 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
10051 setLT_reg(dst),
10052 REX_reg_breg(dst, dst), // movzbl
10053 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
10054 neg_reg(dst));
10055 ins_pipe(pipe_slow);
10056 %}
10057
10058 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
10059 %{
10060 match(Set dst (CmpLTMask dst zero));
10061 effect(KILL cr);
10062
10063 ins_cost(100); // XXX
10064 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10065 opcode(0xC1, 0x7); /* C1 /7 ib */
10066 ins_encode(reg_opc_imm(dst, 0x1F));
10067 ins_pipe(ialu_reg);
10068 %}
10069
10070
10071 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y,
10072 rRegI tmp,
10073 rFlagsReg cr)
10074 %{
10075 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10076 effect(TEMP tmp, KILL cr);
10077
10078 ins_cost(400); // XXX
10079 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t"
10080 "sbbl $tmp, $tmp\n\t"
10081 "andl $tmp, $y\n\t"
10082 "addl $p, $tmp" %}
10083 ins_encode(enc_cmpLTP(p, q, y, tmp));
10084 ins_pipe(pipe_cmplt);
10085 %}
10086
10087 /* If I enable this, I encourage spilling in the inner loop of compress.
10088 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr )
10089 %{
10090 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
10091 effect( TEMP tmp, KILL cr );
10092 ins_cost(400);
10093
10094 format %{ "SUB $p,$q\n\t"
10095 "SBB RCX,RCX\n\t"
10096 "AND RCX,$y\n\t"
10097 "ADD $p,RCX" %}
10098 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
10099 %}
10100 */
10101
10102 //---------- FP Instructions------------------------------------------------
10103
10104 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10105 %{
10106 match(Set cr (CmpF src1 src2));
10107
10108 ins_cost(145);
10109 format %{ "ucomiss $src1, $src2\n\t"
10110 "jnp,s exit\n\t"
10111 "pushfq\t# saw NaN, set CF\n\t"
10112 "andq [rsp], #0xffffff2b\n\t"
10113 "popfq\n"
10114 "exit: nop\t# avoid branch to branch" %}
10115 opcode(0x0F, 0x2E);
10116 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
10117 cmpfp_fixup);
10118 ins_pipe(pipe_slow);
10119 %}
10120
10121 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10122 match(Set cr (CmpF src1 src2));
10123
10124 ins_cost(145);
10125 format %{ "ucomiss $src1, $src2" %}
10126 ins_encode %{
10127 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10128 %}
10129 ins_pipe(pipe_slow);
10130 %}
10131
10132 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10133 %{
10134 match(Set cr (CmpF src1 (LoadF src2)));
10135
10136 ins_cost(145);
10137 format %{ "ucomiss $src1, $src2\n\t"
10138 "jnp,s exit\n\t"
10139 "pushfq\t# saw NaN, set CF\n\t"
10140 "andq [rsp], #0xffffff2b\n\t"
10141 "popfq\n"
10142 "exit: nop\t# avoid branch to branch" %}
10143 opcode(0x0F, 0x2E);
10144 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
10145 cmpfp_fixup);
10146 ins_pipe(pipe_slow);
10147 %}
10148
10149 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10150 match(Set cr (CmpF src1 (LoadF src2)));
10151
10152 ins_cost(100);
10153 format %{ "ucomiss $src1, $src2" %}
10154 opcode(0x0F, 0x2E);
10155 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2));
10156 ins_pipe(pipe_slow);
10157 %}
10158
10159 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2)
10160 %{
10161 match(Set cr (CmpF src1 src2));
10162
10163 ins_cost(145);
10164 format %{ "ucomiss $src1, $src2\n\t"
10165 "jnp,s exit\n\t"
10166 "pushfq\t# saw NaN, set CF\n\t"
10167 "andq [rsp], #0xffffff2b\n\t"
10168 "popfq\n"
10169 "exit: nop\t# avoid branch to branch" %}
10170 opcode(0x0F, 0x2E);
10171 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
10172 cmpfp_fixup);
10173 ins_pipe(pipe_slow);
10174 %}
10175
10176 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src1, immF src2) %{
10177 match(Set cr (CmpF src1 src2));
10178
10179 ins_cost(100);
10180 format %{ "ucomiss $src1, $src2" %}
10181 opcode(0x0F, 0x2E);
10182 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2));
10183 ins_pipe(pipe_slow);
10184 %}
10185
10186 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10187 %{
10188 match(Set cr (CmpD src1 src2));
10189
10190 ins_cost(145);
10191 format %{ "ucomisd $src1, $src2\n\t"
10192 "jnp,s exit\n\t"
10193 "pushfq\t# saw NaN, set CF\n\t"
10194 "andq [rsp], #0xffffff2b\n\t"
10195 "popfq\n"
10196 "exit: nop\t# avoid branch to branch" %}
10197 opcode(0x66, 0x0F, 0x2E);
10198 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
10199 cmpfp_fixup);
10200 ins_pipe(pipe_slow);
10201 %}
10202
10203 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10204 match(Set cr (CmpD src1 src2));
10205
10206 ins_cost(100);
10207 format %{ "ucomisd $src1, $src2 test" %}
10208 ins_encode %{
10209 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10210 %}
10211 ins_pipe(pipe_slow);
10212 %}
10213
10214 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10215 %{
10216 match(Set cr (CmpD src1 (LoadD src2)));
10217
10218 ins_cost(145);
10219 format %{ "ucomisd $src1, $src2\n\t"
10220 "jnp,s exit\n\t"
10221 "pushfq\t# saw NaN, set CF\n\t"
10222 "andq [rsp], #0xffffff2b\n\t"
10223 "popfq\n"
10224 "exit: nop\t# avoid branch to branch" %}
10225 opcode(0x66, 0x0F, 0x2E);
10226 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
10227 cmpfp_fixup);
10228 ins_pipe(pipe_slow);
10229 %}
10230
10231 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10232 match(Set cr (CmpD src1 (LoadD src2)));
10233
10234 ins_cost(100);
10235 format %{ "ucomisd $src1, $src2" %}
10236 opcode(0x66, 0x0F, 0x2E);
10237 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2));
10238 ins_pipe(pipe_slow);
10239 %}
10240
10241 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2)
10242 %{
10243 match(Set cr (CmpD src1 src2));
10244
10245 ins_cost(145);
10246 format %{ "ucomisd $src1, [$src2]\n\t"
10247 "jnp,s exit\n\t"
10248 "pushfq\t# saw NaN, set CF\n\t"
10249 "andq [rsp], #0xffffff2b\n\t"
10250 "popfq\n"
10251 "exit: nop\t# avoid branch to branch" %}
10252 opcode(0x66, 0x0F, 0x2E);
10253 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
10254 cmpfp_fixup);
10255 ins_pipe(pipe_slow);
10256 %}
10257
10258 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src1, immD src2) %{
10259 match(Set cr (CmpD src1 src2));
10260
10261 ins_cost(100);
10262 format %{ "ucomisd $src1, [$src2]" %}
10263 opcode(0x66, 0x0F, 0x2E);
10264 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2));
10265 ins_pipe(pipe_slow);
10266 %}
10267
10268 // Compare into -1,0,1
10269 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10270 %{
10271 match(Set dst (CmpF3 src1 src2));
10272 effect(KILL cr);
10273
10274 ins_cost(275);
10275 format %{ "ucomiss $src1, $src2\n\t"
10276 "movl $dst, #-1\n\t"
10277 "jp,s done\n\t"
10278 "jb,s done\n\t"
10279 "setne $dst\n\t"
10280 "movzbl $dst, $dst\n"
10281 "done:" %}
10282
10283 opcode(0x0F, 0x2E);
10284 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2),
10285 cmpfp3(dst));
10286 ins_pipe(pipe_slow);
10287 %}
10288
10289 // Compare into -1,0,1
10290 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10291 %{
10292 match(Set dst (CmpF3 src1 (LoadF src2)));
10293 effect(KILL cr);
10294
10295 ins_cost(275);
10296 format %{ "ucomiss $src1, $src2\n\t"
10297 "movl $dst, #-1\n\t"
10298 "jp,s done\n\t"
10299 "jb,s done\n\t"
10300 "setne $dst\n\t"
10301 "movzbl $dst, $dst\n"
10302 "done:" %}
10303
10304 opcode(0x0F, 0x2E);
10305 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2),
10306 cmpfp3(dst));
10307 ins_pipe(pipe_slow);
10308 %}
10309
10310 // Compare into -1,0,1
10311 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr)
10312 %{
10313 match(Set dst (CmpF3 src1 src2));
10314 effect(KILL cr);
10315
10316 ins_cost(275);
10317 format %{ "ucomiss $src1, [$src2]\n\t"
10318 "movl $dst, #-1\n\t"
10319 "jp,s done\n\t"
10320 "jb,s done\n\t"
10321 "setne $dst\n\t"
10322 "movzbl $dst, $dst\n"
10323 "done:" %}
10324
10325 opcode(0x0F, 0x2E);
10326 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2),
10327 cmpfp3(dst));
10328 ins_pipe(pipe_slow);
10329 %}
10330
10331 // Compare into -1,0,1
10332 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10333 %{
10334 match(Set dst (CmpD3 src1 src2));
10335 effect(KILL cr);
10336
10337 ins_cost(275);
10338 format %{ "ucomisd $src1, $src2\n\t"
10339 "movl $dst, #-1\n\t"
10340 "jp,s done\n\t"
10341 "jb,s done\n\t"
10342 "setne $dst\n\t"
10343 "movzbl $dst, $dst\n"
10344 "done:" %}
10345
10346 opcode(0x66, 0x0F, 0x2E);
10347 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2),
10348 cmpfp3(dst));
10349 ins_pipe(pipe_slow);
10350 %}
10351
10352 // Compare into -1,0,1
10353 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10354 %{
10355 match(Set dst (CmpD3 src1 (LoadD src2)));
10356 effect(KILL cr);
10357
10358 ins_cost(275);
10359 format %{ "ucomisd $src1, $src2\n\t"
10360 "movl $dst, #-1\n\t"
10361 "jp,s done\n\t"
10362 "jb,s done\n\t"
10363 "setne $dst\n\t"
10364 "movzbl $dst, $dst\n"
10365 "done:" %}
10366
10367 opcode(0x66, 0x0F, 0x2E);
10368 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2),
10369 cmpfp3(dst));
10370 ins_pipe(pipe_slow);
10371 %}
10372
10373 // Compare into -1,0,1
10374 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr)
10375 %{
10376 match(Set dst (CmpD3 src1 src2));
10377 effect(KILL cr);
10378
10379 ins_cost(275);
10380 format %{ "ucomisd $src1, [$src2]\n\t"
10381 "movl $dst, #-1\n\t"
10382 "jp,s done\n\t"
10383 "jb,s done\n\t"
10384 "setne $dst\n\t"
10385 "movzbl $dst, $dst\n"
10386 "done:" %}
10387
10388 opcode(0x66, 0x0F, 0x2E);
10389 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2),
10390 cmpfp3(dst));
10391 ins_pipe(pipe_slow);
10392 %}
10393
10394 instruct addF_reg(regF dst, regF src)
10395 %{
10396 match(Set dst (AddF dst src));
10397
10398 format %{ "addss $dst, $src" %}
10399 ins_cost(150); // XXX
10400 opcode(0xF3, 0x0F, 0x58);
10401 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10402 ins_pipe(pipe_slow);
10403 %}
10404
10405 instruct addF_mem(regF dst, memory src)
10406 %{
10407 match(Set dst (AddF dst (LoadF src)));
10408
10409 format %{ "addss $dst, $src" %}
10410 ins_cost(150); // XXX
10411 opcode(0xF3, 0x0F, 0x58);
10412 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10413 ins_pipe(pipe_slow);
10414 %}
10415
10416 instruct addF_imm(regF dst, immF src)
10417 %{
10418 match(Set dst (AddF dst src));
10419
10420 format %{ "addss $dst, [$src]" %}
10421 ins_cost(150); // XXX
10422 opcode(0xF3, 0x0F, 0x58);
10423 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10424 ins_pipe(pipe_slow);
10425 %}
10426
10427 instruct addD_reg(regD dst, regD src)
10428 %{
10429 match(Set dst (AddD dst src));
10430
10431 format %{ "addsd $dst, $src" %}
10432 ins_cost(150); // XXX
10433 opcode(0xF2, 0x0F, 0x58);
10434 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10435 ins_pipe(pipe_slow);
10436 %}
10437
10438 instruct addD_mem(regD dst, memory src)
10439 %{
10440 match(Set dst (AddD dst (LoadD src)));
10441
10442 format %{ "addsd $dst, $src" %}
10443 ins_cost(150); // XXX
10444 opcode(0xF2, 0x0F, 0x58);
10445 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10446 ins_pipe(pipe_slow);
10447 %}
10448
10449 instruct addD_imm(regD dst, immD src)
10450 %{
10451 match(Set dst (AddD dst src));
10452
10453 format %{ "addsd $dst, [$src]" %}
10454 ins_cost(150); // XXX
10455 opcode(0xF2, 0x0F, 0x58);
10456 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10457 ins_pipe(pipe_slow);
10458 %}
10459
10460 instruct subF_reg(regF dst, regF src)
10461 %{
10462 match(Set dst (SubF dst src));
10463
10464 format %{ "subss $dst, $src" %}
10465 ins_cost(150); // XXX
10466 opcode(0xF3, 0x0F, 0x5C);
10467 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10468 ins_pipe(pipe_slow);
10469 %}
10470
10471 instruct subF_mem(regF dst, memory src)
10472 %{
10473 match(Set dst (SubF dst (LoadF src)));
10474
10475 format %{ "subss $dst, $src" %}
10476 ins_cost(150); // XXX
10477 opcode(0xF3, 0x0F, 0x5C);
10478 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10479 ins_pipe(pipe_slow);
10480 %}
10481
10482 instruct subF_imm(regF dst, immF src)
10483 %{
10484 match(Set dst (SubF dst src));
10485
10486 format %{ "subss $dst, [$src]" %}
10487 ins_cost(150); // XXX
10488 opcode(0xF3, 0x0F, 0x5C);
10489 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10490 ins_pipe(pipe_slow);
10491 %}
10492
10493 instruct subD_reg(regD dst, regD src)
10494 %{
10495 match(Set dst (SubD dst src));
10496
10497 format %{ "subsd $dst, $src" %}
10498 ins_cost(150); // XXX
10499 opcode(0xF2, 0x0F, 0x5C);
10500 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10501 ins_pipe(pipe_slow);
10502 %}
10503
10504 instruct subD_mem(regD dst, memory src)
10505 %{
10506 match(Set dst (SubD dst (LoadD src)));
10507
10508 format %{ "subsd $dst, $src" %}
10509 ins_cost(150); // XXX
10510 opcode(0xF2, 0x0F, 0x5C);
10511 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10512 ins_pipe(pipe_slow);
10513 %}
10514
10515 instruct subD_imm(regD dst, immD src)
10516 %{
10517 match(Set dst (SubD dst src));
10518
10519 format %{ "subsd $dst, [$src]" %}
10520 ins_cost(150); // XXX
10521 opcode(0xF2, 0x0F, 0x5C);
10522 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10523 ins_pipe(pipe_slow);
10524 %}
10525
10526 instruct mulF_reg(regF dst, regF src)
10527 %{
10528 match(Set dst (MulF dst src));
10529
10530 format %{ "mulss $dst, $src" %}
10531 ins_cost(150); // XXX
10532 opcode(0xF3, 0x0F, 0x59);
10533 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10534 ins_pipe(pipe_slow);
10535 %}
10536
10537 instruct mulF_mem(regF dst, memory src)
10538 %{
10539 match(Set dst (MulF dst (LoadF src)));
10540
10541 format %{ "mulss $dst, $src" %}
10542 ins_cost(150); // XXX
10543 opcode(0xF3, 0x0F, 0x59);
10544 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10545 ins_pipe(pipe_slow);
10546 %}
10547
10548 instruct mulF_imm(regF dst, immF src)
10549 %{
10550 match(Set dst (MulF dst src));
10551
10552 format %{ "mulss $dst, [$src]" %}
10553 ins_cost(150); // XXX
10554 opcode(0xF3, 0x0F, 0x59);
10555 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10556 ins_pipe(pipe_slow);
10557 %}
10558
10559 instruct mulD_reg(regD dst, regD src)
10560 %{
10561 match(Set dst (MulD dst src));
10562
10563 format %{ "mulsd $dst, $src" %}
10564 ins_cost(150); // XXX
10565 opcode(0xF2, 0x0F, 0x59);
10566 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10567 ins_pipe(pipe_slow);
10568 %}
10569
10570 instruct mulD_mem(regD dst, memory src)
10571 %{
10572 match(Set dst (MulD dst (LoadD src)));
10573
10574 format %{ "mulsd $dst, $src" %}
10575 ins_cost(150); // XXX
10576 opcode(0xF2, 0x0F, 0x59);
10577 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10578 ins_pipe(pipe_slow);
10579 %}
10580
10581 instruct mulD_imm(regD dst, immD src)
10582 %{
10583 match(Set dst (MulD dst src));
10584
10585 format %{ "mulsd $dst, [$src]" %}
10586 ins_cost(150); // XXX
10587 opcode(0xF2, 0x0F, 0x59);
10588 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10589 ins_pipe(pipe_slow);
10590 %}
10591
10592 instruct divF_reg(regF dst, regF src)
10593 %{
10594 match(Set dst (DivF dst src));
10595
10596 format %{ "divss $dst, $src" %}
10597 ins_cost(150); // XXX
10598 opcode(0xF3, 0x0F, 0x5E);
10599 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10600 ins_pipe(pipe_slow);
10601 %}
10602
10603 instruct divF_mem(regF dst, memory src)
10604 %{
10605 match(Set dst (DivF dst (LoadF src)));
10606
10607 format %{ "divss $dst, $src" %}
10608 ins_cost(150); // XXX
10609 opcode(0xF3, 0x0F, 0x5E);
10610 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10611 ins_pipe(pipe_slow);
10612 %}
10613
10614 instruct divF_imm(regF dst, immF src)
10615 %{
10616 match(Set dst (DivF dst src));
10617
10618 format %{ "divss $dst, [$src]" %}
10619 ins_cost(150); // XXX
10620 opcode(0xF3, 0x0F, 0x5E);
10621 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10622 ins_pipe(pipe_slow);
10623 %}
10624
10625 instruct divD_reg(regD dst, regD src)
10626 %{
10627 match(Set dst (DivD dst src));
10628
10629 format %{ "divsd $dst, $src" %}
10630 ins_cost(150); // XXX
10631 opcode(0xF2, 0x0F, 0x5E);
10632 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10633 ins_pipe(pipe_slow);
10634 %}
10635
10636 instruct divD_mem(regD dst, memory src)
10637 %{
10638 match(Set dst (DivD dst (LoadD src)));
10639
10640 format %{ "divsd $dst, $src" %}
10641 ins_cost(150); // XXX
10642 opcode(0xF2, 0x0F, 0x5E);
10643 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10644 ins_pipe(pipe_slow);
10645 %}
10646
10647 instruct divD_imm(regD dst, immD src)
10648 %{
10649 match(Set dst (DivD dst src));
10650
10651 format %{ "divsd $dst, [$src]" %}
10652 ins_cost(150); // XXX
10653 opcode(0xF2, 0x0F, 0x5E);
10654 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10655 ins_pipe(pipe_slow);
10656 %}
10657
10658 instruct sqrtF_reg(regF dst, regF src)
10659 %{
10660 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10661
10662 format %{ "sqrtss $dst, $src" %}
10663 ins_cost(150); // XXX
10664 opcode(0xF3, 0x0F, 0x51);
10665 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10666 ins_pipe(pipe_slow);
10667 %}
10668
10669 instruct sqrtF_mem(regF dst, memory src)
10670 %{
10671 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
10672
10673 format %{ "sqrtss $dst, $src" %}
10674 ins_cost(150); // XXX
10675 opcode(0xF3, 0x0F, 0x51);
10676 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10677 ins_pipe(pipe_slow);
10678 %}
10679
10680 instruct sqrtF_imm(regF dst, immF src)
10681 %{
10682 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10683
10684 format %{ "sqrtss $dst, [$src]" %}
10685 ins_cost(150); // XXX
10686 opcode(0xF3, 0x0F, 0x51);
10687 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src));
10688 ins_pipe(pipe_slow);
10689 %}
10690
10691 instruct sqrtD_reg(regD dst, regD src)
10692 %{
10693 match(Set dst (SqrtD src));
10694
10695 format %{ "sqrtsd $dst, $src" %}
10696 ins_cost(150); // XXX
10697 opcode(0xF2, 0x0F, 0x51);
10698 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10699 ins_pipe(pipe_slow);
10700 %}
10701
10702 instruct sqrtD_mem(regD dst, memory src)
10703 %{
10704 match(Set dst (SqrtD (LoadD src)));
10705
10706 format %{ "sqrtsd $dst, $src" %}
10707 ins_cost(150); // XXX
10708 opcode(0xF2, 0x0F, 0x51);
10709 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10710 ins_pipe(pipe_slow);
10711 %}
10712
10713 instruct sqrtD_imm(regD dst, immD src)
10714 %{
10715 match(Set dst (SqrtD src));
10716
10717 format %{ "sqrtsd $dst, [$src]" %}
10718 ins_cost(150); // XXX
10719 opcode(0xF2, 0x0F, 0x51);
10720 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src));
10721 ins_pipe(pipe_slow);
10722 %}
10723
10724 instruct absF_reg(regF dst)
10725 %{
10726 match(Set dst (AbsF dst));
10727
10728 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
10729 ins_encode(absF_encoding(dst));
10730 ins_pipe(pipe_slow);
10731 %}
10732
10733 instruct absD_reg(regD dst)
10734 %{
10735 match(Set dst (AbsD dst));
10736
10737 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
10738 "# abs double by sign masking" %}
10739 ins_encode(absD_encoding(dst));
10740 ins_pipe(pipe_slow);
10741 %}
10742
10743 instruct negF_reg(regF dst)
10744 %{
10745 match(Set dst (NegF dst));
10746
10747 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
10748 ins_encode(negF_encoding(dst));
10749 ins_pipe(pipe_slow);
10750 %}
10751
10752 instruct negD_reg(regD dst)
10753 %{
10754 match(Set dst (NegD dst));
10755
10756 format %{ "xorpd $dst, [0x8000000000000000]\t"
10757 "# neg double by sign flipping" %}
10758 ins_encode(negD_encoding(dst));
10759 ins_pipe(pipe_slow);
10760 %}
10761
10762 // -----------Trig and Trancendental Instructions------------------------------
10763 instruct cosD_reg(regD dst) %{
10764 match(Set dst (CosD dst));
10765
10766 format %{ "dcos $dst\n\t" %}
10767 opcode(0xD9, 0xFF);
10768 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10769 ins_pipe( pipe_slow );
10770 %}
10771
10772 instruct sinD_reg(regD dst) %{
10773 match(Set dst (SinD dst));
10774
10775 format %{ "dsin $dst\n\t" %}
10776 opcode(0xD9, 0xFE);
10777 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10778 ins_pipe( pipe_slow );
10779 %}
10780
10781 instruct tanD_reg(regD dst) %{
10782 match(Set dst (TanD dst));
10783
10784 format %{ "dtan $dst\n\t" %}
10785 ins_encode( Push_SrcXD(dst),
10786 Opcode(0xD9), Opcode(0xF2), //fptan
10787 Opcode(0xDD), Opcode(0xD8), //fstp st
10788 Push_ResultXD(dst) );
10789 ins_pipe( pipe_slow );
10790 %}
10791
10792 instruct log10D_reg(regD dst) %{
10793 // The source and result Double operands in XMM registers
10794 match(Set dst (Log10D dst));
10795 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10796 // fyl2x ; compute log_10(2) * log_2(x)
10797 format %{ "fldlg2\t\t\t#Log10\n\t"
10798 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
10799 %}
10800 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
10801 Push_SrcXD(dst),
10802 Opcode(0xD9), Opcode(0xF1), // fyl2x
10803 Push_ResultXD(dst));
10804
10805 ins_pipe( pipe_slow );
10806 %}
10807
10808 instruct logD_reg(regD dst) %{
10809 // The source and result Double operands in XMM registers
10810 match(Set dst (LogD dst));
10811 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10812 // fyl2x ; compute log_e(2) * log_2(x)
10813 format %{ "fldln2\t\t\t#Log_e\n\t"
10814 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
10815 %}
10816 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10817 Push_SrcXD(dst),
10818 Opcode(0xD9), Opcode(0xF1), // fyl2x
10819 Push_ResultXD(dst));
10820 ins_pipe( pipe_slow );
10821 %}
10822
10823
10824
10825 //----------Arithmetic Conversion Instructions---------------------------------
10826
10827 instruct roundFloat_nop(regF dst)
10828 %{
10829 match(Set dst (RoundFloat dst));
10830
10831 ins_cost(0);
10832 ins_encode();
10833 ins_pipe(empty);
10834 %}
10835
10836 instruct roundDouble_nop(regD dst)
10837 %{
10838 match(Set dst (RoundDouble dst));
10839
10840 ins_cost(0);
10841 ins_encode();
10842 ins_pipe(empty);
10843 %}
10844
10845 instruct convF2D_reg_reg(regD dst, regF src)
10846 %{
10847 match(Set dst (ConvF2D src));
10848
10849 format %{ "cvtss2sd $dst, $src" %}
10850 opcode(0xF3, 0x0F, 0x5A);
10851 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10852 ins_pipe(pipe_slow); // XXX
10853 %}
10854
10855 instruct convF2D_reg_mem(regD dst, memory src)
10856 %{
10857 match(Set dst (ConvF2D (LoadF src)));
10858
10859 format %{ "cvtss2sd $dst, $src" %}
10860 opcode(0xF3, 0x0F, 0x5A);
10861 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10862 ins_pipe(pipe_slow); // XXX
10863 %}
10864
10865 instruct convD2F_reg_reg(regF dst, regD src)
10866 %{
10867 match(Set dst (ConvD2F src));
10868
10869 format %{ "cvtsd2ss $dst, $src" %}
10870 opcode(0xF2, 0x0F, 0x5A);
10871 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10872 ins_pipe(pipe_slow); // XXX
10873 %}
10874
10875 instruct convD2F_reg_mem(regF dst, memory src)
10876 %{
10877 match(Set dst (ConvD2F (LoadD src)));
10878
10879 format %{ "cvtsd2ss $dst, $src" %}
10880 opcode(0xF2, 0x0F, 0x5A);
10881 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10882 ins_pipe(pipe_slow); // XXX
10883 %}
10884
10885 // XXX do mem variants
10886 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10887 %{
10888 match(Set dst (ConvF2I src));
10889 effect(KILL cr);
10890
10891 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10892 "cmpl $dst, #0x80000000\n\t"
10893 "jne,s done\n\t"
10894 "subq rsp, #8\n\t"
10895 "movss [rsp], $src\n\t"
10896 "call f2i_fixup\n\t"
10897 "popq $dst\n"
10898 "done: "%}
10899 opcode(0xF3, 0x0F, 0x2C);
10900 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10901 f2i_fixup(dst, src));
10902 ins_pipe(pipe_slow);
10903 %}
10904
10905 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10906 %{
10907 match(Set dst (ConvF2L src));
10908 effect(KILL cr);
10909
10910 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10911 "cmpq $dst, [0x8000000000000000]\n\t"
10912 "jne,s done\n\t"
10913 "subq rsp, #8\n\t"
10914 "movss [rsp], $src\n\t"
10915 "call f2l_fixup\n\t"
10916 "popq $dst\n"
10917 "done: "%}
10918 opcode(0xF3, 0x0F, 0x2C);
10919 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
10920 f2l_fixup(dst, src));
10921 ins_pipe(pipe_slow);
10922 %}
10923
10924 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10925 %{
10926 match(Set dst (ConvD2I src));
10927 effect(KILL cr);
10928
10929 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10930 "cmpl $dst, #0x80000000\n\t"
10931 "jne,s done\n\t"
10932 "subq rsp, #8\n\t"
10933 "movsd [rsp], $src\n\t"
10934 "call d2i_fixup\n\t"
10935 "popq $dst\n"
10936 "done: "%}
10937 opcode(0xF2, 0x0F, 0x2C);
10938 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src),
10939 d2i_fixup(dst, src));
10940 ins_pipe(pipe_slow);
10941 %}
10942
10943 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10944 %{
10945 match(Set dst (ConvD2L src));
10946 effect(KILL cr);
10947
10948 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10949 "cmpq $dst, [0x8000000000000000]\n\t"
10950 "jne,s done\n\t"
10951 "subq rsp, #8\n\t"
10952 "movsd [rsp], $src\n\t"
10953 "call d2l_fixup\n\t"
10954 "popq $dst\n"
10955 "done: "%}
10956 opcode(0xF2, 0x0F, 0x2C);
10957 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src),
10958 d2l_fixup(dst, src));
10959 ins_pipe(pipe_slow);
10960 %}
10961
10962 instruct convI2F_reg_reg(regF dst, rRegI src)
10963 %{
10964 predicate(!UseXmmI2F);
10965 match(Set dst (ConvI2F src));
10966
10967 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10968 opcode(0xF3, 0x0F, 0x2A);
10969 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10970 ins_pipe(pipe_slow); // XXX
10971 %}
10972
10973 instruct convI2F_reg_mem(regF dst, memory src)
10974 %{
10975 match(Set dst (ConvI2F (LoadI src)));
10976
10977 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10978 opcode(0xF3, 0x0F, 0x2A);
10979 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
10980 ins_pipe(pipe_slow); // XXX
10981 %}
10982
10983 instruct convI2D_reg_reg(regD dst, rRegI src)
10984 %{
10985 predicate(!UseXmmI2D);
10986 match(Set dst (ConvI2D src));
10987
10988 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10989 opcode(0xF2, 0x0F, 0x2A);
10990 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src));
10991 ins_pipe(pipe_slow); // XXX
10992 %}
10993
10994 instruct convI2D_reg_mem(regD dst, memory src)
10995 %{
10996 match(Set dst (ConvI2D (LoadI src)));
10997
10998 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10999 opcode(0xF2, 0x0F, 0x2A);
11000 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11001 ins_pipe(pipe_slow); // XXX
11002 %}
11003
11004 instruct convXI2F_reg(regF dst, rRegI src)
11005 %{
11006 predicate(UseXmmI2F);
11007 match(Set dst (ConvI2F src));
11008
11009 format %{ "movdl $dst, $src\n\t"
11010 "cvtdq2psl $dst, $dst\t# i2f" %}
11011 ins_encode %{
11012 __ movdl($dst$$XMMRegister, $src$$Register);
11013 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11014 %}
11015 ins_pipe(pipe_slow); // XXX
11016 %}
11017
11018 instruct convXI2D_reg(regD dst, rRegI src)
11019 %{
11020 predicate(UseXmmI2D);
11021 match(Set dst (ConvI2D src));
11022
11023 format %{ "movdl $dst, $src\n\t"
11024 "cvtdq2pdl $dst, $dst\t# i2d" %}
11025 ins_encode %{
11026 __ movdl($dst$$XMMRegister, $src$$Register);
11027 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11028 %}
11029 ins_pipe(pipe_slow); // XXX
11030 %}
11031
11032 instruct convL2F_reg_reg(regF dst, rRegL src)
11033 %{
11034 match(Set dst (ConvL2F src));
11035
11036 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11037 opcode(0xF3, 0x0F, 0x2A);
11038 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
11039 ins_pipe(pipe_slow); // XXX
11040 %}
11041
11042 instruct convL2F_reg_mem(regF dst, memory src)
11043 %{
11044 match(Set dst (ConvL2F (LoadL src)));
11045
11046 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11047 opcode(0xF3, 0x0F, 0x2A);
11048 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
11049 ins_pipe(pipe_slow); // XXX
11050 %}
11051
11052 instruct convL2D_reg_reg(regD dst, rRegL src)
11053 %{
11054 match(Set dst (ConvL2D src));
11055
11056 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11057 opcode(0xF2, 0x0F, 0x2A);
11058 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src));
11059 ins_pipe(pipe_slow); // XXX
11060 %}
11061
11062 instruct convL2D_reg_mem(regD dst, memory src)
11063 %{
11064 match(Set dst (ConvL2D (LoadL src)));
11065
11066 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11067 opcode(0xF2, 0x0F, 0x2A);
11068 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src));
11069 ins_pipe(pipe_slow); // XXX
11070 %}
11071
11072 instruct convI2L_reg_reg(rRegL dst, rRegI src)
11073 %{
11074 match(Set dst (ConvI2L src));
11075
11076 ins_cost(125);
11077 format %{ "movslq $dst, $src\t# i2l" %}
11078 opcode(0x63); // needs REX.W
11079 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
11080 ins_pipe(ialu_reg_reg);
11081 %}
11082
11083 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
11084 // %{
11085 // match(Set dst (ConvI2L src));
11086 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
11087 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
11088 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
11089 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
11090 // ((const TypeNode*) n)->type()->is_long()->_lo ==
11091 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
11092
11093 // format %{ "movl $dst, $src\t# unsigned i2l" %}
11094 // ins_encode(enc_copy(dst, src));
11095 // // opcode(0x63); // needs REX.W
11096 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
11097 // ins_pipe(ialu_reg_reg);
11098 // %}
11099
11100 instruct convI2L_reg_mem(rRegL dst, memory src)
11101 %{
11102 match(Set dst (ConvI2L (LoadI src)));
11103
11104 format %{ "movslq $dst, $src\t# i2l" %}
11105 opcode(0x63); // needs REX.W
11106 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst,src));
11107 ins_pipe(ialu_reg_mem);
11108 %}
11109
11110 // Zero-extend convert int to long
11111 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
11112 %{
11113 match(Set dst (AndL (ConvI2L src) mask));
11114
11115 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11116 ins_encode(enc_copy(dst, src));
11117 ins_pipe(ialu_reg_reg);
11118 %}
11119
11120 // Zero-extend convert int to long
11121 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
11122 %{
11123 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
11124
11125 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
11126 opcode(0x8B);
11127 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
11128 ins_pipe(ialu_reg_mem);
11129 %}
11130
11131 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
11132 %{
11133 match(Set dst (AndL src mask));
11134
11135 format %{ "movl $dst, $src\t# zero-extend long" %}
11136 ins_encode(enc_copy_always(dst, src));
11137 ins_pipe(ialu_reg_reg);
11138 %}
11139
11140 instruct convL2I_reg_reg(rRegI dst, rRegL src)
11141 %{
11142 match(Set dst (ConvL2I src));
11143
11144 format %{ "movl $dst, $src\t# l2i" %}
11145 ins_encode(enc_copy_always(dst, src));
11146 ins_pipe(ialu_reg_reg);
11147 %}
11148
11149
11150 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11151 match(Set dst (MoveF2I src));
11152 effect(DEF dst, USE src);
11153
11154 ins_cost(125);
11155 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
11156 opcode(0x8B);
11157 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
11158 ins_pipe(ialu_reg_mem);
11159 %}
11160
11161 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11162 match(Set dst (MoveI2F src));
11163 effect(DEF dst, USE src);
11164
11165 ins_cost(125);
11166 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
11167 opcode(0xF3, 0x0F, 0x10);
11168 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11169 ins_pipe(pipe_slow);
11170 %}
11171
11172 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
11173 match(Set dst (MoveD2L src));
11174 effect(DEF dst, USE src);
11175
11176 ins_cost(125);
11177 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
11178 opcode(0x8B);
11179 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
11180 ins_pipe(ialu_reg_mem);
11181 %}
11182
11183 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
11184 predicate(!UseXmmLoadAndClearUpper);
11185 match(Set dst (MoveL2D src));
11186 effect(DEF dst, USE src);
11187
11188 ins_cost(125);
11189 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
11190 opcode(0x66, 0x0F, 0x12);
11191 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11192 ins_pipe(pipe_slow);
11193 %}
11194
11195 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11196 predicate(UseXmmLoadAndClearUpper);
11197 match(Set dst (MoveL2D src));
11198 effect(DEF dst, USE src);
11199
11200 ins_cost(125);
11201 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
11202 opcode(0xF2, 0x0F, 0x10);
11203 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src));
11204 ins_pipe(pipe_slow);
11205 %}
11206
11207
11208 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11209 match(Set dst (MoveF2I src));
11210 effect(DEF dst, USE src);
11211
11212 ins_cost(95); // XXX
11213 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
11214 opcode(0xF3, 0x0F, 0x11);
11215 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
11216 ins_pipe(pipe_slow);
11217 %}
11218
11219 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11220 match(Set dst (MoveI2F src));
11221 effect(DEF dst, USE src);
11222
11223 ins_cost(100);
11224 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
11225 opcode(0x89);
11226 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
11227 ins_pipe( ialu_mem_reg );
11228 %}
11229
11230 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11231 match(Set dst (MoveD2L src));
11232 effect(DEF dst, USE src);
11233
11234 ins_cost(95); // XXX
11235 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11236 opcode(0xF2, 0x0F, 0x11);
11237 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst));
11238 ins_pipe(pipe_slow);
11239 %}
11240
11241 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11242 match(Set dst (MoveL2D src));
11243 effect(DEF dst, USE src);
11244
11245 ins_cost(100);
11246 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11247 opcode(0x89);
11248 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
11249 ins_pipe(ialu_mem_reg);
11250 %}
11251
11252 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11253 match(Set dst (MoveF2I src));
11254 effect(DEF dst, USE src);
11255 ins_cost(85);
11256 format %{ "movd $dst,$src\t# MoveF2I" %}
11257 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %}
11258 ins_pipe( pipe_slow );
11259 %}
11260
11261 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11262 match(Set dst (MoveD2L src));
11263 effect(DEF dst, USE src);
11264 ins_cost(85);
11265 format %{ "movd $dst,$src\t# MoveD2L" %}
11266 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %}
11267 ins_pipe( pipe_slow );
11268 %}
11269
11270 // The next instructions have long latency and use Int unit. Set high cost.
11271 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11272 match(Set dst (MoveI2F src));
11273 effect(DEF dst, USE src);
11274 ins_cost(300);
11275 format %{ "movd $dst,$src\t# MoveI2F" %}
11276 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %}
11277 ins_pipe( pipe_slow );
11278 %}
11279
11280 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11281 match(Set dst (MoveL2D src));
11282 effect(DEF dst, USE src);
11283 ins_cost(300);
11284 format %{ "movd $dst,$src\t# MoveL2D" %}
11285 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %}
11286 ins_pipe( pipe_slow );
11287 %}
11288
11289 // Replicate scalar to packed byte (1 byte) values in xmm
11290 instruct Repl8B_reg(regD dst, regD src) %{
11291 match(Set dst (Replicate8B src));
11292 format %{ "MOVDQA $dst,$src\n\t"
11293 "PUNPCKLBW $dst,$dst\n\t"
11294 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11295 ins_encode( pshufd_8x8(dst, src));
11296 ins_pipe( pipe_slow );
11297 %}
11298
11299 // Replicate scalar to packed byte (1 byte) values in xmm
11300 instruct Repl8B_rRegI(regD dst, rRegI src) %{
11301 match(Set dst (Replicate8B src));
11302 format %{ "MOVD $dst,$src\n\t"
11303 "PUNPCKLBW $dst,$dst\n\t"
11304 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
11305 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
11306 ins_pipe( pipe_slow );
11307 %}
11308
11309 // Replicate scalar zero to packed byte (1 byte) values in xmm
11310 instruct Repl8B_immI0(regD dst, immI0 zero) %{
11311 match(Set dst (Replicate8B zero));
11312 format %{ "PXOR $dst,$dst\t! replicate8B" %}
11313 ins_encode( pxor(dst, dst));
11314 ins_pipe( fpu_reg_reg );
11315 %}
11316
11317 // Replicate scalar to packed shore (2 byte) values in xmm
11318 instruct Repl4S_reg(regD dst, regD src) %{
11319 match(Set dst (Replicate4S src));
11320 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
11321 ins_encode( pshufd_4x16(dst, src));
11322 ins_pipe( fpu_reg_reg );
11323 %}
11324
11325 // Replicate scalar to packed shore (2 byte) values in xmm
11326 instruct Repl4S_rRegI(regD dst, rRegI src) %{
11327 match(Set dst (Replicate4S src));
11328 format %{ "MOVD $dst,$src\n\t"
11329 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
11330 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11331 ins_pipe( fpu_reg_reg );
11332 %}
11333
11334 // Replicate scalar zero to packed short (2 byte) values in xmm
11335 instruct Repl4S_immI0(regD dst, immI0 zero) %{
11336 match(Set dst (Replicate4S zero));
11337 format %{ "PXOR $dst,$dst\t! replicate4S" %}
11338 ins_encode( pxor(dst, dst));
11339 ins_pipe( fpu_reg_reg );
11340 %}
11341
11342 // Replicate scalar to packed char (2 byte) values in xmm
11343 instruct Repl4C_reg(regD dst, regD src) %{
11344 match(Set dst (Replicate4C src));
11345 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
11346 ins_encode( pshufd_4x16(dst, src));
11347 ins_pipe( fpu_reg_reg );
11348 %}
11349
11350 // Replicate scalar to packed char (2 byte) values in xmm
11351 instruct Repl4C_rRegI(regD dst, rRegI src) %{
11352 match(Set dst (Replicate4C src));
11353 format %{ "MOVD $dst,$src\n\t"
11354 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
11355 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
11356 ins_pipe( fpu_reg_reg );
11357 %}
11358
11359 // Replicate scalar zero to packed char (2 byte) values in xmm
11360 instruct Repl4C_immI0(regD dst, immI0 zero) %{
11361 match(Set dst (Replicate4C zero));
11362 format %{ "PXOR $dst,$dst\t! replicate4C" %}
11363 ins_encode( pxor(dst, dst));
11364 ins_pipe( fpu_reg_reg );
11365 %}
11366
11367 // Replicate scalar to packed integer (4 byte) values in xmm
11368 instruct Repl2I_reg(regD dst, regD src) %{
11369 match(Set dst (Replicate2I src));
11370 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
11371 ins_encode( pshufd(dst, src, 0x00));
11372 ins_pipe( fpu_reg_reg );
11373 %}
11374
11375 // Replicate scalar to packed integer (4 byte) values in xmm
11376 instruct Repl2I_rRegI(regD dst, rRegI src) %{
11377 match(Set dst (Replicate2I src));
11378 format %{ "MOVD $dst,$src\n\t"
11379 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
11380 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
11381 ins_pipe( fpu_reg_reg );
11382 %}
11383
11384 // Replicate scalar zero to packed integer (2 byte) values in xmm
11385 instruct Repl2I_immI0(regD dst, immI0 zero) %{
11386 match(Set dst (Replicate2I zero));
11387 format %{ "PXOR $dst,$dst\t! replicate2I" %}
11388 ins_encode( pxor(dst, dst));
11389 ins_pipe( fpu_reg_reg );
11390 %}
11391
11392 // Replicate scalar to packed single precision floating point values in xmm
11393 instruct Repl2F_reg(regD dst, regD src) %{
11394 match(Set dst (Replicate2F src));
11395 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11396 ins_encode( pshufd(dst, src, 0xe0));
11397 ins_pipe( fpu_reg_reg );
11398 %}
11399
11400 // Replicate scalar to packed single precision floating point values in xmm
11401 instruct Repl2F_regF(regD dst, regF src) %{
11402 match(Set dst (Replicate2F src));
11403 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
11404 ins_encode( pshufd(dst, src, 0xe0));
11405 ins_pipe( fpu_reg_reg );
11406 %}
11407
11408 // Replicate scalar to packed single precision floating point values in xmm
11409 instruct Repl2F_immF0(regD dst, immF0 zero) %{
11410 match(Set dst (Replicate2F zero));
11411 format %{ "PXOR $dst,$dst\t! replicate2F" %}
11412 ins_encode( pxor(dst, dst));
11413 ins_pipe( fpu_reg_reg );
11414 %}
11415
11416
11417 // =======================================================================
11418 // fast clearing of an array
11419 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
11420 rFlagsReg cr)
11421 %{
11422 match(Set dummy (ClearArray cnt base));
11423 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11424
11425 format %{ "xorl rax, rax\t# ClearArray:\n\t"
11426 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
11427 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax
11428 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos
11429 ins_pipe(pipe_slow);
11430 %}
11431
11432 instruct string_compare(rdi_RegP str1, rsi_RegP str2, rax_RegI tmp1,
11433 rbx_RegI tmp2, regD6 tmp3, regD7 tmp4, rcx_RegI result, rFlagsReg cr)
11434 %{
11435 match(Set result (StrComp str1 str2));
11436 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
11437 //ins_cost(300);
11438
11439 format %{ "String Compare $str1, $str2 -> $result // XXX KILL RAX, RBX" %}
11440 ins_encode( enc_String_Compare() );
11441 ins_pipe( pipe_slow );
11442 %}
11443
11444 instruct string_indexof(rsi_RegP str1,rdi_RegP str2, rax_RegI tmp1, rcx_RegI tmp2, rdx_RegI tmp3, regD6 tmp4, rbx_RegI result, rFlagsReg cr) %{
11445 predicate(UseSSE>=4 && UseSSE42Intrinsics);
11446 match(Set result (StrIndexOf str1 str2));
11447 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
11448
11449 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX, XMM6" %}
11450 ins_encode( enc_String_IndexOf() );
11451 ins_pipe( pipe_slow );
11452 %}
11453
11454 // fast string equals
11455 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rbx_RegI tmp1, rcx_RegI tmp2, regD6 tmp3, regD7 tmp4, rax_RegI result, rFlagsReg cr) %{
11456 match(Set result (StrEquals str1 str2));
11457 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
11458
11459 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX, EDX, XMM6, XMM7" %}
11460 ins_encode( enc_String_Equals() );
11461 ins_pipe( pipe_slow );
11462 %}
11463
11464 // fast array equals
11465 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI tmp1,
11466 rbx_RegI tmp2, regD6 tmp3, regD7 tmp4, rcx_RegI result, rFlagsReg cr) %{
11467 match(Set result (AryEq ary1 ary2));
11468 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
11469 //ins_cost(300);
11470
11471 format %{ "Array Equals $ary1,$ary2 -> $result // KILL RAX, RBX" %}
11472 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) );
11473 ins_pipe( pipe_slow );
11474 %}
11475
11476 //----------Control Flow Instructions------------------------------------------
11477 // Signed compare Instructions
11478
11479 // XXX more variants!!
11480 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11481 %{
11482 match(Set cr (CmpI op1 op2));
11483 effect(DEF cr, USE op1, USE op2);
11484
11485 format %{ "cmpl $op1, $op2" %}
11486 opcode(0x3B); /* Opcode 3B /r */
11487 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11488 ins_pipe(ialu_cr_reg_reg);
11489 %}
11490
11491 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11492 %{
11493 match(Set cr (CmpI op1 op2));
11494
11495 format %{ "cmpl $op1, $op2" %}
11496 opcode(0x81, 0x07); /* Opcode 81 /7 */
11497 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11498 ins_pipe(ialu_cr_reg_imm);
11499 %}
11500
11501 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11502 %{
11503 match(Set cr (CmpI op1 (LoadI op2)));
11504
11505 ins_cost(500); // XXX
11506 format %{ "cmpl $op1, $op2" %}
11507 opcode(0x3B); /* Opcode 3B /r */
11508 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11509 ins_pipe(ialu_cr_reg_mem);
11510 %}
11511
11512 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11513 %{
11514 match(Set cr (CmpI src zero));
11515
11516 format %{ "testl $src, $src" %}
11517 opcode(0x85);
11518 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11519 ins_pipe(ialu_cr_reg_imm);
11520 %}
11521
11522 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11523 %{
11524 match(Set cr (CmpI (AndI src con) zero));
11525
11526 format %{ "testl $src, $con" %}
11527 opcode(0xF7, 0x00);
11528 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11529 ins_pipe(ialu_cr_reg_imm);
11530 %}
11531
11532 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11533 %{
11534 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11535
11536 format %{ "testl $src, $mem" %}
11537 opcode(0x85);
11538 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11539 ins_pipe(ialu_cr_reg_mem);
11540 %}
11541
11542 // Unsigned compare Instructions; really, same as signed except they
11543 // produce an rFlagsRegU instead of rFlagsReg.
11544 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11545 %{
11546 match(Set cr (CmpU op1 op2));
11547
11548 format %{ "cmpl $op1, $op2\t# unsigned" %}
11549 opcode(0x3B); /* Opcode 3B /r */
11550 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11551 ins_pipe(ialu_cr_reg_reg);
11552 %}
11553
11554 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11555 %{
11556 match(Set cr (CmpU op1 op2));
11557
11558 format %{ "cmpl $op1, $op2\t# unsigned" %}
11559 opcode(0x81,0x07); /* Opcode 81 /7 */
11560 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11561 ins_pipe(ialu_cr_reg_imm);
11562 %}
11563
11564 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11565 %{
11566 match(Set cr (CmpU op1 (LoadI op2)));
11567
11568 ins_cost(500); // XXX
11569 format %{ "cmpl $op1, $op2\t# unsigned" %}
11570 opcode(0x3B); /* Opcode 3B /r */
11571 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11572 ins_pipe(ialu_cr_reg_mem);
11573 %}
11574
11575 // // // Cisc-spilled version of cmpU_rReg
11576 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11577 // //%{
11578 // // match(Set cr (CmpU (LoadI op1) op2));
11579 // //
11580 // // format %{ "CMPu $op1,$op2" %}
11581 // // ins_cost(500);
11582 // // opcode(0x39); /* Opcode 39 /r */
11583 // // ins_encode( OpcP, reg_mem( op1, op2) );
11584 // //%}
11585
11586 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11587 %{
11588 match(Set cr (CmpU src zero));
11589
11590 format %{ "testl $src, $src\t# unsigned" %}
11591 opcode(0x85);
11592 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11593 ins_pipe(ialu_cr_reg_imm);
11594 %}
11595
11596 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11597 %{
11598 match(Set cr (CmpP op1 op2));
11599
11600 format %{ "cmpq $op1, $op2\t# ptr" %}
11601 opcode(0x3B); /* Opcode 3B /r */
11602 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11603 ins_pipe(ialu_cr_reg_reg);
11604 %}
11605
11606 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11607 %{
11608 match(Set cr (CmpP op1 (LoadP op2)));
11609
11610 ins_cost(500); // XXX
11611 format %{ "cmpq $op1, $op2\t# ptr" %}
11612 opcode(0x3B); /* Opcode 3B /r */
11613 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11614 ins_pipe(ialu_cr_reg_mem);
11615 %}
11616
11617 // // // Cisc-spilled version of cmpP_rReg
11618 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11619 // //%{
11620 // // match(Set cr (CmpP (LoadP op1) op2));
11621 // //
11622 // // format %{ "CMPu $op1,$op2" %}
11623 // // ins_cost(500);
11624 // // opcode(0x39); /* Opcode 39 /r */
11625 // // ins_encode( OpcP, reg_mem( op1, op2) );
11626 // //%}
11627
11628 // XXX this is generalized by compP_rReg_mem???
11629 // Compare raw pointer (used in out-of-heap check).
11630 // Only works because non-oop pointers must be raw pointers
11631 // and raw pointers have no anti-dependencies.
11632 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11633 %{
11634 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr());
11635 match(Set cr (CmpP op1 (LoadP op2)));
11636
11637 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11638 opcode(0x3B); /* Opcode 3B /r */
11639 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11640 ins_pipe(ialu_cr_reg_mem);
11641 %}
11642
11643 // This will generate a signed flags result. This should be OK since
11644 // any compare to a zero should be eq/neq.
11645 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11646 %{
11647 match(Set cr (CmpP src zero));
11648
11649 format %{ "testq $src, $src\t# ptr" %}
11650 opcode(0x85);
11651 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11652 ins_pipe(ialu_cr_reg_imm);
11653 %}
11654
11655 // This will generate a signed flags result. This should be OK since
11656 // any compare to a zero should be eq/neq.
11657 instruct testP_reg_mem(rFlagsReg cr, memory op, immP0 zero)
11658 %{
11659 match(Set cr (CmpP (LoadP op) zero));
11660
11661 ins_cost(500); // XXX
11662 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11663 opcode(0xF7); /* Opcode F7 /0 */
11664 ins_encode(REX_mem_wide(op),
11665 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11666 ins_pipe(ialu_cr_reg_imm);
11667 %}
11668
11669
11670 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11671 %{
11672 match(Set cr (CmpN op1 op2));
11673
11674 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11675 ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %}
11676 ins_pipe(ialu_cr_reg_reg);
11677 %}
11678
11679 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11680 %{
11681 match(Set cr (CmpN src (LoadN mem)));
11682
11683 ins_cost(500); // XXX
11684 format %{ "cmpl $src, mem\t# compressed ptr" %}
11685 ins_encode %{
11686 Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
11687 __ cmpl(as_Register($src$$reg), adr);
11688 %}
11689 ins_pipe(ialu_cr_reg_mem);
11690 %}
11691
11692 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11693 match(Set cr (CmpN src zero));
11694
11695 format %{ "testl $src, $src\t# compressed ptr" %}
11696 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11697 ins_pipe(ialu_cr_reg_imm);
11698 %}
11699
11700 instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero)
11701 %{
11702 match(Set cr (CmpN (LoadN mem) zero));
11703
11704 ins_cost(500); // XXX
11705 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11706 ins_encode %{
11707 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
11708 __ cmpl(addr, (int)0xFFFFFFFF);
11709 %}
11710 ins_pipe(ialu_cr_reg_mem);
11711 %}
11712
11713 // Yanked all unsigned pointer compare operations.
11714 // Pointer compares are done with CmpP which is already unsigned.
11715
11716 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11717 %{
11718 match(Set cr (CmpL op1 op2));
11719
11720 format %{ "cmpq $op1, $op2" %}
11721 opcode(0x3B); /* Opcode 3B /r */
11722 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11723 ins_pipe(ialu_cr_reg_reg);
11724 %}
11725
11726 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11727 %{
11728 match(Set cr (CmpL op1 op2));
11729
11730 format %{ "cmpq $op1, $op2" %}
11731 opcode(0x81, 0x07); /* Opcode 81 /7 */
11732 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11733 ins_pipe(ialu_cr_reg_imm);
11734 %}
11735
11736 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11737 %{
11738 match(Set cr (CmpL op1 (LoadL op2)));
11739
11740 ins_cost(500); // XXX
11741 format %{ "cmpq $op1, $op2" %}
11742 opcode(0x3B); /* Opcode 3B /r */
11743 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11744 ins_pipe(ialu_cr_reg_mem);
11745 %}
11746
11747 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11748 %{
11749 match(Set cr (CmpL src zero));
11750
11751 format %{ "testq $src, $src" %}
11752 opcode(0x85);
11753 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11754 ins_pipe(ialu_cr_reg_imm);
11755 %}
11756
11757 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11758 %{
11759 match(Set cr (CmpL (AndL src con) zero));
11760
11761 format %{ "testq $src, $con\t# long" %}
11762 opcode(0xF7, 0x00);
11763 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11764 ins_pipe(ialu_cr_reg_imm);
11765 %}
11766
11767 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11768 %{
11769 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11770
11771 format %{ "testq $src, $mem" %}
11772 opcode(0x85);
11773 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11774 ins_pipe(ialu_cr_reg_mem);
11775 %}
11776
11777 // Manifest a CmpL result in an integer register. Very painful.
11778 // This is the test to avoid.
11779 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11780 %{
11781 match(Set dst (CmpL3 src1 src2));
11782 effect(KILL flags);
11783
11784 ins_cost(275); // XXX
11785 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11786 "movl $dst, -1\n\t"
11787 "jl,s done\n\t"
11788 "setne $dst\n\t"
11789 "movzbl $dst, $dst\n\t"
11790 "done:" %}
11791 ins_encode(cmpl3_flag(src1, src2, dst));
11792 ins_pipe(pipe_slow);
11793 %}
11794
11795 //----------Max and Min--------------------------------------------------------
11796 // Min Instructions
11797
11798 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11799 %{
11800 effect(USE_DEF dst, USE src, USE cr);
11801
11802 format %{ "cmovlgt $dst, $src\t# min" %}
11803 opcode(0x0F, 0x4F);
11804 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11805 ins_pipe(pipe_cmov_reg);
11806 %}
11807
11808
11809 instruct minI_rReg(rRegI dst, rRegI src)
11810 %{
11811 match(Set dst (MinI dst src));
11812
11813 ins_cost(200);
11814 expand %{
11815 rFlagsReg cr;
11816 compI_rReg(cr, dst, src);
11817 cmovI_reg_g(dst, src, cr);
11818 %}
11819 %}
11820
11821 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11822 %{
11823 effect(USE_DEF dst, USE src, USE cr);
11824
11825 format %{ "cmovllt $dst, $src\t# max" %}
11826 opcode(0x0F, 0x4C);
11827 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11828 ins_pipe(pipe_cmov_reg);
11829 %}
11830
11831
11832 instruct maxI_rReg(rRegI dst, rRegI src)
11833 %{
11834 match(Set dst (MaxI dst src));
11835
11836 ins_cost(200);
11837 expand %{
11838 rFlagsReg cr;
11839 compI_rReg(cr, dst, src);
11840 cmovI_reg_l(dst, src, cr);
11841 %}
11842 %}
11843
11844 // ============================================================================
11845 // Branch Instructions
11846
11847 // Jump Direct - Label defines a relative address from JMP+1
11848 instruct jmpDir(label labl)
11849 %{
11850 match(Goto);
11851 effect(USE labl);
11852
11853 ins_cost(300);
11854 format %{ "jmp $labl" %}
11855 size(5);
11856 opcode(0xE9);
11857 ins_encode(OpcP, Lbl(labl));
11858 ins_pipe(pipe_jmp);
11859 ins_pc_relative(1);
11860 %}
11861
11862 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11863 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11864 %{
11865 match(If cop cr);
11866 effect(USE labl);
11867
11868 ins_cost(300);
11869 format %{ "j$cop $labl" %}
11870 size(6);
11871 opcode(0x0F, 0x80);
11872 ins_encode(Jcc(cop, labl));
11873 ins_pipe(pipe_jcc);
11874 ins_pc_relative(1);
11875 %}
11876
11877 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11878 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11879 %{
11880 match(CountedLoopEnd cop cr);
11881 effect(USE labl);
11882
11883 ins_cost(300);
11884 format %{ "j$cop $labl\t# loop end" %}
11885 size(6);
11886 opcode(0x0F, 0x80);
11887 ins_encode(Jcc(cop, labl));
11888 ins_pipe(pipe_jcc);
11889 ins_pc_relative(1);
11890 %}
11891
11892 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11893 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11894 match(CountedLoopEnd cop cmp);
11895 effect(USE labl);
11896
11897 ins_cost(300);
11898 format %{ "j$cop,u $labl\t# loop end" %}
11899 size(6);
11900 opcode(0x0F, 0x80);
11901 ins_encode(Jcc(cop, labl));
11902 ins_pipe(pipe_jcc);
11903 ins_pc_relative(1);
11904 %}
11905
11906 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11907 match(CountedLoopEnd cop cmp);
11908 effect(USE labl);
11909
11910 ins_cost(200);
11911 format %{ "j$cop,u $labl\t# loop end" %}
11912 size(6);
11913 opcode(0x0F, 0x80);
11914 ins_encode(Jcc(cop, labl));
11915 ins_pipe(pipe_jcc);
11916 ins_pc_relative(1);
11917 %}
11918
11919 // Jump Direct Conditional - using unsigned comparison
11920 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11921 match(If cop cmp);
11922 effect(USE labl);
11923
11924 ins_cost(300);
11925 format %{ "j$cop,u $labl" %}
11926 size(6);
11927 opcode(0x0F, 0x80);
11928 ins_encode(Jcc(cop, labl));
11929 ins_pipe(pipe_jcc);
11930 ins_pc_relative(1);
11931 %}
11932
11933 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11934 match(If cop cmp);
11935 effect(USE labl);
11936
11937 ins_cost(200);
11938 format %{ "j$cop,u $labl" %}
11939 size(6);
11940 opcode(0x0F, 0x80);
11941 ins_encode(Jcc(cop, labl));
11942 ins_pipe(pipe_jcc);
11943 ins_pc_relative(1);
11944 %}
11945
11946 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11947 match(If cop cmp);
11948 effect(USE labl);
11949
11950 ins_cost(200);
11951 format %{ $$template
11952 if ($cop$$cmpcode == Assembler::notEqual) {
11953 $$emit$$"jp,u $labl\n\t"
11954 $$emit$$"j$cop,u $labl"
11955 } else {
11956 $$emit$$"jp,u done\n\t"
11957 $$emit$$"j$cop,u $labl\n\t"
11958 $$emit$$"done:"
11959 }
11960 %}
11961 size(12);
11962 opcode(0x0F, 0x80);
11963 ins_encode %{
11964 Label* l = $labl$$label;
11965 $$$emit8$primary;
11966 emit_cc(cbuf, $secondary, Assembler::parity);
11967 int parity_disp = -1;
11968 if ($cop$$cmpcode == Assembler::notEqual) {
11969 // the two jumps 6 bytes apart so the jump distances are too
11970 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
11971 } else if ($cop$$cmpcode == Assembler::equal) {
11972 parity_disp = 6;
11973 } else {
11974 ShouldNotReachHere();
11975 }
11976 emit_d32(cbuf, parity_disp);
11977 $$$emit8$primary;
11978 emit_cc(cbuf, $secondary, $cop$$cmpcode);
11979 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
11980 emit_d32(cbuf, disp);
11981 %}
11982 ins_pipe(pipe_jcc);
11983 ins_pc_relative(1);
11984 %}
11985
11986 // ============================================================================
11987 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11988 // superklass array for an instance of the superklass. Set a hidden
11989 // internal cache on a hit (cache is checked with exposed code in
11990 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11991 // encoding ALSO sets flags.
11992
11993 instruct partialSubtypeCheck(rdi_RegP result,
11994 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11995 rFlagsReg cr)
11996 %{
11997 match(Set result (PartialSubtypeCheck sub super));
11998 effect(KILL rcx, KILL cr);
11999
12000 ins_cost(1100); // slightly larger than the next version
12001 format %{ "cmpq rax, rsi\n\t"
12002 "jeq,s hit\n\t"
12003 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
12004 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
12005 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
12006 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12007 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12008 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
12009 "hit:\n\t"
12010 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12011 "miss:\t" %}
12012
12013 opcode(0x1); // Force a XOR of RDI
12014 ins_encode(enc_PartialSubtypeCheck());
12015 ins_pipe(pipe_slow);
12016 %}
12017
12018 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12019 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12020 immP0 zero,
12021 rdi_RegP result)
12022 %{
12023 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12024 predicate(!UseCompressedOops); // decoding oop kills condition codes
12025 effect(KILL rcx, KILL result);
12026
12027 ins_cost(1000);
12028 format %{ "cmpq rax, rsi\n\t"
12029 "jeq,s miss\t# Actually a hit; we are done.\n\t"
12030 "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t"
12031 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t"
12032 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t"
12033 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12034 "jne,s miss\t\t# Missed: flags nz\n\t"
12035 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t"
12036 "miss:\t" %}
12037
12038 opcode(0x0); // No need to XOR RDI
12039 ins_encode(enc_PartialSubtypeCheck());
12040 ins_pipe(pipe_slow);
12041 %}
12042
12043 // ============================================================================
12044 // Branch Instructions -- short offset versions
12045 //
12046 // These instructions are used to replace jumps of a long offset (the default
12047 // match) with jumps of a shorter offset. These instructions are all tagged
12048 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12049 // match rules in general matching. Instead, the ADLC generates a conversion
12050 // method in the MachNode which can be used to do in-place replacement of the
12051 // long variant with the shorter variant. The compiler will determine if a
12052 // branch can be taken by the is_short_branch_offset() predicate in the machine
12053 // specific code section of the file.
12054
12055 // Jump Direct - Label defines a relative address from JMP+1
12056 instruct jmpDir_short(label labl) %{
12057 match(Goto);
12058 effect(USE labl);
12059
12060 ins_cost(300);
12061 format %{ "jmp,s $labl" %}
12062 size(2);
12063 opcode(0xEB);
12064 ins_encode(OpcP, LblShort(labl));
12065 ins_pipe(pipe_jmp);
12066 ins_pc_relative(1);
12067 ins_short_branch(1);
12068 %}
12069
12070 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12071 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12072 match(If cop cr);
12073 effect(USE labl);
12074
12075 ins_cost(300);
12076 format %{ "j$cop,s $labl" %}
12077 size(2);
12078 opcode(0x70);
12079 ins_encode(JccShort(cop, labl));
12080 ins_pipe(pipe_jcc);
12081 ins_pc_relative(1);
12082 ins_short_branch(1);
12083 %}
12084
12085 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12086 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12087 match(CountedLoopEnd cop cr);
12088 effect(USE labl);
12089
12090 ins_cost(300);
12091 format %{ "j$cop,s $labl\t# loop end" %}
12092 size(2);
12093 opcode(0x70);
12094 ins_encode(JccShort(cop, labl));
12095 ins_pipe(pipe_jcc);
12096 ins_pc_relative(1);
12097 ins_short_branch(1);
12098 %}
12099
12100 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12101 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12102 match(CountedLoopEnd cop cmp);
12103 effect(USE labl);
12104
12105 ins_cost(300);
12106 format %{ "j$cop,us $labl\t# loop end" %}
12107 size(2);
12108 opcode(0x70);
12109 ins_encode(JccShort(cop, labl));
12110 ins_pipe(pipe_jcc);
12111 ins_pc_relative(1);
12112 ins_short_branch(1);
12113 %}
12114
12115 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12116 match(CountedLoopEnd cop cmp);
12117 effect(USE labl);
12118
12119 ins_cost(300);
12120 format %{ "j$cop,us $labl\t# loop end" %}
12121 size(2);
12122 opcode(0x70);
12123 ins_encode(JccShort(cop, labl));
12124 ins_pipe(pipe_jcc);
12125 ins_pc_relative(1);
12126 ins_short_branch(1);
12127 %}
12128
12129 // Jump Direct Conditional - using unsigned comparison
12130 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12131 match(If cop cmp);
12132 effect(USE labl);
12133
12134 ins_cost(300);
12135 format %{ "j$cop,us $labl" %}
12136 size(2);
12137 opcode(0x70);
12138 ins_encode(JccShort(cop, labl));
12139 ins_pipe(pipe_jcc);
12140 ins_pc_relative(1);
12141 ins_short_branch(1);
12142 %}
12143
12144 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12145 match(If cop cmp);
12146 effect(USE labl);
12147
12148 ins_cost(300);
12149 format %{ "j$cop,us $labl" %}
12150 size(2);
12151 opcode(0x70);
12152 ins_encode(JccShort(cop, labl));
12153 ins_pipe(pipe_jcc);
12154 ins_pc_relative(1);
12155 ins_short_branch(1);
12156 %}
12157
12158 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12159 match(If cop cmp);
12160 effect(USE labl);
12161
12162 ins_cost(300);
12163 format %{ $$template
12164 if ($cop$$cmpcode == Assembler::notEqual) {
12165 $$emit$$"jp,u,s $labl\n\t"
12166 $$emit$$"j$cop,u,s $labl"
12167 } else {
12168 $$emit$$"jp,u,s done\n\t"
12169 $$emit$$"j$cop,u,s $labl\n\t"
12170 $$emit$$"done:"
12171 }
12172 %}
12173 size(4);
12174 opcode(0x70);
12175 ins_encode %{
12176 Label* l = $labl$$label;
12177 emit_cc(cbuf, $primary, Assembler::parity);
12178 int parity_disp = -1;
12179 if ($cop$$cmpcode == Assembler::notEqual) {
12180 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12181 } else if ($cop$$cmpcode == Assembler::equal) {
12182 parity_disp = 2;
12183 } else {
12184 ShouldNotReachHere();
12185 }
12186 emit_d8(cbuf, parity_disp);
12187 emit_cc(cbuf, $primary, $cop$$cmpcode);
12188 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12189 emit_d8(cbuf, disp);
12190 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12191 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12192 %}
12193 ins_pipe(pipe_jcc);
12194 ins_pc_relative(1);
12195 ins_short_branch(1);
12196 %}
12197
12198 // ============================================================================
12199 // inlined locking and unlocking
12200
12201 instruct cmpFastLock(rFlagsReg cr,
12202 rRegP object, rRegP box, rax_RegI tmp, rRegP scr)
12203 %{
12204 match(Set cr (FastLock object box));
12205 effect(TEMP tmp, TEMP scr);
12206
12207 ins_cost(300);
12208 format %{ "fastlock $object,$box,$tmp,$scr" %}
12209 ins_encode(Fast_Lock(object, box, tmp, scr));
12210 ins_pipe(pipe_slow);
12211 ins_pc_relative(1);
12212 %}
12213
12214 instruct cmpFastUnlock(rFlagsReg cr,
12215 rRegP object, rax_RegP box, rRegP tmp)
12216 %{
12217 match(Set cr (FastUnlock object box));
12218 effect(TEMP tmp);
12219
12220 ins_cost(300);
12221 format %{ "fastunlock $object, $box, $tmp" %}
12222 ins_encode(Fast_Unlock(object, box, tmp));
12223 ins_pipe(pipe_slow);
12224 ins_pc_relative(1);
12225 %}
12226
12227
12228 // ============================================================================
12229 // Safepoint Instructions
12230 instruct safePoint_poll(rFlagsReg cr)
12231 %{
12232 match(SafePoint);
12233 effect(KILL cr);
12234
12235 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
12236 "# Safepoint: poll for GC" %}
12237 size(6); // Opcode + ModRM + Disp32 == 6 bytes
12238 ins_cost(125);
12239 ins_encode(enc_safepoint_poll);
12240 ins_pipe(ialu_reg_mem);
12241 %}
12242
12243 // ============================================================================
12244 // Procedure Call/Return Instructions
12245 // Call Java Static Instruction
12246 // Note: If this code changes, the corresponding ret_addr_offset() and
12247 // compute_padding() functions will have to be adjusted.
12248 instruct CallStaticJavaDirect(method meth)
12249 %{
12250 match(CallStaticJava);
12251 effect(USE meth);
12252
12253 ins_cost(300);
12254 format %{ "call,static " %}
12255 opcode(0xE8); /* E8 cd */
12256 ins_encode(Java_Static_Call(meth), call_epilog);
12257 ins_pipe(pipe_slow);
12258 ins_pc_relative(1);
12259 ins_alignment(4);
12260 %}
12261
12262 // Call Java Dynamic Instruction
12263 // Note: If this code changes, the corresponding ret_addr_offset() and
12264 // compute_padding() functions will have to be adjusted.
12265 instruct CallDynamicJavaDirect(method meth)
12266 %{
12267 match(CallDynamicJava);
12268 effect(USE meth);
12269
12270 ins_cost(300);
12271 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12272 "call,dynamic " %}
12273 opcode(0xE8); /* E8 cd */
12274 ins_encode(Java_Dynamic_Call(meth), call_epilog);
12275 ins_pipe(pipe_slow);
12276 ins_pc_relative(1);
12277 ins_alignment(4);
12278 %}
12279
12280 // Call Runtime Instruction
12281 instruct CallRuntimeDirect(method meth)
12282 %{
12283 match(CallRuntime);
12284 effect(USE meth);
12285
12286 ins_cost(300);
12287 format %{ "call,runtime " %}
12288 opcode(0xE8); /* E8 cd */
12289 ins_encode(Java_To_Runtime(meth));
12290 ins_pipe(pipe_slow);
12291 ins_pc_relative(1);
12292 %}
12293
12294 // Call runtime without safepoint
12295 instruct CallLeafDirect(method meth)
12296 %{
12297 match(CallLeaf);
12298 effect(USE meth);
12299
12300 ins_cost(300);
12301 format %{ "call_leaf,runtime " %}
12302 opcode(0xE8); /* E8 cd */
12303 ins_encode(Java_To_Runtime(meth));
12304 ins_pipe(pipe_slow);
12305 ins_pc_relative(1);
12306 %}
12307
12308 // Call runtime without safepoint
12309 instruct CallLeafNoFPDirect(method meth)
12310 %{
12311 match(CallLeafNoFP);
12312 effect(USE meth);
12313
12314 ins_cost(300);
12315 format %{ "call_leaf_nofp,runtime " %}
12316 opcode(0xE8); /* E8 cd */
12317 ins_encode(Java_To_Runtime(meth));
12318 ins_pipe(pipe_slow);
12319 ins_pc_relative(1);
12320 %}
12321
12322 // Return Instruction
12323 // Remove the return address & jump to it.
12324 // Notice: We always emit a nop after a ret to make sure there is room
12325 // for safepoint patching
12326 instruct Ret()
12327 %{
12328 match(Return);
12329
12330 format %{ "ret" %}
12331 opcode(0xC3);
12332 ins_encode(OpcP);
12333 ins_pipe(pipe_jmp);
12334 %}
12335
12336 // Tail Call; Jump from runtime stub to Java code.
12337 // Also known as an 'interprocedural jump'.
12338 // Target of jump will eventually return to caller.
12339 // TailJump below removes the return address.
12340 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
12341 %{
12342 match(TailCall jump_target method_oop);
12343
12344 ins_cost(300);
12345 format %{ "jmp $jump_target\t# rbx holds method oop" %}
12346 opcode(0xFF, 0x4); /* Opcode FF /4 */
12347 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
12348 ins_pipe(pipe_jmp);
12349 %}
12350
12351 // Tail Jump; remove the return address; jump to target.
12352 // TailCall above leaves the return address around.
12353 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12354 %{
12355 match(TailJump jump_target ex_oop);
12356
12357 ins_cost(300);
12358 format %{ "popq rdx\t# pop return address\n\t"
12359 "jmp $jump_target" %}
12360 opcode(0xFF, 0x4); /* Opcode FF /4 */
12361 ins_encode(Opcode(0x5a), // popq rdx
12362 REX_reg(jump_target), OpcP, reg_opc(jump_target));
12363 ins_pipe(pipe_jmp);
12364 %}
12365
12366 // Create exception oop: created by stack-crawling runtime code.
12367 // Created exception is now available to this handler, and is setup
12368 // just prior to jumping to this handler. No code emitted.
12369 instruct CreateException(rax_RegP ex_oop)
12370 %{
12371 match(Set ex_oop (CreateEx));
12372
12373 size(0);
12374 // use the following format syntax
12375 format %{ "# exception oop is in rax; no code emitted" %}
12376 ins_encode();
12377 ins_pipe(empty);
12378 %}
12379
12380 // Rethrow exception:
12381 // The exception oop will come in the first argument position.
12382 // Then JUMP (not call) to the rethrow stub code.
12383 instruct RethrowException()
12384 %{
12385 match(Rethrow);
12386
12387 // use the following format syntax
12388 format %{ "jmp rethrow_stub" %}
12389 ins_encode(enc_rethrow);
12390 ins_pipe(pipe_jmp);
12391 %}
12392
12393
12394 //----------PEEPHOLE RULES-----------------------------------------------------
12395 // These must follow all instruction definitions as they use the names
12396 // defined in the instructions definitions.
12397 //
12398 // peepmatch ( root_instr_name [precerding_instruction]* );
12399 //
12400 // peepconstraint %{
12401 // (instruction_number.operand_name relational_op instruction_number.operand_name
12402 // [, ...] );
12403 // // instruction numbers are zero-based using left to right order in peepmatch
12404 //
12405 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12406 // // provide an instruction_number.operand_name for each operand that appears
12407 // // in the replacement instruction's match rule
12408 //
12409 // ---------VM FLAGS---------------------------------------------------------
12410 //
12411 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12412 //
12413 // Each peephole rule is given an identifying number starting with zero and
12414 // increasing by one in the order seen by the parser. An individual peephole
12415 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12416 // on the command-line.
12417 //
12418 // ---------CURRENT LIMITATIONS----------------------------------------------
12419 //
12420 // Only match adjacent instructions in same basic block
12421 // Only equality constraints
12422 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12423 // Only one replacement instruction
12424 //
12425 // ---------EXAMPLE----------------------------------------------------------
12426 //
12427 // // pertinent parts of existing instructions in architecture description
12428 // instruct movI(rRegI dst, rRegI src)
12429 // %{
12430 // match(Set dst (CopyI src));
12431 // %}
12432 //
12433 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12434 // %{
12435 // match(Set dst (AddI dst src));
12436 // effect(KILL cr);
12437 // %}
12438 //
12439 // // Change (inc mov) to lea
12440 // peephole %{
12441 // // increment preceeded by register-register move
12442 // peepmatch ( incI_rReg movI );
12443 // // require that the destination register of the increment
12444 // // match the destination register of the move
12445 // peepconstraint ( 0.dst == 1.dst );
12446 // // construct a replacement instruction that sets
12447 // // the destination to ( move's source register + one )
12448 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12449 // %}
12450 //
12451
12452 // Implementation no longer uses movX instructions since
12453 // machine-independent system no longer uses CopyX nodes.
12454 //
12455 // peephole
12456 // %{
12457 // peepmatch (incI_rReg movI);
12458 // peepconstraint (0.dst == 1.dst);
12459 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12460 // %}
12461
12462 // peephole
12463 // %{
12464 // peepmatch (decI_rReg movI);
12465 // peepconstraint (0.dst == 1.dst);
12466 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12467 // %}
12468
12469 // peephole
12470 // %{
12471 // peepmatch (addI_rReg_imm movI);
12472 // peepconstraint (0.dst == 1.dst);
12473 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12474 // %}
12475
12476 // peephole
12477 // %{
12478 // peepmatch (incL_rReg movL);
12479 // peepconstraint (0.dst == 1.dst);
12480 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12481 // %}
12482
12483 // peephole
12484 // %{
12485 // peepmatch (decL_rReg movL);
12486 // peepconstraint (0.dst == 1.dst);
12487 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12488 // %}
12489
12490 // peephole
12491 // %{
12492 // peepmatch (addL_rReg_imm movL);
12493 // peepconstraint (0.dst == 1.dst);
12494 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12495 // %}
12496
12497 // peephole
12498 // %{
12499 // peepmatch (addP_rReg_imm movP);
12500 // peepconstraint (0.dst == 1.dst);
12501 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12502 // %}
12503
12504 // // Change load of spilled value to only a spill
12505 // instruct storeI(memory mem, rRegI src)
12506 // %{
12507 // match(Set mem (StoreI mem src));
12508 // %}
12509 //
12510 // instruct loadI(rRegI dst, memory mem)
12511 // %{
12512 // match(Set dst (LoadI mem));
12513 // %}
12514 //
12515
12516 peephole
12517 %{
12518 peepmatch (loadI storeI);
12519 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12520 peepreplace (storeI(1.mem 1.mem 1.src));
12521 %}
12522
12523 peephole
12524 %{
12525 peepmatch (loadL storeL);
12526 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12527 peepreplace (storeL(1.mem 1.mem 1.src));
12528 %}
12529
12530 //----------SMARTSPILL RULES---------------------------------------------------
12531 // These must follow all instruction definitions as they use the names
12532 // defined in the instructions definitions.