1 //
2 // Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 // CA 95054 USA or visit www.sun.com if you need additional information or
21 // have any questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Special Registers
78 reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad());
79
80 // Float registers. We treat TOS/FPR0 special. It is invisible to the
81 // allocator, and only shows up in the encodings.
82 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
83 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
84 // Ok so here's the trick FPR1 is really st(0) except in the midst
85 // of emission of assembly for a machnode. During the emission the fpu stack
86 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
87 // the stack will not have this element so FPR1 == st(0) from the
88 // oopMap viewpoint. This same weirdness with numbering causes
89 // instruction encoding to have to play games with the register
90 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
91 // where it does flt->flt moves to see an example
92 //
93 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
94 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
95 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
96 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
97 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
98 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
99 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
100 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
101 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
102 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
103 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
104 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
105 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
106 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
107
108 // XMM registers. 128-bit registers or 4 words each, labeled a-d.
109 // Word a in each register holds a Float, words ab hold a Double.
110 // We currently do not use the SIMD capabilities, so registers cd
111 // are unused at the moment.
112 reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg());
113 reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next());
114 reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg());
115 reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next());
116 reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg());
117 reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next());
118 reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg());
119 reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next());
120 reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg());
121 reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next());
122 reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg());
123 reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next());
124 reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg());
125 reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next());
126 reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg());
127 reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next());
128
129 // Specify priority of register selection within phases of register
130 // allocation. Highest priority is first. A useful heuristic is to
131 // give registers a low priority when they are required by machine
132 // instructions, like EAX and EDX. Registers which are used as
133 // pairs must fall on an even boundry (witness the FPR#L's in this list).
134 // For the Intel integer registers, the equivalent Long pairs are
135 // EDX:EAX, EBX:ECX, and EDI:EBP.
136 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
139 FPR6L, FPR6H, FPR7L, FPR7H );
140
141 alloc_class chunk1( XMM0a, XMM0b,
142 XMM1a, XMM1b,
143 XMM2a, XMM2b,
144 XMM3a, XMM3b,
145 XMM4a, XMM4b,
146 XMM5a, XMM5b,
147 XMM6a, XMM6b,
148 XMM7a, XMM7b, EFLAGS);
149
150
151 //----------Architecture Description Register Classes--------------------------
152 // Several register classes are automatically defined based upon information in
153 // this architecture description.
154 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
155 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
156 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
157 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
158 //
159 // Class for all registers
160 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
161 // Class for general registers
162 reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
163 // Class for general registers which may be used for implicit null checks on win95
164 // Also safe for use by tailjump. We don't want to allocate in rbp,
165 reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
166 // Class of "X" registers
167 reg_class x_reg(EBX, ECX, EDX, EAX);
168 // Class of registers that can appear in an address with no offset.
169 // EBP and ESP require an extra instruction byte for zero offset.
170 // Used in fast-unlock
171 reg_class p_reg(EDX, EDI, ESI, EBX);
172 // Class for general registers not including ECX
173 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
174 // Class for general registers not including EAX
175 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
176 // Class for general registers not including EAX or EBX.
177 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
178 // Class of EAX (for multiply and divide operations)
179 reg_class eax_reg(EAX);
180 // Class of EBX (for atomic add)
181 reg_class ebx_reg(EBX);
182 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
183 reg_class ecx_reg(ECX);
184 // Class of EDX (for multiply and divide operations)
185 reg_class edx_reg(EDX);
186 // Class of EDI (for synchronization)
187 reg_class edi_reg(EDI);
188 // Class of ESI (for synchronization)
189 reg_class esi_reg(ESI);
190 // Singleton class for interpreter's stack pointer
191 reg_class ebp_reg(EBP);
192 // Singleton class for stack pointer
193 reg_class sp_reg(ESP);
194 // Singleton class for instruction pointer
195 // reg_class ip_reg(EIP);
196 // Singleton class for condition codes
197 reg_class int_flags(EFLAGS);
198 // Class of integer register pairs
199 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
200 // Class of integer register pairs that aligns with calling convention
201 reg_class eadx_reg( EAX,EDX );
202 reg_class ebcx_reg( ECX,EBX );
203 // Not AX or DX, used in divides
204 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
205
206 // Floating point registers. Notice FPR0 is not a choice.
207 // FPR0 is not ever allocated; we use clever encodings to fake
208 // a 2-address instructions out of Intels FP stack.
209 reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
210
211 // make a register class for SSE registers
212 reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a);
213
214 // make a double register class for SSE2 registers
215 reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b,
216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b );
217
218 reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
220 FPR7L,FPR7H );
221
222 reg_class flt_reg0( FPR1L );
223 reg_class dbl_reg0( FPR1L,FPR1H );
224 reg_class dbl_reg1( FPR2L,FPR2H );
225 reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
227
228 // XMM6 and XMM7 could be used as temporary registers for long, float and
229 // double values for SSE2.
230 reg_class xdb_reg6( XMM6a,XMM6b );
231 reg_class xdb_reg7( XMM7a,XMM7b );
232 %}
233
234
235 //----------SOURCE BLOCK-------------------------------------------------------
236 // This is a block of C++ code which provides values, functions, and
237 // definitions necessary in the rest of the architecture description
238 source %{
239 #define RELOC_IMM32 Assembler::imm_operand
240 #define RELOC_DISP32 Assembler::disp32_operand
241
242 #define __ _masm.
243
244 // How to find the high register of a Long pair, given the low register
245 #define HIGH_FROM_LOW(x) ((x)+2)
246
247 // These masks are used to provide 128-bit aligned bitmasks to the XMM
248 // instructions, to allow sign-masking or sign-bit flipping. They allow
249 // fast versions of NegF/NegD and AbsF/AbsD.
250
251 // Note: 'double' and 'long long' have 32-bits alignment on x86.
252 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
254 // of 128-bits operands for SSE instructions.
255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
256 // Store the value to a 128-bits operand.
257 operand[0] = lo;
258 operand[1] = hi;
259 return operand;
260 }
261
262 // Buffer for 128-bits masks used by SSE instructions.
263 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
264
265 // Static initialization during VM startup.
266 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
267 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
268 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
269 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
270
271 // !!!!! Special hack to get all type of calls to specify the byte offset
272 // from the start of the call to the point where the return address
273 // will point.
274 int MachCallStaticJavaNode::ret_addr_offset() {
275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points
276 }
277
278 int MachCallDynamicJavaNode::ret_addr_offset() {
279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points
280 }
281
282 static int sizeof_FFree_Float_Stack_All = -1;
283
284 int MachCallRuntimeNode::ret_addr_offset() {
285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0);
287 }
288
289 // Indicate if the safepoint node needs the polling page as an input.
290 // Since x86 does have absolute addressing, it doesn't.
291 bool SafePointNode::needs_polling_address_input() {
292 return false;
293 }
294
295 //
296 // Compute padding required for nodes which need alignment
297 //
298
299 // The address of the call instruction needs to be 4-byte aligned to
300 // ensure that it does not span a cache line so that it can be patched.
301 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
302 if (Compile::current()->in_24_bit_fp_mode())
303 current_offset += 6; // skip fldcw in pre_call_FPU, if any
304 current_offset += 1; // skip call opcode byte
305 return round_to(current_offset, alignment_required()) - current_offset;
306 }
307
308 // The address of the call instruction needs to be 4-byte aligned to
309 // ensure that it does not span a cache line so that it can be patched.
310 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
311 if (Compile::current()->in_24_bit_fp_mode())
312 current_offset += 6; // skip fldcw in pre_call_FPU, if any
313 current_offset += 5; // skip MOV instruction
314 current_offset += 1; // skip call opcode byte
315 return round_to(current_offset, alignment_required()) - current_offset;
316 }
317
318 #ifndef PRODUCT
319 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const {
320 st->print("INT3");
321 }
322 #endif
323
324 // EMIT_RM()
325 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
327 *(cbuf.code_end()) = c;
328 cbuf.set_code_end(cbuf.code_end() + 1);
329 }
330
331 // EMIT_CC()
332 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
333 unsigned char c = (unsigned char)( f1 | f2 );
334 *(cbuf.code_end()) = c;
335 cbuf.set_code_end(cbuf.code_end() + 1);
336 }
337
338 // EMIT_OPCODE()
339 void emit_opcode(CodeBuffer &cbuf, int code) {
340 *(cbuf.code_end()) = (unsigned char)code;
341 cbuf.set_code_end(cbuf.code_end() + 1);
342 }
343
344 // EMIT_OPCODE() w/ relocation information
345 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
346 cbuf.relocate(cbuf.inst_mark() + offset, reloc);
347 emit_opcode(cbuf, code);
348 }
349
350 // EMIT_D8()
351 void emit_d8(CodeBuffer &cbuf, int d8) {
352 *(cbuf.code_end()) = (unsigned char)d8;
353 cbuf.set_code_end(cbuf.code_end() + 1);
354 }
355
356 // EMIT_D16()
357 void emit_d16(CodeBuffer &cbuf, int d16) {
358 *((short *)(cbuf.code_end())) = d16;
359 cbuf.set_code_end(cbuf.code_end() + 2);
360 }
361
362 // EMIT_D32()
363 void emit_d32(CodeBuffer &cbuf, int d32) {
364 *((int *)(cbuf.code_end())) = d32;
365 cbuf.set_code_end(cbuf.code_end() + 4);
366 }
367
368 // emit 32 bit value and construct relocation entry from relocInfo::relocType
369 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
370 int format) {
371 cbuf.relocate(cbuf.inst_mark(), reloc, format);
372
373 *((int *)(cbuf.code_end())) = d32;
374 cbuf.set_code_end(cbuf.code_end() + 4);
375 }
376
377 // emit 32 bit value and construct relocation entry from RelocationHolder
378 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
379 int format) {
380 #ifdef ASSERT
381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code");
383 }
384 #endif
385 cbuf.relocate(cbuf.inst_mark(), rspec, format);
386
387 *((int *)(cbuf.code_end())) = d32;
388 cbuf.set_code_end(cbuf.code_end() + 4);
389 }
390
391 // Access stack slot for load or store
392 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
394 if( -128 <= disp && disp <= 127 ) {
395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
397 emit_d8 (cbuf, disp); // Displacement // R/M byte
398 } else {
399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
401 emit_d32(cbuf, disp); // Displacement // R/M byte
402 }
403 }
404
405 // eRegI ereg, memory mem) %{ // emit_reg_mem
406 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
407 // There is no index & no scale, use form without SIB byte
408 if ((index == 0x4) &&
409 (scale == 0) && (base != ESP_enc)) {
410 // If no displacement, mode is 0x0; unless base is [EBP]
411 if ( (displace == 0) && (base != EBP_enc) ) {
412 emit_rm(cbuf, 0x0, reg_encoding, base);
413 }
414 else { // If 8-bit displacement, mode 0x1
415 if ((displace >= -128) && (displace <= 127)
416 && !(displace_is_oop) ) {
417 emit_rm(cbuf, 0x1, reg_encoding, base);
418 emit_d8(cbuf, displace);
419 }
420 else { // If 32-bit displacement
421 if (base == -1) { // Special flag for absolute address
422 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
423 // (manual lies; no SIB needed here)
424 if ( displace_is_oop ) {
425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
426 } else {
427 emit_d32 (cbuf, displace);
428 }
429 }
430 else { // Normal base + offset
431 emit_rm(cbuf, 0x2, reg_encoding, base);
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441 else { // Else, encode with the SIB byte
442 // If no displacement, mode is 0x0; unless base is [EBP]
443 if (displace == 0 && (base != EBP_enc)) { // If no displacement
444 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
445 emit_rm(cbuf, scale, index, base);
446 }
447 else { // If 8-bit displacement, mode 0x1
448 if ((displace >= -128) && (displace <= 127)
449 && !(displace_is_oop) ) {
450 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
451 emit_rm(cbuf, scale, index, base);
452 emit_d8(cbuf, displace);
453 }
454 else { // If 32-bit displacement
455 if (base == 0x04 ) {
456 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
457 emit_rm(cbuf, scale, index, 0x04);
458 } else {
459 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
460 emit_rm(cbuf, scale, index, base);
461 }
462 if ( displace_is_oop ) {
463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
464 } else {
465 emit_d32 (cbuf, displace);
466 }
467 }
468 }
469 }
470 }
471
472
473 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
474 if( dst_encoding == src_encoding ) {
475 // reg-reg copy, use an empty encoding
476 } else {
477 emit_opcode( cbuf, 0x8B );
478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
479 }
480 }
481
482 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
483 if( dst_encoding == src_encoding ) {
484 // reg-reg copy, use an empty encoding
485 } else {
486 MacroAssembler _masm(&cbuf);
487
488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding));
489 }
490 }
491
492
493 //=============================================================================
494 #ifndef PRODUCT
495 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
496 Compile* C = ra_->C;
497 if( C->in_24_bit_fp_mode() ) {
498 st->print("FLDCW 24 bit fpu control word");
499 st->print_cr(""); st->print("\t");
500 }
501
502 int framesize = C->frame_slots() << LogBytesPerInt;
503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
504 // Remove two words for return addr and rbp,
505 framesize -= 2*wordSize;
506
507 // Calls to C2R adapters often do not accept exceptional returns.
508 // We require that their callers must bang for them. But be careful, because
509 // some VM calls (such as call site linkage) can use several kilobytes of
510 // stack. But the stack safety zone should account for that.
511 // See bugs 4446381, 4468289, 4497237.
512 if (C->need_stack_bang(framesize)) {
513 st->print_cr("# stack bang"); st->print("\t");
514 }
515 st->print_cr("PUSHL EBP"); st->print("\t");
516
517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
518 st->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check");
519 st->print_cr(""); st->print("\t");
520 framesize -= wordSize;
521 }
522
523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
524 if (framesize) {
525 st->print("SUB ESP,%d\t# Create frame",framesize);
526 }
527 } else {
528 st->print("SUB ESP,%d\t# Create frame",framesize);
529 }
530 }
531 #endif
532
533
534 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
535 Compile* C = ra_->C;
536
537 if (UseSSE >= 2 && VerifyFPU) {
538 MacroAssembler masm(&cbuf);
539 masm.verify_FPU(0, "FPU stack must be clean on entry");
540 }
541
542 // WARNING: Initial instruction MUST be 5 bytes or longer so that
543 // NativeJump::patch_verified_entry will be able to patch out the entry
544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack
545 // depth is ok at 5 bytes, the frame allocation can be either 3 or
546 // 6 bytes. So if we don't do the fldcw or the push then we must
547 // use the 6 byte frame allocation even if we have no frame. :-(
548 // If method sets FPU control word do it now
549 if( C->in_24_bit_fp_mode() ) {
550 MacroAssembler masm(&cbuf);
551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
552 }
553
554 int framesize = C->frame_slots() << LogBytesPerInt;
555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
556 // Remove two words for return addr and rbp,
557 framesize -= 2*wordSize;
558
559 // Calls to C2R adapters often do not accept exceptional returns.
560 // We require that their callers must bang for them. But be careful, because
561 // some VM calls (such as call site linkage) can use several kilobytes of
562 // stack. But the stack safety zone should account for that.
563 // See bugs 4446381, 4468289, 4497237.
564 if (C->need_stack_bang(framesize)) {
565 MacroAssembler masm(&cbuf);
566 masm.generate_stack_overflow_check(framesize);
567 }
568
569 // We always push rbp, so that on return to interpreter rbp, will be
570 // restored correctly and we can correct the stack.
571 emit_opcode(cbuf, 0x50 | EBP_enc);
572
573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth
574 emit_opcode(cbuf, 0x68); // push 0xbadb100d
575 emit_d32(cbuf, 0xbadb100d);
576 framesize -= wordSize;
577 }
578
579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) {
580 if (framesize) {
581 emit_opcode(cbuf, 0x83); // sub SP,#framesize
582 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
583 emit_d8(cbuf, framesize);
584 }
585 } else {
586 emit_opcode(cbuf, 0x81); // sub SP,#framesize
587 emit_rm(cbuf, 0x3, 0x05, ESP_enc);
588 emit_d32(cbuf, framesize);
589 }
590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin());
591
592 #ifdef ASSERT
593 if (VerifyStackAtCalls) {
594 Label L;
595 MacroAssembler masm(&cbuf);
596 masm.push(rax);
597 masm.mov(rax, rsp);
598 masm.andptr(rax, StackAlignmentInBytes-1);
599 masm.cmpptr(rax, StackAlignmentInBytes-wordSize);
600 masm.pop(rax);
601 masm.jcc(Assembler::equal, L);
602 masm.stop("Stack is not properly aligned!");
603 masm.bind(L);
604 }
605 #endif
606
607 }
608
609 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
610 return MachNode::size(ra_); // too many variables; just compute it the hard way
611 }
612
613 int MachPrologNode::reloc() const {
614 return 0; // a large enough number
615 }
616
617 //=============================================================================
618 #ifndef PRODUCT
619 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
620 Compile *C = ra_->C;
621 int framesize = C->frame_slots() << LogBytesPerInt;
622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
623 // Remove two words for return addr and rbp,
624 framesize -= 2*wordSize;
625
626 if( C->in_24_bit_fp_mode() ) {
627 st->print("FLDCW standard control word");
628 st->cr(); st->print("\t");
629 }
630 if( framesize ) {
631 st->print("ADD ESP,%d\t# Destroy frame",framesize);
632 st->cr(); st->print("\t");
633 }
634 st->print_cr("POPL EBP"); st->print("\t");
635 if( do_polling() && C->is_method_compilation() ) {
636 st->print("TEST PollPage,EAX\t! Poll Safepoint");
637 st->cr(); st->print("\t");
638 }
639 }
640 #endif
641
642 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
643 Compile *C = ra_->C;
644
645 // If method set FPU control word, restore to standard control word
646 if( C->in_24_bit_fp_mode() ) {
647 MacroAssembler masm(&cbuf);
648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
649 }
650
651 int framesize = C->frame_slots() << LogBytesPerInt;
652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
653 // Remove two words for return addr and rbp,
654 framesize -= 2*wordSize;
655
656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
657
658 if( framesize >= 128 ) {
659 emit_opcode(cbuf, 0x81); // add SP, #framesize
660 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
661 emit_d32(cbuf, framesize);
662 }
663 else if( framesize ) {
664 emit_opcode(cbuf, 0x83); // add SP, #framesize
665 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
666 emit_d8(cbuf, framesize);
667 }
668
669 emit_opcode(cbuf, 0x58 | EBP_enc);
670
671 if( do_polling() && C->is_method_compilation() ) {
672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0);
673 emit_opcode(cbuf,0x85);
674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
675 emit_d32(cbuf, (intptr_t)os::get_polling_page());
676 }
677 }
678
679 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
680 Compile *C = ra_->C;
681 // If method set FPU control word, restore to standard control word
682 int size = C->in_24_bit_fp_mode() ? 6 : 0;
683 if( do_polling() && C->is_method_compilation() ) size += 6;
684
685 int framesize = C->frame_slots() << LogBytesPerInt;
686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
687 // Remove two words for return addr and rbp,
688 framesize -= 2*wordSize;
689
690 size++; // popl rbp,
691
692 if( framesize >= 128 ) {
693 size += 6;
694 } else {
695 size += framesize ? 3 : 0;
696 }
697 return size;
698 }
699
700 int MachEpilogNode::reloc() const {
701 return 0; // a large enough number
702 }
703
704 const Pipeline * MachEpilogNode::pipeline() const {
705 return MachNode::pipeline_class();
706 }
707
708 int MachEpilogNode::safepoint_offset() const { return 0; }
709
710 //=============================================================================
711
712 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
713 static enum RC rc_class( OptoReg::Name reg ) {
714
715 if( !OptoReg::is_valid(reg) ) return rc_bad;
716 if (OptoReg::is_stack(reg)) return rc_stack;
717
718 VMReg r = OptoReg::as_VMReg(reg);
719 if (r->is_Register()) return rc_int;
720 if (r->is_FloatRegister()) {
721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
722 return rc_float;
723 }
724 assert(r->is_XMMRegister(), "must be");
725 return rc_xmm;
726 }
727
728 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
729 int opcode, const char *op_str, int size, outputStream* st ) {
730 if( cbuf ) {
731 emit_opcode (*cbuf, opcode );
732 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
733 #ifndef PRODUCT
734 } else if( !do_size ) {
735 if( size != 0 ) st->print("\n\t");
736 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
737 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
738 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
739 } else { // FLD, FST, PUSH, POP
740 st->print("%s [ESP + #%d]",op_str,offset);
741 }
742 #endif
743 }
744 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
745 return size+3+offset_size;
746 }
747
748 // Helper for XMM registers. Extra opcode bits, limited syntax.
749 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
750 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
751 if( cbuf ) {
752 if( reg_lo+1 == reg_hi ) { // double move?
753 if( is_load && !UseXmmLoadAndClearUpper )
754 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load
755 else
756 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise
757 } else {
758 emit_opcode(*cbuf, 0xF3 );
759 }
760 emit_opcode(*cbuf, 0x0F );
761 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper )
762 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load
763 else
764 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 );
765 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false);
766 #ifndef PRODUCT
767 } else if( !do_size ) {
768 if( size != 0 ) st->print("\n\t");
769 if( reg_lo+1 == reg_hi ) { // double move?
770 if( is_load ) st->print("%s %s,[ESP + #%d]",
771 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
772 Matcher::regName[reg_lo], offset);
773 else st->print("MOVSD [ESP + #%d],%s",
774 offset, Matcher::regName[reg_lo]);
775 } else {
776 if( is_load ) st->print("MOVSS %s,[ESP + #%d]",
777 Matcher::regName[reg_lo], offset);
778 else st->print("MOVSS [ESP + #%d],%s",
779 offset, Matcher::regName[reg_lo]);
780 }
781 #endif
782 }
783 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
784 return size+5+offset_size;
785 }
786
787
788 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
789 int src_hi, int dst_hi, int size, outputStream* st ) {
790 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers
791 if( cbuf ) {
792 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) {
793 emit_opcode(*cbuf, 0x66 );
794 }
795 emit_opcode(*cbuf, 0x0F );
796 emit_opcode(*cbuf, 0x28 );
797 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
798 #ifndef PRODUCT
799 } else if( !do_size ) {
800 if( size != 0 ) st->print("\n\t");
801 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
802 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
803 } else {
804 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
805 }
806 #endif
807 }
808 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3);
809 } else {
810 if( cbuf ) {
811 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 );
812 emit_opcode(*cbuf, 0x0F );
813 emit_opcode(*cbuf, 0x10 );
814 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] );
815 #ifndef PRODUCT
816 } else if( !do_size ) {
817 if( size != 0 ) st->print("\n\t");
818 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
819 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
820 } else {
821 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
822 }
823 #endif
824 }
825 return size+4;
826 }
827 }
828
829 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
830 if( cbuf ) {
831 emit_opcode(*cbuf, 0x8B );
832 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
833 #ifndef PRODUCT
834 } else if( !do_size ) {
835 if( size != 0 ) st->print("\n\t");
836 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
837 #endif
838 }
839 return size+2;
840 }
841
842 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
843 int offset, int size, outputStream* st ) {
844 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
845 if( cbuf ) {
846 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
847 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
848 #ifndef PRODUCT
849 } else if( !do_size ) {
850 if( size != 0 ) st->print("\n\t");
851 st->print("FLD %s",Matcher::regName[src_lo]);
852 #endif
853 }
854 size += 2;
855 }
856
857 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
858 const char *op_str;
859 int op;
860 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
861 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
862 op = 0xDD;
863 } else { // 32-bit store
864 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
865 op = 0xD9;
866 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
867 }
868
869 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
870 }
871
872 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
873 // Get registers to move
874 OptoReg::Name src_second = ra_->get_reg_second(in(1));
875 OptoReg::Name src_first = ra_->get_reg_first(in(1));
876 OptoReg::Name dst_second = ra_->get_reg_second(this );
877 OptoReg::Name dst_first = ra_->get_reg_first(this );
878
879 enum RC src_second_rc = rc_class(src_second);
880 enum RC src_first_rc = rc_class(src_first);
881 enum RC dst_second_rc = rc_class(dst_second);
882 enum RC dst_first_rc = rc_class(dst_first);
883
884 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
885
886 // Generate spill code!
887 int size = 0;
888
889 if( src_first == dst_first && src_second == dst_second )
890 return size; // Self copy, no move
891
892 // --------------------------------------
893 // Check for mem-mem move. push/pop to move.
894 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
895 if( src_second == dst_first ) { // overlapping stack copy ranges
896 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
897 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
898 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
899 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
900 }
901 // move low bits
902 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
903 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
904 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
905 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
906 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
907 }
908 return size;
909 }
910
911 // --------------------------------------
912 // Check for integer reg-reg copy
913 if( src_first_rc == rc_int && dst_first_rc == rc_int )
914 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
915
916 // Check for integer store
917 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
918 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
919
920 // Check for integer load
921 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
922 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
923
924 // --------------------------------------
925 // Check for float reg-reg copy
926 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
927 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
928 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
929 if( cbuf ) {
930
931 // Note the mucking with the register encode to compensate for the 0/1
932 // indexing issue mentioned in a comment in the reg_def sections
933 // for FPR registers many lines above here.
934
935 if( src_first != FPR1L_num ) {
936 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
937 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
938 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
939 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
940 } else {
941 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
942 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
943 }
944 #ifndef PRODUCT
945 } else if( !do_size ) {
946 if( size != 0 ) st->print("\n\t");
947 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
948 else st->print( "FST %s", Matcher::regName[dst_first]);
949 #endif
950 }
951 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
952 }
953
954 // Check for float store
955 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
956 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
957 }
958
959 // Check for float load
960 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
961 int offset = ra_->reg2offset(src_first);
962 const char *op_str;
963 int op;
964 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
965 op_str = "FLD_D";
966 op = 0xDD;
967 } else { // 32-bit load
968 op_str = "FLD_S";
969 op = 0xD9;
970 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
971 }
972 if( cbuf ) {
973 emit_opcode (*cbuf, op );
974 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
975 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
976 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
977 #ifndef PRODUCT
978 } else if( !do_size ) {
979 if( size != 0 ) st->print("\n\t");
980 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
981 #endif
982 }
983 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
984 return size + 3+offset_size+2;
985 }
986
987 // Check for xmm reg-reg copy
988 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
989 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
990 (src_first+1 == src_second && dst_first+1 == dst_second),
991 "no non-adjacent float-moves" );
992 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
993 }
994
995 // Check for xmm store
996 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
997 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
998 }
999
1000 // Check for float xmm load
1001 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1002 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1003 }
1004
1005 // Copy from float reg to xmm reg
1006 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1007 // copy to the top of stack from floating point reg
1008 // and use LEA to preserve flags
1009 if( cbuf ) {
1010 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1011 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1012 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1013 emit_d8(*cbuf,0xF8);
1014 #ifndef PRODUCT
1015 } else if( !do_size ) {
1016 if( size != 0 ) st->print("\n\t");
1017 st->print("LEA ESP,[ESP-8]");
1018 #endif
1019 }
1020 size += 4;
1021
1022 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1023
1024 // Copy from the temp memory to the xmm reg.
1025 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1026
1027 if( cbuf ) {
1028 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1029 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1030 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1031 emit_d8(*cbuf,0x08);
1032 #ifndef PRODUCT
1033 } else if( !do_size ) {
1034 if( size != 0 ) st->print("\n\t");
1035 st->print("LEA ESP,[ESP+8]");
1036 #endif
1037 }
1038 size += 4;
1039 return size;
1040 }
1041
1042 assert( size > 0, "missed a case" );
1043
1044 // --------------------------------------------------------------------
1045 // Check for second bits still needing moving.
1046 if( src_second == dst_second )
1047 return size; // Self copy; no move
1048 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1049
1050 // Check for second word int-int move
1051 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1052 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1053
1054 // Check for second word integer store
1055 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1056 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1057
1058 // Check for second word integer load
1059 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1060 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1061
1062
1063 Unimplemented();
1064 }
1065
1066 #ifndef PRODUCT
1067 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1068 implementation( NULL, ra_, false, st );
1069 }
1070 #endif
1071
1072 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1073 implementation( &cbuf, ra_, false, NULL );
1074 }
1075
1076 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1077 return implementation( NULL, ra_, true, NULL );
1078 }
1079
1080 //=============================================================================
1081 #ifndef PRODUCT
1082 void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const {
1083 st->print("NOP \t# %d bytes pad for loops and calls", _count);
1084 }
1085 #endif
1086
1087 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1088 MacroAssembler _masm(&cbuf);
1089 __ nop(_count);
1090 }
1091
1092 uint MachNopNode::size(PhaseRegAlloc *) const {
1093 return _count;
1094 }
1095
1096
1097 //=============================================================================
1098 #ifndef PRODUCT
1099 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1100 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1101 int reg = ra_->get_reg_first(this);
1102 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1103 }
1104 #endif
1105
1106 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1107 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1108 int reg = ra_->get_encode(this);
1109 if( offset >= 128 ) {
1110 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1111 emit_rm(cbuf, 0x2, reg, 0x04);
1112 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1113 emit_d32(cbuf, offset);
1114 }
1115 else {
1116 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1117 emit_rm(cbuf, 0x1, reg, 0x04);
1118 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1119 emit_d8(cbuf, offset);
1120 }
1121 }
1122
1123 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1124 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1125 if( offset >= 128 ) {
1126 return 7;
1127 }
1128 else {
1129 return 4;
1130 }
1131 }
1132
1133 //=============================================================================
1134
1135 // emit call stub, compiled java to interpreter
1136 void emit_java_to_interp(CodeBuffer &cbuf ) {
1137 // Stub is fixed up when the corresponding call is converted from calling
1138 // compiled code to calling interpreted code.
1139 // mov rbx,0
1140 // jmp -1
1141
1142 address mark = cbuf.inst_mark(); // get mark within main instrs section
1143
1144 // Note that the code buffer's inst_mark is always relative to insts.
1145 // That's why we must use the macroassembler to generate a stub.
1146 MacroAssembler _masm(&cbuf);
1147
1148 address base =
1149 __ start_a_stub(Compile::MAX_stubs_size);
1150 if (base == NULL) return; // CodeBuffer::expand failed
1151 // static stub relocation stores the instruction address of the call
1152 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1153 // static stub relocation also tags the methodOop in the code-stream.
1154 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1155 // This is recognized as unresolved by relocs/nativeInst/ic code
1156 __ jump(RuntimeAddress(__ pc()));
1157
1158 __ end_a_stub();
1159 // Update current stubs pointer and restore code_end.
1160 }
1161 // size of call stub, compiled java to interpretor
1162 uint size_java_to_interp() {
1163 return 10; // movl; jmp
1164 }
1165 // relocation entries for call stub, compiled java to interpretor
1166 uint reloc_java_to_interp() {
1167 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1168 }
1169
1170 //=============================================================================
1171 #ifndef PRODUCT
1172 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1173 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1174 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1175 st->print_cr("\tNOP");
1176 st->print_cr("\tNOP");
1177 if( !OptoBreakpoint )
1178 st->print_cr("\tNOP");
1179 }
1180 #endif
1181
1182 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1183 MacroAssembler masm(&cbuf);
1184 #ifdef ASSERT
1185 uint code_size = cbuf.code_size();
1186 #endif
1187 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1188 masm.jump_cc(Assembler::notEqual,
1189 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1190 /* WARNING these NOPs are critical so that verified entry point is properly
1191 aligned for patching by NativeJump::patch_verified_entry() */
1192 int nops_cnt = 2;
1193 if( !OptoBreakpoint ) // Leave space for int3
1194 nops_cnt += 1;
1195 masm.nop(nops_cnt);
1196
1197 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node");
1198 }
1199
1200 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1201 return OptoBreakpoint ? 11 : 12;
1202 }
1203
1204
1205 //=============================================================================
1206 uint size_exception_handler() {
1207 // NativeCall instruction size is the same as NativeJump.
1208 // exception handler starts out as jump and can be patched to
1209 // a call be deoptimization. (4932387)
1210 // Note that this value is also credited (in output.cpp) to
1211 // the size of the code section.
1212 return NativeJump::instruction_size;
1213 }
1214
1215 // Emit exception handler code. Stuff framesize into a register
1216 // and call a VM stub routine.
1217 int emit_exception_handler(CodeBuffer& cbuf) {
1218
1219 // Note that the code buffer's inst_mark is always relative to insts.
1220 // That's why we must use the macroassembler to generate a handler.
1221 MacroAssembler _masm(&cbuf);
1222 address base =
1223 __ start_a_stub(size_exception_handler());
1224 if (base == NULL) return 0; // CodeBuffer::expand failed
1225 int offset = __ offset();
1226 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin()));
1227 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1228 __ end_a_stub();
1229 return offset;
1230 }
1231
1232 uint size_deopt_handler() {
1233 // NativeCall instruction size is the same as NativeJump.
1234 // exception handler starts out as jump and can be patched to
1235 // a call be deoptimization. (4932387)
1236 // Note that this value is also credited (in output.cpp) to
1237 // the size of the code section.
1238 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1239 }
1240
1241 // Emit deopt handler code.
1242 int emit_deopt_handler(CodeBuffer& cbuf) {
1243
1244 // Note that the code buffer's inst_mark is always relative to insts.
1245 // That's why we must use the macroassembler to generate a handler.
1246 MacroAssembler _masm(&cbuf);
1247 address base =
1248 __ start_a_stub(size_exception_handler());
1249 if (base == NULL) return 0; // CodeBuffer::expand failed
1250 int offset = __ offset();
1251 InternalAddress here(__ pc());
1252 __ pushptr(here.addr());
1253
1254 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1255 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1256 __ end_a_stub();
1257 return offset;
1258 }
1259
1260
1261 static void emit_double_constant(CodeBuffer& cbuf, double x) {
1262 int mark = cbuf.insts()->mark_off();
1263 MacroAssembler _masm(&cbuf);
1264 address double_address = __ double_constant(x);
1265 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1266 emit_d32_reloc(cbuf,
1267 (int)double_address,
1268 internal_word_Relocation::spec(double_address),
1269 RELOC_DISP32);
1270 }
1271
1272 static void emit_float_constant(CodeBuffer& cbuf, float x) {
1273 int mark = cbuf.insts()->mark_off();
1274 MacroAssembler _masm(&cbuf);
1275 address float_address = __ float_constant(x);
1276 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift
1277 emit_d32_reloc(cbuf,
1278 (int)float_address,
1279 internal_word_Relocation::spec(float_address),
1280 RELOC_DISP32);
1281 }
1282
1283
1284 int Matcher::regnum_to_fpu_offset(int regnum) {
1285 return regnum - 32; // The FP registers are in the second chunk
1286 }
1287
1288 bool is_positive_zero_float(jfloat f) {
1289 return jint_cast(f) == jint_cast(0.0F);
1290 }
1291
1292 bool is_positive_one_float(jfloat f) {
1293 return jint_cast(f) == jint_cast(1.0F);
1294 }
1295
1296 bool is_positive_zero_double(jdouble d) {
1297 return jlong_cast(d) == jlong_cast(0.0);
1298 }
1299
1300 bool is_positive_one_double(jdouble d) {
1301 return jlong_cast(d) == jlong_cast(1.0);
1302 }
1303
1304 // This is UltraSparc specific, true just means we have fast l2f conversion
1305 const bool Matcher::convL2FSupported(void) {
1306 return true;
1307 }
1308
1309 // Vector width in bytes
1310 const uint Matcher::vector_width_in_bytes(void) {
1311 return UseSSE >= 2 ? 8 : 0;
1312 }
1313
1314 // Vector ideal reg
1315 const uint Matcher::vector_ideal_reg(void) {
1316 return Op_RegD;
1317 }
1318
1319 // Is this branch offset short enough that a short branch can be used?
1320 //
1321 // NOTE: If the platform does not provide any short branch variants, then
1322 // this method should return false for offset 0.
1323 bool Matcher::is_short_branch_offset(int rule, int offset) {
1324 // the short version of jmpConUCF2 contains multiple branches,
1325 // making the reach slightly less
1326 if (rule == jmpConUCF2_rule)
1327 return (-126 <= offset && offset <= 125);
1328 return (-128 <= offset && offset <= 127);
1329 }
1330
1331 const bool Matcher::isSimpleConstant64(jlong value) {
1332 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1333 return false;
1334 }
1335
1336 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1337 const bool Matcher::init_array_count_is_in_bytes = false;
1338
1339 // Threshold size for cleararray.
1340 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1341
1342 // Should the Matcher clone shifts on addressing modes, expecting them to
1343 // be subsumed into complex addressing expressions or compute them into
1344 // registers? True for Intel but false for most RISCs
1345 const bool Matcher::clone_shift_expressions = true;
1346
1347 // Is it better to copy float constants, or load them directly from memory?
1348 // Intel can load a float constant from a direct address, requiring no
1349 // extra registers. Most RISCs will have to materialize an address into a
1350 // register first, so they would do better to copy the constant from stack.
1351 const bool Matcher::rematerialize_float_constants = true;
1352
1353 // If CPU can load and store mis-aligned doubles directly then no fixup is
1354 // needed. Else we split the double into 2 integer pieces and move it
1355 // piece-by-piece. Only happens when passing doubles into C code as the
1356 // Java calling convention forces doubles to be aligned.
1357 const bool Matcher::misaligned_doubles_ok = true;
1358
1359
1360 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1361 // Get the memory operand from the node
1362 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1363 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1364 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1365 uint opcnt = 1; // First operand
1366 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1367 while( idx >= skipped+num_edges ) {
1368 skipped += num_edges;
1369 opcnt++; // Bump operand count
1370 assert( opcnt < numopnds, "Accessing non-existent operand" );
1371 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1372 }
1373
1374 MachOper *memory = node->_opnds[opcnt];
1375 MachOper *new_memory = NULL;
1376 switch (memory->opcode()) {
1377 case DIRECT:
1378 case INDOFFSET32X:
1379 // No transformation necessary.
1380 return;
1381 case INDIRECT:
1382 new_memory = new (C) indirect_win95_safeOper( );
1383 break;
1384 case INDOFFSET8:
1385 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1386 break;
1387 case INDOFFSET32:
1388 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1389 break;
1390 case INDINDEXOFFSET:
1391 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1392 break;
1393 case INDINDEXSCALE:
1394 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1395 break;
1396 case INDINDEXSCALEOFFSET:
1397 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1398 break;
1399 case LOAD_LONG_INDIRECT:
1400 case LOAD_LONG_INDOFFSET32:
1401 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1402 return;
1403 default:
1404 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1405 return;
1406 }
1407 node->_opnds[opcnt] = new_memory;
1408 }
1409
1410 // Advertise here if the CPU requires explicit rounding operations
1411 // to implement the UseStrictFP mode.
1412 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1413
1414 // Do floats take an entire double register or just half?
1415 const bool Matcher::float_in_double = true;
1416 // Do ints take an entire long register or just half?
1417 const bool Matcher::int_in_long = false;
1418
1419 // Return whether or not this register is ever used as an argument. This
1420 // function is used on startup to build the trampoline stubs in generateOptoStub.
1421 // Registers not mentioned will be killed by the VM call in the trampoline, and
1422 // arguments in those registers not be available to the callee.
1423 bool Matcher::can_be_java_arg( int reg ) {
1424 if( reg == ECX_num || reg == EDX_num ) return true;
1425 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true;
1426 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1427 return false;
1428 }
1429
1430 bool Matcher::is_spillable_arg( int reg ) {
1431 return can_be_java_arg(reg);
1432 }
1433
1434 // Register for DIVI projection of divmodI
1435 RegMask Matcher::divI_proj_mask() {
1436 return EAX_REG_mask;
1437 }
1438
1439 // Register for MODI projection of divmodI
1440 RegMask Matcher::modI_proj_mask() {
1441 return EDX_REG_mask;
1442 }
1443
1444 // Register for DIVL projection of divmodL
1445 RegMask Matcher::divL_proj_mask() {
1446 ShouldNotReachHere();
1447 return RegMask();
1448 }
1449
1450 // Register for MODL projection of divmodL
1451 RegMask Matcher::modL_proj_mask() {
1452 ShouldNotReachHere();
1453 return RegMask();
1454 }
1455
1456 %}
1457
1458 //----------ENCODING BLOCK-----------------------------------------------------
1459 // This block specifies the encoding classes used by the compiler to output
1460 // byte streams. Encoding classes generate functions which are called by
1461 // Machine Instruction Nodes in order to generate the bit encoding of the
1462 // instruction. Operands specify their base encoding interface with the
1463 // interface keyword. There are currently supported four interfaces,
1464 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1465 // operand to generate a function which returns its register number when
1466 // queried. CONST_INTER causes an operand to generate a function which
1467 // returns the value of the constant when queried. MEMORY_INTER causes an
1468 // operand to generate four functions which return the Base Register, the
1469 // Index Register, the Scale Value, and the Offset Value of the operand when
1470 // queried. COND_INTER causes an operand to generate six functions which
1471 // return the encoding code (ie - encoding bits for the instruction)
1472 // associated with each basic boolean condition for a conditional instruction.
1473 // Instructions specify two basic values for encoding. They use the
1474 // ins_encode keyword to specify their encoding class (which must be one of
1475 // the class names specified in the encoding block), and they use the
1476 // opcode keyword to specify, in order, their primary, secondary, and
1477 // tertiary opcode. Only the opcode sections which a particular instruction
1478 // needs for encoding need to be specified.
1479 encode %{
1480 // Build emit functions for each basic byte or larger field in the intel
1481 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1482 // code in the enc_class source block. Emit functions will live in the
1483 // main source block for now. In future, we can generalize this by
1484 // adding a syntax that specifies the sizes of fields in an order,
1485 // so that the adlc can build the emit functions automagically
1486 enc_class OpcP %{ // Emit opcode
1487 emit_opcode(cbuf,$primary);
1488 %}
1489
1490 enc_class OpcS %{ // Emit opcode
1491 emit_opcode(cbuf,$secondary);
1492 %}
1493
1494 enc_class Opcode(immI d8 ) %{ // Emit opcode
1495 emit_opcode(cbuf,$d8$$constant);
1496 %}
1497
1498 enc_class SizePrefix %{
1499 emit_opcode(cbuf,0x66);
1500 %}
1501
1502 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
1503 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1504 %}
1505
1506 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many)
1507 emit_opcode(cbuf,$opcode$$constant);
1508 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1509 %}
1510
1511 enc_class mov_r32_imm0( eRegI dst ) %{
1512 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1513 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1514 %}
1515
1516 enc_class cdq_enc %{
1517 // Full implementation of Java idiv and irem; checks for
1518 // special case as described in JVM spec., p.243 & p.271.
1519 //
1520 // normal case special case
1521 //
1522 // input : rax,: dividend min_int
1523 // reg: divisor -1
1524 //
1525 // output: rax,: quotient (= rax, idiv reg) min_int
1526 // rdx: remainder (= rax, irem reg) 0
1527 //
1528 // Code sequnce:
1529 //
1530 // 81 F8 00 00 00 80 cmp rax,80000000h
1531 // 0F 85 0B 00 00 00 jne normal_case
1532 // 33 D2 xor rdx,edx
1533 // 83 F9 FF cmp rcx,0FFh
1534 // 0F 84 03 00 00 00 je done
1535 // normal_case:
1536 // 99 cdq
1537 // F7 F9 idiv rax,ecx
1538 // done:
1539 //
1540 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1541 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1542 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1543 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1544 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1545 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1546 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1547 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1548 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1549 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1550 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1551 // normal_case:
1552 emit_opcode(cbuf,0x99); // cdq
1553 // idiv (note: must be emitted by the user of this rule)
1554 // normal:
1555 %}
1556
1557 // Dense encoding for older common ops
1558 enc_class Opc_plus(immI opcode, eRegI reg) %{
1559 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1560 %}
1561
1562
1563 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1564 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1565 // Check for 8-bit immediate, and set sign extend bit in opcode
1566 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1567 emit_opcode(cbuf, $primary | 0x02);
1568 }
1569 else { // If 32-bit immediate
1570 emit_opcode(cbuf, $primary);
1571 }
1572 %}
1573
1574 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m
1575 // Emit primary opcode and set sign-extend bit
1576 // Check for 8-bit immediate, and set sign extend bit in opcode
1577 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1578 emit_opcode(cbuf, $primary | 0x02); }
1579 else { // If 32-bit immediate
1580 emit_opcode(cbuf, $primary);
1581 }
1582 // Emit r/m byte with secondary opcode, after primary opcode.
1583 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1584 %}
1585
1586 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1587 // Check for 8-bit immediate, and set sign extend bit in opcode
1588 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1589 $$$emit8$imm$$constant;
1590 }
1591 else { // If 32-bit immediate
1592 // Output immediate
1593 $$$emit32$imm$$constant;
1594 }
1595 %}
1596
1597 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1598 // Emit primary opcode and set sign-extend bit
1599 // Check for 8-bit immediate, and set sign extend bit in opcode
1600 int con = (int)$imm$$constant; // Throw away top bits
1601 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1602 // Emit r/m byte with secondary opcode, after primary opcode.
1603 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1604 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1605 else emit_d32(cbuf,con);
1606 %}
1607
1608 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1609 // Emit primary opcode and set sign-extend bit
1610 // Check for 8-bit immediate, and set sign extend bit in opcode
1611 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1612 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1613 // Emit r/m byte with tertiary opcode, after primary opcode.
1614 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1615 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1616 else emit_d32(cbuf,con);
1617 %}
1618
1619 enc_class Lbl (label labl) %{ // JMP, CALL
1620 Label *l = $labl$$label;
1621 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1622 %}
1623
1624 enc_class LblShort (label labl) %{ // JMP, CALL
1625 Label *l = $labl$$label;
1626 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1627 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1628 emit_d8(cbuf, disp);
1629 %}
1630
1631 enc_class OpcSReg (eRegI dst) %{ // BSWAP
1632 emit_cc(cbuf, $secondary, $dst$$reg );
1633 %}
1634
1635 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1636 int destlo = $dst$$reg;
1637 int desthi = HIGH_FROM_LOW(destlo);
1638 // bswap lo
1639 emit_opcode(cbuf, 0x0F);
1640 emit_cc(cbuf, 0xC8, destlo);
1641 // bswap hi
1642 emit_opcode(cbuf, 0x0F);
1643 emit_cc(cbuf, 0xC8, desthi);
1644 // xchg lo and hi
1645 emit_opcode(cbuf, 0x87);
1646 emit_rm(cbuf, 0x3, destlo, desthi);
1647 %}
1648
1649 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1650 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1651 %}
1652
1653 enc_class Jcc (cmpOp cop, label labl) %{ // JCC
1654 Label *l = $labl$$label;
1655 $$$emit8$primary;
1656 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1657 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0);
1658 %}
1659
1660 enc_class JccShort (cmpOp cop, label labl) %{ // JCC
1661 Label *l = $labl$$label;
1662 emit_cc(cbuf, $primary, $cop$$cmpcode);
1663 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0;
1664 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
1665 emit_d8(cbuf, disp);
1666 %}
1667
1668 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1669 $$$emit8$primary;
1670 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1671 %}
1672
1673 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV
1674 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1675 emit_d8(cbuf, op >> 8 );
1676 emit_d8(cbuf, op & 255);
1677 %}
1678
1679 // emulate a CMOV with a conditional branch around a MOV
1680 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1681 // Invert sense of branch from sense of CMOV
1682 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1683 emit_d8( cbuf, $brOffs$$constant );
1684 %}
1685
1686 enc_class enc_PartialSubtypeCheck( ) %{
1687 Register Redi = as_Register(EDI_enc); // result register
1688 Register Reax = as_Register(EAX_enc); // super class
1689 Register Recx = as_Register(ECX_enc); // killed
1690 Register Resi = as_Register(ESI_enc); // sub class
1691 Label hit, miss;
1692
1693 MacroAssembler _masm(&cbuf);
1694 // Compare super with sub directly, since super is not in its own SSA.
1695 // The compiler used to emit this test, but we fold it in here,
1696 // to allow platform-specific tweaking on sparc.
1697 __ cmpptr(Reax, Resi);
1698 __ jcc(Assembler::equal, hit);
1699 #ifndef PRODUCT
1700 __ incrementl(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1701 #endif //PRODUCT
1702 __ movptr(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes()));
1703 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes()));
1704 __ addptr(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT));
1705 __ repne_scan();
1706 __ jcc(Assembler::notEqual, miss);
1707 __ movptr(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax);
1708 __ bind(hit);
1709 if( $primary )
1710 __ xorptr(Redi,Redi);
1711 __ bind(miss);
1712 %}
1713
1714 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1715 MacroAssembler masm(&cbuf);
1716 int start = masm.offset();
1717 if (UseSSE >= 2) {
1718 if (VerifyFPU) {
1719 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1720 }
1721 } else {
1722 // External c_calling_convention expects the FPU stack to be 'clean'.
1723 // Compiled code leaves it dirty. Do cleanup now.
1724 masm.empty_FPU_stack();
1725 }
1726 if (sizeof_FFree_Float_Stack_All == -1) {
1727 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1728 } else {
1729 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1730 }
1731 %}
1732
1733 enc_class Verify_FPU_For_Leaf %{
1734 if( VerifyFPU ) {
1735 MacroAssembler masm(&cbuf);
1736 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1737 }
1738 %}
1739
1740 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1741 // This is the instruction starting address for relocation info.
1742 cbuf.set_inst_mark();
1743 $$$emit8$primary;
1744 // CALL directly to the runtime
1745 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1746 runtime_call_Relocation::spec(), RELOC_IMM32 );
1747
1748 if (UseSSE >= 2) {
1749 MacroAssembler _masm(&cbuf);
1750 BasicType rt = tf()->return_type();
1751
1752 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1753 // A C runtime call where the return value is unused. In SSE2+
1754 // mode the result needs to be removed from the FPU stack. It's
1755 // likely that this function call could be removed by the
1756 // optimizer if the C function is a pure function.
1757 __ ffree(0);
1758 } else if (rt == T_FLOAT) {
1759 __ lea(rsp, Address(rsp, -4));
1760 __ fstp_s(Address(rsp, 0));
1761 __ movflt(xmm0, Address(rsp, 0));
1762 __ lea(rsp, Address(rsp, 4));
1763 } else if (rt == T_DOUBLE) {
1764 __ lea(rsp, Address(rsp, -8));
1765 __ fstp_d(Address(rsp, 0));
1766 __ movdbl(xmm0, Address(rsp, 0));
1767 __ lea(rsp, Address(rsp, 8));
1768 }
1769 }
1770 %}
1771
1772
1773 enc_class pre_call_FPU %{
1774 // If method sets FPU control word restore it here
1775 if( Compile::current()->in_24_bit_fp_mode() ) {
1776 MacroAssembler masm(&cbuf);
1777 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1778 }
1779 %}
1780
1781 enc_class post_call_FPU %{
1782 // If method sets FPU control word do it here also
1783 if( Compile::current()->in_24_bit_fp_mode() ) {
1784 MacroAssembler masm(&cbuf);
1785 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1786 }
1787 %}
1788
1789 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1790 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1791 // who we intended to call.
1792 cbuf.set_inst_mark();
1793 $$$emit8$primary;
1794 if ( !_method ) {
1795 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1796 runtime_call_Relocation::spec(), RELOC_IMM32 );
1797 } else if(_optimized_virtual) {
1798 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1799 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1800 } else {
1801 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1802 static_call_Relocation::spec(), RELOC_IMM32 );
1803 }
1804 if( _method ) { // Emit stub for static call
1805 emit_java_to_interp(cbuf);
1806 }
1807 %}
1808
1809 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1810 // !!!!!
1811 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1812 // emit_call_dynamic_prologue( cbuf );
1813 cbuf.set_inst_mark();
1814 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1815 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1816 address virtual_call_oop_addr = cbuf.inst_mark();
1817 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1818 // who we intended to call.
1819 cbuf.set_inst_mark();
1820 $$$emit8$primary;
1821 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4),
1822 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1823 %}
1824
1825 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1826 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1827 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1828
1829 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1830 cbuf.set_inst_mark();
1831 $$$emit8$primary;
1832 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1833 emit_d8(cbuf, disp); // Displacement
1834
1835 %}
1836
1837 enc_class Xor_Reg (eRegI dst) %{
1838 emit_opcode(cbuf, 0x33);
1839 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
1840 %}
1841
1842 // Following encoding is no longer used, but may be restored if calling
1843 // convention changes significantly.
1844 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1845 //
1846 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1847 // // int ic_reg = Matcher::inline_cache_reg();
1848 // // int ic_encode = Matcher::_regEncode[ic_reg];
1849 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1850 // // int imo_encode = Matcher::_regEncode[imo_reg];
1851 //
1852 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1853 // // // so we load it immediately before the call
1854 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1855 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1856 //
1857 // // xor rbp,ebp
1858 // emit_opcode(cbuf, 0x33);
1859 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1860 //
1861 // // CALL to interpreter.
1862 // cbuf.set_inst_mark();
1863 // $$$emit8$primary;
1864 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4),
1865 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1866 // %}
1867
1868 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1869 $$$emit8$primary;
1870 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1871 $$$emit8$shift$$constant;
1872 %}
1873
1874 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate
1875 // Load immediate does not have a zero or sign extended version
1876 // for 8-bit immediates
1877 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1878 $$$emit32$src$$constant;
1879 %}
1880
1881 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate
1882 // Load immediate does not have a zero or sign extended version
1883 // for 8-bit immediates
1884 emit_opcode(cbuf, $primary + $dst$$reg);
1885 $$$emit32$src$$constant;
1886 %}
1887
1888 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1889 // Load immediate does not have a zero or sign extended version
1890 // for 8-bit immediates
1891 int dst_enc = $dst$$reg;
1892 int src_con = $src$$constant & 0x0FFFFFFFFL;
1893 if (src_con == 0) {
1894 // xor dst, dst
1895 emit_opcode(cbuf, 0x33);
1896 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1897 } else {
1898 emit_opcode(cbuf, $primary + dst_enc);
1899 emit_d32(cbuf, src_con);
1900 }
1901 %}
1902
1903 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
1904 // Load immediate does not have a zero or sign extended version
1905 // for 8-bit immediates
1906 int dst_enc = $dst$$reg + 2;
1907 int src_con = ((julong)($src$$constant)) >> 32;
1908 if (src_con == 0) {
1909 // xor dst, dst
1910 emit_opcode(cbuf, 0x33);
1911 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
1912 } else {
1913 emit_opcode(cbuf, $primary + dst_enc);
1914 emit_d32(cbuf, src_con);
1915 }
1916 %}
1917
1918
1919 enc_class LdImmD (immD src) %{ // Load Immediate
1920 if( is_positive_zero_double($src$$constant)) {
1921 // FLDZ
1922 emit_opcode(cbuf,0xD9);
1923 emit_opcode(cbuf,0xEE);
1924 } else if( is_positive_one_double($src$$constant)) {
1925 // FLD1
1926 emit_opcode(cbuf,0xD9);
1927 emit_opcode(cbuf,0xE8);
1928 } else {
1929 emit_opcode(cbuf,0xDD);
1930 emit_rm(cbuf, 0x0, 0x0, 0x5);
1931 emit_double_constant(cbuf, $src$$constant);
1932 }
1933 %}
1934
1935
1936 enc_class LdImmF (immF src) %{ // Load Immediate
1937 if( is_positive_zero_float($src$$constant)) {
1938 emit_opcode(cbuf,0xD9);
1939 emit_opcode(cbuf,0xEE);
1940 } else if( is_positive_one_float($src$$constant)) {
1941 emit_opcode(cbuf,0xD9);
1942 emit_opcode(cbuf,0xE8);
1943 } else {
1944 $$$emit8$primary;
1945 // Load immediate does not have a zero or sign extended version
1946 // for 8-bit immediates
1947 // First load to TOS, then move to dst
1948 emit_rm(cbuf, 0x0, 0x0, 0x5);
1949 emit_float_constant(cbuf, $src$$constant);
1950 }
1951 %}
1952
1953 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate
1954 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1955 emit_float_constant(cbuf, $con$$constant);
1956 %}
1957
1958 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate
1959 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1960 emit_double_constant(cbuf, $con$$constant);
1961 %}
1962
1963 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant
1964 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con)
1965 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
1966 emit_opcode(cbuf, 0x0F);
1967 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
1968 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
1969 emit_double_constant(cbuf, $con$$constant);
1970 %}
1971
1972 enc_class Opc_MemImm_F(immF src) %{
1973 cbuf.set_inst_mark();
1974 $$$emit8$primary;
1975 emit_rm(cbuf, 0x0, $secondary, 0x5);
1976 emit_float_constant(cbuf, $src$$constant);
1977 %}
1978
1979
1980 enc_class MovI2X_reg(regX dst, eRegI src) %{
1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1982 emit_opcode(cbuf, 0x0F );
1983 emit_opcode(cbuf, 0x6E );
1984 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1985 %}
1986
1987 enc_class MovX2I_reg(eRegI dst, regX src) %{
1988 emit_opcode(cbuf, 0x66 ); // MOVD dst,src
1989 emit_opcode(cbuf, 0x0F );
1990 emit_opcode(cbuf, 0x7E );
1991 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
1992 %}
1993
1994 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{
1995 { // MOVD $dst,$src.lo
1996 emit_opcode(cbuf,0x66);
1997 emit_opcode(cbuf,0x0F);
1998 emit_opcode(cbuf,0x6E);
1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2000 }
2001 { // MOVD $tmp,$src.hi
2002 emit_opcode(cbuf,0x66);
2003 emit_opcode(cbuf,0x0F);
2004 emit_opcode(cbuf,0x6E);
2005 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2006 }
2007 { // PUNPCKLDQ $dst,$tmp
2008 emit_opcode(cbuf,0x66);
2009 emit_opcode(cbuf,0x0F);
2010 emit_opcode(cbuf,0x62);
2011 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg);
2012 }
2013 %}
2014
2015 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{
2016 { // MOVD $dst.lo,$src
2017 emit_opcode(cbuf,0x66);
2018 emit_opcode(cbuf,0x0F);
2019 emit_opcode(cbuf,0x7E);
2020 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg);
2021 }
2022 { // PSHUFLW $tmp,$src,0x4E (01001110b)
2023 emit_opcode(cbuf,0xF2);
2024 emit_opcode(cbuf,0x0F);
2025 emit_opcode(cbuf,0x70);
2026 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2027 emit_d8(cbuf, 0x4E);
2028 }
2029 { // MOVD $dst.hi,$tmp
2030 emit_opcode(cbuf,0x66);
2031 emit_opcode(cbuf,0x0F);
2032 emit_opcode(cbuf,0x7E);
2033 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
2034 }
2035 %}
2036
2037
2038 // Encode a reg-reg copy. If it is useless, then empty encoding.
2039 enc_class enc_Copy( eRegI dst, eRegI src ) %{
2040 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2041 %}
2042
2043 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{
2044 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2045 %}
2046
2047 // Encode xmm reg-reg copy. If it is useless, then empty encoding.
2048 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{
2049 encode_CopyXD( cbuf, $dst$$reg, $src$$reg );
2050 %}
2051
2052 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many)
2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2054 %}
2055
2056 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2057 $$$emit8$primary;
2058 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2059 %}
2060
2061 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2062 $$$emit8$secondary;
2063 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2064 %}
2065
2066 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2067 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2068 %}
2069
2070 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2071 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2072 %}
2073
2074 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{
2075 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2076 %}
2077
2078 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2079 // Output immediate
2080 $$$emit32$src$$constant;
2081 %}
2082
2083 enc_class Con32F_as_bits(immF src) %{ // storeF_imm
2084 // Output Float immediate bits
2085 jfloat jf = $src$$constant;
2086 int jf_as_bits = jint_cast( jf );
2087 emit_d32(cbuf, jf_as_bits);
2088 %}
2089
2090 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm
2091 // Output Float immediate bits
2092 jfloat jf = $src$$constant;
2093 int jf_as_bits = jint_cast( jf );
2094 emit_d32(cbuf, jf_as_bits);
2095 %}
2096
2097 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2098 // Output immediate
2099 $$$emit16$src$$constant;
2100 %}
2101
2102 enc_class Con_d32(immI src) %{
2103 emit_d32(cbuf,$src$$constant);
2104 %}
2105
2106 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2107 // Output immediate memory reference
2108 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2109 emit_d32(cbuf, 0x00);
2110 %}
2111
2112 enc_class lock_prefix( ) %{
2113 if( os::is_MP() )
2114 emit_opcode(cbuf,0xF0); // [Lock]
2115 %}
2116
2117 // Cmp-xchg long value.
2118 // Note: we need to swap rbx, and rcx before and after the
2119 // cmpxchg8 instruction because the instruction uses
2120 // rcx as the high order word of the new value to store but
2121 // our register encoding uses rbx,.
2122 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2123
2124 // XCHG rbx,ecx
2125 emit_opcode(cbuf,0x87);
2126 emit_opcode(cbuf,0xD9);
2127 // [Lock]
2128 if( os::is_MP() )
2129 emit_opcode(cbuf,0xF0);
2130 // CMPXCHG8 [Eptr]
2131 emit_opcode(cbuf,0x0F);
2132 emit_opcode(cbuf,0xC7);
2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2134 // XCHG rbx,ecx
2135 emit_opcode(cbuf,0x87);
2136 emit_opcode(cbuf,0xD9);
2137 %}
2138
2139 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2140 // [Lock]
2141 if( os::is_MP() )
2142 emit_opcode(cbuf,0xF0);
2143
2144 // CMPXCHG [Eptr]
2145 emit_opcode(cbuf,0x0F);
2146 emit_opcode(cbuf,0xB1);
2147 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2148 %}
2149
2150 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2151 int res_encoding = $res$$reg;
2152
2153 // MOV res,0
2154 emit_opcode( cbuf, 0xB8 + res_encoding);
2155 emit_d32( cbuf, 0 );
2156 // JNE,s fail
2157 emit_opcode(cbuf,0x75);
2158 emit_d8(cbuf, 5 );
2159 // MOV res,1
2160 emit_opcode( cbuf, 0xB8 + res_encoding);
2161 emit_d32( cbuf, 1 );
2162 // fail:
2163 %}
2164
2165 enc_class set_instruction_start( ) %{
2166 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2167 %}
2168
2169 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem
2170 int reg_encoding = $ereg$$reg;
2171 int base = $mem$$base;
2172 int index = $mem$$index;
2173 int scale = $mem$$scale;
2174 int displace = $mem$$disp;
2175 bool disp_is_oop = $mem->disp_is_oop();
2176 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2177 %}
2178
2179 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2180 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2181 int base = $mem$$base;
2182 int index = $mem$$index;
2183 int scale = $mem$$scale;
2184 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2185 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2186 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2187 %}
2188
2189 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2190 int r1, r2;
2191 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2192 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2193 emit_opcode(cbuf,0x0F);
2194 emit_opcode(cbuf,$tertiary);
2195 emit_rm(cbuf, 0x3, r1, r2);
2196 emit_d8(cbuf,$cnt$$constant);
2197 emit_d8(cbuf,$primary);
2198 emit_rm(cbuf, 0x3, $secondary, r1);
2199 emit_d8(cbuf,$cnt$$constant);
2200 %}
2201
2202 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2203 emit_opcode( cbuf, 0x8B ); // Move
2204 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2205 emit_d8(cbuf,$primary);
2206 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2207 emit_d8(cbuf,$cnt$$constant-32);
2208 emit_d8(cbuf,$primary);
2209 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2210 emit_d8(cbuf,31);
2211 %}
2212
2213 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2214 int r1, r2;
2215 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2216 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2217
2218 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2219 emit_rm(cbuf, 0x3, r1, r2);
2220 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2221 emit_opcode(cbuf,$primary);
2222 emit_rm(cbuf, 0x3, $secondary, r1);
2223 emit_d8(cbuf,$cnt$$constant-32);
2224 }
2225 emit_opcode(cbuf,0x33); // XOR r2,r2
2226 emit_rm(cbuf, 0x3, r2, r2);
2227 %}
2228
2229 // Clone of RegMem but accepts an extra parameter to access each
2230 // half of a double in memory; it never needs relocation info.
2231 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{
2232 emit_opcode(cbuf,$opcode$$constant);
2233 int reg_encoding = $rm_reg$$reg;
2234 int base = $mem$$base;
2235 int index = $mem$$index;
2236 int scale = $mem$$scale;
2237 int displace = $mem$$disp + $disp_for_half$$constant;
2238 bool disp_is_oop = false;
2239 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2240 %}
2241
2242 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2243 //
2244 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2245 // and it never needs relocation information.
2246 // Frequently used to move data between FPU's Stack Top and memory.
2247 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2248 int rm_byte_opcode = $rm_opcode$$constant;
2249 int base = $mem$$base;
2250 int index = $mem$$index;
2251 int scale = $mem$$scale;
2252 int displace = $mem$$disp;
2253 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2254 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2255 %}
2256
2257 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2258 int rm_byte_opcode = $rm_opcode$$constant;
2259 int base = $mem$$base;
2260 int index = $mem$$index;
2261 int scale = $mem$$scale;
2262 int displace = $mem$$disp;
2263 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2264 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2265 %}
2266
2267 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea
2268 int reg_encoding = $dst$$reg;
2269 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2270 int index = 0x04; // 0x04 indicates no index
2271 int scale = 0x00; // 0x00 indicates no scale
2272 int displace = $src1$$constant; // 0x00 indicates no displacement
2273 bool disp_is_oop = false;
2274 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2275 %}
2276
2277 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN
2278 // Compare dst,src
2279 emit_opcode(cbuf,0x3B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 // jmp dst < src around move
2282 emit_opcode(cbuf,0x7C);
2283 emit_d8(cbuf,2);
2284 // move dst,src
2285 emit_opcode(cbuf,0x8B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 %}
2288
2289 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX
2290 // Compare dst,src
2291 emit_opcode(cbuf,0x3B);
2292 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2293 // jmp dst > src around move
2294 emit_opcode(cbuf,0x7F);
2295 emit_d8(cbuf,2);
2296 // move dst,src
2297 emit_opcode(cbuf,0x8B);
2298 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2299 %}
2300
2301 enc_class enc_FP_store(memory mem, regD src) %{
2302 // If src is FPR1, we can just FST to store it.
2303 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2304 int reg_encoding = 0x2; // Just store
2305 int base = $mem$$base;
2306 int index = $mem$$index;
2307 int scale = $mem$$scale;
2308 int displace = $mem$$disp;
2309 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2310 if( $src$$reg != FPR1L_enc ) {
2311 reg_encoding = 0x3; // Store & pop
2312 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2313 emit_d8( cbuf, 0xC0-1+$src$$reg );
2314 }
2315 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2316 emit_opcode(cbuf,$primary);
2317 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2318 %}
2319
2320 enc_class neg_reg(eRegI dst) %{
2321 // NEG $dst
2322 emit_opcode(cbuf,0xF7);
2323 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2324 %}
2325
2326 enc_class setLT_reg(eCXRegI dst) %{
2327 // SETLT $dst
2328 emit_opcode(cbuf,0x0F);
2329 emit_opcode(cbuf,0x9C);
2330 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2331 %}
2332
2333 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2334 int tmpReg = $tmp$$reg;
2335
2336 // SUB $p,$q
2337 emit_opcode(cbuf,0x2B);
2338 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2339 // SBB $tmp,$tmp
2340 emit_opcode(cbuf,0x1B);
2341 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2342 // AND $tmp,$y
2343 emit_opcode(cbuf,0x23);
2344 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2345 // ADD $p,$tmp
2346 emit_opcode(cbuf,0x03);
2347 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2348 %}
2349
2350 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT
2351 int tmpReg = $tmp$$reg;
2352
2353 // SUB $p,$q
2354 emit_opcode(cbuf,0x2B);
2355 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2356 // SBB $tmp,$tmp
2357 emit_opcode(cbuf,0x1B);
2358 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2359 // AND $tmp,$y
2360 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand
2361 emit_opcode(cbuf,0x23);
2362 int reg_encoding = tmpReg;
2363 int base = $mem$$base;
2364 int index = $mem$$index;
2365 int scale = $mem$$scale;
2366 int displace = $mem$$disp;
2367 bool disp_is_oop = $mem->disp_is_oop();
2368 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2369 // ADD $p,$tmp
2370 emit_opcode(cbuf,0x03);
2371 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2372 %}
2373
2374 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2375 // TEST shift,32
2376 emit_opcode(cbuf,0xF7);
2377 emit_rm(cbuf, 0x3, 0, ECX_enc);
2378 emit_d32(cbuf,0x20);
2379 // JEQ,s small
2380 emit_opcode(cbuf, 0x74);
2381 emit_d8(cbuf, 0x04);
2382 // MOV $dst.hi,$dst.lo
2383 emit_opcode( cbuf, 0x8B );
2384 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2385 // CLR $dst.lo
2386 emit_opcode(cbuf, 0x33);
2387 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2388 // small:
2389 // SHLD $dst.hi,$dst.lo,$shift
2390 emit_opcode(cbuf,0x0F);
2391 emit_opcode(cbuf,0xA5);
2392 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2393 // SHL $dst.lo,$shift"
2394 emit_opcode(cbuf,0xD3);
2395 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2396 %}
2397
2398 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2399 // TEST shift,32
2400 emit_opcode(cbuf,0xF7);
2401 emit_rm(cbuf, 0x3, 0, ECX_enc);
2402 emit_d32(cbuf,0x20);
2403 // JEQ,s small
2404 emit_opcode(cbuf, 0x74);
2405 emit_d8(cbuf, 0x04);
2406 // MOV $dst.lo,$dst.hi
2407 emit_opcode( cbuf, 0x8B );
2408 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2409 // CLR $dst.hi
2410 emit_opcode(cbuf, 0x33);
2411 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2412 // small:
2413 // SHRD $dst.lo,$dst.hi,$shift
2414 emit_opcode(cbuf,0x0F);
2415 emit_opcode(cbuf,0xAD);
2416 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2417 // SHR $dst.hi,$shift"
2418 emit_opcode(cbuf,0xD3);
2419 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2420 %}
2421
2422 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2423 // TEST shift,32
2424 emit_opcode(cbuf,0xF7);
2425 emit_rm(cbuf, 0x3, 0, ECX_enc);
2426 emit_d32(cbuf,0x20);
2427 // JEQ,s small
2428 emit_opcode(cbuf, 0x74);
2429 emit_d8(cbuf, 0x05);
2430 // MOV $dst.lo,$dst.hi
2431 emit_opcode( cbuf, 0x8B );
2432 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2433 // SAR $dst.hi,31
2434 emit_opcode(cbuf, 0xC1);
2435 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2436 emit_d8(cbuf, 0x1F );
2437 // small:
2438 // SHRD $dst.lo,$dst.hi,$shift
2439 emit_opcode(cbuf,0x0F);
2440 emit_opcode(cbuf,0xAD);
2441 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2442 // SAR $dst.hi,$shift"
2443 emit_opcode(cbuf,0xD3);
2444 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2445 %}
2446
2447
2448 // ----------------- Encodings for floating point unit -----------------
2449 // May leave result in FPU-TOS or FPU reg depending on opcodes
2450 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV
2451 $$$emit8$primary;
2452 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2453 %}
2454
2455 // Pop argument in FPR0 with FSTP ST(0)
2456 enc_class PopFPU() %{
2457 emit_opcode( cbuf, 0xDD );
2458 emit_d8( cbuf, 0xD8 );
2459 %}
2460
2461 // !!!!! equivalent to Pop_Reg_F
2462 enc_class Pop_Reg_D( regD dst ) %{
2463 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2464 emit_d8( cbuf, 0xD8+$dst$$reg );
2465 %}
2466
2467 enc_class Push_Reg_D( regD dst ) %{
2468 emit_opcode( cbuf, 0xD9 );
2469 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2470 %}
2471
2472 enc_class strictfp_bias1( regD dst ) %{
2473 emit_opcode( cbuf, 0xDB ); // FLD m80real
2474 emit_opcode( cbuf, 0x2D );
2475 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2476 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2477 emit_opcode( cbuf, 0xC8+$dst$$reg );
2478 %}
2479
2480 enc_class strictfp_bias2( regD dst ) %{
2481 emit_opcode( cbuf, 0xDB ); // FLD m80real
2482 emit_opcode( cbuf, 0x2D );
2483 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2484 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2485 emit_opcode( cbuf, 0xC8+$dst$$reg );
2486 %}
2487
2488 // Special case for moving an integer register to a stack slot.
2489 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2490 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2491 %}
2492
2493 // Special case for moving a register to a stack slot.
2494 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS
2495 // Opcode already emitted
2496 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2497 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2498 emit_d32(cbuf, $dst$$disp); // Displacement
2499 %}
2500
2501 // Push the integer in stackSlot 'src' onto FP-stack
2502 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2503 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2504 %}
2505
2506 // Push the float in stackSlot 'src' onto FP-stack
2507 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src]
2508 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp );
2509 %}
2510
2511 // Push the double in stackSlot 'src' onto FP-stack
2512 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src]
2513 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp );
2514 %}
2515
2516 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2517 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2518 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2519 %}
2520
2521 // Same as Pop_Mem_F except for opcode
2522 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2523 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2524 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2525 %}
2526
2527 enc_class Pop_Reg_F( regF dst ) %{
2528 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2529 emit_d8( cbuf, 0xD8+$dst$$reg );
2530 %}
2531
2532 enc_class Push_Reg_F( regF dst ) %{
2533 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2534 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2535 %}
2536
2537 // Push FPU's float to a stack-slot, and pop FPU-stack
2538 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{
2539 int pop = 0x02;
2540 if ($src$$reg != FPR1L_enc) {
2541 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2542 emit_d8( cbuf, 0xC0-1+$src$$reg );
2543 pop = 0x03;
2544 }
2545 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2546 %}
2547
2548 // Push FPU's double to a stack-slot, and pop FPU-stack
2549 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{
2550 int pop = 0x02;
2551 if ($src$$reg != FPR1L_enc) {
2552 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2553 emit_d8( cbuf, 0xC0-1+$src$$reg );
2554 pop = 0x03;
2555 }
2556 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2557 %}
2558
2559 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2560 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{
2561 int pop = 0xD0 - 1; // -1 since we skip FLD
2562 if ($src$$reg != FPR1L_enc) {
2563 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2564 emit_d8( cbuf, 0xC0-1+$src$$reg );
2565 pop = 0xD8;
2566 }
2567 emit_opcode( cbuf, 0xDD );
2568 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2569 %}
2570
2571
2572 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{
2573 MacroAssembler masm(&cbuf);
2574 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg
2575 masm.fmul( $src2$$reg+0); // value at TOS
2576 masm.fadd( $src$$reg+0); // value at TOS
2577 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store
2578 %}
2579
2580
2581 enc_class Push_Reg_Mod_D( regD dst, regD src) %{
2582 // load dst in FPR0
2583 emit_opcode( cbuf, 0xD9 );
2584 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2585 if ($src$$reg != FPR1L_enc) {
2586 // fincstp
2587 emit_opcode (cbuf, 0xD9);
2588 emit_opcode (cbuf, 0xF7);
2589 // swap src with FPR1:
2590 // FXCH FPR1 with src
2591 emit_opcode(cbuf, 0xD9);
2592 emit_d8(cbuf, 0xC8-1+$src$$reg );
2593 // fdecstp
2594 emit_opcode (cbuf, 0xD9);
2595 emit_opcode (cbuf, 0xF6);
2596 }
2597 %}
2598
2599 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{
2600 // Allocate a word
2601 emit_opcode(cbuf,0x83); // SUB ESP,8
2602 emit_opcode(cbuf,0xEC);
2603 emit_d8(cbuf,0x08);
2604
2605 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1
2606 emit_opcode (cbuf, 0x0F );
2607 emit_opcode (cbuf, 0x11 );
2608 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2609
2610 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2611 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2612
2613 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0
2614 emit_opcode (cbuf, 0x0F );
2615 emit_opcode (cbuf, 0x11 );
2616 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2617
2618 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2619 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2620
2621 %}
2622
2623 enc_class Push_ModX_encoding( regX src0, regX src1) %{
2624 // Allocate a word
2625 emit_opcode(cbuf,0x83); // SUB ESP,4
2626 emit_opcode(cbuf,0xEC);
2627 emit_d8(cbuf,0x04);
2628
2629 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1
2630 emit_opcode (cbuf, 0x0F );
2631 emit_opcode (cbuf, 0x11 );
2632 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false);
2633
2634 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2635 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2636
2637 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0
2638 emit_opcode (cbuf, 0x0F );
2639 emit_opcode (cbuf, 0x11 );
2640 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false);
2641
2642 emit_opcode(cbuf,0xD9 ); // FLD [ESP]
2643 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2644
2645 %}
2646
2647 enc_class Push_ResultXD(regXD dst) %{
2648 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP]
2649
2650 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp]
2651 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
2652 emit_opcode (cbuf, 0x0F );
2653 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12);
2654 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2655
2656 emit_opcode(cbuf,0x83); // ADD ESP,8
2657 emit_opcode(cbuf,0xC4);
2658 emit_d8(cbuf,0x08);
2659 %}
2660
2661 enc_class Push_ResultX(regX dst, immI d8) %{
2662 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP]
2663
2664 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
2665 emit_opcode (cbuf, 0x0F );
2666 emit_opcode (cbuf, 0x10 );
2667 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
2668
2669 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8)
2670 emit_opcode(cbuf,0xC4);
2671 emit_d8(cbuf,$d8$$constant);
2672 %}
2673
2674 enc_class Push_SrcXD(regXD src) %{
2675 // Allocate a word
2676 emit_opcode(cbuf,0x83); // SUB ESP,8
2677 emit_opcode(cbuf,0xEC);
2678 emit_d8(cbuf,0x08);
2679
2680 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
2681 emit_opcode (cbuf, 0x0F );
2682 emit_opcode (cbuf, 0x11 );
2683 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
2684
2685 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2686 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2687 %}
2688
2689 enc_class push_stack_temp_qword() %{
2690 emit_opcode(cbuf,0x83); // SUB ESP,8
2691 emit_opcode(cbuf,0xEC);
2692 emit_d8 (cbuf,0x08);
2693 %}
2694
2695 enc_class pop_stack_temp_qword() %{
2696 emit_opcode(cbuf,0x83); // ADD ESP,8
2697 emit_opcode(cbuf,0xC4);
2698 emit_d8 (cbuf,0x08);
2699 %}
2700
2701 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{
2702 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src
2703 emit_opcode (cbuf, 0x0F );
2704 emit_opcode (cbuf, 0x11 );
2705 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false);
2706
2707 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
2708 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2709 %}
2710
2711 // Compute X^Y using Intel's fast hardware instructions, if possible.
2712 // Otherwise return a NaN.
2713 enc_class pow_exp_core_encoding %{
2714 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X))
2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q
2716 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q
2717 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q)
2718 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q)
2719 emit_opcode(cbuf,0x1C);
2720 emit_d8(cbuf,0x24);
2721 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1
2722 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1
2723 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q)
2724 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q)
2725 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false);
2726 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask
2727 emit_rm(cbuf, 0x3, 0x0, ECX_enc);
2728 emit_d32(cbuf,0xFFFFF800);
2729 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias
2730 emit_rm(cbuf, 0x3, 0x0, EAX_enc);
2731 emit_d32(cbuf,1023);
2732 emit_opcode(cbuf,0x8B); // mov rbx,eax
2733 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc);
2734 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position
2735 emit_rm(cbuf,0x3,0x4,EAX_enc);
2736 emit_d8(cbuf,20);
2737 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow
2738 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc);
2739 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX
2740 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc);
2741 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word
2742 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false);
2743 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q)
2744 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
2745 emit_d32(cbuf,0);
2746 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q
2747 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false);
2748 %}
2749
2750 // enc_class Pop_Reg_Mod_D( regD dst, regD src)
2751 // was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X()
2752
2753 enc_class Push_Result_Mod_D( regD src) %{
2754 if ($src$$reg != FPR1L_enc) {
2755 // fincstp
2756 emit_opcode (cbuf, 0xD9);
2757 emit_opcode (cbuf, 0xF7);
2758 // FXCH FPR1 with src
2759 emit_opcode(cbuf, 0xD9);
2760 emit_d8(cbuf, 0xC8-1+$src$$reg );
2761 // fdecstp
2762 emit_opcode (cbuf, 0xD9);
2763 emit_opcode (cbuf, 0xF6);
2764 }
2765 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2766 // // FSTP FPR$dst$$reg
2767 // emit_opcode( cbuf, 0xDD );
2768 // emit_d8( cbuf, 0xD8+$dst$$reg );
2769 %}
2770
2771 enc_class fnstsw_sahf_skip_parity() %{
2772 // fnstsw ax
2773 emit_opcode( cbuf, 0xDF );
2774 emit_opcode( cbuf, 0xE0 );
2775 // sahf
2776 emit_opcode( cbuf, 0x9E );
2777 // jnp ::skip
2778 emit_opcode( cbuf, 0x7B );
2779 emit_opcode( cbuf, 0x05 );
2780 %}
2781
2782 enc_class emitModD() %{
2783 // fprem must be iterative
2784 // :: loop
2785 // fprem
2786 emit_opcode( cbuf, 0xD9 );
2787 emit_opcode( cbuf, 0xF8 );
2788 // wait
2789 emit_opcode( cbuf, 0x9b );
2790 // fnstsw ax
2791 emit_opcode( cbuf, 0xDF );
2792 emit_opcode( cbuf, 0xE0 );
2793 // sahf
2794 emit_opcode( cbuf, 0x9E );
2795 // jp ::loop
2796 emit_opcode( cbuf, 0x0F );
2797 emit_opcode( cbuf, 0x8A );
2798 emit_opcode( cbuf, 0xF4 );
2799 emit_opcode( cbuf, 0xFF );
2800 emit_opcode( cbuf, 0xFF );
2801 emit_opcode( cbuf, 0xFF );
2802 %}
2803
2804 enc_class fpu_flags() %{
2805 // fnstsw_ax
2806 emit_opcode( cbuf, 0xDF);
2807 emit_opcode( cbuf, 0xE0);
2808 // test ax,0x0400
2809 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2810 emit_opcode( cbuf, 0xA9 );
2811 emit_d16 ( cbuf, 0x0400 );
2812 // // // This sequence works, but stalls for 12-16 cycles on PPro
2813 // // test rax,0x0400
2814 // emit_opcode( cbuf, 0xA9 );
2815 // emit_d32 ( cbuf, 0x00000400 );
2816 //
2817 // jz exit (no unordered comparison)
2818 emit_opcode( cbuf, 0x74 );
2819 emit_d8 ( cbuf, 0x02 );
2820 // mov ah,1 - treat as LT case (set carry flag)
2821 emit_opcode( cbuf, 0xB4 );
2822 emit_d8 ( cbuf, 0x01 );
2823 // sahf
2824 emit_opcode( cbuf, 0x9E);
2825 %}
2826
2827 enc_class cmpF_P6_fixup() %{
2828 // Fixup the integer flags in case comparison involved a NaN
2829 //
2830 // JNP exit (no unordered comparison, P-flag is set by NaN)
2831 emit_opcode( cbuf, 0x7B );
2832 emit_d8 ( cbuf, 0x03 );
2833 // MOV AH,1 - treat as LT case (set carry flag)
2834 emit_opcode( cbuf, 0xB4 );
2835 emit_d8 ( cbuf, 0x01 );
2836 // SAHF
2837 emit_opcode( cbuf, 0x9E);
2838 // NOP // target for branch to avoid branch to branch
2839 emit_opcode( cbuf, 0x90);
2840 %}
2841
2842 // fnstsw_ax();
2843 // sahf();
2844 // movl(dst, nan_result);
2845 // jcc(Assembler::parity, exit);
2846 // movl(dst, less_result);
2847 // jcc(Assembler::below, exit);
2848 // movl(dst, equal_result);
2849 // jcc(Assembler::equal, exit);
2850 // movl(dst, greater_result);
2851
2852 // less_result = 1;
2853 // greater_result = -1;
2854 // equal_result = 0;
2855 // nan_result = -1;
2856
2857 enc_class CmpF_Result(eRegI dst) %{
2858 // fnstsw_ax();
2859 emit_opcode( cbuf, 0xDF);
2860 emit_opcode( cbuf, 0xE0);
2861 // sahf
2862 emit_opcode( cbuf, 0x9E);
2863 // movl(dst, nan_result);
2864 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2865 emit_d32( cbuf, -1 );
2866 // jcc(Assembler::parity, exit);
2867 emit_opcode( cbuf, 0x7A );
2868 emit_d8 ( cbuf, 0x13 );
2869 // movl(dst, less_result);
2870 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2871 emit_d32( cbuf, -1 );
2872 // jcc(Assembler::below, exit);
2873 emit_opcode( cbuf, 0x72 );
2874 emit_d8 ( cbuf, 0x0C );
2875 // movl(dst, equal_result);
2876 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2877 emit_d32( cbuf, 0 );
2878 // jcc(Assembler::equal, exit);
2879 emit_opcode( cbuf, 0x74 );
2880 emit_d8 ( cbuf, 0x05 );
2881 // movl(dst, greater_result);
2882 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2883 emit_d32( cbuf, 1 );
2884 %}
2885
2886
2887 // XMM version of CmpF_Result. Because the XMM compare
2888 // instructions set the EFLAGS directly. It becomes simpler than
2889 // the float version above.
2890 enc_class CmpX_Result(eRegI dst) %{
2891 MacroAssembler _masm(&cbuf);
2892 Label nan, inc, done;
2893
2894 __ jccb(Assembler::parity, nan);
2895 __ jccb(Assembler::equal, done);
2896 __ jccb(Assembler::above, inc);
2897 __ bind(nan);
2898 __ decrement(as_Register($dst$$reg)); // NO L qqq
2899 __ jmpb(done);
2900 __ bind(inc);
2901 __ increment(as_Register($dst$$reg)); // NO L qqq
2902 __ bind(done);
2903 %}
2904
2905 // Compare the longs and set flags
2906 // BROKEN! Do Not use as-is
2907 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2908 // CMP $src1.hi,$src2.hi
2909 emit_opcode( cbuf, 0x3B );
2910 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2911 // JNE,s done
2912 emit_opcode(cbuf,0x75);
2913 emit_d8(cbuf, 2 );
2914 // CMP $src1.lo,$src2.lo
2915 emit_opcode( cbuf, 0x3B );
2916 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2917 // done:
2918 %}
2919
2920 enc_class convert_int_long( regL dst, eRegI src ) %{
2921 // mov $dst.lo,$src
2922 int dst_encoding = $dst$$reg;
2923 int src_encoding = $src$$reg;
2924 encode_Copy( cbuf, dst_encoding , src_encoding );
2925 // mov $dst.hi,$src
2926 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2927 // sar $dst.hi,31
2928 emit_opcode( cbuf, 0xC1 );
2929 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2930 emit_d8(cbuf, 0x1F );
2931 %}
2932
2933 enc_class convert_long_double( eRegL src ) %{
2934 // push $src.hi
2935 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2936 // push $src.lo
2937 emit_opcode(cbuf, 0x50+$src$$reg );
2938 // fild 64-bits at [SP]
2939 emit_opcode(cbuf,0xdf);
2940 emit_d8(cbuf, 0x6C);
2941 emit_d8(cbuf, 0x24);
2942 emit_d8(cbuf, 0x00);
2943 // pop stack
2944 emit_opcode(cbuf, 0x83); // add SP, #8
2945 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2946 emit_d8(cbuf, 0x8);
2947 %}
2948
2949 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2950 // IMUL EDX:EAX,$src1
2951 emit_opcode( cbuf, 0xF7 );
2952 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2953 // SAR EDX,$cnt-32
2954 int shift_count = ((int)$cnt$$constant) - 32;
2955 if (shift_count > 0) {
2956 emit_opcode(cbuf, 0xC1);
2957 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2958 emit_d8(cbuf, shift_count);
2959 }
2960 %}
2961
2962 // this version doesn't have add sp, 8
2963 enc_class convert_long_double2( eRegL src ) %{
2964 // push $src.hi
2965 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2966 // push $src.lo
2967 emit_opcode(cbuf, 0x50+$src$$reg );
2968 // fild 64-bits at [SP]
2969 emit_opcode(cbuf,0xdf);
2970 emit_d8(cbuf, 0x6C);
2971 emit_d8(cbuf, 0x24);
2972 emit_d8(cbuf, 0x00);
2973 %}
2974
2975 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2976 // Basic idea: long = (long)int * (long)int
2977 // IMUL EDX:EAX, src
2978 emit_opcode( cbuf, 0xF7 );
2979 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2980 %}
2981
2982 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2983 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2984 // MUL EDX:EAX, src
2985 emit_opcode( cbuf, 0xF7 );
2986 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2987 %}
2988
2989 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{
2990 // Basic idea: lo(result) = lo(x_lo * y_lo)
2991 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2992 // MOV $tmp,$src.lo
2993 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2994 // IMUL $tmp,EDX
2995 emit_opcode( cbuf, 0x0F );
2996 emit_opcode( cbuf, 0xAF );
2997 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2998 // MOV EDX,$src.hi
2999 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
3000 // IMUL EDX,EAX
3001 emit_opcode( cbuf, 0x0F );
3002 emit_opcode( cbuf, 0xAF );
3003 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
3004 // ADD $tmp,EDX
3005 emit_opcode( cbuf, 0x03 );
3006 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3007 // MUL EDX:EAX,$src.lo
3008 emit_opcode( cbuf, 0xF7 );
3009 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
3010 // ADD EDX,ESI
3011 emit_opcode( cbuf, 0x03 );
3012 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
3013 %}
3014
3015 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{
3016 // Basic idea: lo(result) = lo(src * y_lo)
3017 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
3018 // IMUL $tmp,EDX,$src
3019 emit_opcode( cbuf, 0x6B );
3020 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
3021 emit_d8( cbuf, (int)$src$$constant );
3022 // MOV EDX,$src
3023 emit_opcode(cbuf, 0xB8 + EDX_enc);
3024 emit_d32( cbuf, (int)$src$$constant );
3025 // MUL EDX:EAX,EDX
3026 emit_opcode( cbuf, 0xF7 );
3027 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
3028 // ADD EDX,ESI
3029 emit_opcode( cbuf, 0x03 );
3030 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
3031 %}
3032
3033 enc_class long_div( eRegL src1, eRegL src2 ) %{
3034 // PUSH src1.hi
3035 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3036 // PUSH src1.lo
3037 emit_opcode(cbuf, 0x50+$src1$$reg );
3038 // PUSH src2.hi
3039 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3040 // PUSH src2.lo
3041 emit_opcode(cbuf, 0x50+$src2$$reg );
3042 // CALL directly to the runtime
3043 cbuf.set_inst_mark();
3044 emit_opcode(cbuf,0xE8); // Call into runtime
3045 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3046 // Restore stack
3047 emit_opcode(cbuf, 0x83); // add SP, #framesize
3048 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3049 emit_d8(cbuf, 4*4);
3050 %}
3051
3052 enc_class long_mod( eRegL src1, eRegL src2 ) %{
3053 // PUSH src1.hi
3054 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
3055 // PUSH src1.lo
3056 emit_opcode(cbuf, 0x50+$src1$$reg );
3057 // PUSH src2.hi
3058 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
3059 // PUSH src2.lo
3060 emit_opcode(cbuf, 0x50+$src2$$reg );
3061 // CALL directly to the runtime
3062 cbuf.set_inst_mark();
3063 emit_opcode(cbuf,0xE8); // Call into runtime
3064 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3065 // Restore stack
3066 emit_opcode(cbuf, 0x83); // add SP, #framesize
3067 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
3068 emit_d8(cbuf, 4*4);
3069 %}
3070
3071 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{
3072 // MOV $tmp,$src.lo
3073 emit_opcode(cbuf, 0x8B);
3074 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
3075 // OR $tmp,$src.hi
3076 emit_opcode(cbuf, 0x0B);
3077 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
3078 %}
3079
3080 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
3081 // CMP $src1.lo,$src2.lo
3082 emit_opcode( cbuf, 0x3B );
3083 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3084 // JNE,s skip
3085 emit_cc(cbuf, 0x70, 0x5);
3086 emit_d8(cbuf,2);
3087 // CMP $src1.hi,$src2.hi
3088 emit_opcode( cbuf, 0x3B );
3089 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
3090 %}
3091
3092 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{
3093 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
3094 emit_opcode( cbuf, 0x3B );
3095 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
3096 // MOV $tmp,$src1.hi
3097 emit_opcode( cbuf, 0x8B );
3098 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
3099 // SBB $tmp,$src2.hi\t! Compute flags for long compare
3100 emit_opcode( cbuf, 0x1B );
3101 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
3102 %}
3103
3104 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{
3105 // XOR $tmp,$tmp
3106 emit_opcode(cbuf,0x33); // XOR
3107 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
3108 // CMP $tmp,$src.lo
3109 emit_opcode( cbuf, 0x3B );
3110 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
3111 // SBB $tmp,$src.hi
3112 emit_opcode( cbuf, 0x1B );
3113 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
3114 %}
3115
3116 // Sniff, sniff... smells like Gnu Superoptimizer
3117 enc_class neg_long( eRegL dst ) %{
3118 emit_opcode(cbuf,0xF7); // NEG hi
3119 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3120 emit_opcode(cbuf,0xF7); // NEG lo
3121 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
3122 emit_opcode(cbuf,0x83); // SBB hi,0
3123 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
3124 emit_d8 (cbuf,0 );
3125 %}
3126
3127 enc_class movq_ld(regXD dst, memory mem) %{
3128 MacroAssembler _masm(&cbuf);
3129 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3130 __ movq(as_XMMRegister($dst$$reg), madr);
3131 %}
3132
3133 enc_class movq_st(memory mem, regXD src) %{
3134 MacroAssembler _masm(&cbuf);
3135 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
3136 __ movq(madr, as_XMMRegister($src$$reg));
3137 %}
3138
3139 enc_class pshufd_8x8(regX dst, regX src) %{
3140 MacroAssembler _masm(&cbuf);
3141
3142 encode_CopyXD(cbuf, $dst$$reg, $src$$reg);
3143 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg));
3144 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00);
3145 %}
3146
3147 enc_class pshufd_4x16(regX dst, regX src) %{
3148 MacroAssembler _masm(&cbuf);
3149
3150 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00);
3151 %}
3152
3153 enc_class pshufd(regXD dst, regXD src, int mode) %{
3154 MacroAssembler _masm(&cbuf);
3155
3156 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode);
3157 %}
3158
3159 enc_class pxor(regXD dst, regXD src) %{
3160 MacroAssembler _masm(&cbuf);
3161
3162 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg));
3163 %}
3164
3165 enc_class mov_i2x(regXD dst, eRegI src) %{
3166 MacroAssembler _masm(&cbuf);
3167
3168 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg));
3169 %}
3170
3171
3172 // Because the transitions from emitted code to the runtime
3173 // monitorenter/exit helper stubs are so slow it's critical that
3174 // we inline both the stack-locking fast-path and the inflated fast path.
3175 //
3176 // See also: cmpFastLock and cmpFastUnlock.
3177 //
3178 // What follows is a specialized inline transliteration of the code
3179 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
3180 // another option would be to emit TrySlowEnter and TrySlowExit methods
3181 // at startup-time. These methods would accept arguments as
3182 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
3183 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
3184 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
3185 // In practice, however, the # of lock sites is bounded and is usually small.
3186 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
3187 // if the processor uses simple bimodal branch predictors keyed by EIP
3188 // Since the helper routines would be called from multiple synchronization
3189 // sites.
3190 //
3191 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
3192 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
3193 // to those specialized methods. That'd give us a mostly platform-independent
3194 // implementation that the JITs could optimize and inline at their pleasure.
3195 // Done correctly, the only time we'd need to cross to native could would be
3196 // to park() or unpark() threads. We'd also need a few more unsafe operators
3197 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
3198 // (b) explicit barriers or fence operations.
3199 //
3200 // TODO:
3201 //
3202 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
3203 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
3204 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
3205 // the lock operators would typically be faster than reifying Self.
3206 //
3207 // * Ideally I'd define the primitives as:
3208 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
3209 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
3210 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
3211 // Instead, we're stuck with a rather awkward and brittle register assignments below.
3212 // Furthermore the register assignments are overconstrained, possibly resulting in
3213 // sub-optimal code near the synchronization site.
3214 //
3215 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3216 // Alternately, use a better sp-proximity test.
3217 //
3218 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3219 // Either one is sufficient to uniquely identify a thread.
3220 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3221 //
3222 // * Intrinsify notify() and notifyAll() for the common cases where the
3223 // object is locked by the calling thread but the waitlist is empty.
3224 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3225 //
3226 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3227 // But beware of excessive branch density on AMD Opterons.
3228 //
3229 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3230 // or failure of the fast-path. If the fast-path fails then we pass
3231 // control to the slow-path, typically in C. In Fast_Lock and
3232 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3233 // will emit a conditional branch immediately after the node.
3234 // So we have branches to branches and lots of ICC.ZF games.
3235 // Instead, it might be better to have C2 pass a "FailureLabel"
3236 // into Fast_Lock and Fast_Unlock. In the case of success, control
3237 // will drop through the node. ICC.ZF is undefined at exit.
3238 // In the case of failure, the node will branch directly to the
3239 // FailureLabel
3240
3241
3242 // obj: object to lock
3243 // box: on-stack box address (displaced header location) - KILLED
3244 // rax,: tmp -- KILLED
3245 // scr: tmp -- KILLED
3246 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3247
3248 Register objReg = as_Register($obj$$reg);
3249 Register boxReg = as_Register($box$$reg);
3250 Register tmpReg = as_Register($tmp$$reg);
3251 Register scrReg = as_Register($scr$$reg);
3252
3253 // Ensure the register assignents are disjoint
3254 guarantee (objReg != boxReg, "") ;
3255 guarantee (objReg != tmpReg, "") ;
3256 guarantee (objReg != scrReg, "") ;
3257 guarantee (boxReg != tmpReg, "") ;
3258 guarantee (boxReg != scrReg, "") ;
3259 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3260
3261 MacroAssembler masm(&cbuf);
3262
3263 if (_counters != NULL) {
3264 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3265 }
3266 if (EmitSync & 1) {
3267 // set box->dhw = unused_mark (3)
3268 // Force all sync thru slow-path: slow_enter() and slow_exit()
3269 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3270 masm.cmpptr (rsp, (int32_t)0) ;
3271 } else
3272 if (EmitSync & 2) {
3273 Label DONE_LABEL ;
3274 if (UseBiasedLocking) {
3275 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3276 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3277 }
3278
3279 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3280 masm.orptr (tmpReg, 0x1);
3281 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3282 if (os::is_MP()) { masm.lock(); }
3283 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3284 masm.jcc(Assembler::equal, DONE_LABEL);
3285 // Recursive locking
3286 masm.subptr(tmpReg, rsp);
3287 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3288 masm.movptr(Address(boxReg, 0), tmpReg);
3289 masm.bind(DONE_LABEL) ;
3290 } else {
3291 // Possible cases that we'll encounter in fast_lock
3292 // ------------------------------------------------
3293 // * Inflated
3294 // -- unlocked
3295 // -- Locked
3296 // = by self
3297 // = by other
3298 // * biased
3299 // -- by Self
3300 // -- by other
3301 // * neutral
3302 // * stack-locked
3303 // -- by self
3304 // = sp-proximity test hits
3305 // = sp-proximity test generates false-negative
3306 // -- by other
3307 //
3308
3309 Label IsInflated, DONE_LABEL, PopDone ;
3310
3311 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3312 // order to reduce the number of conditional branches in the most common cases.
3313 // Beware -- there's a subtle invariant that fetch of the markword
3314 // at [FETCH], below, will never observe a biased encoding (*101b).
3315 // If this invariant is not held we risk exclusion (safety) failure.
3316 if (UseBiasedLocking && !UseOptoBiasInlining) {
3317 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3318 }
3319
3320 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3321 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3322 masm.jccb (Assembler::notZero, IsInflated) ;
3323
3324 // Attempt stack-locking ...
3325 masm.orptr (tmpReg, 0x1);
3326 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3327 if (os::is_MP()) { masm.lock(); }
3328 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3329 if (_counters != NULL) {
3330 masm.cond_inc32(Assembler::equal,
3331 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3332 }
3333 masm.jccb (Assembler::equal, DONE_LABEL);
3334
3335 // Recursive locking
3336 masm.subptr(tmpReg, rsp);
3337 masm.andptr(tmpReg, 0xFFFFF003 );
3338 masm.movptr(Address(boxReg, 0), tmpReg);
3339 if (_counters != NULL) {
3340 masm.cond_inc32(Assembler::equal,
3341 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3342 }
3343 masm.jmp (DONE_LABEL) ;
3344
3345 masm.bind (IsInflated) ;
3346
3347 // The object is inflated.
3348 //
3349 // TODO-FIXME: eliminate the ugly use of manifest constants:
3350 // Use markOopDesc::monitor_value instead of "2".
3351 // use markOop::unused_mark() instead of "3".
3352 // The tmpReg value is an objectMonitor reference ORed with
3353 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3354 // objectmonitor pointer by masking off the "2" bit or we can just
3355 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3356 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3357 //
3358 // I use the latter as it avoids AGI stalls.
3359 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3360 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3361 //
3362 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3363
3364 // boxReg refers to the on-stack BasicLock in the current frame.
3365 // We'd like to write:
3366 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3367 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3368 // additional latency as we have another ST in the store buffer that must drain.
3369
3370 if (EmitSync & 8192) {
3371 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3372 masm.get_thread (scrReg) ;
3373 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3374 masm.movptr(tmpReg, 0); // consider: xor vs mov
3375 if (os::is_MP()) { masm.lock(); }
3376 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3377 } else
3378 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3379 masm.movptr(scrReg, boxReg) ;
3380 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3381
3382 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3383 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3384 // prefetchw [eax + Offset(_owner)-2]
3385 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3386 }
3387
3388 if ((EmitSync & 64) == 0) {
3389 // Optimistic form: consider XORL tmpReg,tmpReg
3390 masm.movptr(tmpReg, 0 ) ;
3391 } else {
3392 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3393 // Test-And-CAS instead of CAS
3394 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3395 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3396 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3397 }
3398
3399 // Appears unlocked - try to swing _owner from null to non-null.
3400 // Ideally, I'd manifest "Self" with get_thread and then attempt
3401 // to CAS the register containing Self into m->Owner.
3402 // But we don't have enough registers, so instead we can either try to CAS
3403 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3404 // we later store "Self" into m->Owner. Transiently storing a stack address
3405 // (rsp or the address of the box) into m->owner is harmless.
3406 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3407 if (os::is_MP()) { masm.lock(); }
3408 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3409 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3410 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3411 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3412 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3413 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3414
3415 // If the CAS fails we can either retry or pass control to the slow-path.
3416 // We use the latter tactic.
3417 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3418 // If the CAS was successful ...
3419 // Self has acquired the lock
3420 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3421 // Intentional fall-through into DONE_LABEL ...
3422 } else {
3423 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3424 masm.movptr(boxReg, tmpReg) ;
3425
3426 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3427 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) {
3428 // prefetchw [eax + Offset(_owner)-2]
3429 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3430 }
3431
3432 if ((EmitSync & 64) == 0) {
3433 // Optimistic form
3434 masm.xorptr (tmpReg, tmpReg) ;
3435 } else {
3436 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3437 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3438 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3439 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3440 }
3441
3442 // Appears unlocked - try to swing _owner from null to non-null.
3443 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3444 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3445 masm.get_thread (scrReg) ;
3446 if (os::is_MP()) { masm.lock(); }
3447 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3448
3449 // If the CAS fails we can either retry or pass control to the slow-path.
3450 // We use the latter tactic.
3451 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3452 // If the CAS was successful ...
3453 // Self has acquired the lock
3454 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3455 // Intentional fall-through into DONE_LABEL ...
3456 }
3457
3458 // DONE_LABEL is a hot target - we'd really like to place it at the
3459 // start of cache line by padding with NOPs.
3460 // See the AMD and Intel software optimization manuals for the
3461 // most efficient "long" NOP encodings.
3462 // Unfortunately none of our alignment mechanisms suffice.
3463 masm.bind(DONE_LABEL);
3464
3465 // Avoid branch-to-branch on AMD processors
3466 // This appears to be superstition.
3467 if (EmitSync & 32) masm.nop() ;
3468
3469
3470 // At DONE_LABEL the icc ZFlag is set as follows ...
3471 // Fast_Unlock uses the same protocol.
3472 // ZFlag == 1 -> Success
3473 // ZFlag == 0 -> Failure - force control through the slow-path
3474 }
3475 %}
3476
3477 // obj: object to unlock
3478 // box: box address (displaced header location), killed. Must be EAX.
3479 // rbx,: killed tmp; cannot be obj nor box.
3480 //
3481 // Some commentary on balanced locking:
3482 //
3483 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3484 // Methods that don't have provably balanced locking are forced to run in the
3485 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3486 // The interpreter provides two properties:
3487 // I1: At return-time the interpreter automatically and quietly unlocks any
3488 // objects acquired the current activation (frame). Recall that the
3489 // interpreter maintains an on-stack list of locks currently held by
3490 // a frame.
3491 // I2: If a method attempts to unlock an object that is not held by the
3492 // the frame the interpreter throws IMSX.
3493 //
3494 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3495 // B() doesn't have provably balanced locking so it runs in the interpreter.
3496 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3497 // is still locked by A().
3498 //
3499 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3500 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3501 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3502 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3503
3504 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3505
3506 Register objReg = as_Register($obj$$reg);
3507 Register boxReg = as_Register($box$$reg);
3508 Register tmpReg = as_Register($tmp$$reg);
3509
3510 guarantee (objReg != boxReg, "") ;
3511 guarantee (objReg != tmpReg, "") ;
3512 guarantee (boxReg != tmpReg, "") ;
3513 guarantee (boxReg == as_Register(EAX_enc), "") ;
3514 MacroAssembler masm(&cbuf);
3515
3516 if (EmitSync & 4) {
3517 // Disable - inhibit all inlining. Force control through the slow-path
3518 masm.cmpptr (rsp, 0) ;
3519 } else
3520 if (EmitSync & 8) {
3521 Label DONE_LABEL ;
3522 if (UseBiasedLocking) {
3523 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3524 }
3525 // classic stack-locking code ...
3526 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3527 masm.testptr(tmpReg, tmpReg) ;
3528 masm.jcc (Assembler::zero, DONE_LABEL) ;
3529 if (os::is_MP()) { masm.lock(); }
3530 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3531 masm.bind(DONE_LABEL);
3532 } else {
3533 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3534
3535 // Critically, the biased locking test must have precedence over
3536 // and appear before the (box->dhw == 0) recursive stack-lock test.
3537 if (UseBiasedLocking && !UseOptoBiasInlining) {
3538 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3539 }
3540
3541 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3542 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3543 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3544
3545 masm.testptr(tmpReg, 0x02) ; // Inflated?
3546 masm.jccb (Assembler::zero, Stacked) ;
3547
3548 masm.bind (Inflated) ;
3549 // It's inflated.
3550 // Despite our balanced locking property we still check that m->_owner == Self
3551 // as java routines or native JNI code called by this thread might
3552 // have released the lock.
3553 // Refer to the comments in synchronizer.cpp for how we might encode extra
3554 // state in _succ so we can avoid fetching EntryList|cxq.
3555 //
3556 // I'd like to add more cases in fast_lock() and fast_unlock() --
3557 // such as recursive enter and exit -- but we have to be wary of
3558 // I$ bloat, T$ effects and BP$ effects.
3559 //
3560 // If there's no contention try a 1-0 exit. That is, exit without
3561 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3562 // we detect and recover from the race that the 1-0 exit admits.
3563 //
3564 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3565 // before it STs null into _owner, releasing the lock. Updates
3566 // to data protected by the critical section must be visible before
3567 // we drop the lock (and thus before any other thread could acquire
3568 // the lock and observe the fields protected by the lock).
3569 // IA32's memory-model is SPO, so STs are ordered with respect to
3570 // each other and there's no need for an explicit barrier (fence).
3571 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3572
3573 masm.get_thread (boxReg) ;
3574 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) {
3575 // prefetchw [ebx + Offset(_owner)-2]
3576 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3577 }
3578
3579 // Note that we could employ various encoding schemes to reduce
3580 // the number of loads below (currently 4) to just 2 or 3.
3581 // Refer to the comments in synchronizer.cpp.
3582 // In practice the chain of fetches doesn't seem to impact performance, however.
3583 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3584 // Attempt to reduce branch density - AMD's branch predictor.
3585 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3586 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3587 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3588 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3589 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3590 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3591 masm.jmpb (DONE_LABEL) ;
3592 } else {
3593 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3594 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3595 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3596 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3597 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3598 masm.jccb (Assembler::notZero, CheckSucc) ;
3599 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3600 masm.jmpb (DONE_LABEL) ;
3601 }
3602
3603 // The Following code fragment (EmitSync & 65536) improves the performance of
3604 // contended applications and contended synchronization microbenchmarks.
3605 // Unfortunately the emission of the code - even though not executed - causes regressions
3606 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3607 // with an equal number of never-executed NOPs results in the same regression.
3608 // We leave it off by default.
3609
3610 if ((EmitSync & 65536) != 0) {
3611 Label LSuccess, LGoSlowPath ;
3612
3613 masm.bind (CheckSucc) ;
3614
3615 // Optional pre-test ... it's safe to elide this
3616 if ((EmitSync & 16) == 0) {
3617 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3618 masm.jccb (Assembler::zero, LGoSlowPath) ;
3619 }
3620
3621 // We have a classic Dekker-style idiom:
3622 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3623 // There are a number of ways to implement the barrier:
3624 // (1) lock:andl &m->_owner, 0
3625 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3626 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3627 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3628 // (2) If supported, an explicit MFENCE is appealing.
3629 // In older IA32 processors MFENCE is slower than lock:add or xchg
3630 // particularly if the write-buffer is full as might be the case if
3631 // if stores closely precede the fence or fence-equivalent instruction.
3632 // In more modern implementations MFENCE appears faster, however.
3633 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3634 // The $lines underlying the top-of-stack should be in M-state.
3635 // The locked add instruction is serializing, of course.
3636 // (4) Use xchg, which is serializing
3637 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3638 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3639 // The integer condition codes will tell us if succ was 0.
3640 // Since _succ and _owner should reside in the same $line and
3641 // we just stored into _owner, it's likely that the $line
3642 // remains in M-state for the lock:orl.
3643 //
3644 // We currently use (3), although it's likely that switching to (2)
3645 // is correct for the future.
3646
3647 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ;
3648 if (os::is_MP()) {
3649 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3650 masm.mfence();
3651 } else {
3652 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3653 }
3654 }
3655 // Ratify _succ remains non-null
3656 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3657 masm.jccb (Assembler::notZero, LSuccess) ;
3658
3659 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3660 if (os::is_MP()) { masm.lock(); }
3661 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3662 masm.jccb (Assembler::notEqual, LSuccess) ;
3663 // Since we're low on registers we installed rsp as a placeholding in _owner.
3664 // Now install Self over rsp. This is safe as we're transitioning from
3665 // non-null to non=null
3666 masm.get_thread (boxReg) ;
3667 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3668 // Intentional fall-through into LGoSlowPath ...
3669
3670 masm.bind (LGoSlowPath) ;
3671 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3672 masm.jmpb (DONE_LABEL) ;
3673
3674 masm.bind (LSuccess) ;
3675 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3676 masm.jmpb (DONE_LABEL) ;
3677 }
3678
3679 masm.bind (Stacked) ;
3680 // It's not inflated and it's not recursively stack-locked and it's not biased.
3681 // It must be stack-locked.
3682 // Try to reset the header to displaced header.
3683 // The "box" value on the stack is stable, so we can reload
3684 // and be assured we observe the same value as above.
3685 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3686 if (os::is_MP()) { masm.lock(); }
3687 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3688 // Intention fall-thru into DONE_LABEL
3689
3690
3691 // DONE_LABEL is a hot target - we'd really like to place it at the
3692 // start of cache line by padding with NOPs.
3693 // See the AMD and Intel software optimization manuals for the
3694 // most efficient "long" NOP encodings.
3695 // Unfortunately none of our alignment mechanisms suffice.
3696 if ((EmitSync & 65536) == 0) {
3697 masm.bind (CheckSucc) ;
3698 }
3699 masm.bind(DONE_LABEL);
3700
3701 // Avoid branch to branch on AMD processors
3702 if (EmitSync & 32768) { masm.nop() ; }
3703 }
3704 %}
3705
3706 enc_class enc_String_Compare() %{
3707 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL,
3708 POP_LABEL, DONE_LABEL, CONT_LABEL,
3709 WHILE_HEAD_LABEL;
3710 MacroAssembler masm(&cbuf);
3711
3712 // Get the first character position in both strings
3713 // [8] char array, [12] offset, [16] count
3714 int value_offset = java_lang_String::value_offset_in_bytes();
3715 int offset_offset = java_lang_String::offset_offset_in_bytes();
3716 int count_offset = java_lang_String::count_offset_in_bytes();
3717 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3718
3719 masm.movptr(rax, Address(rsi, value_offset));
3720 masm.movl(rcx, Address(rsi, offset_offset));
3721 masm.lea(rax, Address(rax, rcx, Address::times_2, base_offset));
3722 masm.movptr(rbx, Address(rdi, value_offset));
3723 masm.movl(rcx, Address(rdi, offset_offset));
3724 masm.lea(rbx, Address(rbx, rcx, Address::times_2, base_offset));
3725
3726 // Compute the minimum of the string lengths(rsi) and the
3727 // difference of the string lengths (stack)
3728
3729
3730 if (VM_Version::supports_cmov()) {
3731 masm.movl(rdi, Address(rdi, count_offset));
3732 masm.movl(rsi, Address(rsi, count_offset));
3733 masm.movl(rcx, rdi);
3734 masm.subl(rdi, rsi);
3735 masm.push(rdi);
3736 masm.cmovl(Assembler::lessEqual, rsi, rcx);
3737 } else {
3738 masm.movl(rdi, Address(rdi, count_offset));
3739 masm.movl(rcx, Address(rsi, count_offset));
3740 masm.movl(rsi, rdi);
3741 masm.subl(rdi, rcx);
3742 masm.push(rdi);
3743 masm.jccb(Assembler::lessEqual, ECX_GOOD_LABEL);
3744 masm.movl(rsi, rcx);
3745 // rsi holds min, rcx is unused
3746 }
3747
3748 // Is the minimum length zero?
3749 masm.bind(ECX_GOOD_LABEL);
3750 masm.testl(rsi, rsi);
3751 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3752
3753 // Load first characters
3754 masm.load_unsigned_word(rcx, Address(rbx, 0));
3755 masm.load_unsigned_word(rdi, Address(rax, 0));
3756
3757 // Compare first characters
3758 masm.subl(rcx, rdi);
3759 masm.jccb(Assembler::notZero, POP_LABEL);
3760 masm.decrementl(rsi);
3761 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3762
3763 {
3764 // Check after comparing first character to see if strings are equivalent
3765 Label LSkip2;
3766 // Check if the strings start at same location
3767 masm.cmpptr(rbx,rax);
3768 masm.jccb(Assembler::notEqual, LSkip2);
3769
3770 // Check if the length difference is zero (from stack)
3771 masm.cmpl(Address(rsp, 0), 0x0);
3772 masm.jccb(Assembler::equal, LENGTH_DIFF_LABEL);
3773
3774 // Strings might not be equivalent
3775 masm.bind(LSkip2);
3776 }
3777
3778 // Advance to next character
3779 masm.addptr(rax, 2);
3780 masm.addptr(rbx, 2);
3781
3782 if (UseSSE >=4 && UseSSE42Intrinsics) {
3783 // With SSE4.2, use double quad vector compare
3784 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
3785 // Setup to compare 16-byte vectors
3786 masm.movl(rdi, rsi);
3787 masm.andl(rsi, 0xfffffff8); // rsi holds the vector count
3788 masm.andl(rdi, 0x00000007); // rdi holds the tail count
3789 masm.testl(rsi, rsi);
3790 masm.jccb(Assembler::zero, COMPARE_TAIL);
3791
3792 masm.lea(rax, Address(rax, rsi, Address::times_2));
3793 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3794 masm.negl(rsi);
3795
3796 masm.bind(COMPARE_VECTORS);
3797 masm.movdqu(xmm6, Address(rax, rsi, Address::times_2));
3798 masm.movdqu(xmm7, Address(rbx, rsi, Address::times_2));
3799 masm.pxor(xmm6, xmm7);
3800 masm.ptest(xmm6, xmm6);
3801 masm.jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
3802 masm.addl(rsi, 8);
3803 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3804 masm.jmpb(COMPARE_TAIL);
3805
3806 // Mismatched characters in the vectors
3807 masm.bind(VECTOR_NOT_EQUAL);
3808 masm.lea(rax, Address(rax, rsi, Address::times_2));
3809 masm.lea(rbx, Address(rbx, rsi, Address::times_2));
3810 masm.movl(rdi, 8);
3811
3812 // Compare tail (< 8 chars), or rescan last vectors to
3813 // find 1st mismatched characters
3814 masm.bind(COMPARE_TAIL);
3815 masm.testl(rdi, rdi);
3816 masm.jccb(Assembler::zero, LENGTH_DIFF_LABEL);
3817 masm.movl(rsi, rdi);
3818 // Fallthru to tail compare
3819 }
3820
3821 //Shift rax, and rbx, to the end of the arrays, negate min
3822 masm.lea(rax, Address(rax, rsi, Address::times_2, 0));
3823 masm.lea(rbx, Address(rbx, rsi, Address::times_2, 0));
3824 masm.negl(rsi);
3825
3826 // Compare the rest of the characters
3827 masm.bind(WHILE_HEAD_LABEL);
3828 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0));
3829 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0));
3830 masm.subl(rcx, rdi);
3831 masm.jccb(Assembler::notZero, POP_LABEL);
3832 masm.incrementl(rsi);
3833 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL);
3834
3835 // Strings are equal up to min length. Return the length difference.
3836 masm.bind(LENGTH_DIFF_LABEL);
3837 masm.pop(rcx);
3838 masm.jmpb(DONE_LABEL);
3839
3840 // Discard the stored length difference
3841 masm.bind(POP_LABEL);
3842 masm.addptr(rsp, 4);
3843
3844 // That's it
3845 masm.bind(DONE_LABEL);
3846 %}
3847
3848 enc_class enc_String_Equals() %{
3849 Label RET_TRUE, RET_FALSE, DONE, COMPARE_VECTORS, COMPARE_CHAR;
3850 MacroAssembler masm(&cbuf);
3851
3852 int value_offset = java_lang_String::value_offset_in_bytes();
3853 int offset_offset = java_lang_String::offset_offset_in_bytes();
3854 int count_offset = java_lang_String::count_offset_in_bytes();
3855 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3856
3857 // does source == target string?
3858 masm.cmpptr(rdi, rsi);
3859 masm.jccb(Assembler::equal, RET_TRUE);
3860
3861 // get and compare counts
3862 masm.movl(rcx, Address(rdi, count_offset));
3863 masm.movl(rax, Address(rsi, count_offset));
3864 masm.cmpl(rcx, rax);
3865 masm.jccb(Assembler::notEqual, RET_FALSE);
3866 masm.testl(rax, rax);
3867 masm.jccb(Assembler::zero, RET_TRUE);
3868
3869 // get source string offset and value
3870 masm.movptr(rbx, Address(rsi, value_offset));
3871 masm.movl(rax, Address(rsi, offset_offset));
3872 masm.leal(rsi, Address(rbx, rax, Address::times_2, base_offset));
3873
3874 // get compare string offset and value
3875 masm.movptr(rbx, Address(rdi, value_offset));
3876 masm.movl(rax, Address(rdi, offset_offset));
3877 masm.leal(rdi, Address(rbx, rax, Address::times_2, base_offset));
3878
3879 // Set byte count
3880 masm.shll(rcx, 1);
3881 masm.movl(rax, rcx);
3882
3883 if (UseSSE >=4 && UseSSE42Intrinsics) {
3884 // With SSE4.2, use double quad vector compare
3885 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
3886 // Compare 16-byte vectors
3887 masm.andl(rcx, 0xfffffff0); // vector count (in bytes)
3888 masm.andl(rax, 0x0000000e); // tail count (in bytes)
3889 masm.testl(rcx, rcx);
3890 masm.jccb(Assembler::zero, COMPARE_TAIL);
3891 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3892 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3893 masm.negl(rcx);
3894
3895 masm.bind(COMPARE_WIDE_VECTORS);
3896 masm.movdqu(xmm6, Address(rdi, rcx, Address::times_1));
3897 masm.movdqu(xmm7, Address(rsi, rcx, Address::times_1));
3898 masm.pxor(xmm6, xmm7);
3899 masm.ptest(xmm6, xmm6);
3900 masm.jccb(Assembler::notZero, RET_FALSE);
3901 masm.addl(rcx, 16);
3902 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
3903 masm.bind(COMPARE_TAIL);
3904 masm.movl(rcx, rax);
3905 // Fallthru to tail compare
3906 }
3907
3908 // Compare 4-byte vectors
3909 masm.andl(rcx, 0xfffffffc); // vector count (in bytes)
3910 masm.andl(rax, 0x00000002); // tail char (in bytes)
3911 masm.testl(rcx, rcx);
3912 masm.jccb(Assembler::zero, COMPARE_CHAR);
3913 masm.lea(rdi, Address(rdi, rcx, Address::times_1));
3914 masm.lea(rsi, Address(rsi, rcx, Address::times_1));
3915 masm.negl(rcx);
3916
3917 masm.bind(COMPARE_VECTORS);
3918 masm.movl(rbx, Address(rdi, rcx, Address::times_1));
3919 masm.cmpl(rbx, Address(rsi, rcx, Address::times_1));
3920 masm.jccb(Assembler::notEqual, RET_FALSE);
3921 masm.addl(rcx, 4);
3922 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
3923
3924 // Compare trailing char (final 2 bytes), if any
3925 masm.bind(COMPARE_CHAR);
3926 masm.testl(rax, rax);
3927 masm.jccb(Assembler::zero, RET_TRUE);
3928 masm.load_unsigned_word(rbx, Address(rdi, 0));
3929 masm.load_unsigned_word(rcx, Address(rsi, 0));
3930 masm.cmpl(rbx, rcx);
3931 masm.jccb(Assembler::notEqual, RET_FALSE);
3932
3933 masm.bind(RET_TRUE);
3934 masm.movl(rax, 1); // return true
3935 masm.jmpb(DONE);
3936
3937 masm.bind(RET_FALSE);
3938 masm.xorl(rax, rax); // return false
3939
3940 masm.bind(DONE);
3941 %}
3942
3943 enc_class enc_String_IndexOf() %{
3944 // SSE4.2 version
3945 Label LOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR,
3946 SCAN_SUBSTR, RET_NEG_ONE, RET_NOT_FOUND, CLEANUP, DONE;
3947 MacroAssembler masm(&cbuf);
3948
3949 // Get the first character position in both strings
3950 // [8] char array, [12] offset, [16] count
3951 int value_offset = java_lang_String::value_offset_in_bytes();
3952 int offset_offset = java_lang_String::offset_offset_in_bytes();
3953 int count_offset = java_lang_String::count_offset_in_bytes();
3954 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3955
3956 // Get counts for string and substr
3957 masm.movl(rdx, Address(rsi, count_offset));
3958 masm.movl(rax, Address(rdi, count_offset));
3959 // Check for substr count > string count
3960 masm.cmpl(rax, rdx);
3961 masm.jccb(Assembler::greater, RET_NEG_ONE);
3962
3963 // Start the indexOf operation
3964 // Get start addr of string
3965 masm.movptr(rbx, Address(rsi, value_offset));
3966 masm.movl(rcx, Address(rsi, offset_offset));
3967 masm.lea(rsi, Address(rbx, rcx, Address::times_2, base_offset));
3968 masm.push(rsi);
3969
3970 // Get start addr of substr
3971 masm.movptr(rbx, Address(rdi, value_offset));
3972 masm.movl(rcx, Address(rdi, offset_offset));
3973 masm.lea(rdi, Address(rbx, rcx, Address::times_2, base_offset));
3974 masm.push(rdi);
3975 masm.push(rax);
3976 masm.jmpb(PREP_FOR_SCAN);
3977
3978 // Substr count saved at sp
3979 // Substr saved at sp+4
3980 // String saved at sp+8
3981
3982 // Prep to load substr for scan
3983 masm.bind(LOAD_SUBSTR);
3984 masm.movptr(rdi, Address(rsp, 4));
3985 masm.movl(rax, Address(rsp, 0));
3986
3987 // Load substr
3988 masm.bind(PREP_FOR_SCAN);
3989 masm.movdqu(xmm6, Address(rdi, 0));
3990 masm.addl(rdx, 8); // prime the loop
3991 masm.subptr(rsi, 16);
3992
3993 // Scan string for substr in 16-byte vectors
3994 masm.bind(SCAN_TO_SUBSTR);
3995 masm.subl(rdx, 8);
3996 masm.addptr(rsi, 16);
3997 masm.pcmpestri(xmm6, Address(rsi, 0), 0x0d);
3998 masm.jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0
3999 masm.jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0
4000
4001 // Fallthru: found a potential substr
4002
4003 // Make sure string is still long enough
4004 masm.subl(rdx, rcx);
4005 masm.cmpl(rdx, rax);
4006 masm.jccb(Assembler::negative, RET_NOT_FOUND);
4007 // Compute start addr of substr
4008 masm.lea(rsi, Address(rsi, rcx, Address::times_2));
4009 masm.movptr(rbx, rsi);
4010
4011 // Compare potential substr
4012 masm.addl(rdx, 8); // prime the loop
4013 masm.addl(rax, 8);
4014 masm.subptr(rsi, 16);
4015 masm.subptr(rdi, 16);
4016
4017 // Scan 16-byte vectors of string and substr
4018 masm.bind(SCAN_SUBSTR);
4019 masm.subl(rax, 8);
4020 masm.subl(rdx, 8);
4021 masm.addptr(rsi, 16);
4022 masm.addptr(rdi, 16);
4023 masm.movdqu(xmm6, Address(rdi, 0));
4024 masm.pcmpestri(xmm6, Address(rsi, 0), 0x0d);
4025 masm.jcc(Assembler::noOverflow, LOAD_SUBSTR); // OF == 0
4026 masm.jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0
4027
4028 // Compute substr offset
4029 masm.movptr(rsi, Address(rsp, 8));
4030 masm.subptr(rbx, rsi);
4031 masm.shrl(rbx, 1);
4032 masm.jmpb(CLEANUP);
4033
4034 masm.bind(RET_NEG_ONE);
4035 masm.movl(rbx, -1);
4036 masm.jmpb(DONE);
4037
4038 masm.bind(RET_NOT_FOUND);
4039 masm.movl(rbx, -1);
4040
4041 masm.bind(CLEANUP);
4042 masm.addptr(rsp, 12);
4043
4044 masm.bind(DONE);
4045 %}
4046
4047
4048 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eBXRegI tmp1, eDXRegI tmp2, regXD6 tmp3, regXD7 tmp5, eAXRegI result) %{
4049 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
4050 MacroAssembler masm(&cbuf);
4051
4052 Register ary1Reg = as_Register($ary1$$reg);
4053 Register ary2Reg = as_Register($ary2$$reg);
4054 Register tmp1Reg = as_Register($tmp1$$reg);
4055 Register tmp2Reg = as_Register($tmp2$$reg);
4056 Register resultReg = as_Register($result$$reg);
4057
4058 int length_offset = arrayOopDesc::length_offset_in_bytes();
4059 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
4060
4061 // Check the input args
4062 masm.cmpptr(ary1Reg, ary2Reg);
4063 masm.jccb(Assembler::equal, TRUE_LABEL);
4064 masm.testptr(ary1Reg, ary1Reg);
4065 masm.jccb(Assembler::zero, FALSE_LABEL);
4066 masm.testptr(ary2Reg, ary2Reg);
4067 masm.jccb(Assembler::zero, FALSE_LABEL);
4068
4069 // Check the lengths
4070 masm.movl(tmp2Reg, Address(ary1Reg, length_offset));
4071 masm.movl(resultReg, Address(ary2Reg, length_offset));
4072 masm.cmpl(tmp2Reg, resultReg);
4073 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4074 masm.testl(resultReg, resultReg);
4075 masm.jccb(Assembler::zero, TRUE_LABEL);
4076
4077 // Load array addrs
4078 masm.lea(ary1Reg, Address(ary1Reg, base_offset));
4079 masm.lea(ary2Reg, Address(ary2Reg, base_offset));
4080
4081 // Set byte count
4082 masm.shll(tmp2Reg, 1);
4083 masm.movl(resultReg, tmp2Reg);
4084
4085
4086 if (UseSSE >=4 && UseSSE42Intrinsics) {
4087 // With SSE4.2, use double quad vector compare
4088 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
4089 // Compare 16-byte vectors
4090 masm.andl(tmp2Reg, 0xfffffff0); // vector count (in bytes)
4091 masm.andl(resultReg, 0x0000000e); // tail count (in bytes)
4092 masm.testl(tmp2Reg, tmp2Reg);
4093 masm.jccb(Assembler::zero, COMPARE_TAIL);
4094 masm.lea(ary1Reg, Address(ary1Reg, tmp2Reg, Address::times_1));
4095 masm.lea(ary2Reg, Address(ary2Reg, tmp2Reg, Address::times_1));
4096 masm.negl(tmp2Reg);
4097
4098 masm.bind(COMPARE_WIDE_VECTORS);
4099 masm.movdqu(xmm6, Address(ary1Reg, tmp2Reg, Address::times_1));
4100 masm.movdqu(xmm7, Address(ary2Reg, tmp2Reg, Address::times_1));
4101 masm.pxor(xmm6, xmm7);
4102 masm.ptest(xmm6, xmm6);
4103
4104 masm.jccb(Assembler::notZero, FALSE_LABEL);
4105 masm.addl(tmp2Reg, 16);
4106 masm.jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
4107 masm.bind(COMPARE_TAIL);
4108 masm.movl(tmp2Reg, resultReg);
4109 // Fallthru to tail compare
4110 }
4111
4112 // Compare 4-byte vectors
4113 masm.andl(tmp2Reg, 0xfffffffc); // vector count (in bytes)
4114 masm.andl(resultReg, 0x00000002); // tail char (in bytes)
4115 masm.testl(tmp2Reg, tmp2Reg);
4116 masm.jccb(Assembler::zero, COMPARE_CHAR);
4117 masm.lea(ary1Reg, Address(ary1Reg, tmp2Reg, Address::times_1));
4118 masm.lea(ary2Reg, Address(ary2Reg, tmp2Reg, Address::times_1));
4119 masm.negl(tmp2Reg);
4120
4121 masm.bind(COMPARE_VECTORS);
4122 masm.movl(tmp1Reg, Address(ary1Reg, tmp2Reg, Address::times_1));
4123 masm.cmpl(tmp1Reg, Address(ary2Reg, tmp2Reg, Address::times_1));
4124 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4125 masm.addl(tmp2Reg, 4);
4126 masm.jcc(Assembler::notZero, COMPARE_VECTORS);
4127
4128 // Compare trailing char (final 2 bytes), if any
4129 masm.bind(COMPARE_CHAR);
4130 masm.testl(resultReg, resultReg);
4131 masm.jccb(Assembler::zero, TRUE_LABEL);
4132 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, 0));
4133 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, 0));
4134 masm.cmpl(tmp1Reg, tmp2Reg);
4135 masm.jccb(Assembler::notEqual, FALSE_LABEL);
4136
4137 masm.bind(TRUE_LABEL);
4138 masm.movl(resultReg, 1); // return true
4139 masm.jmpb(DONE);
4140
4141 masm.bind(FALSE_LABEL);
4142 masm.xorl(resultReg, resultReg); // return false
4143
4144 // That's it
4145 masm.bind(DONE);
4146 %}
4147
4148 enc_class enc_pop_rdx() %{
4149 emit_opcode(cbuf,0x5A);
4150 %}
4151
4152 enc_class enc_rethrow() %{
4153 cbuf.set_inst_mark();
4154 emit_opcode(cbuf, 0xE9); // jmp entry
4155 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4,
4156 runtime_call_Relocation::spec(), RELOC_IMM32 );
4157 %}
4158
4159
4160 // Convert a double to an int. Java semantics require we do complex
4161 // manglelations in the corner cases. So we set the rounding mode to
4162 // 'zero', store the darned double down as an int, and reset the
4163 // rounding mode to 'nearest'. The hardware throws an exception which
4164 // patches up the correct value directly to the stack.
4165 enc_class D2I_encoding( regD src ) %{
4166 // Flip to round-to-zero mode. We attempted to allow invalid-op
4167 // exceptions here, so that a NAN or other corner-case value will
4168 // thrown an exception (but normal values get converted at full speed).
4169 // However, I2C adapters and other float-stack manglers leave pending
4170 // invalid-op exceptions hanging. We would have to clear them before
4171 // enabling them and that is more expensive than just testing for the
4172 // invalid value Intel stores down in the corner cases.
4173 emit_opcode(cbuf,0xD9); // FLDCW trunc
4174 emit_opcode(cbuf,0x2D);
4175 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4176 // Allocate a word
4177 emit_opcode(cbuf,0x83); // SUB ESP,4
4178 emit_opcode(cbuf,0xEC);
4179 emit_d8(cbuf,0x04);
4180 // Encoding assumes a double has been pushed into FPR0.
4181 // Store down the double as an int, popping the FPU stack
4182 emit_opcode(cbuf,0xDB); // FISTP [ESP]
4183 emit_opcode(cbuf,0x1C);
4184 emit_d8(cbuf,0x24);
4185 // Restore the rounding mode; mask the exception
4186 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4187 emit_opcode(cbuf,0x2D);
4188 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4189 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4190 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4191
4192 // Load the converted int; adjust CPU stack
4193 emit_opcode(cbuf,0x58); // POP EAX
4194 emit_opcode(cbuf,0x3D); // CMP EAX,imm
4195 emit_d32 (cbuf,0x80000000); // 0x80000000
4196 emit_opcode(cbuf,0x75); // JNE around_slow_call
4197 emit_d8 (cbuf,0x07); // Size of slow_call
4198 // Push src onto stack slow-path
4199 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4200 emit_d8 (cbuf,0xC0-1+$src$$reg );
4201 // CALL directly to the runtime
4202 cbuf.set_inst_mark();
4203 emit_opcode(cbuf,0xE8); // Call into runtime
4204 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4205 // Carry on here...
4206 %}
4207
4208 enc_class D2L_encoding( regD src ) %{
4209 emit_opcode(cbuf,0xD9); // FLDCW trunc
4210 emit_opcode(cbuf,0x2D);
4211 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4212 // Allocate a word
4213 emit_opcode(cbuf,0x83); // SUB ESP,8
4214 emit_opcode(cbuf,0xEC);
4215 emit_d8(cbuf,0x08);
4216 // Encoding assumes a double has been pushed into FPR0.
4217 // Store down the double as a long, popping the FPU stack
4218 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4219 emit_opcode(cbuf,0x3C);
4220 emit_d8(cbuf,0x24);
4221 // Restore the rounding mode; mask the exception
4222 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4223 emit_opcode(cbuf,0x2D);
4224 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4225 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4226 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4227
4228 // Load the converted int; adjust CPU stack
4229 emit_opcode(cbuf,0x58); // POP EAX
4230 emit_opcode(cbuf,0x5A); // POP EDX
4231 emit_opcode(cbuf,0x81); // CMP EDX,imm
4232 emit_d8 (cbuf,0xFA); // rdx
4233 emit_d32 (cbuf,0x80000000); // 0x80000000
4234 emit_opcode(cbuf,0x75); // JNE around_slow_call
4235 emit_d8 (cbuf,0x07+4); // Size of slow_call
4236 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4237 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4238 emit_opcode(cbuf,0x75); // JNE around_slow_call
4239 emit_d8 (cbuf,0x07); // Size of slow_call
4240 // Push src onto stack slow-path
4241 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
4242 emit_d8 (cbuf,0xC0-1+$src$$reg );
4243 // CALL directly to the runtime
4244 cbuf.set_inst_mark();
4245 emit_opcode(cbuf,0xE8); // Call into runtime
4246 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4247 // Carry on here...
4248 %}
4249
4250 enc_class X2L_encoding( regX src ) %{
4251 // Allocate a word
4252 emit_opcode(cbuf,0x83); // SUB ESP,8
4253 emit_opcode(cbuf,0xEC);
4254 emit_d8(cbuf,0x08);
4255
4256 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4257 emit_opcode (cbuf, 0x0F );
4258 emit_opcode (cbuf, 0x11 );
4259 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4260
4261 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4262 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4263
4264 emit_opcode(cbuf,0xD9); // FLDCW trunc
4265 emit_opcode(cbuf,0x2D);
4266 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4267
4268 // Encoding assumes a double has been pushed into FPR0.
4269 // Store down the double as a long, popping the FPU stack
4270 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4271 emit_opcode(cbuf,0x3C);
4272 emit_d8(cbuf,0x24);
4273
4274 // Restore the rounding mode; mask the exception
4275 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4276 emit_opcode(cbuf,0x2D);
4277 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4278 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4279 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4280
4281 // Load the converted int; adjust CPU stack
4282 emit_opcode(cbuf,0x58); // POP EAX
4283
4284 emit_opcode(cbuf,0x5A); // POP EDX
4285
4286 emit_opcode(cbuf,0x81); // CMP EDX,imm
4287 emit_d8 (cbuf,0xFA); // rdx
4288 emit_d32 (cbuf,0x80000000);// 0x80000000
4289
4290 emit_opcode(cbuf,0x75); // JNE around_slow_call
4291 emit_d8 (cbuf,0x13+4); // Size of slow_call
4292
4293 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4294 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4295
4296 emit_opcode(cbuf,0x75); // JNE around_slow_call
4297 emit_d8 (cbuf,0x13); // Size of slow_call
4298
4299 // Allocate a word
4300 emit_opcode(cbuf,0x83); // SUB ESP,4
4301 emit_opcode(cbuf,0xEC);
4302 emit_d8(cbuf,0x04);
4303
4304 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src
4305 emit_opcode (cbuf, 0x0F );
4306 emit_opcode (cbuf, 0x11 );
4307 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4308
4309 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4310 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4311
4312 emit_opcode(cbuf,0x83); // ADD ESP,4
4313 emit_opcode(cbuf,0xC4);
4314 emit_d8(cbuf,0x04);
4315
4316 // CALL directly to the runtime
4317 cbuf.set_inst_mark();
4318 emit_opcode(cbuf,0xE8); // Call into runtime
4319 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4320 // Carry on here...
4321 %}
4322
4323 enc_class XD2L_encoding( regXD src ) %{
4324 // Allocate a word
4325 emit_opcode(cbuf,0x83); // SUB ESP,8
4326 emit_opcode(cbuf,0xEC);
4327 emit_d8(cbuf,0x08);
4328
4329 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4330 emit_opcode (cbuf, 0x0F );
4331 emit_opcode (cbuf, 0x11 );
4332 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4333
4334 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4335 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4336
4337 emit_opcode(cbuf,0xD9); // FLDCW trunc
4338 emit_opcode(cbuf,0x2D);
4339 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
4340
4341 // Encoding assumes a double has been pushed into FPR0.
4342 // Store down the double as a long, popping the FPU stack
4343 emit_opcode(cbuf,0xDF); // FISTP [ESP]
4344 emit_opcode(cbuf,0x3C);
4345 emit_d8(cbuf,0x24);
4346
4347 // Restore the rounding mode; mask the exception
4348 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
4349 emit_opcode(cbuf,0x2D);
4350 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
4351 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
4352 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
4353
4354 // Load the converted int; adjust CPU stack
4355 emit_opcode(cbuf,0x58); // POP EAX
4356
4357 emit_opcode(cbuf,0x5A); // POP EDX
4358
4359 emit_opcode(cbuf,0x81); // CMP EDX,imm
4360 emit_d8 (cbuf,0xFA); // rdx
4361 emit_d32 (cbuf,0x80000000); // 0x80000000
4362
4363 emit_opcode(cbuf,0x75); // JNE around_slow_call
4364 emit_d8 (cbuf,0x13+4); // Size of slow_call
4365
4366 emit_opcode(cbuf,0x85); // TEST EAX,EAX
4367 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
4368
4369 emit_opcode(cbuf,0x75); // JNE around_slow_call
4370 emit_d8 (cbuf,0x13); // Size of slow_call
4371
4372 // Push src onto stack slow-path
4373 // Allocate a word
4374 emit_opcode(cbuf,0x83); // SUB ESP,8
4375 emit_opcode(cbuf,0xEC);
4376 emit_d8(cbuf,0x08);
4377
4378 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src
4379 emit_opcode (cbuf, 0x0F );
4380 emit_opcode (cbuf, 0x11 );
4381 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4382
4383 emit_opcode(cbuf,0xDD ); // FLD_D [ESP]
4384 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4385
4386 emit_opcode(cbuf,0x83); // ADD ESP,8
4387 emit_opcode(cbuf,0xC4);
4388 emit_d8(cbuf,0x08);
4389
4390 // CALL directly to the runtime
4391 cbuf.set_inst_mark();
4392 emit_opcode(cbuf,0xE8); // Call into runtime
4393 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4394 // Carry on here...
4395 %}
4396
4397 enc_class D2X_encoding( regX dst, regD src ) %{
4398 // Allocate a word
4399 emit_opcode(cbuf,0x83); // SUB ESP,4
4400 emit_opcode(cbuf,0xEC);
4401 emit_d8(cbuf,0x04);
4402 int pop = 0x02;
4403 if ($src$$reg != FPR1L_enc) {
4404 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
4405 emit_d8( cbuf, 0xC0-1+$src$$reg );
4406 pop = 0x03;
4407 }
4408 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP]
4409
4410 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP]
4411 emit_opcode (cbuf, 0x0F );
4412 emit_opcode (cbuf, 0x10 );
4413 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false);
4414
4415 emit_opcode(cbuf,0x83); // ADD ESP,4
4416 emit_opcode(cbuf,0xC4);
4417 emit_d8(cbuf,0x04);
4418 // Carry on here...
4419 %}
4420
4421 enc_class FX2I_encoding( regX src, eRegI dst ) %{
4422 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
4423
4424 // Compare the result to see if we need to go to the slow path
4425 emit_opcode(cbuf,0x81); // CMP dst,imm
4426 emit_rm (cbuf,0x3,0x7,$dst$$reg);
4427 emit_d32 (cbuf,0x80000000); // 0x80000000
4428
4429 emit_opcode(cbuf,0x75); // JNE around_slow_call
4430 emit_d8 (cbuf,0x13); // Size of slow_call
4431 // Store xmm to a temp memory
4432 // location and push it onto stack.
4433
4434 emit_opcode(cbuf,0x83); // SUB ESP,4
4435 emit_opcode(cbuf,0xEC);
4436 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4437
4438 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm
4439 emit_opcode (cbuf, 0x0F );
4440 emit_opcode (cbuf, 0x11 );
4441 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4442
4443 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP]
4444 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4445
4446 emit_opcode(cbuf,0x83); // ADD ESP,4
4447 emit_opcode(cbuf,0xC4);
4448 emit_d8(cbuf, $primary ? 0x8 : 0x4);
4449
4450 // CALL directly to the runtime
4451 cbuf.set_inst_mark();
4452 emit_opcode(cbuf,0xE8); // Call into runtime
4453 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
4454
4455 // Carry on here...
4456 %}
4457
4458 enc_class X2D_encoding( regD dst, regX src ) %{
4459 // Allocate a word
4460 emit_opcode(cbuf,0x83); // SUB ESP,4
4461 emit_opcode(cbuf,0xEC);
4462 emit_d8(cbuf,0x04);
4463
4464 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm
4465 emit_opcode (cbuf, 0x0F );
4466 emit_opcode (cbuf, 0x11 );
4467 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false);
4468
4469 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP]
4470 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false);
4471
4472 emit_opcode(cbuf,0x83); // ADD ESP,4
4473 emit_opcode(cbuf,0xC4);
4474 emit_d8(cbuf,0x04);
4475
4476 // Carry on here...
4477 %}
4478
4479 enc_class AbsXF_encoding(regX dst) %{
4480 address signmask_address=(address)float_signmask_pool;
4481 // andpd:\tANDPS $dst,[signconst]
4482 emit_opcode(cbuf, 0x0F);
4483 emit_opcode(cbuf, 0x54);
4484 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4485 emit_d32(cbuf, (int)signmask_address);
4486 %}
4487
4488 enc_class AbsXD_encoding(regXD dst) %{
4489 address signmask_address=(address)double_signmask_pool;
4490 // andpd:\tANDPD $dst,[signconst]
4491 emit_opcode(cbuf, 0x66);
4492 emit_opcode(cbuf, 0x0F);
4493 emit_opcode(cbuf, 0x54);
4494 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4495 emit_d32(cbuf, (int)signmask_address);
4496 %}
4497
4498 enc_class NegXF_encoding(regX dst) %{
4499 address signmask_address=(address)float_signflip_pool;
4500 // andpd:\tXORPS $dst,[signconst]
4501 emit_opcode(cbuf, 0x0F);
4502 emit_opcode(cbuf, 0x57);
4503 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4504 emit_d32(cbuf, (int)signmask_address);
4505 %}
4506
4507 enc_class NegXD_encoding(regXD dst) %{
4508 address signmask_address=(address)double_signflip_pool;
4509 // andpd:\tXORPD $dst,[signconst]
4510 emit_opcode(cbuf, 0x66);
4511 emit_opcode(cbuf, 0x0F);
4512 emit_opcode(cbuf, 0x57);
4513 emit_rm(cbuf, 0x0, $dst$$reg, 0x5);
4514 emit_d32(cbuf, (int)signmask_address);
4515 %}
4516
4517 enc_class FMul_ST_reg( eRegF src1 ) %{
4518 // Operand was loaded from memory into fp ST (stack top)
4519 // FMUL ST,$src /* D8 C8+i */
4520 emit_opcode(cbuf, 0xD8);
4521 emit_opcode(cbuf, 0xC8 + $src1$$reg);
4522 %}
4523
4524 enc_class FAdd_ST_reg( eRegF src2 ) %{
4525 // FADDP ST,src2 /* D8 C0+i */
4526 emit_opcode(cbuf, 0xD8);
4527 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4528 //could use FADDP src2,fpST /* DE C0+i */
4529 %}
4530
4531 enc_class FAddP_reg_ST( eRegF src2 ) %{
4532 // FADDP src2,ST /* DE C0+i */
4533 emit_opcode(cbuf, 0xDE);
4534 emit_opcode(cbuf, 0xC0 + $src2$$reg);
4535 %}
4536
4537 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{
4538 // Operand has been loaded into fp ST (stack top)
4539 // FSUB ST,$src1
4540 emit_opcode(cbuf, 0xD8);
4541 emit_opcode(cbuf, 0xE0 + $src1$$reg);
4542
4543 // FDIV
4544 emit_opcode(cbuf, 0xD8);
4545 emit_opcode(cbuf, 0xF0 + $src2$$reg);
4546 %}
4547
4548 enc_class MulFAddF (eRegF src1, eRegF src2) %{
4549 // Operand was loaded from memory into fp ST (stack top)
4550 // FADD ST,$src /* D8 C0+i */
4551 emit_opcode(cbuf, 0xD8);
4552 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4553
4554 // FMUL ST,src2 /* D8 C*+i */
4555 emit_opcode(cbuf, 0xD8);
4556 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4557 %}
4558
4559
4560 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{
4561 // Operand was loaded from memory into fp ST (stack top)
4562 // FADD ST,$src /* D8 C0+i */
4563 emit_opcode(cbuf, 0xD8);
4564 emit_opcode(cbuf, 0xC0 + $src1$$reg);
4565
4566 // FMULP src2,ST /* DE C8+i */
4567 emit_opcode(cbuf, 0xDE);
4568 emit_opcode(cbuf, 0xC8 + $src2$$reg);
4569 %}
4570
4571 enc_class enc_membar_acquire %{
4572 // Doug Lea believes this is not needed with current Sparcs and TSO.
4573 // MacroAssembler masm(&cbuf);
4574 // masm.membar();
4575 %}
4576
4577 enc_class enc_membar_release %{
4578 // Doug Lea believes this is not needed with current Sparcs and TSO.
4579 // MacroAssembler masm(&cbuf);
4580 // masm.membar();
4581 %}
4582
4583 enc_class enc_membar_volatile %{
4584 MacroAssembler masm(&cbuf);
4585 masm.membar(Assembler::Membar_mask_bits(Assembler::StoreLoad |
4586 Assembler::StoreStore));
4587 %}
4588
4589 // Atomically load the volatile long
4590 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
4591 emit_opcode(cbuf,0xDF);
4592 int rm_byte_opcode = 0x05;
4593 int base = $mem$$base;
4594 int index = $mem$$index;
4595 int scale = $mem$$scale;
4596 int displace = $mem$$disp;
4597 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4598 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4599 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
4600 %}
4601
4602 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{
4603 { // Atomic long load
4604 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4605 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4606 emit_opcode(cbuf,0x0F);
4607 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4608 int base = $mem$$base;
4609 int index = $mem$$index;
4610 int scale = $mem$$scale;
4611 int displace = $mem$$disp;
4612 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4613 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4614 }
4615 { // MOVSD $dst,$tmp ! atomic long store
4616 emit_opcode(cbuf,0xF2);
4617 emit_opcode(cbuf,0x0F);
4618 emit_opcode(cbuf,0x11);
4619 int base = $dst$$base;
4620 int index = $dst$$index;
4621 int scale = $dst$$scale;
4622 int displace = $dst$$disp;
4623 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals
4624 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4625 }
4626 %}
4627
4628 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{
4629 { // Atomic long load
4630 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem
4631 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4632 emit_opcode(cbuf,0x0F);
4633 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4634 int base = $mem$$base;
4635 int index = $mem$$index;
4636 int scale = $mem$$scale;
4637 int displace = $mem$$disp;
4638 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4639 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4640 }
4641 { // MOVD $dst.lo,$tmp
4642 emit_opcode(cbuf,0x66);
4643 emit_opcode(cbuf,0x0F);
4644 emit_opcode(cbuf,0x7E);
4645 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg);
4646 }
4647 { // PSRLQ $tmp,32
4648 emit_opcode(cbuf,0x66);
4649 emit_opcode(cbuf,0x0F);
4650 emit_opcode(cbuf,0x73);
4651 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg);
4652 emit_d8(cbuf, 0x20);
4653 }
4654 { // MOVD $dst.hi,$tmp
4655 emit_opcode(cbuf,0x66);
4656 emit_opcode(cbuf,0x0F);
4657 emit_opcode(cbuf,0x7E);
4658 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg));
4659 }
4660 %}
4661
4662 // Volatile Store Long. Must be atomic, so move it into
4663 // the FP TOS and then do a 64-bit FIST. Has to probe the
4664 // target address before the store (for null-ptr checks)
4665 // so the memory operand is used twice in the encoding.
4666 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
4667 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
4668 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop
4669 emit_opcode(cbuf,0xDF);
4670 int rm_byte_opcode = 0x07;
4671 int base = $mem$$base;
4672 int index = $mem$$index;
4673 int scale = $mem$$scale;
4674 int displace = $mem$$disp;
4675 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4676 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
4677 %}
4678
4679 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{
4680 { // Atomic long load
4681 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src]
4682 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66);
4683 emit_opcode(cbuf,0x0F);
4684 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12);
4685 int base = $src$$base;
4686 int index = $src$$index;
4687 int scale = $src$$scale;
4688 int displace = $src$$disp;
4689 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals
4690 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4691 }
4692 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4693 { // MOVSD $mem,$tmp ! atomic long store
4694 emit_opcode(cbuf,0xF2);
4695 emit_opcode(cbuf,0x0F);
4696 emit_opcode(cbuf,0x11);
4697 int base = $mem$$base;
4698 int index = $mem$$index;
4699 int scale = $mem$$scale;
4700 int displace = $mem$$disp;
4701 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4702 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4703 }
4704 %}
4705
4706 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{
4707 { // MOVD $tmp,$src.lo
4708 emit_opcode(cbuf,0x66);
4709 emit_opcode(cbuf,0x0F);
4710 emit_opcode(cbuf,0x6E);
4711 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
4712 }
4713 { // MOVD $tmp2,$src.hi
4714 emit_opcode(cbuf,0x66);
4715 emit_opcode(cbuf,0x0F);
4716 emit_opcode(cbuf,0x6E);
4717 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg));
4718 }
4719 { // PUNPCKLDQ $tmp,$tmp2
4720 emit_opcode(cbuf,0x66);
4721 emit_opcode(cbuf,0x0F);
4722 emit_opcode(cbuf,0x62);
4723 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg);
4724 }
4725 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop
4726 { // MOVSD $mem,$tmp ! atomic long store
4727 emit_opcode(cbuf,0xF2);
4728 emit_opcode(cbuf,0x0F);
4729 emit_opcode(cbuf,0x11);
4730 int base = $mem$$base;
4731 int index = $mem$$index;
4732 int scale = $mem$$scale;
4733 int displace = $mem$$disp;
4734 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
4735 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop);
4736 }
4737 %}
4738
4739 // Safepoint Poll. This polls the safepoint page, and causes an
4740 // exception if it is not readable. Unfortunately, it kills the condition code
4741 // in the process
4742 // We current use TESTL [spp],EDI
4743 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
4744
4745 enc_class Safepoint_Poll() %{
4746 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0);
4747 emit_opcode(cbuf,0x85);
4748 emit_rm (cbuf, 0x0, 0x7, 0x5);
4749 emit_d32(cbuf, (intptr_t)os::get_polling_page());
4750 %}
4751 %}
4752
4753
4754 //----------FRAME--------------------------------------------------------------
4755 // Definition of frame structure and management information.
4756 //
4757 // S T A C K L A Y O U T Allocators stack-slot number
4758 // | (to get allocators register number
4759 // G Owned by | | v add OptoReg::stack0())
4760 // r CALLER | |
4761 // o | +--------+ pad to even-align allocators stack-slot
4762 // w V | pad0 | numbers; owned by CALLER
4763 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
4764 // h ^ | in | 5
4765 // | | args | 4 Holes in incoming args owned by SELF
4766 // | | | | 3
4767 // | | +--------+
4768 // V | | old out| Empty on Intel, window on Sparc
4769 // | old |preserve| Must be even aligned.
4770 // | SP-+--------+----> Matcher::_old_SP, even aligned
4771 // | | in | 3 area for Intel ret address
4772 // Owned by |preserve| Empty on Sparc.
4773 // SELF +--------+
4774 // | | pad2 | 2 pad to align old SP
4775 // | +--------+ 1
4776 // | | locks | 0
4777 // | +--------+----> OptoReg::stack0(), even aligned
4778 // | | pad1 | 11 pad to align new SP
4779 // | +--------+
4780 // | | | 10
4781 // | | spills | 9 spills
4782 // V | | 8 (pad0 slot for callee)
4783 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
4784 // ^ | out | 7
4785 // | | args | 6 Holes in outgoing args owned by CALLEE
4786 // Owned by +--------+
4787 // CALLEE | new out| 6 Empty on Intel, window on Sparc
4788 // | new |preserve| Must be even-aligned.
4789 // | SP-+--------+----> Matcher::_new_SP, even aligned
4790 // | | |
4791 //
4792 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
4793 // known from SELF's arguments and the Java calling convention.
4794 // Region 6-7 is determined per call site.
4795 // Note 2: If the calling convention leaves holes in the incoming argument
4796 // area, those holes are owned by SELF. Holes in the outgoing area
4797 // are owned by the CALLEE. Holes should not be nessecary in the
4798 // incoming area, as the Java calling convention is completely under
4799 // the control of the AD file. Doubles can be sorted and packed to
4800 // avoid holes. Holes in the outgoing arguments may be nessecary for
4801 // varargs C calling conventions.
4802 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
4803 // even aligned with pad0 as needed.
4804 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
4805 // region 6-11 is even aligned; it may be padded out more so that
4806 // the region from SP to FP meets the minimum stack alignment.
4807
4808 frame %{
4809 // What direction does stack grow in (assumed to be same for C & Java)
4810 stack_direction(TOWARDS_LOW);
4811
4812 // These three registers define part of the calling convention
4813 // between compiled code and the interpreter.
4814 inline_cache_reg(EAX); // Inline Cache Register
4815 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
4816
4817 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
4818 cisc_spilling_operand_name(indOffset32);
4819
4820 // Number of stack slots consumed by locking an object
4821 sync_stack_slots(1);
4822
4823 // Compiled code's Frame Pointer
4824 frame_pointer(ESP);
4825 // Interpreter stores its frame pointer in a register which is
4826 // stored to the stack by I2CAdaptors.
4827 // I2CAdaptors convert from interpreted java to compiled java.
4828 interpreter_frame_pointer(EBP);
4829
4830 // Stack alignment requirement
4831 // Alignment size in bytes (128-bit -> 16 bytes)
4832 stack_alignment(StackAlignmentInBytes);
4833
4834 // Number of stack slots between incoming argument block and the start of
4835 // a new frame. The PROLOG must add this many slots to the stack. The
4836 // EPILOG must remove this many slots. Intel needs one slot for
4837 // return address and one for rbp, (must save rbp)
4838 in_preserve_stack_slots(2+VerifyStackAtCalls);
4839
4840 // Number of outgoing stack slots killed above the out_preserve_stack_slots
4841 // for calls to C. Supports the var-args backing area for register parms.
4842 varargs_C_out_slots_killed(0);
4843
4844 // The after-PROLOG location of the return address. Location of
4845 // return address specifies a type (REG or STACK) and a number
4846 // representing the register number (i.e. - use a register name) or
4847 // stack slot.
4848 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
4849 // Otherwise, it is above the locks and verification slot and alignment word
4850 return_addr(STACK - 1 +
4851 round_to(1+VerifyStackAtCalls+
4852 Compile::current()->fixed_slots(),
4853 (StackAlignmentInBytes/wordSize)));
4854
4855 // Body of function which returns an integer array locating
4856 // arguments either in registers or in stack slots. Passed an array
4857 // of ideal registers called "sig" and a "length" count. Stack-slot
4858 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4859 // arguments for a CALLEE. Incoming stack arguments are
4860 // automatically biased by the preserve_stack_slots field above.
4861 calling_convention %{
4862 // No difference between ingoing/outgoing just pass false
4863 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
4864 %}
4865
4866
4867 // Body of function which returns an integer array locating
4868 // arguments either in registers or in stack slots. Passed an array
4869 // of ideal registers called "sig" and a "length" count. Stack-slot
4870 // offsets are based on outgoing arguments, i.e. a CALLER setting up
4871 // arguments for a CALLEE. Incoming stack arguments are
4872 // automatically biased by the preserve_stack_slots field above.
4873 c_calling_convention %{
4874 // This is obviously always outgoing
4875 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
4876 %}
4877
4878 // Location of C & interpreter return values
4879 c_return_value %{
4880 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4881 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4882 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4883
4884 // in SSE2+ mode we want to keep the FPU stack clean so pretend
4885 // that C functions return float and double results in XMM0.
4886 if( ideal_reg == Op_RegD && UseSSE>=2 )
4887 return OptoRegPair(XMM0b_num,XMM0a_num);
4888 if( ideal_reg == Op_RegF && UseSSE>=2 )
4889 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4890
4891 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4892 %}
4893
4894 // Location of return values
4895 return_value %{
4896 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
4897 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
4898 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
4899 if( ideal_reg == Op_RegD && UseSSE>=2 )
4900 return OptoRegPair(XMM0b_num,XMM0a_num);
4901 if( ideal_reg == Op_RegF && UseSSE>=1 )
4902 return OptoRegPair(OptoReg::Bad,XMM0a_num);
4903 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
4904 %}
4905
4906 %}
4907
4908 //----------ATTRIBUTES---------------------------------------------------------
4909 //----------Operand Attributes-------------------------------------------------
4910 op_attrib op_cost(0); // Required cost attribute
4911
4912 //----------Instruction Attributes---------------------------------------------
4913 ins_attrib ins_cost(100); // Required cost attribute
4914 ins_attrib ins_size(8); // Required size attribute (in bits)
4915 ins_attrib ins_pc_relative(0); // Required PC Relative flag
4916 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
4917 // non-matching short branch variant of some
4918 // long branch?
4919 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
4920 // specifies the alignment that some part of the instruction (not
4921 // necessarily the start) requires. If > 1, a compute_padding()
4922 // function must be provided for the instruction
4923
4924 //----------OPERANDS-----------------------------------------------------------
4925 // Operand definitions must precede instruction definitions for correct parsing
4926 // in the ADLC because operands constitute user defined types which are used in
4927 // instruction definitions.
4928
4929 //----------Simple Operands----------------------------------------------------
4930 // Immediate Operands
4931 // Integer Immediate
4932 operand immI() %{
4933 match(ConI);
4934
4935 op_cost(10);
4936 format %{ %}
4937 interface(CONST_INTER);
4938 %}
4939
4940 // Constant for test vs zero
4941 operand immI0() %{
4942 predicate(n->get_int() == 0);
4943 match(ConI);
4944
4945 op_cost(0);
4946 format %{ %}
4947 interface(CONST_INTER);
4948 %}
4949
4950 // Constant for increment
4951 operand immI1() %{
4952 predicate(n->get_int() == 1);
4953 match(ConI);
4954
4955 op_cost(0);
4956 format %{ %}
4957 interface(CONST_INTER);
4958 %}
4959
4960 // Constant for decrement
4961 operand immI_M1() %{
4962 predicate(n->get_int() == -1);
4963 match(ConI);
4964
4965 op_cost(0);
4966 format %{ %}
4967 interface(CONST_INTER);
4968 %}
4969
4970 // Valid scale values for addressing modes
4971 operand immI2() %{
4972 predicate(0 <= n->get_int() && (n->get_int() <= 3));
4973 match(ConI);
4974
4975 format %{ %}
4976 interface(CONST_INTER);
4977 %}
4978
4979 operand immI8() %{
4980 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
4981 match(ConI);
4982
4983 op_cost(5);
4984 format %{ %}
4985 interface(CONST_INTER);
4986 %}
4987
4988 operand immI16() %{
4989 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
4990 match(ConI);
4991
4992 op_cost(10);
4993 format %{ %}
4994 interface(CONST_INTER);
4995 %}
4996
4997 // Constant for long shifts
4998 operand immI_32() %{
4999 predicate( n->get_int() == 32 );
5000 match(ConI);
5001
5002 op_cost(0);
5003 format %{ %}
5004 interface(CONST_INTER);
5005 %}
5006
5007 operand immI_1_31() %{
5008 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
5009 match(ConI);
5010
5011 op_cost(0);
5012 format %{ %}
5013 interface(CONST_INTER);
5014 %}
5015
5016 operand immI_32_63() %{
5017 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
5018 match(ConI);
5019 op_cost(0);
5020
5021 format %{ %}
5022 interface(CONST_INTER);
5023 %}
5024
5025 operand immI_1() %{
5026 predicate( n->get_int() == 1 );
5027 match(ConI);
5028
5029 op_cost(0);
5030 format %{ %}
5031 interface(CONST_INTER);
5032 %}
5033
5034 operand immI_2() %{
5035 predicate( n->get_int() == 2 );
5036 match(ConI);
5037
5038 op_cost(0);
5039 format %{ %}
5040 interface(CONST_INTER);
5041 %}
5042
5043 operand immI_3() %{
5044 predicate( n->get_int() == 3 );
5045 match(ConI);
5046
5047 op_cost(0);
5048 format %{ %}
5049 interface(CONST_INTER);
5050 %}
5051
5052 // Pointer Immediate
5053 operand immP() %{
5054 match(ConP);
5055
5056 op_cost(10);
5057 format %{ %}
5058 interface(CONST_INTER);
5059 %}
5060
5061 // NULL Pointer Immediate
5062 operand immP0() %{
5063 predicate( n->get_ptr() == 0 );
5064 match(ConP);
5065 op_cost(0);
5066
5067 format %{ %}
5068 interface(CONST_INTER);
5069 %}
5070
5071 // Long Immediate
5072 operand immL() %{
5073 match(ConL);
5074
5075 op_cost(20);
5076 format %{ %}
5077 interface(CONST_INTER);
5078 %}
5079
5080 // Long Immediate zero
5081 operand immL0() %{
5082 predicate( n->get_long() == 0L );
5083 match(ConL);
5084 op_cost(0);
5085
5086 format %{ %}
5087 interface(CONST_INTER);
5088 %}
5089
5090 // Long Immediate zero
5091 operand immL_M1() %{
5092 predicate( n->get_long() == -1L );
5093 match(ConL);
5094 op_cost(0);
5095
5096 format %{ %}
5097 interface(CONST_INTER);
5098 %}
5099
5100 // Long immediate from 0 to 127.
5101 // Used for a shorter form of long mul by 10.
5102 operand immL_127() %{
5103 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
5104 match(ConL);
5105 op_cost(0);
5106
5107 format %{ %}
5108 interface(CONST_INTER);
5109 %}
5110
5111 // Long Immediate: low 32-bit mask
5112 operand immL_32bits() %{
5113 predicate(n->get_long() == 0xFFFFFFFFL);
5114 match(ConL);
5115 op_cost(0);
5116
5117 format %{ %}
5118 interface(CONST_INTER);
5119 %}
5120
5121 // Long Immediate: low 32-bit mask
5122 operand immL32() %{
5123 predicate(n->get_long() == (int)(n->get_long()));
5124 match(ConL);
5125 op_cost(20);
5126
5127 format %{ %}
5128 interface(CONST_INTER);
5129 %}
5130
5131 //Double Immediate zero
5132 operand immD0() %{
5133 // Do additional (and counter-intuitive) test against NaN to work around VC++
5134 // bug that generates code such that NaNs compare equal to 0.0
5135 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
5136 match(ConD);
5137
5138 op_cost(5);
5139 format %{ %}
5140 interface(CONST_INTER);
5141 %}
5142
5143 // Double Immediate
5144 operand immD1() %{
5145 predicate( UseSSE<=1 && n->getd() == 1.0 );
5146 match(ConD);
5147
5148 op_cost(5);
5149 format %{ %}
5150 interface(CONST_INTER);
5151 %}
5152
5153 // Double Immediate
5154 operand immD() %{
5155 predicate(UseSSE<=1);
5156 match(ConD);
5157
5158 op_cost(5);
5159 format %{ %}
5160 interface(CONST_INTER);
5161 %}
5162
5163 operand immXD() %{
5164 predicate(UseSSE>=2);
5165 match(ConD);
5166
5167 op_cost(5);
5168 format %{ %}
5169 interface(CONST_INTER);
5170 %}
5171
5172 // Double Immediate zero
5173 operand immXD0() %{
5174 // Do additional (and counter-intuitive) test against NaN to work around VC++
5175 // bug that generates code such that NaNs compare equal to 0.0 AND do not
5176 // compare equal to -0.0.
5177 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
5178 match(ConD);
5179
5180 format %{ %}
5181 interface(CONST_INTER);
5182 %}
5183
5184 // Float Immediate zero
5185 operand immF0() %{
5186 predicate( UseSSE == 0 && n->getf() == 0.0 );
5187 match(ConF);
5188
5189 op_cost(5);
5190 format %{ %}
5191 interface(CONST_INTER);
5192 %}
5193
5194 // Float Immediate
5195 operand immF() %{
5196 predicate( UseSSE == 0 );
5197 match(ConF);
5198
5199 op_cost(5);
5200 format %{ %}
5201 interface(CONST_INTER);
5202 %}
5203
5204 // Float Immediate
5205 operand immXF() %{
5206 predicate(UseSSE >= 1);
5207 match(ConF);
5208
5209 op_cost(5);
5210 format %{ %}
5211 interface(CONST_INTER);
5212 %}
5213
5214 // Float Immediate zero. Zero and not -0.0
5215 operand immXF0() %{
5216 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
5217 match(ConF);
5218
5219 op_cost(5);
5220 format %{ %}
5221 interface(CONST_INTER);
5222 %}
5223
5224 // Immediates for special shifts (sign extend)
5225
5226 // Constants for increment
5227 operand immI_16() %{
5228 predicate( n->get_int() == 16 );
5229 match(ConI);
5230
5231 format %{ %}
5232 interface(CONST_INTER);
5233 %}
5234
5235 operand immI_24() %{
5236 predicate( n->get_int() == 24 );
5237 match(ConI);
5238
5239 format %{ %}
5240 interface(CONST_INTER);
5241 %}
5242
5243 // Constant for byte-wide masking
5244 operand immI_255() %{
5245 predicate( n->get_int() == 255 );
5246 match(ConI);
5247
5248 format %{ %}
5249 interface(CONST_INTER);
5250 %}
5251
5252 // Register Operands
5253 // Integer Register
5254 operand eRegI() %{
5255 constraint(ALLOC_IN_RC(e_reg));
5256 match(RegI);
5257 match(xRegI);
5258 match(eAXRegI);
5259 match(eBXRegI);
5260 match(eCXRegI);
5261 match(eDXRegI);
5262 match(eDIRegI);
5263 match(eSIRegI);
5264
5265 format %{ %}
5266 interface(REG_INTER);
5267 %}
5268
5269 // Subset of Integer Register
5270 operand xRegI(eRegI reg) %{
5271 constraint(ALLOC_IN_RC(x_reg));
5272 match(reg);
5273 match(eAXRegI);
5274 match(eBXRegI);
5275 match(eCXRegI);
5276 match(eDXRegI);
5277
5278 format %{ %}
5279 interface(REG_INTER);
5280 %}
5281
5282 // Special Registers
5283 operand eAXRegI(xRegI reg) %{
5284 constraint(ALLOC_IN_RC(eax_reg));
5285 match(reg);
5286 match(eRegI);
5287
5288 format %{ "EAX" %}
5289 interface(REG_INTER);
5290 %}
5291
5292 // Special Registers
5293 operand eBXRegI(xRegI reg) %{
5294 constraint(ALLOC_IN_RC(ebx_reg));
5295 match(reg);
5296 match(eRegI);
5297
5298 format %{ "EBX" %}
5299 interface(REG_INTER);
5300 %}
5301
5302 operand eCXRegI(xRegI reg) %{
5303 constraint(ALLOC_IN_RC(ecx_reg));
5304 match(reg);
5305 match(eRegI);
5306
5307 format %{ "ECX" %}
5308 interface(REG_INTER);
5309 %}
5310
5311 operand eDXRegI(xRegI reg) %{
5312 constraint(ALLOC_IN_RC(edx_reg));
5313 match(reg);
5314 match(eRegI);
5315
5316 format %{ "EDX" %}
5317 interface(REG_INTER);
5318 %}
5319
5320 operand eDIRegI(xRegI reg) %{
5321 constraint(ALLOC_IN_RC(edi_reg));
5322 match(reg);
5323 match(eRegI);
5324
5325 format %{ "EDI" %}
5326 interface(REG_INTER);
5327 %}
5328
5329 operand naxRegI() %{
5330 constraint(ALLOC_IN_RC(nax_reg));
5331 match(RegI);
5332 match(eCXRegI);
5333 match(eDXRegI);
5334 match(eSIRegI);
5335 match(eDIRegI);
5336
5337 format %{ %}
5338 interface(REG_INTER);
5339 %}
5340
5341 operand nadxRegI() %{
5342 constraint(ALLOC_IN_RC(nadx_reg));
5343 match(RegI);
5344 match(eBXRegI);
5345 match(eCXRegI);
5346 match(eSIRegI);
5347 match(eDIRegI);
5348
5349 format %{ %}
5350 interface(REG_INTER);
5351 %}
5352
5353 operand ncxRegI() %{
5354 constraint(ALLOC_IN_RC(ncx_reg));
5355 match(RegI);
5356 match(eAXRegI);
5357 match(eDXRegI);
5358 match(eSIRegI);
5359 match(eDIRegI);
5360
5361 format %{ %}
5362 interface(REG_INTER);
5363 %}
5364
5365 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
5366 // //
5367 operand eSIRegI(xRegI reg) %{
5368 constraint(ALLOC_IN_RC(esi_reg));
5369 match(reg);
5370 match(eRegI);
5371
5372 format %{ "ESI" %}
5373 interface(REG_INTER);
5374 %}
5375
5376 // Pointer Register
5377 operand anyRegP() %{
5378 constraint(ALLOC_IN_RC(any_reg));
5379 match(RegP);
5380 match(eAXRegP);
5381 match(eBXRegP);
5382 match(eCXRegP);
5383 match(eDIRegP);
5384 match(eRegP);
5385
5386 format %{ %}
5387 interface(REG_INTER);
5388 %}
5389
5390 operand eRegP() %{
5391 constraint(ALLOC_IN_RC(e_reg));
5392 match(RegP);
5393 match(eAXRegP);
5394 match(eBXRegP);
5395 match(eCXRegP);
5396 match(eDIRegP);
5397
5398 format %{ %}
5399 interface(REG_INTER);
5400 %}
5401
5402 // On windows95, EBP is not safe to use for implicit null tests.
5403 operand eRegP_no_EBP() %{
5404 constraint(ALLOC_IN_RC(e_reg_no_rbp));
5405 match(RegP);
5406 match(eAXRegP);
5407 match(eBXRegP);
5408 match(eCXRegP);
5409 match(eDIRegP);
5410
5411 op_cost(100);
5412 format %{ %}
5413 interface(REG_INTER);
5414 %}
5415
5416 operand naxRegP() %{
5417 constraint(ALLOC_IN_RC(nax_reg));
5418 match(RegP);
5419 match(eBXRegP);
5420 match(eDXRegP);
5421 match(eCXRegP);
5422 match(eSIRegP);
5423 match(eDIRegP);
5424
5425 format %{ %}
5426 interface(REG_INTER);
5427 %}
5428
5429 operand nabxRegP() %{
5430 constraint(ALLOC_IN_RC(nabx_reg));
5431 match(RegP);
5432 match(eCXRegP);
5433 match(eDXRegP);
5434 match(eSIRegP);
5435 match(eDIRegP);
5436
5437 format %{ %}
5438 interface(REG_INTER);
5439 %}
5440
5441 operand pRegP() %{
5442 constraint(ALLOC_IN_RC(p_reg));
5443 match(RegP);
5444 match(eBXRegP);
5445 match(eDXRegP);
5446 match(eSIRegP);
5447 match(eDIRegP);
5448
5449 format %{ %}
5450 interface(REG_INTER);
5451 %}
5452
5453 // Special Registers
5454 // Return a pointer value
5455 operand eAXRegP(eRegP reg) %{
5456 constraint(ALLOC_IN_RC(eax_reg));
5457 match(reg);
5458 format %{ "EAX" %}
5459 interface(REG_INTER);
5460 %}
5461
5462 // Used in AtomicAdd
5463 operand eBXRegP(eRegP reg) %{
5464 constraint(ALLOC_IN_RC(ebx_reg));
5465 match(reg);
5466 format %{ "EBX" %}
5467 interface(REG_INTER);
5468 %}
5469
5470 // Tail-call (interprocedural jump) to interpreter
5471 operand eCXRegP(eRegP reg) %{
5472 constraint(ALLOC_IN_RC(ecx_reg));
5473 match(reg);
5474 format %{ "ECX" %}
5475 interface(REG_INTER);
5476 %}
5477
5478 operand eSIRegP(eRegP reg) %{
5479 constraint(ALLOC_IN_RC(esi_reg));
5480 match(reg);
5481 format %{ "ESI" %}
5482 interface(REG_INTER);
5483 %}
5484
5485 // Used in rep stosw
5486 operand eDIRegP(eRegP reg) %{
5487 constraint(ALLOC_IN_RC(edi_reg));
5488 match(reg);
5489 format %{ "EDI" %}
5490 interface(REG_INTER);
5491 %}
5492
5493 operand eBPRegP() %{
5494 constraint(ALLOC_IN_RC(ebp_reg));
5495 match(RegP);
5496 format %{ "EBP" %}
5497 interface(REG_INTER);
5498 %}
5499
5500 operand eRegL() %{
5501 constraint(ALLOC_IN_RC(long_reg));
5502 match(RegL);
5503 match(eADXRegL);
5504
5505 format %{ %}
5506 interface(REG_INTER);
5507 %}
5508
5509 operand eADXRegL( eRegL reg ) %{
5510 constraint(ALLOC_IN_RC(eadx_reg));
5511 match(reg);
5512
5513 format %{ "EDX:EAX" %}
5514 interface(REG_INTER);
5515 %}
5516
5517 operand eBCXRegL( eRegL reg ) %{
5518 constraint(ALLOC_IN_RC(ebcx_reg));
5519 match(reg);
5520
5521 format %{ "EBX:ECX" %}
5522 interface(REG_INTER);
5523 %}
5524
5525 // Special case for integer high multiply
5526 operand eADXRegL_low_only() %{
5527 constraint(ALLOC_IN_RC(eadx_reg));
5528 match(RegL);
5529
5530 format %{ "EAX" %}
5531 interface(REG_INTER);
5532 %}
5533
5534 // Flags register, used as output of compare instructions
5535 operand eFlagsReg() %{
5536 constraint(ALLOC_IN_RC(int_flags));
5537 match(RegFlags);
5538
5539 format %{ "EFLAGS" %}
5540 interface(REG_INTER);
5541 %}
5542
5543 // Flags register, used as output of FLOATING POINT compare instructions
5544 operand eFlagsRegU() %{
5545 constraint(ALLOC_IN_RC(int_flags));
5546 match(RegFlags);
5547
5548 format %{ "EFLAGS_U" %}
5549 interface(REG_INTER);
5550 %}
5551
5552 operand eFlagsRegUCF() %{
5553 constraint(ALLOC_IN_RC(int_flags));
5554 match(RegFlags);
5555 predicate(false);
5556
5557 format %{ "EFLAGS_U_CF" %}
5558 interface(REG_INTER);
5559 %}
5560
5561 // Condition Code Register used by long compare
5562 operand flagsReg_long_LTGE() %{
5563 constraint(ALLOC_IN_RC(int_flags));
5564 match(RegFlags);
5565 format %{ "FLAGS_LTGE" %}
5566 interface(REG_INTER);
5567 %}
5568 operand flagsReg_long_EQNE() %{
5569 constraint(ALLOC_IN_RC(int_flags));
5570 match(RegFlags);
5571 format %{ "FLAGS_EQNE" %}
5572 interface(REG_INTER);
5573 %}
5574 operand flagsReg_long_LEGT() %{
5575 constraint(ALLOC_IN_RC(int_flags));
5576 match(RegFlags);
5577 format %{ "FLAGS_LEGT" %}
5578 interface(REG_INTER);
5579 %}
5580
5581 // Float register operands
5582 operand regD() %{
5583 predicate( UseSSE < 2 );
5584 constraint(ALLOC_IN_RC(dbl_reg));
5585 match(RegD);
5586 match(regDPR1);
5587 match(regDPR2);
5588 format %{ %}
5589 interface(REG_INTER);
5590 %}
5591
5592 operand regDPR1(regD reg) %{
5593 predicate( UseSSE < 2 );
5594 constraint(ALLOC_IN_RC(dbl_reg0));
5595 match(reg);
5596 format %{ "FPR1" %}
5597 interface(REG_INTER);
5598 %}
5599
5600 operand regDPR2(regD reg) %{
5601 predicate( UseSSE < 2 );
5602 constraint(ALLOC_IN_RC(dbl_reg1));
5603 match(reg);
5604 format %{ "FPR2" %}
5605 interface(REG_INTER);
5606 %}
5607
5608 operand regnotDPR1(regD reg) %{
5609 predicate( UseSSE < 2 );
5610 constraint(ALLOC_IN_RC(dbl_notreg0));
5611 match(reg);
5612 format %{ %}
5613 interface(REG_INTER);
5614 %}
5615
5616 // XMM Double register operands
5617 operand regXD() %{
5618 predicate( UseSSE>=2 );
5619 constraint(ALLOC_IN_RC(xdb_reg));
5620 match(RegD);
5621 match(regXD6);
5622 match(regXD7);
5623 format %{ %}
5624 interface(REG_INTER);
5625 %}
5626
5627 // XMM6 double register operands
5628 operand regXD6(regXD reg) %{
5629 predicate( UseSSE>=2 );
5630 constraint(ALLOC_IN_RC(xdb_reg6));
5631 match(reg);
5632 format %{ "XMM6" %}
5633 interface(REG_INTER);
5634 %}
5635
5636 // XMM7 double register operands
5637 operand regXD7(regXD reg) %{
5638 predicate( UseSSE>=2 );
5639 constraint(ALLOC_IN_RC(xdb_reg7));
5640 match(reg);
5641 format %{ "XMM7" %}
5642 interface(REG_INTER);
5643 %}
5644
5645 // Float register operands
5646 operand regF() %{
5647 predicate( UseSSE < 2 );
5648 constraint(ALLOC_IN_RC(flt_reg));
5649 match(RegF);
5650 match(regFPR1);
5651 format %{ %}
5652 interface(REG_INTER);
5653 %}
5654
5655 // Float register operands
5656 operand regFPR1(regF reg) %{
5657 predicate( UseSSE < 2 );
5658 constraint(ALLOC_IN_RC(flt_reg0));
5659 match(reg);
5660 format %{ "FPR1" %}
5661 interface(REG_INTER);
5662 %}
5663
5664 // XMM register operands
5665 operand regX() %{
5666 predicate( UseSSE>=1 );
5667 constraint(ALLOC_IN_RC(xmm_reg));
5668 match(RegF);
5669 format %{ %}
5670 interface(REG_INTER);
5671 %}
5672
5673
5674 //----------Memory Operands----------------------------------------------------
5675 // Direct Memory Operand
5676 operand direct(immP addr) %{
5677 match(addr);
5678
5679 format %{ "[$addr]" %}
5680 interface(MEMORY_INTER) %{
5681 base(0xFFFFFFFF);
5682 index(0x4);
5683 scale(0x0);
5684 disp($addr);
5685 %}
5686 %}
5687
5688 // Indirect Memory Operand
5689 operand indirect(eRegP reg) %{
5690 constraint(ALLOC_IN_RC(e_reg));
5691 match(reg);
5692
5693 format %{ "[$reg]" %}
5694 interface(MEMORY_INTER) %{
5695 base($reg);
5696 index(0x4);
5697 scale(0x0);
5698 disp(0x0);
5699 %}
5700 %}
5701
5702 // Indirect Memory Plus Short Offset Operand
5703 operand indOffset8(eRegP reg, immI8 off) %{
5704 match(AddP reg off);
5705
5706 format %{ "[$reg + $off]" %}
5707 interface(MEMORY_INTER) %{
5708 base($reg);
5709 index(0x4);
5710 scale(0x0);
5711 disp($off);
5712 %}
5713 %}
5714
5715 // Indirect Memory Plus Long Offset Operand
5716 operand indOffset32(eRegP reg, immI off) %{
5717 match(AddP reg off);
5718
5719 format %{ "[$reg + $off]" %}
5720 interface(MEMORY_INTER) %{
5721 base($reg);
5722 index(0x4);
5723 scale(0x0);
5724 disp($off);
5725 %}
5726 %}
5727
5728 // Indirect Memory Plus Long Offset Operand
5729 operand indOffset32X(eRegI reg, immP off) %{
5730 match(AddP off reg);
5731
5732 format %{ "[$reg + $off]" %}
5733 interface(MEMORY_INTER) %{
5734 base($reg);
5735 index(0x4);
5736 scale(0x0);
5737 disp($off);
5738 %}
5739 %}
5740
5741 // Indirect Memory Plus Index Register Plus Offset Operand
5742 operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{
5743 match(AddP (AddP reg ireg) off);
5744
5745 op_cost(10);
5746 format %{"[$reg + $off + $ireg]" %}
5747 interface(MEMORY_INTER) %{
5748 base($reg);
5749 index($ireg);
5750 scale(0x0);
5751 disp($off);
5752 %}
5753 %}
5754
5755 // Indirect Memory Plus Index Register Plus Offset Operand
5756 operand indIndex(eRegP reg, eRegI ireg) %{
5757 match(AddP reg ireg);
5758
5759 op_cost(10);
5760 format %{"[$reg + $ireg]" %}
5761 interface(MEMORY_INTER) %{
5762 base($reg);
5763 index($ireg);
5764 scale(0x0);
5765 disp(0x0);
5766 %}
5767 %}
5768
5769 // // -------------------------------------------------------------------------
5770 // // 486 architecture doesn't support "scale * index + offset" with out a base
5771 // // -------------------------------------------------------------------------
5772 // // Scaled Memory Operands
5773 // // Indirect Memory Times Scale Plus Offset Operand
5774 // operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{
5775 // match(AddP off (LShiftI ireg scale));
5776 //
5777 // op_cost(10);
5778 // format %{"[$off + $ireg << $scale]" %}
5779 // interface(MEMORY_INTER) %{
5780 // base(0x4);
5781 // index($ireg);
5782 // scale($scale);
5783 // disp($off);
5784 // %}
5785 // %}
5786
5787 // Indirect Memory Times Scale Plus Index Register
5788 operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{
5789 match(AddP reg (LShiftI ireg scale));
5790
5791 op_cost(10);
5792 format %{"[$reg + $ireg << $scale]" %}
5793 interface(MEMORY_INTER) %{
5794 base($reg);
5795 index($ireg);
5796 scale($scale);
5797 disp(0x0);
5798 %}
5799 %}
5800
5801 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
5802 operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{
5803 match(AddP (AddP reg (LShiftI ireg scale)) off);
5804
5805 op_cost(10);
5806 format %{"[$reg + $off + $ireg << $scale]" %}
5807 interface(MEMORY_INTER) %{
5808 base($reg);
5809 index($ireg);
5810 scale($scale);
5811 disp($off);
5812 %}
5813 %}
5814
5815 //----------Load Long Memory Operands------------------------------------------
5816 // The load-long idiom will use it's address expression again after loading
5817 // the first word of the long. If the load-long destination overlaps with
5818 // registers used in the addressing expression, the 2nd half will be loaded
5819 // from a clobbered address. Fix this by requiring that load-long use
5820 // address registers that do not overlap with the load-long target.
5821
5822 // load-long support
5823 operand load_long_RegP() %{
5824 constraint(ALLOC_IN_RC(esi_reg));
5825 match(RegP);
5826 match(eSIRegP);
5827 op_cost(100);
5828 format %{ %}
5829 interface(REG_INTER);
5830 %}
5831
5832 // Indirect Memory Operand Long
5833 operand load_long_indirect(load_long_RegP reg) %{
5834 constraint(ALLOC_IN_RC(esi_reg));
5835 match(reg);
5836
5837 format %{ "[$reg]" %}
5838 interface(MEMORY_INTER) %{
5839 base($reg);
5840 index(0x4);
5841 scale(0x0);
5842 disp(0x0);
5843 %}
5844 %}
5845
5846 // Indirect Memory Plus Long Offset Operand
5847 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
5848 match(AddP reg off);
5849
5850 format %{ "[$reg + $off]" %}
5851 interface(MEMORY_INTER) %{
5852 base($reg);
5853 index(0x4);
5854 scale(0x0);
5855 disp($off);
5856 %}
5857 %}
5858
5859 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
5860
5861
5862 //----------Special Memory Operands--------------------------------------------
5863 // Stack Slot Operand - This operand is used for loading and storing temporary
5864 // values on the stack where a match requires a value to
5865 // flow through memory.
5866 operand stackSlotP(sRegP reg) %{
5867 constraint(ALLOC_IN_RC(stack_slots));
5868 // No match rule because this operand is only generated in matching
5869 format %{ "[$reg]" %}
5870 interface(MEMORY_INTER) %{
5871 base(0x4); // ESP
5872 index(0x4); // No Index
5873 scale(0x0); // No Scale
5874 disp($reg); // Stack Offset
5875 %}
5876 %}
5877
5878 operand stackSlotI(sRegI reg) %{
5879 constraint(ALLOC_IN_RC(stack_slots));
5880 // No match rule because this operand is only generated in matching
5881 format %{ "[$reg]" %}
5882 interface(MEMORY_INTER) %{
5883 base(0x4); // ESP
5884 index(0x4); // No Index
5885 scale(0x0); // No Scale
5886 disp($reg); // Stack Offset
5887 %}
5888 %}
5889
5890 operand stackSlotF(sRegF reg) %{
5891 constraint(ALLOC_IN_RC(stack_slots));
5892 // No match rule because this operand is only generated in matching
5893 format %{ "[$reg]" %}
5894 interface(MEMORY_INTER) %{
5895 base(0x4); // ESP
5896 index(0x4); // No Index
5897 scale(0x0); // No Scale
5898 disp($reg); // Stack Offset
5899 %}
5900 %}
5901
5902 operand stackSlotD(sRegD reg) %{
5903 constraint(ALLOC_IN_RC(stack_slots));
5904 // No match rule because this operand is only generated in matching
5905 format %{ "[$reg]" %}
5906 interface(MEMORY_INTER) %{
5907 base(0x4); // ESP
5908 index(0x4); // No Index
5909 scale(0x0); // No Scale
5910 disp($reg); // Stack Offset
5911 %}
5912 %}
5913
5914 operand stackSlotL(sRegL reg) %{
5915 constraint(ALLOC_IN_RC(stack_slots));
5916 // No match rule because this operand is only generated in matching
5917 format %{ "[$reg]" %}
5918 interface(MEMORY_INTER) %{
5919 base(0x4); // ESP
5920 index(0x4); // No Index
5921 scale(0x0); // No Scale
5922 disp($reg); // Stack Offset
5923 %}
5924 %}
5925
5926 //----------Memory Operands - Win95 Implicit Null Variants----------------
5927 // Indirect Memory Operand
5928 operand indirect_win95_safe(eRegP_no_EBP reg)
5929 %{
5930 constraint(ALLOC_IN_RC(e_reg));
5931 match(reg);
5932
5933 op_cost(100);
5934 format %{ "[$reg]" %}
5935 interface(MEMORY_INTER) %{
5936 base($reg);
5937 index(0x4);
5938 scale(0x0);
5939 disp(0x0);
5940 %}
5941 %}
5942
5943 // Indirect Memory Plus Short Offset Operand
5944 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
5945 %{
5946 match(AddP reg off);
5947
5948 op_cost(100);
5949 format %{ "[$reg + $off]" %}
5950 interface(MEMORY_INTER) %{
5951 base($reg);
5952 index(0x4);
5953 scale(0x0);
5954 disp($off);
5955 %}
5956 %}
5957
5958 // Indirect Memory Plus Long Offset Operand
5959 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
5960 %{
5961 match(AddP reg off);
5962
5963 op_cost(100);
5964 format %{ "[$reg + $off]" %}
5965 interface(MEMORY_INTER) %{
5966 base($reg);
5967 index(0x4);
5968 scale(0x0);
5969 disp($off);
5970 %}
5971 %}
5972
5973 // Indirect Memory Plus Index Register Plus Offset Operand
5974 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off)
5975 %{
5976 match(AddP (AddP reg ireg) off);
5977
5978 op_cost(100);
5979 format %{"[$reg + $off + $ireg]" %}
5980 interface(MEMORY_INTER) %{
5981 base($reg);
5982 index($ireg);
5983 scale(0x0);
5984 disp($off);
5985 %}
5986 %}
5987
5988 // Indirect Memory Times Scale Plus Index Register
5989 operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale)
5990 %{
5991 match(AddP reg (LShiftI ireg scale));
5992
5993 op_cost(100);
5994 format %{"[$reg + $ireg << $scale]" %}
5995 interface(MEMORY_INTER) %{
5996 base($reg);
5997 index($ireg);
5998 scale($scale);
5999 disp(0x0);
6000 %}
6001 %}
6002
6003 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
6004 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale)
6005 %{
6006 match(AddP (AddP reg (LShiftI ireg scale)) off);
6007
6008 op_cost(100);
6009 format %{"[$reg + $off + $ireg << $scale]" %}
6010 interface(MEMORY_INTER) %{
6011 base($reg);
6012 index($ireg);
6013 scale($scale);
6014 disp($off);
6015 %}
6016 %}
6017
6018 //----------Conditional Branch Operands----------------------------------------
6019 // Comparison Op - This is the operation of the comparison, and is limited to
6020 // the following set of codes:
6021 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
6022 //
6023 // Other attributes of the comparison, such as unsignedness, are specified
6024 // by the comparison instruction that sets a condition code flags register.
6025 // That result is represented by a flags operand whose subtype is appropriate
6026 // to the unsignedness (etc.) of the comparison.
6027 //
6028 // Later, the instruction which matches both the Comparison Op (a Bool) and
6029 // the flags (produced by the Cmp) specifies the coding of the comparison op
6030 // by matching a specific subtype of Bool operand below, such as cmpOpU.
6031
6032 // Comparision Code
6033 operand cmpOp() %{
6034 match(Bool);
6035
6036 format %{ "" %}
6037 interface(COND_INTER) %{
6038 equal(0x4, "e");
6039 not_equal(0x5, "ne");
6040 less(0xC, "l");
6041 greater_equal(0xD, "ge");
6042 less_equal(0xE, "le");
6043 greater(0xF, "g");
6044 %}
6045 %}
6046
6047 // Comparison Code, unsigned compare. Used by FP also, with
6048 // C2 (unordered) turned into GT or LT already. The other bits
6049 // C0 and C3 are turned into Carry & Zero flags.
6050 operand cmpOpU() %{
6051 match(Bool);
6052
6053 format %{ "" %}
6054 interface(COND_INTER) %{
6055 equal(0x4, "e");
6056 not_equal(0x5, "ne");
6057 less(0x2, "b");
6058 greater_equal(0x3, "nb");
6059 less_equal(0x6, "be");
6060 greater(0x7, "nbe");
6061 %}
6062 %}
6063
6064 // Floating comparisons that don't require any fixup for the unordered case
6065 operand cmpOpUCF() %{
6066 match(Bool);
6067 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
6068 n->as_Bool()->_test._test == BoolTest::ge ||
6069 n->as_Bool()->_test._test == BoolTest::le ||
6070 n->as_Bool()->_test._test == BoolTest::gt);
6071 format %{ "" %}
6072 interface(COND_INTER) %{
6073 equal(0x4, "e");
6074 not_equal(0x5, "ne");
6075 less(0x2, "b");
6076 greater_equal(0x3, "nb");
6077 less_equal(0x6, "be");
6078 greater(0x7, "nbe");
6079 %}
6080 %}
6081
6082
6083 // Floating comparisons that can be fixed up with extra conditional jumps
6084 operand cmpOpUCF2() %{
6085 match(Bool);
6086 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
6087 n->as_Bool()->_test._test == BoolTest::eq);
6088 format %{ "" %}
6089 interface(COND_INTER) %{
6090 equal(0x4, "e");
6091 not_equal(0x5, "ne");
6092 less(0x2, "b");
6093 greater_equal(0x3, "nb");
6094 less_equal(0x6, "be");
6095 greater(0x7, "nbe");
6096 %}
6097 %}
6098
6099 // Comparison Code for FP conditional move
6100 operand cmpOp_fcmov() %{
6101 match(Bool);
6102
6103 format %{ "" %}
6104 interface(COND_INTER) %{
6105 equal (0x0C8);
6106 not_equal (0x1C8);
6107 less (0x0C0);
6108 greater_equal(0x1C0);
6109 less_equal (0x0D0);
6110 greater (0x1D0);
6111 %}
6112 %}
6113
6114 // Comparision Code used in long compares
6115 operand cmpOp_commute() %{
6116 match(Bool);
6117
6118 format %{ "" %}
6119 interface(COND_INTER) %{
6120 equal(0x4, "e");
6121 not_equal(0x5, "ne");
6122 less(0xF, "g");
6123 greater_equal(0xE, "le");
6124 less_equal(0xD, "ge");
6125 greater(0xC, "l");
6126 %}
6127 %}
6128
6129 //----------OPERAND CLASSES----------------------------------------------------
6130 // Operand Classes are groups of operands that are used as to simplify
6131 // instruction definitions by not requiring the AD writer to specify seperate
6132 // instructions for every form of operand when the instruction accepts
6133 // multiple operand types with the same basic encoding and format. The classic
6134 // case of this is memory operands.
6135
6136 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
6137 indIndex, indIndexScale, indIndexScaleOffset);
6138
6139 // Long memory operations are encoded in 2 instructions and a +4 offset.
6140 // This means some kind of offset is always required and you cannot use
6141 // an oop as the offset (done when working on static globals).
6142 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
6143 indIndex, indIndexScale, indIndexScaleOffset);
6144
6145
6146 //----------PIPELINE-----------------------------------------------------------
6147 // Rules which define the behavior of the target architectures pipeline.
6148 pipeline %{
6149
6150 //----------ATTRIBUTES---------------------------------------------------------
6151 attributes %{
6152 variable_size_instructions; // Fixed size instructions
6153 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
6154 instruction_unit_size = 1; // An instruction is 1 bytes long
6155 instruction_fetch_unit_size = 16; // The processor fetches one line
6156 instruction_fetch_units = 1; // of 16 bytes
6157
6158 // List of nop instructions
6159 nops( MachNop );
6160 %}
6161
6162 //----------RESOURCES----------------------------------------------------------
6163 // Resources are the functional units available to the machine
6164
6165 // Generic P2/P3 pipeline
6166 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
6167 // 3 instructions decoded per cycle.
6168 // 2 load/store ops per cycle, 1 branch, 1 FPU,
6169 // 2 ALU op, only ALU0 handles mul/div instructions.
6170 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
6171 MS0, MS1, MEM = MS0 | MS1,
6172 BR, FPU,
6173 ALU0, ALU1, ALU = ALU0 | ALU1 );
6174
6175 //----------PIPELINE DESCRIPTION-----------------------------------------------
6176 // Pipeline Description specifies the stages in the machine's pipeline
6177
6178 // Generic P2/P3 pipeline
6179 pipe_desc(S0, S1, S2, S3, S4, S5);
6180
6181 //----------PIPELINE CLASSES---------------------------------------------------
6182 // Pipeline Classes describe the stages in which input and output are
6183 // referenced by the hardware pipeline.
6184
6185 // Naming convention: ialu or fpu
6186 // Then: _reg
6187 // Then: _reg if there is a 2nd register
6188 // Then: _long if it's a pair of instructions implementing a long
6189 // Then: _fat if it requires the big decoder
6190 // Or: _mem if it requires the big decoder and a memory unit.
6191
6192 // Integer ALU reg operation
6193 pipe_class ialu_reg(eRegI dst) %{
6194 single_instruction;
6195 dst : S4(write);
6196 dst : S3(read);
6197 DECODE : S0; // any decoder
6198 ALU : S3; // any alu
6199 %}
6200
6201 // Long ALU reg operation
6202 pipe_class ialu_reg_long(eRegL dst) %{
6203 instruction_count(2);
6204 dst : S4(write);
6205 dst : S3(read);
6206 DECODE : S0(2); // any 2 decoders
6207 ALU : S3(2); // both alus
6208 %}
6209
6210 // Integer ALU reg operation using big decoder
6211 pipe_class ialu_reg_fat(eRegI dst) %{
6212 single_instruction;
6213 dst : S4(write);
6214 dst : S3(read);
6215 D0 : S0; // big decoder only
6216 ALU : S3; // any alu
6217 %}
6218
6219 // Long ALU reg operation using big decoder
6220 pipe_class ialu_reg_long_fat(eRegL dst) %{
6221 instruction_count(2);
6222 dst : S4(write);
6223 dst : S3(read);
6224 D0 : S0(2); // big decoder only; twice
6225 ALU : S3(2); // any 2 alus
6226 %}
6227
6228 // Integer ALU reg-reg operation
6229 pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{
6230 single_instruction;
6231 dst : S4(write);
6232 src : S3(read);
6233 DECODE : S0; // any decoder
6234 ALU : S3; // any alu
6235 %}
6236
6237 // Long ALU reg-reg operation
6238 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
6239 instruction_count(2);
6240 dst : S4(write);
6241 src : S3(read);
6242 DECODE : S0(2); // any 2 decoders
6243 ALU : S3(2); // both alus
6244 %}
6245
6246 // Integer ALU reg-reg operation
6247 pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{
6248 single_instruction;
6249 dst : S4(write);
6250 src : S3(read);
6251 D0 : S0; // big decoder only
6252 ALU : S3; // any alu
6253 %}
6254
6255 // Long ALU reg-reg operation
6256 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
6257 instruction_count(2);
6258 dst : S4(write);
6259 src : S3(read);
6260 D0 : S0(2); // big decoder only; twice
6261 ALU : S3(2); // both alus
6262 %}
6263
6264 // Integer ALU reg-mem operation
6265 pipe_class ialu_reg_mem(eRegI dst, memory mem) %{
6266 single_instruction;
6267 dst : S5(write);
6268 mem : S3(read);
6269 D0 : S0; // big decoder only
6270 ALU : S4; // any alu
6271 MEM : S3; // any mem
6272 %}
6273
6274 // Long ALU reg-mem operation
6275 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
6276 instruction_count(2);
6277 dst : S5(write);
6278 mem : S3(read);
6279 D0 : S0(2); // big decoder only; twice
6280 ALU : S4(2); // any 2 alus
6281 MEM : S3(2); // both mems
6282 %}
6283
6284 // Integer mem operation (prefetch)
6285 pipe_class ialu_mem(memory mem)
6286 %{
6287 single_instruction;
6288 mem : S3(read);
6289 D0 : S0; // big decoder only
6290 MEM : S3; // any mem
6291 %}
6292
6293 // Integer Store to Memory
6294 pipe_class ialu_mem_reg(memory mem, eRegI src) %{
6295 single_instruction;
6296 mem : S3(read);
6297 src : S5(read);
6298 D0 : S0; // big decoder only
6299 ALU : S4; // any alu
6300 MEM : S3;
6301 %}
6302
6303 // Long Store to Memory
6304 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
6305 instruction_count(2);
6306 mem : S3(read);
6307 src : S5(read);
6308 D0 : S0(2); // big decoder only; twice
6309 ALU : S4(2); // any 2 alus
6310 MEM : S3(2); // Both mems
6311 %}
6312
6313 // Integer Store to Memory
6314 pipe_class ialu_mem_imm(memory mem) %{
6315 single_instruction;
6316 mem : S3(read);
6317 D0 : S0; // big decoder only
6318 ALU : S4; // any alu
6319 MEM : S3;
6320 %}
6321
6322 // Integer ALU0 reg-reg operation
6323 pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{
6324 single_instruction;
6325 dst : S4(write);
6326 src : S3(read);
6327 D0 : S0; // Big decoder only
6328 ALU0 : S3; // only alu0
6329 %}
6330
6331 // Integer ALU0 reg-mem operation
6332 pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{
6333 single_instruction;
6334 dst : S5(write);
6335 mem : S3(read);
6336 D0 : S0; // big decoder only
6337 ALU0 : S4; // ALU0 only
6338 MEM : S3; // any mem
6339 %}
6340
6341 // Integer ALU reg-reg operation
6342 pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{
6343 single_instruction;
6344 cr : S4(write);
6345 src1 : S3(read);
6346 src2 : S3(read);
6347 DECODE : S0; // any decoder
6348 ALU : S3; // any alu
6349 %}
6350
6351 // Integer ALU reg-imm operation
6352 pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{
6353 single_instruction;
6354 cr : S4(write);
6355 src1 : S3(read);
6356 DECODE : S0; // any decoder
6357 ALU : S3; // any alu
6358 %}
6359
6360 // Integer ALU reg-mem operation
6361 pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{
6362 single_instruction;
6363 cr : S4(write);
6364 src1 : S3(read);
6365 src2 : S3(read);
6366 D0 : S0; // big decoder only
6367 ALU : S4; // any alu
6368 MEM : S3;
6369 %}
6370
6371 // Conditional move reg-reg
6372 pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{
6373 instruction_count(4);
6374 y : S4(read);
6375 q : S3(read);
6376 p : S3(read);
6377 DECODE : S0(4); // any decoder
6378 %}
6379
6380 // Conditional move reg-reg
6381 pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{
6382 single_instruction;
6383 dst : S4(write);
6384 src : S3(read);
6385 cr : S3(read);
6386 DECODE : S0; // any decoder
6387 %}
6388
6389 // Conditional move reg-mem
6390 pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{
6391 single_instruction;
6392 dst : S4(write);
6393 src : S3(read);
6394 cr : S3(read);
6395 DECODE : S0; // any decoder
6396 MEM : S3;
6397 %}
6398
6399 // Conditional move reg-reg long
6400 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
6401 single_instruction;
6402 dst : S4(write);
6403 src : S3(read);
6404 cr : S3(read);
6405 DECODE : S0(2); // any 2 decoders
6406 %}
6407
6408 // Conditional move double reg-reg
6409 pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{
6410 single_instruction;
6411 dst : S4(write);
6412 src : S3(read);
6413 cr : S3(read);
6414 DECODE : S0; // any decoder
6415 %}
6416
6417 // Float reg-reg operation
6418 pipe_class fpu_reg(regD dst) %{
6419 instruction_count(2);
6420 dst : S3(read);
6421 DECODE : S0(2); // any 2 decoders
6422 FPU : S3;
6423 %}
6424
6425 // Float reg-reg operation
6426 pipe_class fpu_reg_reg(regD dst, regD src) %{
6427 instruction_count(2);
6428 dst : S4(write);
6429 src : S3(read);
6430 DECODE : S0(2); // any 2 decoders
6431 FPU : S3;
6432 %}
6433
6434 // Float reg-reg operation
6435 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{
6436 instruction_count(3);
6437 dst : S4(write);
6438 src1 : S3(read);
6439 src2 : S3(read);
6440 DECODE : S0(3); // any 3 decoders
6441 FPU : S3(2);
6442 %}
6443
6444 // Float reg-reg operation
6445 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
6446 instruction_count(4);
6447 dst : S4(write);
6448 src1 : S3(read);
6449 src2 : S3(read);
6450 src3 : S3(read);
6451 DECODE : S0(4); // any 3 decoders
6452 FPU : S3(2);
6453 %}
6454
6455 // Float reg-reg operation
6456 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{
6457 instruction_count(4);
6458 dst : S4(write);
6459 src1 : S3(read);
6460 src2 : S3(read);
6461 src3 : S3(read);
6462 DECODE : S1(3); // any 3 decoders
6463 D0 : S0; // Big decoder only
6464 FPU : S3(2);
6465 MEM : S3;
6466 %}
6467
6468 // Float reg-mem operation
6469 pipe_class fpu_reg_mem(regD dst, memory mem) %{
6470 instruction_count(2);
6471 dst : S5(write);
6472 mem : S3(read);
6473 D0 : S0; // big decoder only
6474 DECODE : S1; // any decoder for FPU POP
6475 FPU : S4;
6476 MEM : S3; // any mem
6477 %}
6478
6479 // Float reg-mem operation
6480 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{
6481 instruction_count(3);
6482 dst : S5(write);
6483 src1 : S3(read);
6484 mem : S3(read);
6485 D0 : S0; // big decoder only
6486 DECODE : S1(2); // any decoder for FPU POP
6487 FPU : S4;
6488 MEM : S3; // any mem
6489 %}
6490
6491 // Float mem-reg operation
6492 pipe_class fpu_mem_reg(memory mem, regD src) %{
6493 instruction_count(2);
6494 src : S5(read);
6495 mem : S3(read);
6496 DECODE : S0; // any decoder for FPU PUSH
6497 D0 : S1; // big decoder only
6498 FPU : S4;
6499 MEM : S3; // any mem
6500 %}
6501
6502 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{
6503 instruction_count(3);
6504 src1 : S3(read);
6505 src2 : S3(read);
6506 mem : S3(read);
6507 DECODE : S0(2); // any decoder for FPU PUSH
6508 D0 : S1; // big decoder only
6509 FPU : S4;
6510 MEM : S3; // any mem
6511 %}
6512
6513 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{
6514 instruction_count(3);
6515 src1 : S3(read);
6516 src2 : S3(read);
6517 mem : S4(read);
6518 DECODE : S0; // any decoder for FPU PUSH
6519 D0 : S0(2); // big decoder only
6520 FPU : S4;
6521 MEM : S3(2); // any mem
6522 %}
6523
6524 pipe_class fpu_mem_mem(memory dst, memory src1) %{
6525 instruction_count(2);
6526 src1 : S3(read);
6527 dst : S4(read);
6528 D0 : S0(2); // big decoder only
6529 MEM : S3(2); // any mem
6530 %}
6531
6532 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
6533 instruction_count(3);
6534 src1 : S3(read);
6535 src2 : S3(read);
6536 dst : S4(read);
6537 D0 : S0(3); // big decoder only
6538 FPU : S4;
6539 MEM : S3(3); // any mem
6540 %}
6541
6542 pipe_class fpu_mem_reg_con(memory mem, regD src1) %{
6543 instruction_count(3);
6544 src1 : S4(read);
6545 mem : S4(read);
6546 DECODE : S0; // any decoder for FPU PUSH
6547 D0 : S0(2); // big decoder only
6548 FPU : S4;
6549 MEM : S3(2); // any mem
6550 %}
6551
6552 // Float load constant
6553 pipe_class fpu_reg_con(regD dst) %{
6554 instruction_count(2);
6555 dst : S5(write);
6556 D0 : S0; // big decoder only for the load
6557 DECODE : S1; // any decoder for FPU POP
6558 FPU : S4;
6559 MEM : S3; // any mem
6560 %}
6561
6562 // Float load constant
6563 pipe_class fpu_reg_reg_con(regD dst, regD src) %{
6564 instruction_count(3);
6565 dst : S5(write);
6566 src : S3(read);
6567 D0 : S0; // big decoder only for the load
6568 DECODE : S1(2); // any decoder for FPU POP
6569 FPU : S4;
6570 MEM : S3; // any mem
6571 %}
6572
6573 // UnConditional branch
6574 pipe_class pipe_jmp( label labl ) %{
6575 single_instruction;
6576 BR : S3;
6577 %}
6578
6579 // Conditional branch
6580 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
6581 single_instruction;
6582 cr : S1(read);
6583 BR : S3;
6584 %}
6585
6586 // Allocation idiom
6587 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
6588 instruction_count(1); force_serialization;
6589 fixed_latency(6);
6590 heap_ptr : S3(read);
6591 DECODE : S0(3);
6592 D0 : S2;
6593 MEM : S3;
6594 ALU : S3(2);
6595 dst : S5(write);
6596 BR : S5;
6597 %}
6598
6599 // Generic big/slow expanded idiom
6600 pipe_class pipe_slow( ) %{
6601 instruction_count(10); multiple_bundles; force_serialization;
6602 fixed_latency(100);
6603 D0 : S0(2);
6604 MEM : S3(2);
6605 %}
6606
6607 // The real do-nothing guy
6608 pipe_class empty( ) %{
6609 instruction_count(0);
6610 %}
6611
6612 // Define the class for the Nop node
6613 define %{
6614 MachNop = empty;
6615 %}
6616
6617 %}
6618
6619 //----------INSTRUCTIONS-------------------------------------------------------
6620 //
6621 // match -- States which machine-independent subtree may be replaced
6622 // by this instruction.
6623 // ins_cost -- The estimated cost of this instruction is used by instruction
6624 // selection to identify a minimum cost tree of machine
6625 // instructions that matches a tree of machine-independent
6626 // instructions.
6627 // format -- A string providing the disassembly for this instruction.
6628 // The value of an instruction's operand may be inserted
6629 // by referring to it with a '$' prefix.
6630 // opcode -- Three instruction opcodes may be provided. These are referred
6631 // to within an encode class as $primary, $secondary, and $tertiary
6632 // respectively. The primary opcode is commonly used to
6633 // indicate the type of machine instruction, while secondary
6634 // and tertiary are often used for prefix options or addressing
6635 // modes.
6636 // ins_encode -- A list of encode classes with parameters. The encode class
6637 // name must have been defined in an 'enc_class' specification
6638 // in the encode section of the architecture description.
6639
6640 //----------BSWAP-Instruction--------------------------------------------------
6641 instruct bytes_reverse_int(eRegI dst) %{
6642 match(Set dst (ReverseBytesI dst));
6643
6644 format %{ "BSWAP $dst" %}
6645 opcode(0x0F, 0xC8);
6646 ins_encode( OpcP, OpcSReg(dst) );
6647 ins_pipe( ialu_reg );
6648 %}
6649
6650 instruct bytes_reverse_long(eRegL dst) %{
6651 match(Set dst (ReverseBytesL dst));
6652
6653 format %{ "BSWAP $dst.lo\n\t"
6654 "BSWAP $dst.hi\n\t"
6655 "XCHG $dst.lo $dst.hi" %}
6656
6657 ins_cost(125);
6658 ins_encode( bswap_long_bytes(dst) );
6659 ins_pipe( ialu_reg_reg);
6660 %}
6661
6662
6663 //----------Load/Store/Move Instructions---------------------------------------
6664 //----------Load Instructions--------------------------------------------------
6665 // Load Byte (8bit signed)
6666 instruct loadB(xRegI dst, memory mem) %{
6667 match(Set dst (LoadB mem));
6668
6669 ins_cost(125);
6670 format %{ "MOVSX8 $dst,$mem" %}
6671 opcode(0xBE, 0x0F);
6672 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6673 ins_pipe( ialu_reg_mem );
6674 %}
6675
6676 // Load Byte (8bit UNsigned)
6677 instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{
6678 match(Set dst (AndI (LoadB mem) bytemask));
6679
6680 ins_cost(125);
6681 format %{ "MOVZX8 $dst,$mem" %}
6682 opcode(0xB6, 0x0F);
6683 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6684 ins_pipe( ialu_reg_mem );
6685 %}
6686
6687 // Load Unsigned Short/Char (16bit unsigned)
6688 instruct loadUS(eRegI dst, memory mem) %{
6689 match(Set dst (LoadUS mem));
6690
6691 ins_cost(125);
6692 format %{ "MOVZX $dst,$mem" %}
6693 opcode(0xB7, 0x0F);
6694 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6695 ins_pipe( ialu_reg_mem );
6696 %}
6697
6698 // Load Integer
6699 instruct loadI(eRegI dst, memory mem) %{
6700 match(Set dst (LoadI mem));
6701
6702 ins_cost(125);
6703 format %{ "MOV $dst,$mem" %}
6704 opcode(0x8B);
6705 ins_encode( OpcP, RegMem(dst,mem));
6706 ins_pipe( ialu_reg_mem );
6707 %}
6708
6709 // Load Long. Cannot clobber address while loading, so restrict address
6710 // register to ESI
6711 instruct loadL(eRegL dst, load_long_memory mem) %{
6712 predicate(!((LoadLNode*)n)->require_atomic_access());
6713 match(Set dst (LoadL mem));
6714
6715 ins_cost(250);
6716 format %{ "MOV $dst.lo,$mem\n\t"
6717 "MOV $dst.hi,$mem+4" %}
6718 opcode(0x8B, 0x8B);
6719 ins_encode( OpcP, RegMem(dst,mem), OpcS, RegMem_Hi(dst,mem));
6720 ins_pipe( ialu_reg_long_mem );
6721 %}
6722
6723 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6724 // then store it down to the stack and reload on the int
6725 // side.
6726 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6727 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6728 match(Set dst (LoadL mem));
6729
6730 ins_cost(200);
6731 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6732 "FISTp $dst" %}
6733 ins_encode(enc_loadL_volatile(mem,dst));
6734 ins_pipe( fpu_reg_mem );
6735 %}
6736
6737 instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{
6738 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6739 match(Set dst (LoadL mem));
6740 effect(TEMP tmp);
6741 ins_cost(180);
6742 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6743 "MOVSD $dst,$tmp" %}
6744 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
6745 ins_pipe( pipe_slow );
6746 %}
6747
6748 instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{
6749 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6750 match(Set dst (LoadL mem));
6751 effect(TEMP tmp);
6752 ins_cost(160);
6753 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6754 "MOVD $dst.lo,$tmp\n\t"
6755 "PSRLQ $tmp,32\n\t"
6756 "MOVD $dst.hi,$tmp" %}
6757 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
6758 ins_pipe( pipe_slow );
6759 %}
6760
6761 // Load Range
6762 instruct loadRange(eRegI dst, memory mem) %{
6763 match(Set dst (LoadRange mem));
6764
6765 ins_cost(125);
6766 format %{ "MOV $dst,$mem" %}
6767 opcode(0x8B);
6768 ins_encode( OpcP, RegMem(dst,mem));
6769 ins_pipe( ialu_reg_mem );
6770 %}
6771
6772
6773 // Load Pointer
6774 instruct loadP(eRegP dst, memory mem) %{
6775 match(Set dst (LoadP mem));
6776
6777 ins_cost(125);
6778 format %{ "MOV $dst,$mem" %}
6779 opcode(0x8B);
6780 ins_encode( OpcP, RegMem(dst,mem));
6781 ins_pipe( ialu_reg_mem );
6782 %}
6783
6784 // Load Klass Pointer
6785 instruct loadKlass(eRegP dst, memory mem) %{
6786 match(Set dst (LoadKlass mem));
6787
6788 ins_cost(125);
6789 format %{ "MOV $dst,$mem" %}
6790 opcode(0x8B);
6791 ins_encode( OpcP, RegMem(dst,mem));
6792 ins_pipe( ialu_reg_mem );
6793 %}
6794
6795 // Load Short (16bit signed)
6796 instruct loadS(eRegI dst, memory mem) %{
6797 match(Set dst (LoadS mem));
6798
6799 ins_cost(125);
6800 format %{ "MOVSX $dst,$mem" %}
6801 opcode(0xBF, 0x0F);
6802 ins_encode( OpcS, OpcP, RegMem(dst,mem));
6803 ins_pipe( ialu_reg_mem );
6804 %}
6805
6806 // Load Double
6807 instruct loadD(regD dst, memory mem) %{
6808 predicate(UseSSE<=1);
6809 match(Set dst (LoadD mem));
6810
6811 ins_cost(150);
6812 format %{ "FLD_D ST,$mem\n\t"
6813 "FSTP $dst" %}
6814 opcode(0xDD); /* DD /0 */
6815 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6816 Pop_Reg_D(dst) );
6817 ins_pipe( fpu_reg_mem );
6818 %}
6819
6820 // Load Double to XMM
6821 instruct loadXD(regXD dst, memory mem) %{
6822 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6823 match(Set dst (LoadD mem));
6824 ins_cost(145);
6825 format %{ "MOVSD $dst,$mem" %}
6826 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6827 ins_pipe( pipe_slow );
6828 %}
6829
6830 instruct loadXD_partial(regXD dst, memory mem) %{
6831 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6832 match(Set dst (LoadD mem));
6833 ins_cost(145);
6834 format %{ "MOVLPD $dst,$mem" %}
6835 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem));
6836 ins_pipe( pipe_slow );
6837 %}
6838
6839 // Load to XMM register (single-precision floating point)
6840 // MOVSS instruction
6841 instruct loadX(regX dst, memory mem) %{
6842 predicate(UseSSE>=1);
6843 match(Set dst (LoadF mem));
6844 ins_cost(145);
6845 format %{ "MOVSS $dst,$mem" %}
6846 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem));
6847 ins_pipe( pipe_slow );
6848 %}
6849
6850 // Load Float
6851 instruct loadF(regF dst, memory mem) %{
6852 predicate(UseSSE==0);
6853 match(Set dst (LoadF mem));
6854
6855 ins_cost(150);
6856 format %{ "FLD_S ST,$mem\n\t"
6857 "FSTP $dst" %}
6858 opcode(0xD9); /* D9 /0 */
6859 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6860 Pop_Reg_F(dst) );
6861 ins_pipe( fpu_reg_mem );
6862 %}
6863
6864 // Load Aligned Packed Byte to XMM register
6865 instruct loadA8B(regXD dst, memory mem) %{
6866 predicate(UseSSE>=1);
6867 match(Set dst (Load8B mem));
6868 ins_cost(125);
6869 format %{ "MOVQ $dst,$mem\t! packed8B" %}
6870 ins_encode( movq_ld(dst, mem));
6871 ins_pipe( pipe_slow );
6872 %}
6873
6874 // Load Aligned Packed Short to XMM register
6875 instruct loadA4S(regXD dst, memory mem) %{
6876 predicate(UseSSE>=1);
6877 match(Set dst (Load4S mem));
6878 ins_cost(125);
6879 format %{ "MOVQ $dst,$mem\t! packed4S" %}
6880 ins_encode( movq_ld(dst, mem));
6881 ins_pipe( pipe_slow );
6882 %}
6883
6884 // Load Aligned Packed Char to XMM register
6885 instruct loadA4C(regXD dst, memory mem) %{
6886 predicate(UseSSE>=1);
6887 match(Set dst (Load4C mem));
6888 ins_cost(125);
6889 format %{ "MOVQ $dst,$mem\t! packed4C" %}
6890 ins_encode( movq_ld(dst, mem));
6891 ins_pipe( pipe_slow );
6892 %}
6893
6894 // Load Aligned Packed Integer to XMM register
6895 instruct load2IU(regXD dst, memory mem) %{
6896 predicate(UseSSE>=1);
6897 match(Set dst (Load2I mem));
6898 ins_cost(125);
6899 format %{ "MOVQ $dst,$mem\t! packed2I" %}
6900 ins_encode( movq_ld(dst, mem));
6901 ins_pipe( pipe_slow );
6902 %}
6903
6904 // Load Aligned Packed Single to XMM
6905 instruct loadA2F(regXD dst, memory mem) %{
6906 predicate(UseSSE>=1);
6907 match(Set dst (Load2F mem));
6908 ins_cost(145);
6909 format %{ "MOVQ $dst,$mem\t! packed2F" %}
6910 ins_encode( movq_ld(dst, mem));
6911 ins_pipe( pipe_slow );
6912 %}
6913
6914 // Load Effective Address
6915 instruct leaP8(eRegP dst, indOffset8 mem) %{
6916 match(Set dst mem);
6917
6918 ins_cost(110);
6919 format %{ "LEA $dst,$mem" %}
6920 opcode(0x8D);
6921 ins_encode( OpcP, RegMem(dst,mem));
6922 ins_pipe( ialu_reg_reg_fat );
6923 %}
6924
6925 instruct leaP32(eRegP dst, indOffset32 mem) %{
6926 match(Set dst mem);
6927
6928 ins_cost(110);
6929 format %{ "LEA $dst,$mem" %}
6930 opcode(0x8D);
6931 ins_encode( OpcP, RegMem(dst,mem));
6932 ins_pipe( ialu_reg_reg_fat );
6933 %}
6934
6935 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6936 match(Set dst mem);
6937
6938 ins_cost(110);
6939 format %{ "LEA $dst,$mem" %}
6940 opcode(0x8D);
6941 ins_encode( OpcP, RegMem(dst,mem));
6942 ins_pipe( ialu_reg_reg_fat );
6943 %}
6944
6945 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6946 match(Set dst mem);
6947
6948 ins_cost(110);
6949 format %{ "LEA $dst,$mem" %}
6950 opcode(0x8D);
6951 ins_encode( OpcP, RegMem(dst,mem));
6952 ins_pipe( ialu_reg_reg_fat );
6953 %}
6954
6955 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6956 match(Set dst mem);
6957
6958 ins_cost(110);
6959 format %{ "LEA $dst,$mem" %}
6960 opcode(0x8D);
6961 ins_encode( OpcP, RegMem(dst,mem));
6962 ins_pipe( ialu_reg_reg_fat );
6963 %}
6964
6965 // Load Constant
6966 instruct loadConI(eRegI dst, immI src) %{
6967 match(Set dst src);
6968
6969 format %{ "MOV $dst,$src" %}
6970 ins_encode( LdImmI(dst, src) );
6971 ins_pipe( ialu_reg_fat );
6972 %}
6973
6974 // Load Constant zero
6975 instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{
6976 match(Set dst src);
6977 effect(KILL cr);
6978
6979 ins_cost(50);
6980 format %{ "XOR $dst,$dst" %}
6981 opcode(0x33); /* + rd */
6982 ins_encode( OpcP, RegReg( dst, dst ) );
6983 ins_pipe( ialu_reg );
6984 %}
6985
6986 instruct loadConP(eRegP dst, immP src) %{
6987 match(Set dst src);
6988
6989 format %{ "MOV $dst,$src" %}
6990 opcode(0xB8); /* + rd */
6991 ins_encode( LdImmP(dst, src) );
6992 ins_pipe( ialu_reg_fat );
6993 %}
6994
6995 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6996 match(Set dst src);
6997 effect(KILL cr);
6998 ins_cost(200);
6999 format %{ "MOV $dst.lo,$src.lo\n\t"
7000 "MOV $dst.hi,$src.hi" %}
7001 opcode(0xB8);
7002 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
7003 ins_pipe( ialu_reg_long_fat );
7004 %}
7005
7006 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
7007 match(Set dst src);
7008 effect(KILL cr);
7009 ins_cost(150);
7010 format %{ "XOR $dst.lo,$dst.lo\n\t"
7011 "XOR $dst.hi,$dst.hi" %}
7012 opcode(0x33,0x33);
7013 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
7014 ins_pipe( ialu_reg_long );
7015 %}
7016
7017 // The instruction usage is guarded by predicate in operand immF().
7018 instruct loadConF(regF dst, immF src) %{
7019 match(Set dst src);
7020 ins_cost(125);
7021
7022 format %{ "FLD_S ST,$src\n\t"
7023 "FSTP $dst" %}
7024 opcode(0xD9, 0x00); /* D9 /0 */
7025 ins_encode(LdImmF(src), Pop_Reg_F(dst) );
7026 ins_pipe( fpu_reg_con );
7027 %}
7028
7029 // The instruction usage is guarded by predicate in operand immXF().
7030 instruct loadConX(regX dst, immXF con) %{
7031 match(Set dst con);
7032 ins_cost(125);
7033 format %{ "MOVSS $dst,[$con]" %}
7034 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con));
7035 ins_pipe( pipe_slow );
7036 %}
7037
7038 // The instruction usage is guarded by predicate in operand immXF0().
7039 instruct loadConX0(regX dst, immXF0 src) %{
7040 match(Set dst src);
7041 ins_cost(100);
7042 format %{ "XORPS $dst,$dst\t# float 0.0" %}
7043 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7044 ins_pipe( pipe_slow );
7045 %}
7046
7047 // The instruction usage is guarded by predicate in operand immD().
7048 instruct loadConD(regD dst, immD src) %{
7049 match(Set dst src);
7050 ins_cost(125);
7051
7052 format %{ "FLD_D ST,$src\n\t"
7053 "FSTP $dst" %}
7054 ins_encode(LdImmD(src), Pop_Reg_D(dst) );
7055 ins_pipe( fpu_reg_con );
7056 %}
7057
7058 // The instruction usage is guarded by predicate in operand immXD().
7059 instruct loadConXD(regXD dst, immXD con) %{
7060 match(Set dst con);
7061 ins_cost(125);
7062 format %{ "MOVSD $dst,[$con]" %}
7063 ins_encode(load_conXD(dst, con));
7064 ins_pipe( pipe_slow );
7065 %}
7066
7067 // The instruction usage is guarded by predicate in operand immXD0().
7068 instruct loadConXD0(regXD dst, immXD0 src) %{
7069 match(Set dst src);
7070 ins_cost(100);
7071 format %{ "XORPD $dst,$dst\t# double 0.0" %}
7072 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst));
7073 ins_pipe( pipe_slow );
7074 %}
7075
7076 // Load Stack Slot
7077 instruct loadSSI(eRegI dst, stackSlotI src) %{
7078 match(Set dst src);
7079 ins_cost(125);
7080
7081 format %{ "MOV $dst,$src" %}
7082 opcode(0x8B);
7083 ins_encode( OpcP, RegMem(dst,src));
7084 ins_pipe( ialu_reg_mem );
7085 %}
7086
7087 instruct loadSSL(eRegL dst, stackSlotL src) %{
7088 match(Set dst src);
7089
7090 ins_cost(200);
7091 format %{ "MOV $dst,$src.lo\n\t"
7092 "MOV $dst+4,$src.hi" %}
7093 opcode(0x8B, 0x8B);
7094 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
7095 ins_pipe( ialu_mem_long_reg );
7096 %}
7097
7098 // Load Stack Slot
7099 instruct loadSSP(eRegP dst, stackSlotP src) %{
7100 match(Set dst src);
7101 ins_cost(125);
7102
7103 format %{ "MOV $dst,$src" %}
7104 opcode(0x8B);
7105 ins_encode( OpcP, RegMem(dst,src));
7106 ins_pipe( ialu_reg_mem );
7107 %}
7108
7109 // Load Stack Slot
7110 instruct loadSSF(regF dst, stackSlotF src) %{
7111 match(Set dst src);
7112 ins_cost(125);
7113
7114 format %{ "FLD_S $src\n\t"
7115 "FSTP $dst" %}
7116 opcode(0xD9); /* D9 /0, FLD m32real */
7117 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7118 Pop_Reg_F(dst) );
7119 ins_pipe( fpu_reg_mem );
7120 %}
7121
7122 // Load Stack Slot
7123 instruct loadSSD(regD dst, stackSlotD src) %{
7124 match(Set dst src);
7125 ins_cost(125);
7126
7127 format %{ "FLD_D $src\n\t"
7128 "FSTP $dst" %}
7129 opcode(0xDD); /* DD /0, FLD m64real */
7130 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
7131 Pop_Reg_D(dst) );
7132 ins_pipe( fpu_reg_mem );
7133 %}
7134
7135 // Prefetch instructions.
7136 // Must be safe to execute with invalid address (cannot fault).
7137
7138 instruct prefetchr0( memory mem ) %{
7139 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7140 match(PrefetchRead mem);
7141 ins_cost(0);
7142 size(0);
7143 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
7144 ins_encode();
7145 ins_pipe(empty);
7146 %}
7147
7148 instruct prefetchr( memory mem ) %{
7149 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3);
7150 match(PrefetchRead mem);
7151 ins_cost(100);
7152
7153 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7154 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */
7155 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7156 ins_pipe(ialu_mem);
7157 %}
7158
7159 instruct prefetchrNTA( memory mem ) %{
7160 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7161 match(PrefetchRead mem);
7162 ins_cost(100);
7163
7164 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7165 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7166 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7167 ins_pipe(ialu_mem);
7168 %}
7169
7170 instruct prefetchrT0( memory mem ) %{
7171 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7172 match(PrefetchRead mem);
7173 ins_cost(100);
7174
7175 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7176 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7177 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7178 ins_pipe(ialu_mem);
7179 %}
7180
7181 instruct prefetchrT2( memory mem ) %{
7182 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7183 match(PrefetchRead mem);
7184 ins_cost(100);
7185
7186 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7187 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7188 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7189 ins_pipe(ialu_mem);
7190 %}
7191
7192 instruct prefetchw0( memory mem ) %{
7193 predicate(UseSSE==0 && !VM_Version::supports_3dnow());
7194 match(PrefetchWrite mem);
7195 ins_cost(0);
7196 size(0);
7197 format %{ "Prefetch (non-SSE is empty encoding)" %}
7198 ins_encode();
7199 ins_pipe(empty);
7200 %}
7201
7202 instruct prefetchw( memory mem ) %{
7203 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3);
7204 match( PrefetchWrite mem );
7205 ins_cost(100);
7206
7207 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7208 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */
7209 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7210 ins_pipe(ialu_mem);
7211 %}
7212
7213 instruct prefetchwNTA( memory mem ) %{
7214 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7215 match(PrefetchWrite mem);
7216 ins_cost(100);
7217
7218 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7219 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */
7220 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem));
7221 ins_pipe(ialu_mem);
7222 %}
7223
7224 instruct prefetchwT0( memory mem ) %{
7225 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7226 match(PrefetchWrite mem);
7227 ins_cost(100);
7228
7229 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %}
7230 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */
7231 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem));
7232 ins_pipe(ialu_mem);
7233 %}
7234
7235 instruct prefetchwT2( memory mem ) %{
7236 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7237 match(PrefetchWrite mem);
7238 ins_cost(100);
7239
7240 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %}
7241 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */
7242 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem));
7243 ins_pipe(ialu_mem);
7244 %}
7245
7246 //----------Store Instructions-------------------------------------------------
7247
7248 // Store Byte
7249 instruct storeB(memory mem, xRegI src) %{
7250 match(Set mem (StoreB mem src));
7251
7252 ins_cost(125);
7253 format %{ "MOV8 $mem,$src" %}
7254 opcode(0x88);
7255 ins_encode( OpcP, RegMem( src, mem ) );
7256 ins_pipe( ialu_mem_reg );
7257 %}
7258
7259 // Store Char/Short
7260 instruct storeC(memory mem, eRegI src) %{
7261 match(Set mem (StoreC mem src));
7262
7263 ins_cost(125);
7264 format %{ "MOV16 $mem,$src" %}
7265 opcode(0x89, 0x66);
7266 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
7267 ins_pipe( ialu_mem_reg );
7268 %}
7269
7270 // Store Integer
7271 instruct storeI(memory mem, eRegI src) %{
7272 match(Set mem (StoreI mem src));
7273
7274 ins_cost(125);
7275 format %{ "MOV $mem,$src" %}
7276 opcode(0x89);
7277 ins_encode( OpcP, RegMem( src, mem ) );
7278 ins_pipe( ialu_mem_reg );
7279 %}
7280
7281 // Store Long
7282 instruct storeL(long_memory mem, eRegL src) %{
7283 predicate(!((StoreLNode*)n)->require_atomic_access());
7284 match(Set mem (StoreL mem src));
7285
7286 ins_cost(200);
7287 format %{ "MOV $mem,$src.lo\n\t"
7288 "MOV $mem+4,$src.hi" %}
7289 opcode(0x89, 0x89);
7290 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
7291 ins_pipe( ialu_mem_long_reg );
7292 %}
7293
7294 // Volatile Store Long. Must be atomic, so move it into
7295 // the FP TOS and then do a 64-bit FIST. Has to probe the
7296 // target address before the store (for null-ptr checks)
7297 // so the memory operand is used twice in the encoding.
7298 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
7299 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
7300 match(Set mem (StoreL mem src));
7301 effect( KILL cr );
7302 ins_cost(400);
7303 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7304 "FILD $src\n\t"
7305 "FISTp $mem\t # 64-bit atomic volatile long store" %}
7306 opcode(0x3B);
7307 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
7308 ins_pipe( fpu_reg_mem );
7309 %}
7310
7311 instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{
7312 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7313 match(Set mem (StoreL mem src));
7314 effect( TEMP tmp, KILL cr );
7315 ins_cost(380);
7316 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7317 "MOVSD $tmp,$src\n\t"
7318 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7319 opcode(0x3B);
7320 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp));
7321 ins_pipe( pipe_slow );
7322 %}
7323
7324 instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{
7325 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
7326 match(Set mem (StoreL mem src));
7327 effect( TEMP tmp2 , TEMP tmp, KILL cr );
7328 ins_cost(360);
7329 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
7330 "MOVD $tmp,$src.lo\n\t"
7331 "MOVD $tmp2,$src.hi\n\t"
7332 "PUNPCKLDQ $tmp,$tmp2\n\t"
7333 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
7334 opcode(0x3B);
7335 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2));
7336 ins_pipe( pipe_slow );
7337 %}
7338
7339 // Store Pointer; for storing unknown oops and raw pointers
7340 instruct storeP(memory mem, anyRegP src) %{
7341 match(Set mem (StoreP mem src));
7342
7343 ins_cost(125);
7344 format %{ "MOV $mem,$src" %}
7345 opcode(0x89);
7346 ins_encode( OpcP, RegMem( src, mem ) );
7347 ins_pipe( ialu_mem_reg );
7348 %}
7349
7350 // Store Integer Immediate
7351 instruct storeImmI(memory mem, immI src) %{
7352 match(Set mem (StoreI mem src));
7353
7354 ins_cost(150);
7355 format %{ "MOV $mem,$src" %}
7356 opcode(0xC7); /* C7 /0 */
7357 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7358 ins_pipe( ialu_mem_imm );
7359 %}
7360
7361 // Store Short/Char Immediate
7362 instruct storeImmI16(memory mem, immI16 src) %{
7363 predicate(UseStoreImmI16);
7364 match(Set mem (StoreC mem src));
7365
7366 ins_cost(150);
7367 format %{ "MOV16 $mem,$src" %}
7368 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
7369 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
7370 ins_pipe( ialu_mem_imm );
7371 %}
7372
7373 // Store Pointer Immediate; null pointers or constant oops that do not
7374 // need card-mark barriers.
7375 instruct storeImmP(memory mem, immP src) %{
7376 match(Set mem (StoreP mem src));
7377
7378 ins_cost(150);
7379 format %{ "MOV $mem,$src" %}
7380 opcode(0xC7); /* C7 /0 */
7381 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
7382 ins_pipe( ialu_mem_imm );
7383 %}
7384
7385 // Store Byte Immediate
7386 instruct storeImmB(memory mem, immI8 src) %{
7387 match(Set mem (StoreB mem src));
7388
7389 ins_cost(150);
7390 format %{ "MOV8 $mem,$src" %}
7391 opcode(0xC6); /* C6 /0 */
7392 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7393 ins_pipe( ialu_mem_imm );
7394 %}
7395
7396 // Store Aligned Packed Byte XMM register to memory
7397 instruct storeA8B(memory mem, regXD src) %{
7398 predicate(UseSSE>=1);
7399 match(Set mem (Store8B mem src));
7400 ins_cost(145);
7401 format %{ "MOVQ $mem,$src\t! packed8B" %}
7402 ins_encode( movq_st(mem, src));
7403 ins_pipe( pipe_slow );
7404 %}
7405
7406 // Store Aligned Packed Char/Short XMM register to memory
7407 instruct storeA4C(memory mem, regXD src) %{
7408 predicate(UseSSE>=1);
7409 match(Set mem (Store4C mem src));
7410 ins_cost(145);
7411 format %{ "MOVQ $mem,$src\t! packed4C" %}
7412 ins_encode( movq_st(mem, src));
7413 ins_pipe( pipe_slow );
7414 %}
7415
7416 // Store Aligned Packed Integer XMM register to memory
7417 instruct storeA2I(memory mem, regXD src) %{
7418 predicate(UseSSE>=1);
7419 match(Set mem (Store2I mem src));
7420 ins_cost(145);
7421 format %{ "MOVQ $mem,$src\t! packed2I" %}
7422 ins_encode( movq_st(mem, src));
7423 ins_pipe( pipe_slow );
7424 %}
7425
7426 // Store CMS card-mark Immediate
7427 instruct storeImmCM(memory mem, immI8 src) %{
7428 match(Set mem (StoreCM mem src));
7429
7430 ins_cost(150);
7431 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7432 opcode(0xC6); /* C6 /0 */
7433 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7434 ins_pipe( ialu_mem_imm );
7435 %}
7436
7437 // Store Double
7438 instruct storeD( memory mem, regDPR1 src) %{
7439 predicate(UseSSE<=1);
7440 match(Set mem (StoreD mem src));
7441
7442 ins_cost(100);
7443 format %{ "FST_D $mem,$src" %}
7444 opcode(0xDD); /* DD /2 */
7445 ins_encode( enc_FP_store(mem,src) );
7446 ins_pipe( fpu_mem_reg );
7447 %}
7448
7449 // Store double does rounding on x86
7450 instruct storeD_rounded( memory mem, regDPR1 src) %{
7451 predicate(UseSSE<=1);
7452 match(Set mem (StoreD mem (RoundDouble src)));
7453
7454 ins_cost(100);
7455 format %{ "FST_D $mem,$src\t# round" %}
7456 opcode(0xDD); /* DD /2 */
7457 ins_encode( enc_FP_store(mem,src) );
7458 ins_pipe( fpu_mem_reg );
7459 %}
7460
7461 // Store XMM register to memory (double-precision floating points)
7462 // MOVSD instruction
7463 instruct storeXD(memory mem, regXD src) %{
7464 predicate(UseSSE>=2);
7465 match(Set mem (StoreD mem src));
7466 ins_cost(95);
7467 format %{ "MOVSD $mem,$src" %}
7468 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7469 ins_pipe( pipe_slow );
7470 %}
7471
7472 // Store XMM register to memory (single-precision floating point)
7473 // MOVSS instruction
7474 instruct storeX(memory mem, regX src) %{
7475 predicate(UseSSE>=1);
7476 match(Set mem (StoreF mem src));
7477 ins_cost(95);
7478 format %{ "MOVSS $mem,$src" %}
7479 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem));
7480 ins_pipe( pipe_slow );
7481 %}
7482
7483 // Store Aligned Packed Single Float XMM register to memory
7484 instruct storeA2F(memory mem, regXD src) %{
7485 predicate(UseSSE>=1);
7486 match(Set mem (Store2F mem src));
7487 ins_cost(145);
7488 format %{ "MOVQ $mem,$src\t! packed2F" %}
7489 ins_encode( movq_st(mem, src));
7490 ins_pipe( pipe_slow );
7491 %}
7492
7493 // Store Float
7494 instruct storeF( memory mem, regFPR1 src) %{
7495 predicate(UseSSE==0);
7496 match(Set mem (StoreF mem src));
7497
7498 ins_cost(100);
7499 format %{ "FST_S $mem,$src" %}
7500 opcode(0xD9); /* D9 /2 */
7501 ins_encode( enc_FP_store(mem,src) );
7502 ins_pipe( fpu_mem_reg );
7503 %}
7504
7505 // Store Float does rounding on x86
7506 instruct storeF_rounded( memory mem, regFPR1 src) %{
7507 predicate(UseSSE==0);
7508 match(Set mem (StoreF mem (RoundFloat src)));
7509
7510 ins_cost(100);
7511 format %{ "FST_S $mem,$src\t# round" %}
7512 opcode(0xD9); /* D9 /2 */
7513 ins_encode( enc_FP_store(mem,src) );
7514 ins_pipe( fpu_mem_reg );
7515 %}
7516
7517 // Store Float does rounding on x86
7518 instruct storeF_Drounded( memory mem, regDPR1 src) %{
7519 predicate(UseSSE<=1);
7520 match(Set mem (StoreF mem (ConvD2F src)));
7521
7522 ins_cost(100);
7523 format %{ "FST_S $mem,$src\t# D-round" %}
7524 opcode(0xD9); /* D9 /2 */
7525 ins_encode( enc_FP_store(mem,src) );
7526 ins_pipe( fpu_mem_reg );
7527 %}
7528
7529 // Store immediate Float value (it is faster than store from FPU register)
7530 // The instruction usage is guarded by predicate in operand immF().
7531 instruct storeF_imm( memory mem, immF src) %{
7532 match(Set mem (StoreF mem src));
7533
7534 ins_cost(50);
7535 format %{ "MOV $mem,$src\t# store float" %}
7536 opcode(0xC7); /* C7 /0 */
7537 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7538 ins_pipe( ialu_mem_imm );
7539 %}
7540
7541 // Store immediate Float value (it is faster than store from XMM register)
7542 // The instruction usage is guarded by predicate in operand immXF().
7543 instruct storeX_imm( memory mem, immXF src) %{
7544 match(Set mem (StoreF mem src));
7545
7546 ins_cost(50);
7547 format %{ "MOV $mem,$src\t# store float" %}
7548 opcode(0xC7); /* C7 /0 */
7549 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src ));
7550 ins_pipe( ialu_mem_imm );
7551 %}
7552
7553 // Store Integer to stack slot
7554 instruct storeSSI(stackSlotI dst, eRegI src) %{
7555 match(Set dst src);
7556
7557 ins_cost(100);
7558 format %{ "MOV $dst,$src" %}
7559 opcode(0x89);
7560 ins_encode( OpcPRegSS( dst, src ) );
7561 ins_pipe( ialu_mem_reg );
7562 %}
7563
7564 // Store Integer to stack slot
7565 instruct storeSSP(stackSlotP dst, eRegP src) %{
7566 match(Set dst src);
7567
7568 ins_cost(100);
7569 format %{ "MOV $dst,$src" %}
7570 opcode(0x89);
7571 ins_encode( OpcPRegSS( dst, src ) );
7572 ins_pipe( ialu_mem_reg );
7573 %}
7574
7575 // Store Long to stack slot
7576 instruct storeSSL(stackSlotL dst, eRegL src) %{
7577 match(Set dst src);
7578
7579 ins_cost(200);
7580 format %{ "MOV $dst,$src.lo\n\t"
7581 "MOV $dst+4,$src.hi" %}
7582 opcode(0x89, 0x89);
7583 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7584 ins_pipe( ialu_mem_long_reg );
7585 %}
7586
7587 //----------MemBar Instructions-----------------------------------------------
7588 // Memory barrier flavors
7589
7590 instruct membar_acquire() %{
7591 match(MemBarAcquire);
7592 ins_cost(400);
7593
7594 size(0);
7595 format %{ "MEMBAR-acquire" %}
7596 ins_encode( enc_membar_acquire );
7597 ins_pipe(pipe_slow);
7598 %}
7599
7600 instruct membar_acquire_lock() %{
7601 match(MemBarAcquire);
7602 predicate(Matcher::prior_fast_lock(n));
7603 ins_cost(0);
7604
7605 size(0);
7606 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7607 ins_encode( );
7608 ins_pipe(empty);
7609 %}
7610
7611 instruct membar_release() %{
7612 match(MemBarRelease);
7613 ins_cost(400);
7614
7615 size(0);
7616 format %{ "MEMBAR-release" %}
7617 ins_encode( enc_membar_release );
7618 ins_pipe(pipe_slow);
7619 %}
7620
7621 instruct membar_release_lock() %{
7622 match(MemBarRelease);
7623 predicate(Matcher::post_fast_unlock(n));
7624 ins_cost(0);
7625
7626 size(0);
7627 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7628 ins_encode( );
7629 ins_pipe(empty);
7630 %}
7631
7632 instruct membar_volatile() %{
7633 match(MemBarVolatile);
7634 ins_cost(400);
7635
7636 format %{ "MEMBAR-volatile" %}
7637 ins_encode( enc_membar_volatile );
7638 ins_pipe(pipe_slow);
7639 %}
7640
7641 instruct unnecessary_membar_volatile() %{
7642 match(MemBarVolatile);
7643 predicate(Matcher::post_store_load_barrier(n));
7644 ins_cost(0);
7645
7646 size(0);
7647 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7648 ins_encode( );
7649 ins_pipe(empty);
7650 %}
7651
7652 //----------Move Instructions--------------------------------------------------
7653 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7654 match(Set dst (CastX2P src));
7655 format %{ "# X2P $dst, $src" %}
7656 ins_encode( /*empty encoding*/ );
7657 ins_cost(0);
7658 ins_pipe(empty);
7659 %}
7660
7661 instruct castP2X(eRegI dst, eRegP src ) %{
7662 match(Set dst (CastP2X src));
7663 ins_cost(50);
7664 format %{ "MOV $dst, $src\t# CastP2X" %}
7665 ins_encode( enc_Copy( dst, src) );
7666 ins_pipe( ialu_reg_reg );
7667 %}
7668
7669 //----------Conditional Move---------------------------------------------------
7670 // Conditional move
7671 instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{
7672 predicate(VM_Version::supports_cmov() );
7673 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7674 ins_cost(200);
7675 format %{ "CMOV$cop $dst,$src" %}
7676 opcode(0x0F,0x40);
7677 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7678 ins_pipe( pipe_cmov_reg );
7679 %}
7680
7681 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, eRegI dst, eRegI src ) %{
7682 predicate(VM_Version::supports_cmov() );
7683 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7684 ins_cost(200);
7685 format %{ "CMOV$cop $dst,$src" %}
7686 opcode(0x0F,0x40);
7687 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7688 ins_pipe( pipe_cmov_reg );
7689 %}
7690
7691 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, eRegI src ) %{
7692 predicate(VM_Version::supports_cmov() );
7693 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7694 ins_cost(200);
7695 expand %{
7696 cmovI_regU(cop, cr, dst, src);
7697 %}
7698 %}
7699
7700 // Conditional move
7701 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{
7702 predicate(VM_Version::supports_cmov() );
7703 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7704 ins_cost(250);
7705 format %{ "CMOV$cop $dst,$src" %}
7706 opcode(0x0F,0x40);
7707 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7708 ins_pipe( pipe_cmov_mem );
7709 %}
7710
7711 // Conditional move
7712 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{
7713 predicate(VM_Version::supports_cmov() );
7714 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7715 ins_cost(250);
7716 format %{ "CMOV$cop $dst,$src" %}
7717 opcode(0x0F,0x40);
7718 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7719 ins_pipe( pipe_cmov_mem );
7720 %}
7721
7722 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegI dst, memory src) %{
7723 predicate(VM_Version::supports_cmov() );
7724 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7725 ins_cost(250);
7726 expand %{
7727 cmovI_memU(cop, cr, dst, src);
7728 %}
7729 %}
7730
7731 // Conditional move
7732 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7733 predicate(VM_Version::supports_cmov() );
7734 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7735 ins_cost(200);
7736 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7737 opcode(0x0F,0x40);
7738 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7739 ins_pipe( pipe_cmov_reg );
7740 %}
7741
7742 // Conditional move (non-P6 version)
7743 // Note: a CMoveP is generated for stubs and native wrappers
7744 // regardless of whether we are on a P6, so we
7745 // emulate a cmov here
7746 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7747 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7748 ins_cost(300);
7749 format %{ "Jn$cop skip\n\t"
7750 "MOV $dst,$src\t# pointer\n"
7751 "skip:" %}
7752 opcode(0x8b);
7753 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7754 ins_pipe( pipe_cmov_reg );
7755 %}
7756
7757 // Conditional move
7758 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7759 predicate(VM_Version::supports_cmov() );
7760 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7761 ins_cost(200);
7762 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7763 opcode(0x0F,0x40);
7764 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7765 ins_pipe( pipe_cmov_reg );
7766 %}
7767
7768 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7769 predicate(VM_Version::supports_cmov() );
7770 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7771 ins_cost(200);
7772 expand %{
7773 cmovP_regU(cop, cr, dst, src);
7774 %}
7775 %}
7776
7777 // DISABLED: Requires the ADLC to emit a bottom_type call that
7778 // correctly meets the two pointer arguments; one is an incoming
7779 // register but the other is a memory operand. ALSO appears to
7780 // be buggy with implicit null checks.
7781 //
7782 //// Conditional move
7783 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7784 // predicate(VM_Version::supports_cmov() );
7785 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7786 // ins_cost(250);
7787 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7788 // opcode(0x0F,0x40);
7789 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7790 // ins_pipe( pipe_cmov_mem );
7791 //%}
7792 //
7793 //// Conditional move
7794 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7795 // predicate(VM_Version::supports_cmov() );
7796 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7797 // ins_cost(250);
7798 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7799 // opcode(0x0F,0x40);
7800 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7801 // ins_pipe( pipe_cmov_mem );
7802 //%}
7803
7804 // Conditional move
7805 instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{
7806 predicate(UseSSE<=1);
7807 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7808 ins_cost(200);
7809 format %{ "FCMOV$cop $dst,$src\t# double" %}
7810 opcode(0xDA);
7811 ins_encode( enc_cmov_d(cop,src) );
7812 ins_pipe( pipe_cmovD_reg );
7813 %}
7814
7815 // Conditional move
7816 instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{
7817 predicate(UseSSE==0);
7818 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7819 ins_cost(200);
7820 format %{ "FCMOV$cop $dst,$src\t# float" %}
7821 opcode(0xDA);
7822 ins_encode( enc_cmov_d(cop,src) );
7823 ins_pipe( pipe_cmovD_reg );
7824 %}
7825
7826 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7827 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7828 predicate(UseSSE<=1);
7829 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7830 ins_cost(200);
7831 format %{ "Jn$cop skip\n\t"
7832 "MOV $dst,$src\t# double\n"
7833 "skip:" %}
7834 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7835 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) );
7836 ins_pipe( pipe_cmovD_reg );
7837 %}
7838
7839 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7840 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7841 predicate(UseSSE==0);
7842 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7843 ins_cost(200);
7844 format %{ "Jn$cop skip\n\t"
7845 "MOV $dst,$src\t# float\n"
7846 "skip:" %}
7847 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7848 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) );
7849 ins_pipe( pipe_cmovD_reg );
7850 %}
7851
7852 // No CMOVE with SSE/SSE2
7853 instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{
7854 predicate (UseSSE>=1);
7855 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7856 ins_cost(200);
7857 format %{ "Jn$cop skip\n\t"
7858 "MOVSS $dst,$src\t# float\n"
7859 "skip:" %}
7860 ins_encode %{
7861 Label skip;
7862 // Invert sense of branch from sense of CMOV
7863 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7864 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7865 __ bind(skip);
7866 %}
7867 ins_pipe( pipe_slow );
7868 %}
7869
7870 // No CMOVE with SSE/SSE2
7871 instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{
7872 predicate (UseSSE>=2);
7873 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7874 ins_cost(200);
7875 format %{ "Jn$cop skip\n\t"
7876 "MOVSD $dst,$src\t# float\n"
7877 "skip:" %}
7878 ins_encode %{
7879 Label skip;
7880 // Invert sense of branch from sense of CMOV
7881 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7882 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7883 __ bind(skip);
7884 %}
7885 ins_pipe( pipe_slow );
7886 %}
7887
7888 // unsigned version
7889 instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{
7890 predicate (UseSSE>=1);
7891 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7892 ins_cost(200);
7893 format %{ "Jn$cop skip\n\t"
7894 "MOVSS $dst,$src\t# float\n"
7895 "skip:" %}
7896 ins_encode %{
7897 Label skip;
7898 // Invert sense of branch from sense of CMOV
7899 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7900 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7901 __ bind(skip);
7902 %}
7903 ins_pipe( pipe_slow );
7904 %}
7905
7906 instruct fcmovX_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regX dst, regX src) %{
7907 predicate (UseSSE>=1);
7908 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7909 ins_cost(200);
7910 expand %{
7911 fcmovX_regU(cop, cr, dst, src);
7912 %}
7913 %}
7914
7915 // unsigned version
7916 instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{
7917 predicate (UseSSE>=2);
7918 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7919 ins_cost(200);
7920 format %{ "Jn$cop skip\n\t"
7921 "MOVSD $dst,$src\t# float\n"
7922 "skip:" %}
7923 ins_encode %{
7924 Label skip;
7925 // Invert sense of branch from sense of CMOV
7926 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7927 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7928 __ bind(skip);
7929 %}
7930 ins_pipe( pipe_slow );
7931 %}
7932
7933 instruct fcmovXD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regXD dst, regXD src) %{
7934 predicate (UseSSE>=2);
7935 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7936 ins_cost(200);
7937 expand %{
7938 fcmovXD_regU(cop, cr, dst, src);
7939 %}
7940 %}
7941
7942 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7943 predicate(VM_Version::supports_cmov() );
7944 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7945 ins_cost(200);
7946 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7947 "CMOV$cop $dst.hi,$src.hi" %}
7948 opcode(0x0F,0x40);
7949 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7950 ins_pipe( pipe_cmov_reg_long );
7951 %}
7952
7953 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7954 predicate(VM_Version::supports_cmov() );
7955 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7956 ins_cost(200);
7957 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7958 "CMOV$cop $dst.hi,$src.hi" %}
7959 opcode(0x0F,0x40);
7960 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7961 ins_pipe( pipe_cmov_reg_long );
7962 %}
7963
7964 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7965 predicate(VM_Version::supports_cmov() );
7966 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7967 ins_cost(200);
7968 expand %{
7969 cmovL_regU(cop, cr, dst, src);
7970 %}
7971 %}
7972
7973 //----------Arithmetic Instructions--------------------------------------------
7974 //----------Addition Instructions----------------------------------------------
7975 // Integer Addition Instructions
7976 instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
7977 match(Set dst (AddI dst src));
7978 effect(KILL cr);
7979
7980 size(2);
7981 format %{ "ADD $dst,$src" %}
7982 opcode(0x03);
7983 ins_encode( OpcP, RegReg( dst, src) );
7984 ins_pipe( ialu_reg_reg );
7985 %}
7986
7987 instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
7988 match(Set dst (AddI dst src));
7989 effect(KILL cr);
7990
7991 format %{ "ADD $dst,$src" %}
7992 opcode(0x81, 0x00); /* /0 id */
7993 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7994 ins_pipe( ialu_reg );
7995 %}
7996
7997 instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
7998 predicate(UseIncDec);
7999 match(Set dst (AddI dst src));
8000 effect(KILL cr);
8001
8002 size(1);
8003 format %{ "INC $dst" %}
8004 opcode(0x40); /* */
8005 ins_encode( Opc_plus( primary, dst ) );
8006 ins_pipe( ialu_reg );
8007 %}
8008
8009 instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{
8010 match(Set dst (AddI src0 src1));
8011 ins_cost(110);
8012
8013 format %{ "LEA $dst,[$src0 + $src1]" %}
8014 opcode(0x8D); /* 0x8D /r */
8015 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8016 ins_pipe( ialu_reg_reg );
8017 %}
8018
8019 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
8020 match(Set dst (AddP src0 src1));
8021 ins_cost(110);
8022
8023 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
8024 opcode(0x8D); /* 0x8D /r */
8025 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
8026 ins_pipe( ialu_reg_reg );
8027 %}
8028
8029 instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{
8030 predicate(UseIncDec);
8031 match(Set dst (AddI dst src));
8032 effect(KILL cr);
8033
8034 size(1);
8035 format %{ "DEC $dst" %}
8036 opcode(0x48); /* */
8037 ins_encode( Opc_plus( primary, dst ) );
8038 ins_pipe( ialu_reg );
8039 %}
8040
8041 instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{
8042 match(Set dst (AddP dst src));
8043 effect(KILL cr);
8044
8045 size(2);
8046 format %{ "ADD $dst,$src" %}
8047 opcode(0x03);
8048 ins_encode( OpcP, RegReg( dst, src) );
8049 ins_pipe( ialu_reg_reg );
8050 %}
8051
8052 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
8053 match(Set dst (AddP dst src));
8054 effect(KILL cr);
8055
8056 format %{ "ADD $dst,$src" %}
8057 opcode(0x81,0x00); /* Opcode 81 /0 id */
8058 // ins_encode( RegImm( dst, src) );
8059 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8060 ins_pipe( ialu_reg );
8061 %}
8062
8063 instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8064 match(Set dst (AddI dst (LoadI src)));
8065 effect(KILL cr);
8066
8067 ins_cost(125);
8068 format %{ "ADD $dst,$src" %}
8069 opcode(0x03);
8070 ins_encode( OpcP, RegMem( dst, src) );
8071 ins_pipe( ialu_reg_mem );
8072 %}
8073
8074 instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8075 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8076 effect(KILL cr);
8077
8078 ins_cost(150);
8079 format %{ "ADD $dst,$src" %}
8080 opcode(0x01); /* Opcode 01 /r */
8081 ins_encode( OpcP, RegMem( src, dst ) );
8082 ins_pipe( ialu_mem_reg );
8083 %}
8084
8085 // Add Memory with Immediate
8086 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8087 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8088 effect(KILL cr);
8089
8090 ins_cost(125);
8091 format %{ "ADD $dst,$src" %}
8092 opcode(0x81); /* Opcode 81 /0 id */
8093 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
8094 ins_pipe( ialu_mem_imm );
8095 %}
8096
8097 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
8098 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8099 effect(KILL cr);
8100
8101 ins_cost(125);
8102 format %{ "INC $dst" %}
8103 opcode(0xFF); /* Opcode FF /0 */
8104 ins_encode( OpcP, RMopc_Mem(0x00,dst));
8105 ins_pipe( ialu_mem_imm );
8106 %}
8107
8108 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
8109 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
8110 effect(KILL cr);
8111
8112 ins_cost(125);
8113 format %{ "DEC $dst" %}
8114 opcode(0xFF); /* Opcode FF /1 */
8115 ins_encode( OpcP, RMopc_Mem(0x01,dst));
8116 ins_pipe( ialu_mem_imm );
8117 %}
8118
8119
8120 instruct checkCastPP( eRegP dst ) %{
8121 match(Set dst (CheckCastPP dst));
8122
8123 size(0);
8124 format %{ "#checkcastPP of $dst" %}
8125 ins_encode( /*empty encoding*/ );
8126 ins_pipe( empty );
8127 %}
8128
8129 instruct castPP( eRegP dst ) %{
8130 match(Set dst (CastPP dst));
8131 format %{ "#castPP of $dst" %}
8132 ins_encode( /*empty encoding*/ );
8133 ins_pipe( empty );
8134 %}
8135
8136 instruct castII( eRegI dst ) %{
8137 match(Set dst (CastII dst));
8138 format %{ "#castII of $dst" %}
8139 ins_encode( /*empty encoding*/ );
8140 ins_cost(0);
8141 ins_pipe( empty );
8142 %}
8143
8144
8145 // Load-locked - same as a regular pointer load when used with compare-swap
8146 instruct loadPLocked(eRegP dst, memory mem) %{
8147 match(Set dst (LoadPLocked mem));
8148
8149 ins_cost(125);
8150 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
8151 opcode(0x8B);
8152 ins_encode( OpcP, RegMem(dst,mem));
8153 ins_pipe( ialu_reg_mem );
8154 %}
8155
8156 // LoadLong-locked - same as a volatile long load when used with compare-swap
8157 instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{
8158 predicate(UseSSE<=1);
8159 match(Set dst (LoadLLocked mem));
8160
8161 ins_cost(200);
8162 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
8163 "FISTp $dst" %}
8164 ins_encode(enc_loadL_volatile(mem,dst));
8165 ins_pipe( fpu_reg_mem );
8166 %}
8167
8168 instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{
8169 predicate(UseSSE>=2);
8170 match(Set dst (LoadLLocked mem));
8171 effect(TEMP tmp);
8172 ins_cost(180);
8173 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8174 "MOVSD $dst,$tmp" %}
8175 ins_encode(enc_loadLX_volatile(mem, dst, tmp));
8176 ins_pipe( pipe_slow );
8177 %}
8178
8179 instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{
8180 predicate(UseSSE>=2);
8181 match(Set dst (LoadLLocked mem));
8182 effect(TEMP tmp);
8183 ins_cost(160);
8184 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
8185 "MOVD $dst.lo,$tmp\n\t"
8186 "PSRLQ $tmp,32\n\t"
8187 "MOVD $dst.hi,$tmp" %}
8188 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp));
8189 ins_pipe( pipe_slow );
8190 %}
8191
8192 // Conditional-store of the updated heap-top.
8193 // Used during allocation of the shared heap.
8194 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
8195 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
8196 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
8197 // EAX is killed if there is contention, but then it's also unused.
8198 // In the common case of no contention, EAX holds the new oop address.
8199 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
8200 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
8201 ins_pipe( pipe_cmpxchg );
8202 %}
8203
8204 // Conditional-store of an int value.
8205 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
8206 instruct storeIConditional( memory mem, eAXRegI oldval, eRegI newval, eFlagsReg cr ) %{
8207 match(Set cr (StoreIConditional mem (Binary oldval newval)));
8208 effect(KILL oldval);
8209 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
8210 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
8211 ins_pipe( pipe_cmpxchg );
8212 %}
8213
8214 // Conditional-store of a long value.
8215 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
8216 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8217 match(Set cr (StoreLConditional mem (Binary oldval newval)));
8218 effect(KILL oldval);
8219 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
8220 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
8221 "XCHG EBX,ECX"
8222 %}
8223 ins_encode %{
8224 // Note: we need to swap rbx, and rcx before and after the
8225 // cmpxchg8 instruction because the instruction uses
8226 // rcx as the high order word of the new value to store but
8227 // our register encoding uses rbx.
8228 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8229 if( os::is_MP() )
8230 __ lock();
8231 __ cmpxchg8(Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp));
8232 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
8233 %}
8234 ins_pipe( pipe_cmpxchg );
8235 %}
8236
8237 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
8238
8239 instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
8240 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
8241 effect(KILL cr, KILL oldval);
8242 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8243 "MOV $res,0\n\t"
8244 "JNE,s fail\n\t"
8245 "MOV $res,1\n"
8246 "fail:" %}
8247 ins_encode( enc_cmpxchg8(mem_ptr),
8248 enc_flags_ne_to_boolean(res) );
8249 ins_pipe( pipe_cmpxchg );
8250 %}
8251
8252 instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
8253 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
8254 effect(KILL cr, KILL oldval);
8255 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8256 "MOV $res,0\n\t"
8257 "JNE,s fail\n\t"
8258 "MOV $res,1\n"
8259 "fail:" %}
8260 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8261 ins_pipe( pipe_cmpxchg );
8262 %}
8263
8264 instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
8265 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
8266 effect(KILL cr, KILL oldval);
8267 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
8268 "MOV $res,0\n\t"
8269 "JNE,s fail\n\t"
8270 "MOV $res,1\n"
8271 "fail:" %}
8272 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
8273 ins_pipe( pipe_cmpxchg );
8274 %}
8275
8276 //----------Subtraction Instructions-------------------------------------------
8277 // Integer Subtraction Instructions
8278 instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8279 match(Set dst (SubI dst src));
8280 effect(KILL cr);
8281
8282 size(2);
8283 format %{ "SUB $dst,$src" %}
8284 opcode(0x2B);
8285 ins_encode( OpcP, RegReg( dst, src) );
8286 ins_pipe( ialu_reg_reg );
8287 %}
8288
8289 instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8290 match(Set dst (SubI dst src));
8291 effect(KILL cr);
8292
8293 format %{ "SUB $dst,$src" %}
8294 opcode(0x81,0x05); /* Opcode 81 /5 */
8295 // ins_encode( RegImm( dst, src) );
8296 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8297 ins_pipe( ialu_reg );
8298 %}
8299
8300 instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8301 match(Set dst (SubI dst (LoadI src)));
8302 effect(KILL cr);
8303
8304 ins_cost(125);
8305 format %{ "SUB $dst,$src" %}
8306 opcode(0x2B);
8307 ins_encode( OpcP, RegMem( dst, src) );
8308 ins_pipe( ialu_reg_mem );
8309 %}
8310
8311 instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8312 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8313 effect(KILL cr);
8314
8315 ins_cost(150);
8316 format %{ "SUB $dst,$src" %}
8317 opcode(0x29); /* Opcode 29 /r */
8318 ins_encode( OpcP, RegMem( src, dst ) );
8319 ins_pipe( ialu_mem_reg );
8320 %}
8321
8322 // Subtract from a pointer
8323 instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{
8324 match(Set dst (AddP dst (SubI zero src)));
8325 effect(KILL cr);
8326
8327 size(2);
8328 format %{ "SUB $dst,$src" %}
8329 opcode(0x2B);
8330 ins_encode( OpcP, RegReg( dst, src) );
8331 ins_pipe( ialu_reg_reg );
8332 %}
8333
8334 instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{
8335 match(Set dst (SubI zero dst));
8336 effect(KILL cr);
8337
8338 size(2);
8339 format %{ "NEG $dst" %}
8340 opcode(0xF7,0x03); // Opcode F7 /3
8341 ins_encode( OpcP, RegOpc( dst ) );
8342 ins_pipe( ialu_reg );
8343 %}
8344
8345
8346 //----------Multiplication/Division Instructions-------------------------------
8347 // Integer Multiplication Instructions
8348 // Multiply Register
8349 instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8350 match(Set dst (MulI dst src));
8351 effect(KILL cr);
8352
8353 size(3);
8354 ins_cost(300);
8355 format %{ "IMUL $dst,$src" %}
8356 opcode(0xAF, 0x0F);
8357 ins_encode( OpcS, OpcP, RegReg( dst, src) );
8358 ins_pipe( ialu_reg_reg_alu0 );
8359 %}
8360
8361 // Multiply 32-bit Immediate
8362 instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{
8363 match(Set dst (MulI src imm));
8364 effect(KILL cr);
8365
8366 ins_cost(300);
8367 format %{ "IMUL $dst,$src,$imm" %}
8368 opcode(0x69); /* 69 /r id */
8369 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8370 ins_pipe( ialu_reg_reg_alu0 );
8371 %}
8372
8373 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8374 match(Set dst src);
8375 effect(KILL cr);
8376
8377 // Note that this is artificially increased to make it more expensive than loadConL
8378 ins_cost(250);
8379 format %{ "MOV EAX,$src\t// low word only" %}
8380 opcode(0xB8);
8381 ins_encode( LdImmL_Lo(dst, src) );
8382 ins_pipe( ialu_reg_fat );
8383 %}
8384
8385 // Multiply by 32-bit Immediate, taking the shifted high order results
8386 // (special case for shift by 32)
8387 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8388 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8389 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8390 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8391 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8392 effect(USE src1, KILL cr);
8393
8394 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8395 ins_cost(0*100 + 1*400 - 150);
8396 format %{ "IMUL EDX:EAX,$src1" %}
8397 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8398 ins_pipe( pipe_slow );
8399 %}
8400
8401 // Multiply by 32-bit Immediate, taking the shifted high order results
8402 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8403 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8404 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8405 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8406 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8407 effect(USE src1, KILL cr);
8408
8409 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8410 ins_cost(1*100 + 1*400 - 150);
8411 format %{ "IMUL EDX:EAX,$src1\n\t"
8412 "SAR EDX,$cnt-32" %}
8413 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8414 ins_pipe( pipe_slow );
8415 %}
8416
8417 // Multiply Memory 32-bit Immediate
8418 instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{
8419 match(Set dst (MulI (LoadI src) imm));
8420 effect(KILL cr);
8421
8422 ins_cost(300);
8423 format %{ "IMUL $dst,$src,$imm" %}
8424 opcode(0x69); /* 69 /r id */
8425 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8426 ins_pipe( ialu_reg_mem_alu0 );
8427 %}
8428
8429 // Multiply Memory
8430 instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{
8431 match(Set dst (MulI dst (LoadI src)));
8432 effect(KILL cr);
8433
8434 ins_cost(350);
8435 format %{ "IMUL $dst,$src" %}
8436 opcode(0xAF, 0x0F);
8437 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8438 ins_pipe( ialu_reg_mem_alu0 );
8439 %}
8440
8441 // Multiply Register Int to Long
8442 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8443 // Basic Idea: long = (long)int * (long)int
8444 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8445 effect(DEF dst, USE src, USE src1, KILL flags);
8446
8447 ins_cost(300);
8448 format %{ "IMUL $dst,$src1" %}
8449
8450 ins_encode( long_int_multiply( dst, src1 ) );
8451 ins_pipe( ialu_reg_reg_alu0 );
8452 %}
8453
8454 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8455 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8456 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8457 effect(KILL flags);
8458
8459 ins_cost(300);
8460 format %{ "MUL $dst,$src1" %}
8461
8462 ins_encode( long_uint_multiply(dst, src1) );
8463 ins_pipe( ialu_reg_reg_alu0 );
8464 %}
8465
8466 // Multiply Register Long
8467 instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{
8468 match(Set dst (MulL dst src));
8469 effect(KILL cr, TEMP tmp);
8470 ins_cost(4*100+3*400);
8471 // Basic idea: lo(result) = lo(x_lo * y_lo)
8472 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8473 format %{ "MOV $tmp,$src.lo\n\t"
8474 "IMUL $tmp,EDX\n\t"
8475 "MOV EDX,$src.hi\n\t"
8476 "IMUL EDX,EAX\n\t"
8477 "ADD $tmp,EDX\n\t"
8478 "MUL EDX:EAX,$src.lo\n\t"
8479 "ADD EDX,$tmp" %}
8480 ins_encode( long_multiply( dst, src, tmp ) );
8481 ins_pipe( pipe_slow );
8482 %}
8483
8484 // Multiply Register Long by small constant
8485 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{
8486 match(Set dst (MulL dst src));
8487 effect(KILL cr, TEMP tmp);
8488 ins_cost(2*100+2*400);
8489 size(12);
8490 // Basic idea: lo(result) = lo(src * EAX)
8491 // hi(result) = hi(src * EAX) + lo(src * EDX)
8492 format %{ "IMUL $tmp,EDX,$src\n\t"
8493 "MOV EDX,$src\n\t"
8494 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8495 "ADD EDX,$tmp" %}
8496 ins_encode( long_multiply_con( dst, src, tmp ) );
8497 ins_pipe( pipe_slow );
8498 %}
8499
8500 // Integer DIV with Register
8501 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8502 match(Set rax (DivI rax div));
8503 effect(KILL rdx, KILL cr);
8504 size(26);
8505 ins_cost(30*100+10*100);
8506 format %{ "CMP EAX,0x80000000\n\t"
8507 "JNE,s normal\n\t"
8508 "XOR EDX,EDX\n\t"
8509 "CMP ECX,-1\n\t"
8510 "JE,s done\n"
8511 "normal: CDQ\n\t"
8512 "IDIV $div\n\t"
8513 "done:" %}
8514 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8515 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8516 ins_pipe( ialu_reg_reg_alu0 );
8517 %}
8518
8519 // Divide Register Long
8520 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8521 match(Set dst (DivL src1 src2));
8522 effect( KILL cr, KILL cx, KILL bx );
8523 ins_cost(10000);
8524 format %{ "PUSH $src1.hi\n\t"
8525 "PUSH $src1.lo\n\t"
8526 "PUSH $src2.hi\n\t"
8527 "PUSH $src2.lo\n\t"
8528 "CALL SharedRuntime::ldiv\n\t"
8529 "ADD ESP,16" %}
8530 ins_encode( long_div(src1,src2) );
8531 ins_pipe( pipe_slow );
8532 %}
8533
8534 // Integer DIVMOD with Register, both quotient and mod results
8535 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8536 match(DivModI rax div);
8537 effect(KILL cr);
8538 size(26);
8539 ins_cost(30*100+10*100);
8540 format %{ "CMP EAX,0x80000000\n\t"
8541 "JNE,s normal\n\t"
8542 "XOR EDX,EDX\n\t"
8543 "CMP ECX,-1\n\t"
8544 "JE,s done\n"
8545 "normal: CDQ\n\t"
8546 "IDIV $div\n\t"
8547 "done:" %}
8548 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8549 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8550 ins_pipe( pipe_slow );
8551 %}
8552
8553 // Integer MOD with Register
8554 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8555 match(Set rdx (ModI rax div));
8556 effect(KILL rax, KILL cr);
8557
8558 size(26);
8559 ins_cost(300);
8560 format %{ "CDQ\n\t"
8561 "IDIV $div" %}
8562 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8563 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8564 ins_pipe( ialu_reg_reg_alu0 );
8565 %}
8566
8567 // Remainder Register Long
8568 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8569 match(Set dst (ModL src1 src2));
8570 effect( KILL cr, KILL cx, KILL bx );
8571 ins_cost(10000);
8572 format %{ "PUSH $src1.hi\n\t"
8573 "PUSH $src1.lo\n\t"
8574 "PUSH $src2.hi\n\t"
8575 "PUSH $src2.lo\n\t"
8576 "CALL SharedRuntime::lrem\n\t"
8577 "ADD ESP,16" %}
8578 ins_encode( long_mod(src1,src2) );
8579 ins_pipe( pipe_slow );
8580 %}
8581
8582 // Integer Shift Instructions
8583 // Shift Left by one
8584 instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8585 match(Set dst (LShiftI dst shift));
8586 effect(KILL cr);
8587
8588 size(2);
8589 format %{ "SHL $dst,$shift" %}
8590 opcode(0xD1, 0x4); /* D1 /4 */
8591 ins_encode( OpcP, RegOpc( dst ) );
8592 ins_pipe( ialu_reg );
8593 %}
8594
8595 // Shift Left by 8-bit immediate
8596 instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8597 match(Set dst (LShiftI dst shift));
8598 effect(KILL cr);
8599
8600 size(3);
8601 format %{ "SHL $dst,$shift" %}
8602 opcode(0xC1, 0x4); /* C1 /4 ib */
8603 ins_encode( RegOpcImm( dst, shift) );
8604 ins_pipe( ialu_reg );
8605 %}
8606
8607 // Shift Left by variable
8608 instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8609 match(Set dst (LShiftI dst shift));
8610 effect(KILL cr);
8611
8612 size(2);
8613 format %{ "SHL $dst,$shift" %}
8614 opcode(0xD3, 0x4); /* D3 /4 */
8615 ins_encode( OpcP, RegOpc( dst ) );
8616 ins_pipe( ialu_reg_reg );
8617 %}
8618
8619 // Arithmetic shift right by one
8620 instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8621 match(Set dst (RShiftI dst shift));
8622 effect(KILL cr);
8623
8624 size(2);
8625 format %{ "SAR $dst,$shift" %}
8626 opcode(0xD1, 0x7); /* D1 /7 */
8627 ins_encode( OpcP, RegOpc( dst ) );
8628 ins_pipe( ialu_reg );
8629 %}
8630
8631 // Arithmetic shift right by one
8632 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8633 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8634 effect(KILL cr);
8635 format %{ "SAR $dst,$shift" %}
8636 opcode(0xD1, 0x7); /* D1 /7 */
8637 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8638 ins_pipe( ialu_mem_imm );
8639 %}
8640
8641 // Arithmetic Shift Right by 8-bit immediate
8642 instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8643 match(Set dst (RShiftI dst shift));
8644 effect(KILL cr);
8645
8646 size(3);
8647 format %{ "SAR $dst,$shift" %}
8648 opcode(0xC1, 0x7); /* C1 /7 ib */
8649 ins_encode( RegOpcImm( dst, shift ) );
8650 ins_pipe( ialu_mem_imm );
8651 %}
8652
8653 // Arithmetic Shift Right by 8-bit immediate
8654 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8655 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8656 effect(KILL cr);
8657
8658 format %{ "SAR $dst,$shift" %}
8659 opcode(0xC1, 0x7); /* C1 /7 ib */
8660 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8661 ins_pipe( ialu_mem_imm );
8662 %}
8663
8664 // Arithmetic Shift Right by variable
8665 instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8666 match(Set dst (RShiftI dst shift));
8667 effect(KILL cr);
8668
8669 size(2);
8670 format %{ "SAR $dst,$shift" %}
8671 opcode(0xD3, 0x7); /* D3 /7 */
8672 ins_encode( OpcP, RegOpc( dst ) );
8673 ins_pipe( ialu_reg_reg );
8674 %}
8675
8676 // Logical shift right by one
8677 instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8678 match(Set dst (URShiftI dst shift));
8679 effect(KILL cr);
8680
8681 size(2);
8682 format %{ "SHR $dst,$shift" %}
8683 opcode(0xD1, 0x5); /* D1 /5 */
8684 ins_encode( OpcP, RegOpc( dst ) );
8685 ins_pipe( ialu_reg );
8686 %}
8687
8688 // Logical Shift Right by 8-bit immediate
8689 instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{
8690 match(Set dst (URShiftI dst shift));
8691 effect(KILL cr);
8692
8693 size(3);
8694 format %{ "SHR $dst,$shift" %}
8695 opcode(0xC1, 0x5); /* C1 /5 ib */
8696 ins_encode( RegOpcImm( dst, shift) );
8697 ins_pipe( ialu_reg );
8698 %}
8699
8700
8701 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8702 // This idiom is used by the compiler for the i2b bytecode.
8703 instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{
8704 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8705 effect(KILL cr);
8706
8707 size(3);
8708 format %{ "MOVSX $dst,$src :8" %}
8709 opcode(0xBE, 0x0F);
8710 ins_encode( OpcS, OpcP, RegReg( dst, src));
8711 ins_pipe( ialu_reg_reg );
8712 %}
8713
8714 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8715 // This idiom is used by the compiler the i2s bytecode.
8716 instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{
8717 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8718 effect(KILL cr);
8719
8720 size(3);
8721 format %{ "MOVSX $dst,$src :16" %}
8722 opcode(0xBF, 0x0F);
8723 ins_encode( OpcS, OpcP, RegReg( dst, src));
8724 ins_pipe( ialu_reg_reg );
8725 %}
8726
8727
8728 // Logical Shift Right by variable
8729 instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{
8730 match(Set dst (URShiftI dst shift));
8731 effect(KILL cr);
8732
8733 size(2);
8734 format %{ "SHR $dst,$shift" %}
8735 opcode(0xD3, 0x5); /* D3 /5 */
8736 ins_encode( OpcP, RegOpc( dst ) );
8737 ins_pipe( ialu_reg_reg );
8738 %}
8739
8740
8741 //----------Logical Instructions-----------------------------------------------
8742 //----------Integer Logical Instructions---------------------------------------
8743 // And Instructions
8744 // And Register with Register
8745 instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8746 match(Set dst (AndI dst src));
8747 effect(KILL cr);
8748
8749 size(2);
8750 format %{ "AND $dst,$src" %}
8751 opcode(0x23);
8752 ins_encode( OpcP, RegReg( dst, src) );
8753 ins_pipe( ialu_reg_reg );
8754 %}
8755
8756 // And Register with Immediate
8757 instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8758 match(Set dst (AndI dst src));
8759 effect(KILL cr);
8760
8761 format %{ "AND $dst,$src" %}
8762 opcode(0x81,0x04); /* Opcode 81 /4 */
8763 // ins_encode( RegImm( dst, src) );
8764 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8765 ins_pipe( ialu_reg );
8766 %}
8767
8768 // And Register with Memory
8769 instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8770 match(Set dst (AndI dst (LoadI src)));
8771 effect(KILL cr);
8772
8773 ins_cost(125);
8774 format %{ "AND $dst,$src" %}
8775 opcode(0x23);
8776 ins_encode( OpcP, RegMem( dst, src) );
8777 ins_pipe( ialu_reg_mem );
8778 %}
8779
8780 // And Memory with Register
8781 instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8782 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8783 effect(KILL cr);
8784
8785 ins_cost(150);
8786 format %{ "AND $dst,$src" %}
8787 opcode(0x21); /* Opcode 21 /r */
8788 ins_encode( OpcP, RegMem( src, dst ) );
8789 ins_pipe( ialu_mem_reg );
8790 %}
8791
8792 // And Memory with Immediate
8793 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8794 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8795 effect(KILL cr);
8796
8797 ins_cost(125);
8798 format %{ "AND $dst,$src" %}
8799 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8800 // ins_encode( MemImm( dst, src) );
8801 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8802 ins_pipe( ialu_mem_imm );
8803 %}
8804
8805 // Or Instructions
8806 // Or Register with Register
8807 instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
8808 match(Set dst (OrI dst src));
8809 effect(KILL cr);
8810
8811 size(2);
8812 format %{ "OR $dst,$src" %}
8813 opcode(0x0B);
8814 ins_encode( OpcP, RegReg( dst, src) );
8815 ins_pipe( ialu_reg_reg );
8816 %}
8817
8818 instruct orI_eReg_castP2X(eRegI dst, eRegP src, eFlagsReg cr) %{
8819 match(Set dst (OrI dst (CastP2X src)));
8820 effect(KILL cr);
8821
8822 size(2);
8823 format %{ "OR $dst,$src" %}
8824 opcode(0x0B);
8825 ins_encode( OpcP, RegReg( dst, src) );
8826 ins_pipe( ialu_reg_reg );
8827 %}
8828
8829
8830 // Or Register with Immediate
8831 instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
8832 match(Set dst (OrI dst src));
8833 effect(KILL cr);
8834
8835 format %{ "OR $dst,$src" %}
8836 opcode(0x81,0x01); /* Opcode 81 /1 id */
8837 // ins_encode( RegImm( dst, src) );
8838 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8839 ins_pipe( ialu_reg );
8840 %}
8841
8842 // Or Register with Memory
8843 instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
8844 match(Set dst (OrI dst (LoadI src)));
8845 effect(KILL cr);
8846
8847 ins_cost(125);
8848 format %{ "OR $dst,$src" %}
8849 opcode(0x0B);
8850 ins_encode( OpcP, RegMem( dst, src) );
8851 ins_pipe( ialu_reg_mem );
8852 %}
8853
8854 // Or Memory with Register
8855 instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
8856 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8857 effect(KILL cr);
8858
8859 ins_cost(150);
8860 format %{ "OR $dst,$src" %}
8861 opcode(0x09); /* Opcode 09 /r */
8862 ins_encode( OpcP, RegMem( src, dst ) );
8863 ins_pipe( ialu_mem_reg );
8864 %}
8865
8866 // Or Memory with Immediate
8867 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8868 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8869 effect(KILL cr);
8870
8871 ins_cost(125);
8872 format %{ "OR $dst,$src" %}
8873 opcode(0x81,0x1); /* Opcode 81 /1 id */
8874 // ins_encode( MemImm( dst, src) );
8875 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8876 ins_pipe( ialu_mem_imm );
8877 %}
8878
8879 // ROL/ROR
8880 // ROL expand
8881 instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8882 effect(USE_DEF dst, USE shift, KILL cr);
8883
8884 format %{ "ROL $dst, $shift" %}
8885 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8886 ins_encode( OpcP, RegOpc( dst ));
8887 ins_pipe( ialu_reg );
8888 %}
8889
8890 instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8891 effect(USE_DEF dst, USE shift, KILL cr);
8892
8893 format %{ "ROL $dst, $shift" %}
8894 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8895 ins_encode( RegOpcImm(dst, shift) );
8896 ins_pipe(ialu_reg);
8897 %}
8898
8899 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8900 effect(USE_DEF dst, USE shift, KILL cr);
8901
8902 format %{ "ROL $dst, $shift" %}
8903 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8904 ins_encode(OpcP, RegOpc(dst));
8905 ins_pipe( ialu_reg_reg );
8906 %}
8907 // end of ROL expand
8908
8909 // ROL 32bit by one once
8910 instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8911 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8912
8913 expand %{
8914 rolI_eReg_imm1(dst, lshift, cr);
8915 %}
8916 %}
8917
8918 // ROL 32bit var by imm8 once
8919 instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8920 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8921 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8922
8923 expand %{
8924 rolI_eReg_imm8(dst, lshift, cr);
8925 %}
8926 %}
8927
8928 // ROL 32bit var by var once
8929 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8930 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8931
8932 expand %{
8933 rolI_eReg_CL(dst, shift, cr);
8934 %}
8935 %}
8936
8937 // ROL 32bit var by var once
8938 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8939 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8940
8941 expand %{
8942 rolI_eReg_CL(dst, shift, cr);
8943 %}
8944 %}
8945
8946 // ROR expand
8947 instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{
8948 effect(USE_DEF dst, USE shift, KILL cr);
8949
8950 format %{ "ROR $dst, $shift" %}
8951 opcode(0xD1,0x1); /* Opcode D1 /1 */
8952 ins_encode( OpcP, RegOpc( dst ) );
8953 ins_pipe( ialu_reg );
8954 %}
8955
8956 instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{
8957 effect (USE_DEF dst, USE shift, KILL cr);
8958
8959 format %{ "ROR $dst, $shift" %}
8960 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8961 ins_encode( RegOpcImm(dst, shift) );
8962 ins_pipe( ialu_reg );
8963 %}
8964
8965 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8966 effect(USE_DEF dst, USE shift, KILL cr);
8967
8968 format %{ "ROR $dst, $shift" %}
8969 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8970 ins_encode(OpcP, RegOpc(dst));
8971 ins_pipe( ialu_reg_reg );
8972 %}
8973 // end of ROR expand
8974
8975 // ROR right once
8976 instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8977 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8978
8979 expand %{
8980 rorI_eReg_imm1(dst, rshift, cr);
8981 %}
8982 %}
8983
8984 // ROR 32bit by immI8 once
8985 instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8986 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8987 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8988
8989 expand %{
8990 rorI_eReg_imm8(dst, rshift, cr);
8991 %}
8992 %}
8993
8994 // ROR 32bit var by var once
8995 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8996 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8997
8998 expand %{
8999 rorI_eReg_CL(dst, shift, cr);
9000 %}
9001 %}
9002
9003 // ROR 32bit var by var once
9004 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
9005 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
9006
9007 expand %{
9008 rorI_eReg_CL(dst, shift, cr);
9009 %}
9010 %}
9011
9012 // Xor Instructions
9013 // Xor Register with Register
9014 instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{
9015 match(Set dst (XorI dst src));
9016 effect(KILL cr);
9017
9018 size(2);
9019 format %{ "XOR $dst,$src" %}
9020 opcode(0x33);
9021 ins_encode( OpcP, RegReg( dst, src) );
9022 ins_pipe( ialu_reg_reg );
9023 %}
9024
9025 // Xor Register with Immediate -1
9026 instruct xorI_eReg_im1(eRegI dst, immI_M1 imm) %{
9027 match(Set dst (XorI dst imm));
9028
9029 size(2);
9030 format %{ "NOT $dst" %}
9031 ins_encode %{
9032 __ notl($dst$$Register);
9033 %}
9034 ins_pipe( ialu_reg );
9035 %}
9036
9037 // Xor Register with Immediate
9038 instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{
9039 match(Set dst (XorI dst src));
9040 effect(KILL cr);
9041
9042 format %{ "XOR $dst,$src" %}
9043 opcode(0x81,0x06); /* Opcode 81 /6 id */
9044 // ins_encode( RegImm( dst, src) );
9045 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
9046 ins_pipe( ialu_reg );
9047 %}
9048
9049 // Xor Register with Memory
9050 instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{
9051 match(Set dst (XorI dst (LoadI src)));
9052 effect(KILL cr);
9053
9054 ins_cost(125);
9055 format %{ "XOR $dst,$src" %}
9056 opcode(0x33);
9057 ins_encode( OpcP, RegMem(dst, src) );
9058 ins_pipe( ialu_reg_mem );
9059 %}
9060
9061 // Xor Memory with Register
9062 instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{
9063 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9064 effect(KILL cr);
9065
9066 ins_cost(150);
9067 format %{ "XOR $dst,$src" %}
9068 opcode(0x31); /* Opcode 31 /r */
9069 ins_encode( OpcP, RegMem( src, dst ) );
9070 ins_pipe( ialu_mem_reg );
9071 %}
9072
9073 // Xor Memory with Immediate
9074 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
9075 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9076 effect(KILL cr);
9077
9078 ins_cost(125);
9079 format %{ "XOR $dst,$src" %}
9080 opcode(0x81,0x6); /* Opcode 81 /6 id */
9081 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
9082 ins_pipe( ialu_mem_imm );
9083 %}
9084
9085 //----------Convert Int to Boolean---------------------------------------------
9086
9087 instruct movI_nocopy(eRegI dst, eRegI src) %{
9088 effect( DEF dst, USE src );
9089 format %{ "MOV $dst,$src" %}
9090 ins_encode( enc_Copy( dst, src) );
9091 ins_pipe( ialu_reg_reg );
9092 %}
9093
9094 instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{
9095 effect( USE_DEF dst, USE src, KILL cr );
9096
9097 size(4);
9098 format %{ "NEG $dst\n\t"
9099 "ADC $dst,$src" %}
9100 ins_encode( neg_reg(dst),
9101 OpcRegReg(0x13,dst,src) );
9102 ins_pipe( ialu_reg_reg_long );
9103 %}
9104
9105 instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{
9106 match(Set dst (Conv2B src));
9107
9108 expand %{
9109 movI_nocopy(dst,src);
9110 ci2b(dst,src,cr);
9111 %}
9112 %}
9113
9114 instruct movP_nocopy(eRegI dst, eRegP src) %{
9115 effect( DEF dst, USE src );
9116 format %{ "MOV $dst,$src" %}
9117 ins_encode( enc_Copy( dst, src) );
9118 ins_pipe( ialu_reg_reg );
9119 %}
9120
9121 instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{
9122 effect( USE_DEF dst, USE src, KILL cr );
9123 format %{ "NEG $dst\n\t"
9124 "ADC $dst,$src" %}
9125 ins_encode( neg_reg(dst),
9126 OpcRegReg(0x13,dst,src) );
9127 ins_pipe( ialu_reg_reg_long );
9128 %}
9129
9130 instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{
9131 match(Set dst (Conv2B src));
9132
9133 expand %{
9134 movP_nocopy(dst,src);
9135 cp2b(dst,src,cr);
9136 %}
9137 %}
9138
9139 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{
9140 match(Set dst (CmpLTMask p q));
9141 effect( KILL cr );
9142 ins_cost(400);
9143
9144 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
9145 format %{ "XOR $dst,$dst\n\t"
9146 "CMP $p,$q\n\t"
9147 "SETlt $dst\n\t"
9148 "NEG $dst" %}
9149 ins_encode( OpcRegReg(0x33,dst,dst),
9150 OpcRegReg(0x3B,p,q),
9151 setLT_reg(dst), neg_reg(dst) );
9152 ins_pipe( pipe_slow );
9153 %}
9154
9155 instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{
9156 match(Set dst (CmpLTMask dst zero));
9157 effect( DEF dst, KILL cr );
9158 ins_cost(100);
9159
9160 format %{ "SAR $dst,31" %}
9161 opcode(0xC1, 0x7); /* C1 /7 ib */
9162 ins_encode( RegOpcImm( dst, 0x1F ) );
9163 ins_pipe( ialu_reg );
9164 %}
9165
9166
9167 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{
9168 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9169 effect( KILL tmp, KILL cr );
9170 ins_cost(400);
9171 // annoyingly, $tmp has no edges so you cant ask for it in
9172 // any format or encoding
9173 format %{ "SUB $p,$q\n\t"
9174 "SBB ECX,ECX\n\t"
9175 "AND ECX,$y\n\t"
9176 "ADD $p,ECX" %}
9177 ins_encode( enc_cmpLTP(p,q,y,tmp) );
9178 ins_pipe( pipe_cmplt );
9179 %}
9180
9181 /* If I enable this, I encourage spilling in the inner loop of compress.
9182 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{
9183 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9184 effect( USE_KILL tmp, KILL cr );
9185 ins_cost(400);
9186
9187 format %{ "SUB $p,$q\n\t"
9188 "SBB ECX,ECX\n\t"
9189 "AND ECX,$y\n\t"
9190 "ADD $p,ECX" %}
9191 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) );
9192 %}
9193 */
9194
9195 //----------Long Instructions------------------------------------------------
9196 // Add Long Register with Register
9197 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9198 match(Set dst (AddL dst src));
9199 effect(KILL cr);
9200 ins_cost(200);
9201 format %{ "ADD $dst.lo,$src.lo\n\t"
9202 "ADC $dst.hi,$src.hi" %}
9203 opcode(0x03, 0x13);
9204 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9205 ins_pipe( ialu_reg_reg_long );
9206 %}
9207
9208 // Add Long Register with Immediate
9209 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9210 match(Set dst (AddL dst src));
9211 effect(KILL cr);
9212 format %{ "ADD $dst.lo,$src.lo\n\t"
9213 "ADC $dst.hi,$src.hi" %}
9214 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9215 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9216 ins_pipe( ialu_reg_long );
9217 %}
9218
9219 // Add Long Register with Memory
9220 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9221 match(Set dst (AddL dst (LoadL mem)));
9222 effect(KILL cr);
9223 ins_cost(125);
9224 format %{ "ADD $dst.lo,$mem\n\t"
9225 "ADC $dst.hi,$mem+4" %}
9226 opcode(0x03, 0x13);
9227 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9228 ins_pipe( ialu_reg_long_mem );
9229 %}
9230
9231 // Subtract Long Register with Register.
9232 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9233 match(Set dst (SubL dst src));
9234 effect(KILL cr);
9235 ins_cost(200);
9236 format %{ "SUB $dst.lo,$src.lo\n\t"
9237 "SBB $dst.hi,$src.hi" %}
9238 opcode(0x2B, 0x1B);
9239 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9240 ins_pipe( ialu_reg_reg_long );
9241 %}
9242
9243 // Subtract Long Register with Immediate
9244 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9245 match(Set dst (SubL dst src));
9246 effect(KILL cr);
9247 format %{ "SUB $dst.lo,$src.lo\n\t"
9248 "SBB $dst.hi,$src.hi" %}
9249 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9250 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9251 ins_pipe( ialu_reg_long );
9252 %}
9253
9254 // Subtract Long Register with Memory
9255 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9256 match(Set dst (SubL dst (LoadL mem)));
9257 effect(KILL cr);
9258 ins_cost(125);
9259 format %{ "SUB $dst.lo,$mem\n\t"
9260 "SBB $dst.hi,$mem+4" %}
9261 opcode(0x2B, 0x1B);
9262 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9263 ins_pipe( ialu_reg_long_mem );
9264 %}
9265
9266 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9267 match(Set dst (SubL zero dst));
9268 effect(KILL cr);
9269 ins_cost(300);
9270 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9271 ins_encode( neg_long(dst) );
9272 ins_pipe( ialu_reg_reg_long );
9273 %}
9274
9275 // And Long Register with Register
9276 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9277 match(Set dst (AndL dst src));
9278 effect(KILL cr);
9279 format %{ "AND $dst.lo,$src.lo\n\t"
9280 "AND $dst.hi,$src.hi" %}
9281 opcode(0x23,0x23);
9282 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9283 ins_pipe( ialu_reg_reg_long );
9284 %}
9285
9286 // And Long Register with Immediate
9287 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9288 match(Set dst (AndL dst src));
9289 effect(KILL cr);
9290 format %{ "AND $dst.lo,$src.lo\n\t"
9291 "AND $dst.hi,$src.hi" %}
9292 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9293 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9294 ins_pipe( ialu_reg_long );
9295 %}
9296
9297 // And Long Register with Memory
9298 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9299 match(Set dst (AndL dst (LoadL mem)));
9300 effect(KILL cr);
9301 ins_cost(125);
9302 format %{ "AND $dst.lo,$mem\n\t"
9303 "AND $dst.hi,$mem+4" %}
9304 opcode(0x23, 0x23);
9305 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9306 ins_pipe( ialu_reg_long_mem );
9307 %}
9308
9309 // Or Long Register with Register
9310 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9311 match(Set dst (OrL dst src));
9312 effect(KILL cr);
9313 format %{ "OR $dst.lo,$src.lo\n\t"
9314 "OR $dst.hi,$src.hi" %}
9315 opcode(0x0B,0x0B);
9316 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9317 ins_pipe( ialu_reg_reg_long );
9318 %}
9319
9320 // Or Long Register with Immediate
9321 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9322 match(Set dst (OrL dst src));
9323 effect(KILL cr);
9324 format %{ "OR $dst.lo,$src.lo\n\t"
9325 "OR $dst.hi,$src.hi" %}
9326 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9327 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9328 ins_pipe( ialu_reg_long );
9329 %}
9330
9331 // Or Long Register with Memory
9332 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9333 match(Set dst (OrL dst (LoadL mem)));
9334 effect(KILL cr);
9335 ins_cost(125);
9336 format %{ "OR $dst.lo,$mem\n\t"
9337 "OR $dst.hi,$mem+4" %}
9338 opcode(0x0B,0x0B);
9339 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9340 ins_pipe( ialu_reg_long_mem );
9341 %}
9342
9343 // Xor Long Register with Register
9344 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9345 match(Set dst (XorL dst src));
9346 effect(KILL cr);
9347 format %{ "XOR $dst.lo,$src.lo\n\t"
9348 "XOR $dst.hi,$src.hi" %}
9349 opcode(0x33,0x33);
9350 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9351 ins_pipe( ialu_reg_reg_long );
9352 %}
9353
9354 // Xor Long Register with Immediate -1
9355 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9356 match(Set dst (XorL dst imm));
9357 format %{ "NOT $dst.lo\n\t"
9358 "NOT $dst.hi" %}
9359 ins_encode %{
9360 __ notl($dst$$Register);
9361 __ notl(HIGH_FROM_LOW($dst$$Register));
9362 %}
9363 ins_pipe( ialu_reg_long );
9364 %}
9365
9366 // Xor Long Register with Immediate
9367 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9368 match(Set dst (XorL dst src));
9369 effect(KILL cr);
9370 format %{ "XOR $dst.lo,$src.lo\n\t"
9371 "XOR $dst.hi,$src.hi" %}
9372 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9373 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9374 ins_pipe( ialu_reg_long );
9375 %}
9376
9377 // Xor Long Register with Memory
9378 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9379 match(Set dst (XorL dst (LoadL mem)));
9380 effect(KILL cr);
9381 ins_cost(125);
9382 format %{ "XOR $dst.lo,$mem\n\t"
9383 "XOR $dst.hi,$mem+4" %}
9384 opcode(0x33,0x33);
9385 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9386 ins_pipe( ialu_reg_long_mem );
9387 %}
9388
9389 // Shift Left Long by 1
9390 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9391 predicate(UseNewLongLShift);
9392 match(Set dst (LShiftL dst cnt));
9393 effect(KILL cr);
9394 ins_cost(100);
9395 format %{ "ADD $dst.lo,$dst.lo\n\t"
9396 "ADC $dst.hi,$dst.hi" %}
9397 ins_encode %{
9398 __ addl($dst$$Register,$dst$$Register);
9399 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9400 %}
9401 ins_pipe( ialu_reg_long );
9402 %}
9403
9404 // Shift Left Long by 2
9405 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9406 predicate(UseNewLongLShift);
9407 match(Set dst (LShiftL dst cnt));
9408 effect(KILL cr);
9409 ins_cost(100);
9410 format %{ "ADD $dst.lo,$dst.lo\n\t"
9411 "ADC $dst.hi,$dst.hi\n\t"
9412 "ADD $dst.lo,$dst.lo\n\t"
9413 "ADC $dst.hi,$dst.hi" %}
9414 ins_encode %{
9415 __ addl($dst$$Register,$dst$$Register);
9416 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9417 __ addl($dst$$Register,$dst$$Register);
9418 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9419 %}
9420 ins_pipe( ialu_reg_long );
9421 %}
9422
9423 // Shift Left Long by 3
9424 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9425 predicate(UseNewLongLShift);
9426 match(Set dst (LShiftL dst cnt));
9427 effect(KILL cr);
9428 ins_cost(100);
9429 format %{ "ADD $dst.lo,$dst.lo\n\t"
9430 "ADC $dst.hi,$dst.hi\n\t"
9431 "ADD $dst.lo,$dst.lo\n\t"
9432 "ADC $dst.hi,$dst.hi\n\t"
9433 "ADD $dst.lo,$dst.lo\n\t"
9434 "ADC $dst.hi,$dst.hi" %}
9435 ins_encode %{
9436 __ addl($dst$$Register,$dst$$Register);
9437 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9438 __ addl($dst$$Register,$dst$$Register);
9439 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9440 __ addl($dst$$Register,$dst$$Register);
9441 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9442 %}
9443 ins_pipe( ialu_reg_long );
9444 %}
9445
9446 // Shift Left Long by 1-31
9447 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9448 match(Set dst (LShiftL dst cnt));
9449 effect(KILL cr);
9450 ins_cost(200);
9451 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9452 "SHL $dst.lo,$cnt" %}
9453 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9454 ins_encode( move_long_small_shift(dst,cnt) );
9455 ins_pipe( ialu_reg_long );
9456 %}
9457
9458 // Shift Left Long by 32-63
9459 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9460 match(Set dst (LShiftL dst cnt));
9461 effect(KILL cr);
9462 ins_cost(300);
9463 format %{ "MOV $dst.hi,$dst.lo\n"
9464 "\tSHL $dst.hi,$cnt-32\n"
9465 "\tXOR $dst.lo,$dst.lo" %}
9466 opcode(0xC1, 0x4); /* C1 /4 ib */
9467 ins_encode( move_long_big_shift_clr(dst,cnt) );
9468 ins_pipe( ialu_reg_long );
9469 %}
9470
9471 // Shift Left Long by variable
9472 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9473 match(Set dst (LShiftL dst shift));
9474 effect(KILL cr);
9475 ins_cost(500+200);
9476 size(17);
9477 format %{ "TEST $shift,32\n\t"
9478 "JEQ,s small\n\t"
9479 "MOV $dst.hi,$dst.lo\n\t"
9480 "XOR $dst.lo,$dst.lo\n"
9481 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9482 "SHL $dst.lo,$shift" %}
9483 ins_encode( shift_left_long( dst, shift ) );
9484 ins_pipe( pipe_slow );
9485 %}
9486
9487 // Shift Right Long by 1-31
9488 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9489 match(Set dst (URShiftL dst cnt));
9490 effect(KILL cr);
9491 ins_cost(200);
9492 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9493 "SHR $dst.hi,$cnt" %}
9494 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9495 ins_encode( move_long_small_shift(dst,cnt) );
9496 ins_pipe( ialu_reg_long );
9497 %}
9498
9499 // Shift Right Long by 32-63
9500 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9501 match(Set dst (URShiftL dst cnt));
9502 effect(KILL cr);
9503 ins_cost(300);
9504 format %{ "MOV $dst.lo,$dst.hi\n"
9505 "\tSHR $dst.lo,$cnt-32\n"
9506 "\tXOR $dst.hi,$dst.hi" %}
9507 opcode(0xC1, 0x5); /* C1 /5 ib */
9508 ins_encode( move_long_big_shift_clr(dst,cnt) );
9509 ins_pipe( ialu_reg_long );
9510 %}
9511
9512 // Shift Right Long by variable
9513 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9514 match(Set dst (URShiftL dst shift));
9515 effect(KILL cr);
9516 ins_cost(600);
9517 size(17);
9518 format %{ "TEST $shift,32\n\t"
9519 "JEQ,s small\n\t"
9520 "MOV $dst.lo,$dst.hi\n\t"
9521 "XOR $dst.hi,$dst.hi\n"
9522 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9523 "SHR $dst.hi,$shift" %}
9524 ins_encode( shift_right_long( dst, shift ) );
9525 ins_pipe( pipe_slow );
9526 %}
9527
9528 // Shift Right Long by 1-31
9529 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9530 match(Set dst (RShiftL dst cnt));
9531 effect(KILL cr);
9532 ins_cost(200);
9533 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9534 "SAR $dst.hi,$cnt" %}
9535 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9536 ins_encode( move_long_small_shift(dst,cnt) );
9537 ins_pipe( ialu_reg_long );
9538 %}
9539
9540 // Shift Right Long by 32-63
9541 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9542 match(Set dst (RShiftL dst cnt));
9543 effect(KILL cr);
9544 ins_cost(300);
9545 format %{ "MOV $dst.lo,$dst.hi\n"
9546 "\tSAR $dst.lo,$cnt-32\n"
9547 "\tSAR $dst.hi,31" %}
9548 opcode(0xC1, 0x7); /* C1 /7 ib */
9549 ins_encode( move_long_big_shift_sign(dst,cnt) );
9550 ins_pipe( ialu_reg_long );
9551 %}
9552
9553 // Shift Right arithmetic Long by variable
9554 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9555 match(Set dst (RShiftL dst shift));
9556 effect(KILL cr);
9557 ins_cost(600);
9558 size(18);
9559 format %{ "TEST $shift,32\n\t"
9560 "JEQ,s small\n\t"
9561 "MOV $dst.lo,$dst.hi\n\t"
9562 "SAR $dst.hi,31\n"
9563 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9564 "SAR $dst.hi,$shift" %}
9565 ins_encode( shift_right_arith_long( dst, shift ) );
9566 ins_pipe( pipe_slow );
9567 %}
9568
9569
9570 //----------Double Instructions------------------------------------------------
9571 // Double Math
9572
9573 // Compare & branch
9574
9575 // P6 version of float compare, sets condition codes in EFLAGS
9576 instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9577 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9578 match(Set cr (CmpD src1 src2));
9579 effect(KILL rax);
9580 ins_cost(150);
9581 format %{ "FLD $src1\n\t"
9582 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9583 "JNP exit\n\t"
9584 "MOV ah,1 // saw a NaN, set CF\n\t"
9585 "SAHF\n"
9586 "exit:\tNOP // avoid branch to branch" %}
9587 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9588 ins_encode( Push_Reg_D(src1),
9589 OpcP, RegOpc(src2),
9590 cmpF_P6_fixup );
9591 ins_pipe( pipe_slow );
9592 %}
9593
9594 instruct cmpD_cc_P6CF(eFlagsRegUCF cr, regD src1, regD src2) %{
9595 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9596 match(Set cr (CmpD src1 src2));
9597 ins_cost(150);
9598 format %{ "FLD $src1\n\t"
9599 "FUCOMIP ST,$src2 // P6 instruction" %}
9600 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9601 ins_encode( Push_Reg_D(src1),
9602 OpcP, RegOpc(src2));
9603 ins_pipe( pipe_slow );
9604 %}
9605
9606 // Compare & branch
9607 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{
9608 predicate(UseSSE<=1);
9609 match(Set cr (CmpD src1 src2));
9610 effect(KILL rax);
9611 ins_cost(200);
9612 format %{ "FLD $src1\n\t"
9613 "FCOMp $src2\n\t"
9614 "FNSTSW AX\n\t"
9615 "TEST AX,0x400\n\t"
9616 "JZ,s flags\n\t"
9617 "MOV AH,1\t# unordered treat as LT\n"
9618 "flags:\tSAHF" %}
9619 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9620 ins_encode( Push_Reg_D(src1),
9621 OpcP, RegOpc(src2),
9622 fpu_flags);
9623 ins_pipe( pipe_slow );
9624 %}
9625
9626 // Compare vs zero into -1,0,1
9627 instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{
9628 predicate(UseSSE<=1);
9629 match(Set dst (CmpD3 src1 zero));
9630 effect(KILL cr, KILL rax);
9631 ins_cost(280);
9632 format %{ "FTSTD $dst,$src1" %}
9633 opcode(0xE4, 0xD9);
9634 ins_encode( Push_Reg_D(src1),
9635 OpcS, OpcP, PopFPU,
9636 CmpF_Result(dst));
9637 ins_pipe( pipe_slow );
9638 %}
9639
9640 // Compare into -1,0,1
9641 instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{
9642 predicate(UseSSE<=1);
9643 match(Set dst (CmpD3 src1 src2));
9644 effect(KILL cr, KILL rax);
9645 ins_cost(300);
9646 format %{ "FCMPD $dst,$src1,$src2" %}
9647 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9648 ins_encode( Push_Reg_D(src1),
9649 OpcP, RegOpc(src2),
9650 CmpF_Result(dst));
9651 ins_pipe( pipe_slow );
9652 %}
9653
9654 // float compare and set condition codes in EFLAGS by XMM regs
9655 instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{
9656 predicate(UseSSE>=2);
9657 match(Set cr (CmpD dst src));
9658 effect(KILL rax);
9659 ins_cost(125);
9660 format %{ "COMISD $dst,$src\n"
9661 "\tJNP exit\n"
9662 "\tMOV ah,1 // saw a NaN, set CF\n"
9663 "\tSAHF\n"
9664 "exit:\tNOP // avoid branch to branch" %}
9665 opcode(0x66, 0x0F, 0x2F);
9666 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup);
9667 ins_pipe( pipe_slow );
9668 %}
9669
9670 instruct cmpXD_ccCF(eFlagsRegUCF cr, regXD dst, regXD src) %{
9671 predicate(UseSSE>=2);
9672 match(Set cr (CmpD dst src));
9673 ins_cost(100);
9674 format %{ "COMISD $dst,$src" %}
9675 opcode(0x66, 0x0F, 0x2F);
9676 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
9677 ins_pipe( pipe_slow );
9678 %}
9679
9680 // float compare and set condition codes in EFLAGS by XMM regs
9681 instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{
9682 predicate(UseSSE>=2);
9683 match(Set cr (CmpD dst (LoadD src)));
9684 effect(KILL rax);
9685 ins_cost(145);
9686 format %{ "COMISD $dst,$src\n"
9687 "\tJNP exit\n"
9688 "\tMOV ah,1 // saw a NaN, set CF\n"
9689 "\tSAHF\n"
9690 "exit:\tNOP // avoid branch to branch" %}
9691 opcode(0x66, 0x0F, 0x2F);
9692 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup);
9693 ins_pipe( pipe_slow );
9694 %}
9695
9696 instruct cmpXD_ccmemCF(eFlagsRegUCF cr, regXD dst, memory src) %{
9697 predicate(UseSSE>=2);
9698 match(Set cr (CmpD dst (LoadD src)));
9699 ins_cost(100);
9700 format %{ "COMISD $dst,$src" %}
9701 opcode(0x66, 0x0F, 0x2F);
9702 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src));
9703 ins_pipe( pipe_slow );
9704 %}
9705
9706 // Compare into -1,0,1 in XMM
9707 instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{
9708 predicate(UseSSE>=2);
9709 match(Set dst (CmpD3 src1 src2));
9710 effect(KILL cr);
9711 ins_cost(255);
9712 format %{ "XOR $dst,$dst\n"
9713 "\tCOMISD $src1,$src2\n"
9714 "\tJP,s nan\n"
9715 "\tJEQ,s exit\n"
9716 "\tJA,s inc\n"
9717 "nan:\tDEC $dst\n"
9718 "\tJMP,s exit\n"
9719 "inc:\tINC $dst\n"
9720 "exit:"
9721 %}
9722 opcode(0x66, 0x0F, 0x2F);
9723 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2),
9724 CmpX_Result(dst));
9725 ins_pipe( pipe_slow );
9726 %}
9727
9728 // Compare into -1,0,1 in XMM and memory
9729 instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{
9730 predicate(UseSSE>=2);
9731 match(Set dst (CmpD3 src1 (LoadD mem)));
9732 effect(KILL cr);
9733 ins_cost(275);
9734 format %{ "COMISD $src1,$mem\n"
9735 "\tMOV $dst,0\t\t# do not blow flags\n"
9736 "\tJP,s nan\n"
9737 "\tJEQ,s exit\n"
9738 "\tJA,s inc\n"
9739 "nan:\tDEC $dst\n"
9740 "\tJMP,s exit\n"
9741 "inc:\tINC $dst\n"
9742 "exit:"
9743 %}
9744 opcode(0x66, 0x0F, 0x2F);
9745 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem),
9746 LdImmI(dst,0x0), CmpX_Result(dst));
9747 ins_pipe( pipe_slow );
9748 %}
9749
9750
9751 instruct subD_reg(regD dst, regD src) %{
9752 predicate (UseSSE <=1);
9753 match(Set dst (SubD dst src));
9754
9755 format %{ "FLD $src\n\t"
9756 "DSUBp $dst,ST" %}
9757 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9758 ins_cost(150);
9759 ins_encode( Push_Reg_D(src),
9760 OpcP, RegOpc(dst) );
9761 ins_pipe( fpu_reg_reg );
9762 %}
9763
9764 instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9765 predicate (UseSSE <=1);
9766 match(Set dst (RoundDouble (SubD src1 src2)));
9767 ins_cost(250);
9768
9769 format %{ "FLD $src2\n\t"
9770 "DSUB ST,$src1\n\t"
9771 "FSTP_D $dst\t# D-round" %}
9772 opcode(0xD8, 0x5);
9773 ins_encode( Push_Reg_D(src2),
9774 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9775 ins_pipe( fpu_mem_reg_reg );
9776 %}
9777
9778
9779 instruct subD_reg_mem(regD dst, memory src) %{
9780 predicate (UseSSE <=1);
9781 match(Set dst (SubD dst (LoadD src)));
9782 ins_cost(150);
9783
9784 format %{ "FLD $src\n\t"
9785 "DSUBp $dst,ST" %}
9786 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9787 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9788 OpcP, RegOpc(dst) );
9789 ins_pipe( fpu_reg_mem );
9790 %}
9791
9792 instruct absD_reg(regDPR1 dst, regDPR1 src) %{
9793 predicate (UseSSE<=1);
9794 match(Set dst (AbsD src));
9795 ins_cost(100);
9796 format %{ "FABS" %}
9797 opcode(0xE1, 0xD9);
9798 ins_encode( OpcS, OpcP );
9799 ins_pipe( fpu_reg_reg );
9800 %}
9801
9802 instruct absXD_reg( regXD dst ) %{
9803 predicate(UseSSE>=2);
9804 match(Set dst (AbsD dst));
9805 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %}
9806 ins_encode( AbsXD_encoding(dst));
9807 ins_pipe( pipe_slow );
9808 %}
9809
9810 instruct negD_reg(regDPR1 dst, regDPR1 src) %{
9811 predicate(UseSSE<=1);
9812 match(Set dst (NegD src));
9813 ins_cost(100);
9814 format %{ "FCHS" %}
9815 opcode(0xE0, 0xD9);
9816 ins_encode( OpcS, OpcP );
9817 ins_pipe( fpu_reg_reg );
9818 %}
9819
9820 instruct negXD_reg( regXD dst ) %{
9821 predicate(UseSSE>=2);
9822 match(Set dst (NegD dst));
9823 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %}
9824 ins_encode %{
9825 __ xorpd($dst$$XMMRegister,
9826 ExternalAddress((address)double_signflip_pool));
9827 %}
9828 ins_pipe( pipe_slow );
9829 %}
9830
9831 instruct addD_reg(regD dst, regD src) %{
9832 predicate(UseSSE<=1);
9833 match(Set dst (AddD dst src));
9834 format %{ "FLD $src\n\t"
9835 "DADD $dst,ST" %}
9836 size(4);
9837 ins_cost(150);
9838 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9839 ins_encode( Push_Reg_D(src),
9840 OpcP, RegOpc(dst) );
9841 ins_pipe( fpu_reg_reg );
9842 %}
9843
9844
9845 instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{
9846 predicate(UseSSE<=1);
9847 match(Set dst (RoundDouble (AddD src1 src2)));
9848 ins_cost(250);
9849
9850 format %{ "FLD $src2\n\t"
9851 "DADD ST,$src1\n\t"
9852 "FSTP_D $dst\t# D-round" %}
9853 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9854 ins_encode( Push_Reg_D(src2),
9855 OpcP, RegOpc(src1), Pop_Mem_D(dst) );
9856 ins_pipe( fpu_mem_reg_reg );
9857 %}
9858
9859
9860 instruct addD_reg_mem(regD dst, memory src) %{
9861 predicate(UseSSE<=1);
9862 match(Set dst (AddD dst (LoadD src)));
9863 ins_cost(150);
9864
9865 format %{ "FLD $src\n\t"
9866 "DADDp $dst,ST" %}
9867 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9868 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9869 OpcP, RegOpc(dst) );
9870 ins_pipe( fpu_reg_mem );
9871 %}
9872
9873 // add-to-memory
9874 instruct addD_mem_reg(memory dst, regD src) %{
9875 predicate(UseSSE<=1);
9876 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9877 ins_cost(150);
9878
9879 format %{ "FLD_D $dst\n\t"
9880 "DADD ST,$src\n\t"
9881 "FST_D $dst" %}
9882 opcode(0xDD, 0x0);
9883 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9884 Opcode(0xD8), RegOpc(src),
9885 set_instruction_start,
9886 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9887 ins_pipe( fpu_reg_mem );
9888 %}
9889
9890 instruct addD_reg_imm1(regD dst, immD1 src) %{
9891 predicate(UseSSE<=1);
9892 match(Set dst (AddD dst src));
9893 ins_cost(125);
9894 format %{ "FLD1\n\t"
9895 "DADDp $dst,ST" %}
9896 opcode(0xDE, 0x00);
9897 ins_encode( LdImmD(src),
9898 OpcP, RegOpc(dst) );
9899 ins_pipe( fpu_reg );
9900 %}
9901
9902 instruct addD_reg_imm(regD dst, immD src) %{
9903 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9904 match(Set dst (AddD dst src));
9905 ins_cost(200);
9906 format %{ "FLD_D [$src]\n\t"
9907 "DADDp $dst,ST" %}
9908 opcode(0xDE, 0x00); /* DE /0 */
9909 ins_encode( LdImmD(src),
9910 OpcP, RegOpc(dst));
9911 ins_pipe( fpu_reg_mem );
9912 %}
9913
9914 instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{
9915 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9916 match(Set dst (RoundDouble (AddD src con)));
9917 ins_cost(200);
9918 format %{ "FLD_D [$con]\n\t"
9919 "DADD ST,$src\n\t"
9920 "FSTP_D $dst\t# D-round" %}
9921 opcode(0xD8, 0x00); /* D8 /0 */
9922 ins_encode( LdImmD(con),
9923 OpcP, RegOpc(src), Pop_Mem_D(dst));
9924 ins_pipe( fpu_mem_reg_con );
9925 %}
9926
9927 // Add two double precision floating point values in xmm
9928 instruct addXD_reg(regXD dst, regXD src) %{
9929 predicate(UseSSE>=2);
9930 match(Set dst (AddD dst src));
9931 format %{ "ADDSD $dst,$src" %}
9932 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
9933 ins_pipe( pipe_slow );
9934 %}
9935
9936 instruct addXD_imm(regXD dst, immXD con) %{
9937 predicate(UseSSE>=2);
9938 match(Set dst (AddD dst con));
9939 format %{ "ADDSD $dst,[$con]" %}
9940 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) );
9941 ins_pipe( pipe_slow );
9942 %}
9943
9944 instruct addXD_mem(regXD dst, memory mem) %{
9945 predicate(UseSSE>=2);
9946 match(Set dst (AddD dst (LoadD mem)));
9947 format %{ "ADDSD $dst,$mem" %}
9948 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem));
9949 ins_pipe( pipe_slow );
9950 %}
9951
9952 // Sub two double precision floating point values in xmm
9953 instruct subXD_reg(regXD dst, regXD src) %{
9954 predicate(UseSSE>=2);
9955 match(Set dst (SubD dst src));
9956 format %{ "SUBSD $dst,$src" %}
9957 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
9958 ins_pipe( pipe_slow );
9959 %}
9960
9961 instruct subXD_imm(regXD dst, immXD con) %{
9962 predicate(UseSSE>=2);
9963 match(Set dst (SubD dst con));
9964 format %{ "SUBSD $dst,[$con]" %}
9965 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) );
9966 ins_pipe( pipe_slow );
9967 %}
9968
9969 instruct subXD_mem(regXD dst, memory mem) %{
9970 predicate(UseSSE>=2);
9971 match(Set dst (SubD dst (LoadD mem)));
9972 format %{ "SUBSD $dst,$mem" %}
9973 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
9974 ins_pipe( pipe_slow );
9975 %}
9976
9977 // Mul two double precision floating point values in xmm
9978 instruct mulXD_reg(regXD dst, regXD src) %{
9979 predicate(UseSSE>=2);
9980 match(Set dst (MulD dst src));
9981 format %{ "MULSD $dst,$src" %}
9982 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
9983 ins_pipe( pipe_slow );
9984 %}
9985
9986 instruct mulXD_imm(regXD dst, immXD con) %{
9987 predicate(UseSSE>=2);
9988 match(Set dst (MulD dst con));
9989 format %{ "MULSD $dst,[$con]" %}
9990 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) );
9991 ins_pipe( pipe_slow );
9992 %}
9993
9994 instruct mulXD_mem(regXD dst, memory mem) %{
9995 predicate(UseSSE>=2);
9996 match(Set dst (MulD dst (LoadD mem)));
9997 format %{ "MULSD $dst,$mem" %}
9998 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
9999 ins_pipe( pipe_slow );
10000 %}
10001
10002 // Div two double precision floating point values in xmm
10003 instruct divXD_reg(regXD dst, regXD src) %{
10004 predicate(UseSSE>=2);
10005 match(Set dst (DivD dst src));
10006 format %{ "DIVSD $dst,$src" %}
10007 opcode(0xF2, 0x0F, 0x5E);
10008 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10009 ins_pipe( pipe_slow );
10010 %}
10011
10012 instruct divXD_imm(regXD dst, immXD con) %{
10013 predicate(UseSSE>=2);
10014 match(Set dst (DivD dst con));
10015 format %{ "DIVSD $dst,[$con]" %}
10016 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con));
10017 ins_pipe( pipe_slow );
10018 %}
10019
10020 instruct divXD_mem(regXD dst, memory mem) %{
10021 predicate(UseSSE>=2);
10022 match(Set dst (DivD dst (LoadD mem)));
10023 format %{ "DIVSD $dst,$mem" %}
10024 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10025 ins_pipe( pipe_slow );
10026 %}
10027
10028
10029 instruct mulD_reg(regD dst, regD src) %{
10030 predicate(UseSSE<=1);
10031 match(Set dst (MulD dst src));
10032 format %{ "FLD $src\n\t"
10033 "DMULp $dst,ST" %}
10034 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10035 ins_cost(150);
10036 ins_encode( Push_Reg_D(src),
10037 OpcP, RegOpc(dst) );
10038 ins_pipe( fpu_reg_reg );
10039 %}
10040
10041 // Strict FP instruction biases argument before multiply then
10042 // biases result to avoid double rounding of subnormals.
10043 //
10044 // scale arg1 by multiplying arg1 by 2^(-15360)
10045 // load arg2
10046 // multiply scaled arg1 by arg2
10047 // rescale product by 2^(15360)
10048 //
10049 instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{
10050 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10051 match(Set dst (MulD dst src));
10052 ins_cost(1); // Select this instruction for all strict FP double multiplies
10053
10054 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10055 "DMULp $dst,ST\n\t"
10056 "FLD $src\n\t"
10057 "DMULp $dst,ST\n\t"
10058 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10059 "DMULp $dst,ST\n\t" %}
10060 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
10061 ins_encode( strictfp_bias1(dst),
10062 Push_Reg_D(src),
10063 OpcP, RegOpc(dst),
10064 strictfp_bias2(dst) );
10065 ins_pipe( fpu_reg_reg );
10066 %}
10067
10068 instruct mulD_reg_imm(regD dst, immD src) %{
10069 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
10070 match(Set dst (MulD dst src));
10071 ins_cost(200);
10072 format %{ "FLD_D [$src]\n\t"
10073 "DMULp $dst,ST" %}
10074 opcode(0xDE, 0x1); /* DE /1 */
10075 ins_encode( LdImmD(src),
10076 OpcP, RegOpc(dst) );
10077 ins_pipe( fpu_reg_mem );
10078 %}
10079
10080
10081 instruct mulD_reg_mem(regD dst, memory src) %{
10082 predicate( UseSSE<=1 );
10083 match(Set dst (MulD dst (LoadD src)));
10084 ins_cost(200);
10085 format %{ "FLD_D $src\n\t"
10086 "DMULp $dst,ST" %}
10087 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
10088 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10089 OpcP, RegOpc(dst) );
10090 ins_pipe( fpu_reg_mem );
10091 %}
10092
10093 //
10094 // Cisc-alternate to reg-reg multiply
10095 instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{
10096 predicate( UseSSE<=1 );
10097 match(Set dst (MulD src (LoadD mem)));
10098 ins_cost(250);
10099 format %{ "FLD_D $mem\n\t"
10100 "DMUL ST,$src\n\t"
10101 "FSTP_D $dst" %}
10102 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
10103 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
10104 OpcReg_F(src),
10105 Pop_Reg_D(dst) );
10106 ins_pipe( fpu_reg_reg_mem );
10107 %}
10108
10109
10110 // MACRO3 -- addD a mulD
10111 // This instruction is a '2-address' instruction in that the result goes
10112 // back to src2. This eliminates a move from the macro; possibly the
10113 // register allocator will have to add it back (and maybe not).
10114 instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{
10115 predicate( UseSSE<=1 );
10116 match(Set src2 (AddD (MulD src0 src1) src2));
10117 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10118 "DMUL ST,$src1\n\t"
10119 "DADDp $src2,ST" %}
10120 ins_cost(250);
10121 opcode(0xDD); /* LoadD DD /0 */
10122 ins_encode( Push_Reg_F(src0),
10123 FMul_ST_reg(src1),
10124 FAddP_reg_ST(src2) );
10125 ins_pipe( fpu_reg_reg_reg );
10126 %}
10127
10128
10129 // MACRO3 -- subD a mulD
10130 instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{
10131 predicate( UseSSE<=1 );
10132 match(Set src2 (SubD (MulD src0 src1) src2));
10133 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
10134 "DMUL ST,$src1\n\t"
10135 "DSUBRp $src2,ST" %}
10136 ins_cost(250);
10137 ins_encode( Push_Reg_F(src0),
10138 FMul_ST_reg(src1),
10139 Opcode(0xDE), Opc_plus(0xE0,src2));
10140 ins_pipe( fpu_reg_reg_reg );
10141 %}
10142
10143
10144 instruct divD_reg(regD dst, regD src) %{
10145 predicate( UseSSE<=1 );
10146 match(Set dst (DivD dst src));
10147
10148 format %{ "FLD $src\n\t"
10149 "FDIVp $dst,ST" %}
10150 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10151 ins_cost(150);
10152 ins_encode( Push_Reg_D(src),
10153 OpcP, RegOpc(dst) );
10154 ins_pipe( fpu_reg_reg );
10155 %}
10156
10157 // Strict FP instruction biases argument before division then
10158 // biases result, to avoid double rounding of subnormals.
10159 //
10160 // scale dividend by multiplying dividend by 2^(-15360)
10161 // load divisor
10162 // divide scaled dividend by divisor
10163 // rescale quotient by 2^(15360)
10164 //
10165 instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{
10166 predicate (UseSSE<=1);
10167 match(Set dst (DivD dst src));
10168 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
10169 ins_cost(01);
10170
10171 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
10172 "DMULp $dst,ST\n\t"
10173 "FLD $src\n\t"
10174 "FDIVp $dst,ST\n\t"
10175 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
10176 "DMULp $dst,ST\n\t" %}
10177 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10178 ins_encode( strictfp_bias1(dst),
10179 Push_Reg_D(src),
10180 OpcP, RegOpc(dst),
10181 strictfp_bias2(dst) );
10182 ins_pipe( fpu_reg_reg );
10183 %}
10184
10185 instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{
10186 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
10187 match(Set dst (RoundDouble (DivD src1 src2)));
10188
10189 format %{ "FLD $src1\n\t"
10190 "FDIV ST,$src2\n\t"
10191 "FSTP_D $dst\t# D-round" %}
10192 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
10193 ins_encode( Push_Reg_D(src1),
10194 OpcP, RegOpc(src2), Pop_Mem_D(dst) );
10195 ins_pipe( fpu_mem_reg_reg );
10196 %}
10197
10198
10199 instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{
10200 predicate(UseSSE<=1);
10201 match(Set dst (ModD dst src));
10202 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
10203
10204 format %{ "DMOD $dst,$src" %}
10205 ins_cost(250);
10206 ins_encode(Push_Reg_Mod_D(dst, src),
10207 emitModD(),
10208 Push_Result_Mod_D(src),
10209 Pop_Reg_D(dst));
10210 ins_pipe( pipe_slow );
10211 %}
10212
10213 instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{
10214 predicate(UseSSE>=2);
10215 match(Set dst (ModD src0 src1));
10216 effect(KILL rax, KILL cr);
10217
10218 format %{ "SUB ESP,8\t # DMOD\n"
10219 "\tMOVSD [ESP+0],$src1\n"
10220 "\tFLD_D [ESP+0]\n"
10221 "\tMOVSD [ESP+0],$src0\n"
10222 "\tFLD_D [ESP+0]\n"
10223 "loop:\tFPREM\n"
10224 "\tFWAIT\n"
10225 "\tFNSTSW AX\n"
10226 "\tSAHF\n"
10227 "\tJP loop\n"
10228 "\tFSTP_D [ESP+0]\n"
10229 "\tMOVSD $dst,[ESP+0]\n"
10230 "\tADD ESP,8\n"
10231 "\tFSTP ST0\t # Restore FPU Stack"
10232 %}
10233 ins_cost(250);
10234 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU);
10235 ins_pipe( pipe_slow );
10236 %}
10237
10238 instruct sinD_reg(regDPR1 dst, regDPR1 src) %{
10239 predicate (UseSSE<=1);
10240 match(Set dst (SinD src));
10241 ins_cost(1800);
10242 format %{ "DSIN $dst" %}
10243 opcode(0xD9, 0xFE);
10244 ins_encode( OpcP, OpcS );
10245 ins_pipe( pipe_slow );
10246 %}
10247
10248 instruct sinXD_reg(regXD dst, eFlagsReg cr) %{
10249 predicate (UseSSE>=2);
10250 match(Set dst (SinD dst));
10251 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10252 ins_cost(1800);
10253 format %{ "DSIN $dst" %}
10254 opcode(0xD9, 0xFE);
10255 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10256 ins_pipe( pipe_slow );
10257 %}
10258
10259 instruct cosD_reg(regDPR1 dst, regDPR1 src) %{
10260 predicate (UseSSE<=1);
10261 match(Set dst (CosD src));
10262 ins_cost(1800);
10263 format %{ "DCOS $dst" %}
10264 opcode(0xD9, 0xFF);
10265 ins_encode( OpcP, OpcS );
10266 ins_pipe( pipe_slow );
10267 %}
10268
10269 instruct cosXD_reg(regXD dst, eFlagsReg cr) %{
10270 predicate (UseSSE>=2);
10271 match(Set dst (CosD dst));
10272 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10273 ins_cost(1800);
10274 format %{ "DCOS $dst" %}
10275 opcode(0xD9, 0xFF);
10276 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
10277 ins_pipe( pipe_slow );
10278 %}
10279
10280 instruct tanD_reg(regDPR1 dst, regDPR1 src) %{
10281 predicate (UseSSE<=1);
10282 match(Set dst(TanD src));
10283 format %{ "DTAN $dst" %}
10284 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10285 Opcode(0xDD), Opcode(0xD8)); // fstp st
10286 ins_pipe( pipe_slow );
10287 %}
10288
10289 instruct tanXD_reg(regXD dst, eFlagsReg cr) %{
10290 predicate (UseSSE>=2);
10291 match(Set dst(TanD dst));
10292 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10293 format %{ "DTAN $dst" %}
10294 ins_encode( Push_SrcXD(dst),
10295 Opcode(0xD9), Opcode(0xF2), // fptan
10296 Opcode(0xDD), Opcode(0xD8), // fstp st
10297 Push_ResultXD(dst) );
10298 ins_pipe( pipe_slow );
10299 %}
10300
10301 instruct atanD_reg(regD dst, regD src) %{
10302 predicate (UseSSE<=1);
10303 match(Set dst(AtanD dst src));
10304 format %{ "DATA $dst,$src" %}
10305 opcode(0xD9, 0xF3);
10306 ins_encode( Push_Reg_D(src),
10307 OpcP, OpcS, RegOpc(dst) );
10308 ins_pipe( pipe_slow );
10309 %}
10310
10311 instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10312 predicate (UseSSE>=2);
10313 match(Set dst(AtanD dst src));
10314 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8"
10315 format %{ "DATA $dst,$src" %}
10316 opcode(0xD9, 0xF3);
10317 ins_encode( Push_SrcXD(src),
10318 OpcP, OpcS, Push_ResultXD(dst) );
10319 ins_pipe( pipe_slow );
10320 %}
10321
10322 instruct sqrtD_reg(regD dst, regD src) %{
10323 predicate (UseSSE<=1);
10324 match(Set dst (SqrtD src));
10325 format %{ "DSQRT $dst,$src" %}
10326 opcode(0xFA, 0xD9);
10327 ins_encode( Push_Reg_D(src),
10328 OpcS, OpcP, Pop_Reg_D(dst) );
10329 ins_pipe( pipe_slow );
10330 %}
10331
10332 instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10333 predicate (UseSSE<=1);
10334 match(Set Y (PowD X Y)); // Raise X to the Yth power
10335 effect(KILL rax, KILL rbx, KILL rcx);
10336 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10337 "FLD_D $X\n\t"
10338 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10339
10340 "FDUP \t\t\t# Q Q\n\t"
10341 "FRNDINT\t\t\t# int(Q) Q\n\t"
10342 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10343 "FISTP dword [ESP]\n\t"
10344 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10345 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10346 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10347 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10348 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10349 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10350 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10351 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10352 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10353 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10354 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10355 "MOV [ESP+0],0\n\t"
10356 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10357
10358 "ADD ESP,8"
10359 %}
10360 ins_encode( push_stack_temp_qword,
10361 Push_Reg_D(X),
10362 Opcode(0xD9), Opcode(0xF1), // fyl2x
10363 pow_exp_core_encoding,
10364 pop_stack_temp_qword);
10365 ins_pipe( pipe_slow );
10366 %}
10367
10368 instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{
10369 predicate (UseSSE>=2);
10370 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10371 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx );
10372 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t"
10373 "MOVSD [ESP],$src1\n\t"
10374 "FLD FPR1,$src1\n\t"
10375 "MOVSD [ESP],$src0\n\t"
10376 "FLD FPR1,$src0\n\t"
10377 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t"
10378
10379 "FDUP \t\t\t# Q Q\n\t"
10380 "FRNDINT\t\t\t# int(Q) Q\n\t"
10381 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10382 "FISTP dword [ESP]\n\t"
10383 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10384 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10385 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10386 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10387 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10388 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10389 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10390 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10391 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10392 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10393 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10394 "MOV [ESP+0],0\n\t"
10395 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10396
10397 "FST_D [ESP]\n\t"
10398 "MOVSD $dst,[ESP]\n\t"
10399 "ADD ESP,8"
10400 %}
10401 ins_encode( push_stack_temp_qword,
10402 push_xmm_to_fpr1(src1),
10403 push_xmm_to_fpr1(src0),
10404 Opcode(0xD9), Opcode(0xF1), // fyl2x
10405 pow_exp_core_encoding,
10406 Push_ResultXD(dst) );
10407 ins_pipe( pipe_slow );
10408 %}
10409
10410
10411 instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10412 predicate (UseSSE<=1);
10413 match(Set dpr1 (ExpD dpr1));
10414 effect(KILL rax, KILL rbx, KILL rcx);
10415 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding"
10416 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10417 "FMULP \t\t\t# Q=X*log2(e)\n\t"
10418
10419 "FDUP \t\t\t# Q Q\n\t"
10420 "FRNDINT\t\t\t# int(Q) Q\n\t"
10421 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10422 "FISTP dword [ESP]\n\t"
10423 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10424 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10425 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10426 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10427 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10428 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10429 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10430 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10431 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10432 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10433 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10434 "MOV [ESP+0],0\n\t"
10435 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10436
10437 "ADD ESP,8"
10438 %}
10439 ins_encode( push_stack_temp_qword,
10440 Opcode(0xD9), Opcode(0xEA), // fldl2e
10441 Opcode(0xDE), Opcode(0xC9), // fmulp
10442 pow_exp_core_encoding,
10443 pop_stack_temp_qword);
10444 ins_pipe( pipe_slow );
10445 %}
10446
10447 instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{
10448 predicate (UseSSE>=2);
10449 match(Set dst (ExpD src));
10450 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx);
10451 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t"
10452 "MOVSD [ESP],$src\n\t"
10453 "FLDL2E \t\t\t# Ld log2(e) X\n\t"
10454 "FMULP \t\t\t# Q=X*log2(e) X\n\t"
10455
10456 "FDUP \t\t\t# Q Q\n\t"
10457 "FRNDINT\t\t\t# int(Q) Q\n\t"
10458 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t"
10459 "FISTP dword [ESP]\n\t"
10460 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t"
10461 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t"
10462 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead
10463 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t"
10464 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t"
10465 "ADD EAX,1023\t\t# Double exponent bias\n\t"
10466 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t"
10467 "SHL EAX,20\t\t# Shift exponent into place\n\t"
10468 "TEST EBX,ECX\t\t# Check for overflow\n\t"
10469 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t"
10470 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t"
10471 "MOV [ESP+0],0\n\t"
10472 "FMUL ST(0),[ESP+0]\t# Scale\n\t"
10473
10474 "FST_D [ESP]\n\t"
10475 "MOVSD $dst,[ESP]\n\t"
10476 "ADD ESP,8"
10477 %}
10478 ins_encode( Push_SrcXD(src),
10479 Opcode(0xD9), Opcode(0xEA), // fldl2e
10480 Opcode(0xDE), Opcode(0xC9), // fmulp
10481 pow_exp_core_encoding,
10482 Push_ResultXD(dst) );
10483 ins_pipe( pipe_slow );
10484 %}
10485
10486
10487
10488 instruct log10D_reg(regDPR1 dst, regDPR1 src) %{
10489 predicate (UseSSE<=1);
10490 // The source Double operand on FPU stack
10491 match(Set dst (Log10D src));
10492 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10493 // fxch ; swap ST(0) with ST(1)
10494 // fyl2x ; compute log_10(2) * log_2(x)
10495 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10496 "FXCH \n\t"
10497 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10498 %}
10499 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10500 Opcode(0xD9), Opcode(0xC9), // fxch
10501 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10502
10503 ins_pipe( pipe_slow );
10504 %}
10505
10506 instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10507 predicate (UseSSE>=2);
10508 effect(KILL cr);
10509 match(Set dst (Log10D src));
10510 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10511 // fyl2x ; compute log_10(2) * log_2(x)
10512 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10513 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10514 %}
10515 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10516 Push_SrcXD(src),
10517 Opcode(0xD9), Opcode(0xF1), // fyl2x
10518 Push_ResultXD(dst));
10519
10520 ins_pipe( pipe_slow );
10521 %}
10522
10523 instruct logD_reg(regDPR1 dst, regDPR1 src) %{
10524 predicate (UseSSE<=1);
10525 // The source Double operand on FPU stack
10526 match(Set dst (LogD src));
10527 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10528 // fxch ; swap ST(0) with ST(1)
10529 // fyl2x ; compute log_e(2) * log_2(x)
10530 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10531 "FXCH \n\t"
10532 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10533 %}
10534 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10535 Opcode(0xD9), Opcode(0xC9), // fxch
10536 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10537
10538 ins_pipe( pipe_slow );
10539 %}
10540
10541 instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{
10542 predicate (UseSSE>=2);
10543 effect(KILL cr);
10544 // The source and result Double operands in XMM registers
10545 match(Set dst (LogD src));
10546 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10547 // fyl2x ; compute log_e(2) * log_2(x)
10548 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10549 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10550 %}
10551 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10552 Push_SrcXD(src),
10553 Opcode(0xD9), Opcode(0xF1), // fyl2x
10554 Push_ResultXD(dst));
10555 ins_pipe( pipe_slow );
10556 %}
10557
10558 //-------------Float Instructions-------------------------------
10559 // Float Math
10560
10561 // Code for float compare:
10562 // fcompp();
10563 // fwait(); fnstsw_ax();
10564 // sahf();
10565 // movl(dst, unordered_result);
10566 // jcc(Assembler::parity, exit);
10567 // movl(dst, less_result);
10568 // jcc(Assembler::below, exit);
10569 // movl(dst, equal_result);
10570 // jcc(Assembler::equal, exit);
10571 // movl(dst, greater_result);
10572 // exit:
10573
10574 // P6 version of float compare, sets condition codes in EFLAGS
10575 instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10576 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10577 match(Set cr (CmpF src1 src2));
10578 effect(KILL rax);
10579 ins_cost(150);
10580 format %{ "FLD $src1\n\t"
10581 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10582 "JNP exit\n\t"
10583 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10584 "SAHF\n"
10585 "exit:\tNOP // avoid branch to branch" %}
10586 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10587 ins_encode( Push_Reg_D(src1),
10588 OpcP, RegOpc(src2),
10589 cmpF_P6_fixup );
10590 ins_pipe( pipe_slow );
10591 %}
10592
10593 instruct cmpF_cc_P6CF(eFlagsRegUCF cr, regF src1, regF src2) %{
10594 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10595 match(Set cr (CmpF src1 src2));
10596 ins_cost(100);
10597 format %{ "FLD $src1\n\t"
10598 "FUCOMIP ST,$src2 // P6 instruction" %}
10599 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10600 ins_encode( Push_Reg_D(src1),
10601 OpcP, RegOpc(src2));
10602 ins_pipe( pipe_slow );
10603 %}
10604
10605
10606 // Compare & branch
10607 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{
10608 predicate(UseSSE == 0);
10609 match(Set cr (CmpF src1 src2));
10610 effect(KILL rax);
10611 ins_cost(200);
10612 format %{ "FLD $src1\n\t"
10613 "FCOMp $src2\n\t"
10614 "FNSTSW AX\n\t"
10615 "TEST AX,0x400\n\t"
10616 "JZ,s flags\n\t"
10617 "MOV AH,1\t# unordered treat as LT\n"
10618 "flags:\tSAHF" %}
10619 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10620 ins_encode( Push_Reg_D(src1),
10621 OpcP, RegOpc(src2),
10622 fpu_flags);
10623 ins_pipe( pipe_slow );
10624 %}
10625
10626 // Compare vs zero into -1,0,1
10627 instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{
10628 predicate(UseSSE == 0);
10629 match(Set dst (CmpF3 src1 zero));
10630 effect(KILL cr, KILL rax);
10631 ins_cost(280);
10632 format %{ "FTSTF $dst,$src1" %}
10633 opcode(0xE4, 0xD9);
10634 ins_encode( Push_Reg_D(src1),
10635 OpcS, OpcP, PopFPU,
10636 CmpF_Result(dst));
10637 ins_pipe( pipe_slow );
10638 %}
10639
10640 // Compare into -1,0,1
10641 instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
10642 predicate(UseSSE == 0);
10643 match(Set dst (CmpF3 src1 src2));
10644 effect(KILL cr, KILL rax);
10645 ins_cost(300);
10646 format %{ "FCMPF $dst,$src1,$src2" %}
10647 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10648 ins_encode( Push_Reg_D(src1),
10649 OpcP, RegOpc(src2),
10650 CmpF_Result(dst));
10651 ins_pipe( pipe_slow );
10652 %}
10653
10654 // float compare and set condition codes in EFLAGS by XMM regs
10655 instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{
10656 predicate(UseSSE>=1);
10657 match(Set cr (CmpF dst src));
10658 effect(KILL rax);
10659 ins_cost(145);
10660 format %{ "COMISS $dst,$src\n"
10661 "\tJNP exit\n"
10662 "\tMOV ah,1 // saw a NaN, set CF\n"
10663 "\tSAHF\n"
10664 "exit:\tNOP // avoid branch to branch" %}
10665 opcode(0x0F, 0x2F);
10666 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup);
10667 ins_pipe( pipe_slow );
10668 %}
10669
10670 instruct cmpX_ccCF(eFlagsRegUCF cr, regX dst, regX src) %{
10671 predicate(UseSSE>=1);
10672 match(Set cr (CmpF dst src));
10673 ins_cost(100);
10674 format %{ "COMISS $dst,$src" %}
10675 opcode(0x0F, 0x2F);
10676 ins_encode(OpcP, OpcS, RegReg(dst, src));
10677 ins_pipe( pipe_slow );
10678 %}
10679
10680 // float compare and set condition codes in EFLAGS by XMM regs
10681 instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{
10682 predicate(UseSSE>=1);
10683 match(Set cr (CmpF dst (LoadF src)));
10684 effect(KILL rax);
10685 ins_cost(165);
10686 format %{ "COMISS $dst,$src\n"
10687 "\tJNP exit\n"
10688 "\tMOV ah,1 // saw a NaN, set CF\n"
10689 "\tSAHF\n"
10690 "exit:\tNOP // avoid branch to branch" %}
10691 opcode(0x0F, 0x2F);
10692 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup);
10693 ins_pipe( pipe_slow );
10694 %}
10695
10696 instruct cmpX_ccmemCF(eFlagsRegUCF cr, regX dst, memory src) %{
10697 predicate(UseSSE>=1);
10698 match(Set cr (CmpF dst (LoadF src)));
10699 ins_cost(100);
10700 format %{ "COMISS $dst,$src" %}
10701 opcode(0x0F, 0x2F);
10702 ins_encode(OpcP, OpcS, RegMem(dst, src));
10703 ins_pipe( pipe_slow );
10704 %}
10705
10706 // Compare into -1,0,1 in XMM
10707 instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{
10708 predicate(UseSSE>=1);
10709 match(Set dst (CmpF3 src1 src2));
10710 effect(KILL cr);
10711 ins_cost(255);
10712 format %{ "XOR $dst,$dst\n"
10713 "\tCOMISS $src1,$src2\n"
10714 "\tJP,s nan\n"
10715 "\tJEQ,s exit\n"
10716 "\tJA,s inc\n"
10717 "nan:\tDEC $dst\n"
10718 "\tJMP,s exit\n"
10719 "inc:\tINC $dst\n"
10720 "exit:"
10721 %}
10722 opcode(0x0F, 0x2F);
10723 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst));
10724 ins_pipe( pipe_slow );
10725 %}
10726
10727 // Compare into -1,0,1 in XMM and memory
10728 instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{
10729 predicate(UseSSE>=1);
10730 match(Set dst (CmpF3 src1 (LoadF mem)));
10731 effect(KILL cr);
10732 ins_cost(275);
10733 format %{ "COMISS $src1,$mem\n"
10734 "\tMOV $dst,0\t\t# do not blow flags\n"
10735 "\tJP,s nan\n"
10736 "\tJEQ,s exit\n"
10737 "\tJA,s inc\n"
10738 "nan:\tDEC $dst\n"
10739 "\tJMP,s exit\n"
10740 "inc:\tINC $dst\n"
10741 "exit:"
10742 %}
10743 opcode(0x0F, 0x2F);
10744 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst));
10745 ins_pipe( pipe_slow );
10746 %}
10747
10748 // Spill to obtain 24-bit precision
10749 instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{
10750 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10751 match(Set dst (SubF src1 src2));
10752
10753 format %{ "FSUB $dst,$src1 - $src2" %}
10754 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10755 ins_encode( Push_Reg_F(src1),
10756 OpcReg_F(src2),
10757 Pop_Mem_F(dst) );
10758 ins_pipe( fpu_mem_reg_reg );
10759 %}
10760 //
10761 // This instruction does not round to 24-bits
10762 instruct subF_reg(regF dst, regF src) %{
10763 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10764 match(Set dst (SubF dst src));
10765
10766 format %{ "FSUB $dst,$src" %}
10767 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10768 ins_encode( Push_Reg_F(src),
10769 OpcP, RegOpc(dst) );
10770 ins_pipe( fpu_reg_reg );
10771 %}
10772
10773 // Spill to obtain 24-bit precision
10774 instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{
10775 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10776 match(Set dst (AddF src1 src2));
10777
10778 format %{ "FADD $dst,$src1,$src2" %}
10779 opcode(0xD8, 0x0); /* D8 C0+i */
10780 ins_encode( Push_Reg_F(src2),
10781 OpcReg_F(src1),
10782 Pop_Mem_F(dst) );
10783 ins_pipe( fpu_mem_reg_reg );
10784 %}
10785 //
10786 // This instruction does not round to 24-bits
10787 instruct addF_reg(regF dst, regF src) %{
10788 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10789 match(Set dst (AddF dst src));
10790
10791 format %{ "FLD $src\n\t"
10792 "FADDp $dst,ST" %}
10793 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10794 ins_encode( Push_Reg_F(src),
10795 OpcP, RegOpc(dst) );
10796 ins_pipe( fpu_reg_reg );
10797 %}
10798
10799 // Add two single precision floating point values in xmm
10800 instruct addX_reg(regX dst, regX src) %{
10801 predicate(UseSSE>=1);
10802 match(Set dst (AddF dst src));
10803 format %{ "ADDSS $dst,$src" %}
10804 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src));
10805 ins_pipe( pipe_slow );
10806 %}
10807
10808 instruct addX_imm(regX dst, immXF con) %{
10809 predicate(UseSSE>=1);
10810 match(Set dst (AddF dst con));
10811 format %{ "ADDSS $dst,[$con]" %}
10812 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) );
10813 ins_pipe( pipe_slow );
10814 %}
10815
10816 instruct addX_mem(regX dst, memory mem) %{
10817 predicate(UseSSE>=1);
10818 match(Set dst (AddF dst (LoadF mem)));
10819 format %{ "ADDSS $dst,$mem" %}
10820 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem));
10821 ins_pipe( pipe_slow );
10822 %}
10823
10824 // Subtract two single precision floating point values in xmm
10825 instruct subX_reg(regX dst, regX src) %{
10826 predicate(UseSSE>=1);
10827 match(Set dst (SubF dst src));
10828 format %{ "SUBSS $dst,$src" %}
10829 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src));
10830 ins_pipe( pipe_slow );
10831 %}
10832
10833 instruct subX_imm(regX dst, immXF con) %{
10834 predicate(UseSSE>=1);
10835 match(Set dst (SubF dst con));
10836 format %{ "SUBSS $dst,[$con]" %}
10837 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) );
10838 ins_pipe( pipe_slow );
10839 %}
10840
10841 instruct subX_mem(regX dst, memory mem) %{
10842 predicate(UseSSE>=1);
10843 match(Set dst (SubF dst (LoadF mem)));
10844 format %{ "SUBSS $dst,$mem" %}
10845 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem));
10846 ins_pipe( pipe_slow );
10847 %}
10848
10849 // Multiply two single precision floating point values in xmm
10850 instruct mulX_reg(regX dst, regX src) %{
10851 predicate(UseSSE>=1);
10852 match(Set dst (MulF dst src));
10853 format %{ "MULSS $dst,$src" %}
10854 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src));
10855 ins_pipe( pipe_slow );
10856 %}
10857
10858 instruct mulX_imm(regX dst, immXF con) %{
10859 predicate(UseSSE>=1);
10860 match(Set dst (MulF dst con));
10861 format %{ "MULSS $dst,[$con]" %}
10862 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) );
10863 ins_pipe( pipe_slow );
10864 %}
10865
10866 instruct mulX_mem(regX dst, memory mem) %{
10867 predicate(UseSSE>=1);
10868 match(Set dst (MulF dst (LoadF mem)));
10869 format %{ "MULSS $dst,$mem" %}
10870 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem));
10871 ins_pipe( pipe_slow );
10872 %}
10873
10874 // Divide two single precision floating point values in xmm
10875 instruct divX_reg(regX dst, regX src) %{
10876 predicate(UseSSE>=1);
10877 match(Set dst (DivF dst src));
10878 format %{ "DIVSS $dst,$src" %}
10879 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src));
10880 ins_pipe( pipe_slow );
10881 %}
10882
10883 instruct divX_imm(regX dst, immXF con) %{
10884 predicate(UseSSE>=1);
10885 match(Set dst (DivF dst con));
10886 format %{ "DIVSS $dst,[$con]" %}
10887 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) );
10888 ins_pipe( pipe_slow );
10889 %}
10890
10891 instruct divX_mem(regX dst, memory mem) %{
10892 predicate(UseSSE>=1);
10893 match(Set dst (DivF dst (LoadF mem)));
10894 format %{ "DIVSS $dst,$mem" %}
10895 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem));
10896 ins_pipe( pipe_slow );
10897 %}
10898
10899 // Get the square root of a single precision floating point values in xmm
10900 instruct sqrtX_reg(regX dst, regX src) %{
10901 predicate(UseSSE>=1);
10902 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10903 format %{ "SQRTSS $dst,$src" %}
10904 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10905 ins_pipe( pipe_slow );
10906 %}
10907
10908 instruct sqrtX_mem(regX dst, memory mem) %{
10909 predicate(UseSSE>=1);
10910 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem)))));
10911 format %{ "SQRTSS $dst,$mem" %}
10912 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10913 ins_pipe( pipe_slow );
10914 %}
10915
10916 // Get the square root of a double precision floating point values in xmm
10917 instruct sqrtXD_reg(regXD dst, regXD src) %{
10918 predicate(UseSSE>=2);
10919 match(Set dst (SqrtD src));
10920 format %{ "SQRTSD $dst,$src" %}
10921 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src));
10922 ins_pipe( pipe_slow );
10923 %}
10924
10925 instruct sqrtXD_mem(regXD dst, memory mem) %{
10926 predicate(UseSSE>=2);
10927 match(Set dst (SqrtD (LoadD mem)));
10928 format %{ "SQRTSD $dst,$mem" %}
10929 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem));
10930 ins_pipe( pipe_slow );
10931 %}
10932
10933 instruct absF_reg(regFPR1 dst, regFPR1 src) %{
10934 predicate(UseSSE==0);
10935 match(Set dst (AbsF src));
10936 ins_cost(100);
10937 format %{ "FABS" %}
10938 opcode(0xE1, 0xD9);
10939 ins_encode( OpcS, OpcP );
10940 ins_pipe( fpu_reg_reg );
10941 %}
10942
10943 instruct absX_reg(regX dst ) %{
10944 predicate(UseSSE>=1);
10945 match(Set dst (AbsF dst));
10946 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %}
10947 ins_encode( AbsXF_encoding(dst));
10948 ins_pipe( pipe_slow );
10949 %}
10950
10951 instruct negF_reg(regFPR1 dst, regFPR1 src) %{
10952 predicate(UseSSE==0);
10953 match(Set dst (NegF src));
10954 ins_cost(100);
10955 format %{ "FCHS" %}
10956 opcode(0xE0, 0xD9);
10957 ins_encode( OpcS, OpcP );
10958 ins_pipe( fpu_reg_reg );
10959 %}
10960
10961 instruct negX_reg( regX dst ) %{
10962 predicate(UseSSE>=1);
10963 match(Set dst (NegF dst));
10964 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %}
10965 ins_encode( NegXF_encoding(dst));
10966 ins_pipe( pipe_slow );
10967 %}
10968
10969 // Cisc-alternate to addF_reg
10970 // Spill to obtain 24-bit precision
10971 instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
10972 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10973 match(Set dst (AddF src1 (LoadF src2)));
10974
10975 format %{ "FLD $src2\n\t"
10976 "FADD ST,$src1\n\t"
10977 "FSTP_S $dst" %}
10978 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10979 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10980 OpcReg_F(src1),
10981 Pop_Mem_F(dst) );
10982 ins_pipe( fpu_mem_reg_mem );
10983 %}
10984 //
10985 // Cisc-alternate to addF_reg
10986 // This instruction does not round to 24-bits
10987 instruct addF_reg_mem(regF dst, memory src) %{
10988 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10989 match(Set dst (AddF dst (LoadF src)));
10990
10991 format %{ "FADD $dst,$src" %}
10992 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10993 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10994 OpcP, RegOpc(dst) );
10995 ins_pipe( fpu_reg_mem );
10996 %}
10997
10998 // // Following two instructions for _222_mpegaudio
10999 // Spill to obtain 24-bit precision
11000 instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{
11001 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11002 match(Set dst (AddF src1 src2));
11003
11004 format %{ "FADD $dst,$src1,$src2" %}
11005 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11006 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
11007 OpcReg_F(src2),
11008 Pop_Mem_F(dst) );
11009 ins_pipe( fpu_mem_reg_mem );
11010 %}
11011
11012 // Cisc-spill variant
11013 // Spill to obtain 24-bit precision
11014 instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
11015 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11016 match(Set dst (AddF src1 (LoadF src2)));
11017
11018 format %{ "FADD $dst,$src1,$src2 cisc" %}
11019 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
11020 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11021 set_instruction_start,
11022 OpcP, RMopc_Mem(secondary,src1),
11023 Pop_Mem_F(dst) );
11024 ins_pipe( fpu_mem_mem_mem );
11025 %}
11026
11027 // Spill to obtain 24-bit precision
11028 instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11029 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11030 match(Set dst (AddF src1 src2));
11031
11032 format %{ "FADD $dst,$src1,$src2" %}
11033 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
11034 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11035 set_instruction_start,
11036 OpcP, RMopc_Mem(secondary,src1),
11037 Pop_Mem_F(dst) );
11038 ins_pipe( fpu_mem_mem_mem );
11039 %}
11040
11041
11042 // Spill to obtain 24-bit precision
11043 instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11044 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11045 match(Set dst (AddF src1 src2));
11046 format %{ "FLD $src1\n\t"
11047 "FADD $src2\n\t"
11048 "FSTP_S $dst" %}
11049 opcode(0xD8, 0x00); /* D8 /0 */
11050 ins_encode( Push_Reg_F(src1),
11051 Opc_MemImm_F(src2),
11052 Pop_Mem_F(dst));
11053 ins_pipe( fpu_mem_reg_con );
11054 %}
11055 //
11056 // This instruction does not round to 24-bits
11057 instruct addF_reg_imm(regF dst, regF src1, immF src2) %{
11058 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11059 match(Set dst (AddF src1 src2));
11060 format %{ "FLD $src1\n\t"
11061 "FADD $src2\n\t"
11062 "FSTP_S $dst" %}
11063 opcode(0xD8, 0x00); /* D8 /0 */
11064 ins_encode( Push_Reg_F(src1),
11065 Opc_MemImm_F(src2),
11066 Pop_Reg_F(dst));
11067 ins_pipe( fpu_reg_reg_con );
11068 %}
11069
11070 // Spill to obtain 24-bit precision
11071 instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{
11072 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11073 match(Set dst (MulF src1 src2));
11074
11075 format %{ "FLD $src1\n\t"
11076 "FMUL $src2\n\t"
11077 "FSTP_S $dst" %}
11078 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
11079 ins_encode( Push_Reg_F(src1),
11080 OpcReg_F(src2),
11081 Pop_Mem_F(dst) );
11082 ins_pipe( fpu_mem_reg_reg );
11083 %}
11084 //
11085 // This instruction does not round to 24-bits
11086 instruct mulF_reg(regF dst, regF src1, regF src2) %{
11087 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11088 match(Set dst (MulF src1 src2));
11089
11090 format %{ "FLD $src1\n\t"
11091 "FMUL $src2\n\t"
11092 "FSTP_S $dst" %}
11093 opcode(0xD8, 0x1); /* D8 C8+i */
11094 ins_encode( Push_Reg_F(src2),
11095 OpcReg_F(src1),
11096 Pop_Reg_F(dst) );
11097 ins_pipe( fpu_reg_reg_reg );
11098 %}
11099
11100
11101 // Spill to obtain 24-bit precision
11102 // Cisc-alternate to reg-reg multiply
11103 instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{
11104 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11105 match(Set dst (MulF src1 (LoadF src2)));
11106
11107 format %{ "FLD_S $src2\n\t"
11108 "FMUL $src1\n\t"
11109 "FSTP_S $dst" %}
11110 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
11111 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11112 OpcReg_F(src1),
11113 Pop_Mem_F(dst) );
11114 ins_pipe( fpu_mem_reg_mem );
11115 %}
11116 //
11117 // This instruction does not round to 24-bits
11118 // Cisc-alternate to reg-reg multiply
11119 instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{
11120 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11121 match(Set dst (MulF src1 (LoadF src2)));
11122
11123 format %{ "FMUL $dst,$src1,$src2" %}
11124 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
11125 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11126 OpcReg_F(src1),
11127 Pop_Reg_F(dst) );
11128 ins_pipe( fpu_reg_reg_mem );
11129 %}
11130
11131 // Spill to obtain 24-bit precision
11132 instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
11133 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11134 match(Set dst (MulF src1 src2));
11135
11136 format %{ "FMUL $dst,$src1,$src2" %}
11137 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
11138 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
11139 set_instruction_start,
11140 OpcP, RMopc_Mem(secondary,src1),
11141 Pop_Mem_F(dst) );
11142 ins_pipe( fpu_mem_mem_mem );
11143 %}
11144
11145 // Spill to obtain 24-bit precision
11146 instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{
11147 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11148 match(Set dst (MulF src1 src2));
11149
11150 format %{ "FMULc $dst,$src1,$src2" %}
11151 opcode(0xD8, 0x1); /* D8 /1*/
11152 ins_encode( Push_Reg_F(src1),
11153 Opc_MemImm_F(src2),
11154 Pop_Mem_F(dst));
11155 ins_pipe( fpu_mem_reg_con );
11156 %}
11157 //
11158 // This instruction does not round to 24-bits
11159 instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{
11160 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11161 match(Set dst (MulF src1 src2));
11162
11163 format %{ "FMULc $dst. $src1, $src2" %}
11164 opcode(0xD8, 0x1); /* D8 /1*/
11165 ins_encode( Push_Reg_F(src1),
11166 Opc_MemImm_F(src2),
11167 Pop_Reg_F(dst));
11168 ins_pipe( fpu_reg_reg_con );
11169 %}
11170
11171
11172 //
11173 // MACRO1 -- subsume unshared load into mulF
11174 // This instruction does not round to 24-bits
11175 instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{
11176 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11177 match(Set dst (MulF (LoadF mem1) src));
11178
11179 format %{ "FLD $mem1 ===MACRO1===\n\t"
11180 "FMUL ST,$src\n\t"
11181 "FSTP $dst" %}
11182 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
11183 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
11184 OpcReg_F(src),
11185 Pop_Reg_F(dst) );
11186 ins_pipe( fpu_reg_reg_mem );
11187 %}
11188 //
11189 // MACRO2 -- addF a mulF which subsumed an unshared load
11190 // This instruction does not round to 24-bits
11191 instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{
11192 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11193 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
11194 ins_cost(95);
11195
11196 format %{ "FLD $mem1 ===MACRO2===\n\t"
11197 "FMUL ST,$src1 subsume mulF left load\n\t"
11198 "FADD ST,$src2\n\t"
11199 "FSTP $dst" %}
11200 opcode(0xD9); /* LoadF D9 /0 */
11201 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
11202 FMul_ST_reg(src1),
11203 FAdd_ST_reg(src2),
11204 Pop_Reg_F(dst) );
11205 ins_pipe( fpu_reg_mem_reg_reg );
11206 %}
11207
11208 // MACRO3 -- addF a mulF
11209 // This instruction does not round to 24-bits. It is a '2-address'
11210 // instruction in that the result goes back to src2. This eliminates
11211 // a move from the macro; possibly the register allocator will have
11212 // to add it back (and maybe not).
11213 instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{
11214 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11215 match(Set src2 (AddF (MulF src0 src1) src2));
11216
11217 format %{ "FLD $src0 ===MACRO3===\n\t"
11218 "FMUL ST,$src1\n\t"
11219 "FADDP $src2,ST" %}
11220 opcode(0xD9); /* LoadF D9 /0 */
11221 ins_encode( Push_Reg_F(src0),
11222 FMul_ST_reg(src1),
11223 FAddP_reg_ST(src2) );
11224 ins_pipe( fpu_reg_reg_reg );
11225 %}
11226
11227 // MACRO4 -- divF subF
11228 // This instruction does not round to 24-bits
11229 instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{
11230 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11231 match(Set dst (DivF (SubF src2 src1) src3));
11232
11233 format %{ "FLD $src2 ===MACRO4===\n\t"
11234 "FSUB ST,$src1\n\t"
11235 "FDIV ST,$src3\n\t"
11236 "FSTP $dst" %}
11237 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11238 ins_encode( Push_Reg_F(src2),
11239 subF_divF_encode(src1,src3),
11240 Pop_Reg_F(dst) );
11241 ins_pipe( fpu_reg_reg_reg_reg );
11242 %}
11243
11244 // Spill to obtain 24-bit precision
11245 instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{
11246 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
11247 match(Set dst (DivF src1 src2));
11248
11249 format %{ "FDIV $dst,$src1,$src2" %}
11250 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
11251 ins_encode( Push_Reg_F(src1),
11252 OpcReg_F(src2),
11253 Pop_Mem_F(dst) );
11254 ins_pipe( fpu_mem_reg_reg );
11255 %}
11256 //
11257 // This instruction does not round to 24-bits
11258 instruct divF_reg(regF dst, regF src) %{
11259 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
11260 match(Set dst (DivF dst src));
11261
11262 format %{ "FDIV $dst,$src" %}
11263 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
11264 ins_encode( Push_Reg_F(src),
11265 OpcP, RegOpc(dst) );
11266 ins_pipe( fpu_reg_reg );
11267 %}
11268
11269
11270 // Spill to obtain 24-bit precision
11271 instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{
11272 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11273 match(Set dst (ModF src1 src2));
11274 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11275
11276 format %{ "FMOD $dst,$src1,$src2" %}
11277 ins_encode( Push_Reg_Mod_D(src1, src2),
11278 emitModD(),
11279 Push_Result_Mod_D(src2),
11280 Pop_Mem_F(dst));
11281 ins_pipe( pipe_slow );
11282 %}
11283 //
11284 // This instruction does not round to 24-bits
11285 instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{
11286 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11287 match(Set dst (ModF dst src));
11288 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS
11289
11290 format %{ "FMOD $dst,$src" %}
11291 ins_encode(Push_Reg_Mod_D(dst, src),
11292 emitModD(),
11293 Push_Result_Mod_D(src),
11294 Pop_Reg_F(dst));
11295 ins_pipe( pipe_slow );
11296 %}
11297
11298 instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{
11299 predicate(UseSSE>=1);
11300 match(Set dst (ModF src0 src1));
11301 effect(KILL rax, KILL cr);
11302 format %{ "SUB ESP,4\t # FMOD\n"
11303 "\tMOVSS [ESP+0],$src1\n"
11304 "\tFLD_S [ESP+0]\n"
11305 "\tMOVSS [ESP+0],$src0\n"
11306 "\tFLD_S [ESP+0]\n"
11307 "loop:\tFPREM\n"
11308 "\tFWAIT\n"
11309 "\tFNSTSW AX\n"
11310 "\tSAHF\n"
11311 "\tJP loop\n"
11312 "\tFSTP_S [ESP+0]\n"
11313 "\tMOVSS $dst,[ESP+0]\n"
11314 "\tADD ESP,4\n"
11315 "\tFSTP ST0\t # Restore FPU Stack"
11316 %}
11317 ins_cost(250);
11318 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU);
11319 ins_pipe( pipe_slow );
11320 %}
11321
11322
11323 //----------Arithmetic Conversion Instructions---------------------------------
11324 // The conversions operations are all Alpha sorted. Please keep it that way!
11325
11326 instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{
11327 predicate(UseSSE==0);
11328 match(Set dst (RoundFloat src));
11329 ins_cost(125);
11330 format %{ "FST_S $dst,$src\t# F-round" %}
11331 ins_encode( Pop_Mem_Reg_F(dst, src) );
11332 ins_pipe( fpu_mem_reg );
11333 %}
11334
11335 instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{
11336 predicate(UseSSE<=1);
11337 match(Set dst (RoundDouble src));
11338 ins_cost(125);
11339 format %{ "FST_D $dst,$src\t# D-round" %}
11340 ins_encode( Pop_Mem_Reg_D(dst, src) );
11341 ins_pipe( fpu_mem_reg );
11342 %}
11343
11344 // Force rounding to 24-bit precision and 6-bit exponent
11345 instruct convD2F_reg(stackSlotF dst, regD src) %{
11346 predicate(UseSSE==0);
11347 match(Set dst (ConvD2F src));
11348 format %{ "FST_S $dst,$src\t# F-round" %}
11349 expand %{
11350 roundFloat_mem_reg(dst,src);
11351 %}
11352 %}
11353
11354 // Force rounding to 24-bit precision and 6-bit exponent
11355 instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{
11356 predicate(UseSSE==1);
11357 match(Set dst (ConvD2F src));
11358 effect( KILL cr );
11359 format %{ "SUB ESP,4\n\t"
11360 "FST_S [ESP],$src\t# F-round\n\t"
11361 "MOVSS $dst,[ESP]\n\t"
11362 "ADD ESP,4" %}
11363 ins_encode( D2X_encoding(dst, src) );
11364 ins_pipe( pipe_slow );
11365 %}
11366
11367 // Force rounding double precision to single precision
11368 instruct convXD2X_reg(regX dst, regXD src) %{
11369 predicate(UseSSE>=2);
11370 match(Set dst (ConvD2F src));
11371 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
11372 opcode(0xF2, 0x0F, 0x5A);
11373 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11374 ins_pipe( pipe_slow );
11375 %}
11376
11377 instruct convF2D_reg_reg(regD dst, regF src) %{
11378 predicate(UseSSE==0);
11379 match(Set dst (ConvF2D src));
11380 format %{ "FST_S $dst,$src\t# D-round" %}
11381 ins_encode( Pop_Reg_Reg_D(dst, src));
11382 ins_pipe( fpu_reg_reg );
11383 %}
11384
11385 instruct convF2D_reg(stackSlotD dst, regF src) %{
11386 predicate(UseSSE==1);
11387 match(Set dst (ConvF2D src));
11388 format %{ "FST_D $dst,$src\t# D-round" %}
11389 expand %{
11390 roundDouble_mem_reg(dst,src);
11391 %}
11392 %}
11393
11394 instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{
11395 predicate(UseSSE==1);
11396 match(Set dst (ConvF2D src));
11397 effect( KILL cr );
11398 format %{ "SUB ESP,4\n\t"
11399 "MOVSS [ESP] $src\n\t"
11400 "FLD_S [ESP]\n\t"
11401 "ADD ESP,4\n\t"
11402 "FSTP $dst\t# D-round" %}
11403 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst));
11404 ins_pipe( pipe_slow );
11405 %}
11406
11407 instruct convX2XD_reg(regXD dst, regX src) %{
11408 predicate(UseSSE>=2);
11409 match(Set dst (ConvF2D src));
11410 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
11411 opcode(0xF3, 0x0F, 0x5A);
11412 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11413 ins_pipe( pipe_slow );
11414 %}
11415
11416 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11417 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
11418 predicate(UseSSE<=1);
11419 match(Set dst (ConvD2I src));
11420 effect( KILL tmp, KILL cr );
11421 format %{ "FLD $src\t# Convert double to int \n\t"
11422 "FLDCW trunc mode\n\t"
11423 "SUB ESP,4\n\t"
11424 "FISTp [ESP + #0]\n\t"
11425 "FLDCW std/24-bit mode\n\t"
11426 "POP EAX\n\t"
11427 "CMP EAX,0x80000000\n\t"
11428 "JNE,s fast\n\t"
11429 "FLD_D $src\n\t"
11430 "CALL d2i_wrapper\n"
11431 "fast:" %}
11432 ins_encode( Push_Reg_D(src), D2I_encoding(src) );
11433 ins_pipe( pipe_slow );
11434 %}
11435
11436 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
11437 instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{
11438 predicate(UseSSE>=2);
11439 match(Set dst (ConvD2I src));
11440 effect( KILL tmp, KILL cr );
11441 format %{ "CVTTSD2SI $dst, $src\n\t"
11442 "CMP $dst,0x80000000\n\t"
11443 "JNE,s fast\n\t"
11444 "SUB ESP, 8\n\t"
11445 "MOVSD [ESP], $src\n\t"
11446 "FLD_D [ESP]\n\t"
11447 "ADD ESP, 8\n\t"
11448 "CALL d2i_wrapper\n"
11449 "fast:" %}
11450 opcode(0x1); // double-precision conversion
11451 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11452 ins_pipe( pipe_slow );
11453 %}
11454
11455 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11456 predicate(UseSSE<=1);
11457 match(Set dst (ConvD2L src));
11458 effect( KILL cr );
11459 format %{ "FLD $src\t# Convert double to long\n\t"
11460 "FLDCW trunc mode\n\t"
11461 "SUB ESP,8\n\t"
11462 "FISTp [ESP + #0]\n\t"
11463 "FLDCW std/24-bit mode\n\t"
11464 "POP EAX\n\t"
11465 "POP EDX\n\t"
11466 "CMP EDX,0x80000000\n\t"
11467 "JNE,s fast\n\t"
11468 "TEST EAX,EAX\n\t"
11469 "JNE,s fast\n\t"
11470 "FLD $src\n\t"
11471 "CALL d2l_wrapper\n"
11472 "fast:" %}
11473 ins_encode( Push_Reg_D(src), D2L_encoding(src) );
11474 ins_pipe( pipe_slow );
11475 %}
11476
11477 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11478 instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{
11479 predicate (UseSSE>=2);
11480 match(Set dst (ConvD2L src));
11481 effect( KILL cr );
11482 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11483 "MOVSD [ESP],$src\n\t"
11484 "FLD_D [ESP]\n\t"
11485 "FLDCW trunc mode\n\t"
11486 "FISTp [ESP + #0]\n\t"
11487 "FLDCW std/24-bit mode\n\t"
11488 "POP EAX\n\t"
11489 "POP EDX\n\t"
11490 "CMP EDX,0x80000000\n\t"
11491 "JNE,s fast\n\t"
11492 "TEST EAX,EAX\n\t"
11493 "JNE,s fast\n\t"
11494 "SUB ESP,8\n\t"
11495 "MOVSD [ESP],$src\n\t"
11496 "FLD_D [ESP]\n\t"
11497 "CALL d2l_wrapper\n"
11498 "fast:" %}
11499 ins_encode( XD2L_encoding(src) );
11500 ins_pipe( pipe_slow );
11501 %}
11502
11503 // Convert a double to an int. Java semantics require we do complex
11504 // manglations in the corner cases. So we set the rounding mode to
11505 // 'zero', store the darned double down as an int, and reset the
11506 // rounding mode to 'nearest'. The hardware stores a flag value down
11507 // if we would overflow or converted a NAN; we check for this and
11508 // and go the slow path if needed.
11509 instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11510 predicate(UseSSE==0);
11511 match(Set dst (ConvF2I src));
11512 effect( KILL tmp, KILL cr );
11513 format %{ "FLD $src\t# Convert float to int \n\t"
11514 "FLDCW trunc mode\n\t"
11515 "SUB ESP,4\n\t"
11516 "FISTp [ESP + #0]\n\t"
11517 "FLDCW std/24-bit mode\n\t"
11518 "POP EAX\n\t"
11519 "CMP EAX,0x80000000\n\t"
11520 "JNE,s fast\n\t"
11521 "FLD $src\n\t"
11522 "CALL d2i_wrapper\n"
11523 "fast:" %}
11524 // D2I_encoding works for F2I
11525 ins_encode( Push_Reg_F(src), D2I_encoding(src) );
11526 ins_pipe( pipe_slow );
11527 %}
11528
11529 // Convert a float in xmm to an int reg.
11530 instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{
11531 predicate(UseSSE>=1);
11532 match(Set dst (ConvF2I src));
11533 effect( KILL tmp, KILL cr );
11534 format %{ "CVTTSS2SI $dst, $src\n\t"
11535 "CMP $dst,0x80000000\n\t"
11536 "JNE,s fast\n\t"
11537 "SUB ESP, 4\n\t"
11538 "MOVSS [ESP], $src\n\t"
11539 "FLD [ESP]\n\t"
11540 "ADD ESP, 4\n\t"
11541 "CALL d2i_wrapper\n"
11542 "fast:" %}
11543 opcode(0x0); // single-precision conversion
11544 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst));
11545 ins_pipe( pipe_slow );
11546 %}
11547
11548 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11549 predicate(UseSSE==0);
11550 match(Set dst (ConvF2L src));
11551 effect( KILL cr );
11552 format %{ "FLD $src\t# Convert float to long\n\t"
11553 "FLDCW trunc mode\n\t"
11554 "SUB ESP,8\n\t"
11555 "FISTp [ESP + #0]\n\t"
11556 "FLDCW std/24-bit mode\n\t"
11557 "POP EAX\n\t"
11558 "POP EDX\n\t"
11559 "CMP EDX,0x80000000\n\t"
11560 "JNE,s fast\n\t"
11561 "TEST EAX,EAX\n\t"
11562 "JNE,s fast\n\t"
11563 "FLD $src\n\t"
11564 "CALL d2l_wrapper\n"
11565 "fast:" %}
11566 // D2L_encoding works for F2L
11567 ins_encode( Push_Reg_F(src), D2L_encoding(src) );
11568 ins_pipe( pipe_slow );
11569 %}
11570
11571 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11572 instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{
11573 predicate (UseSSE>=1);
11574 match(Set dst (ConvF2L src));
11575 effect( KILL cr );
11576 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11577 "MOVSS [ESP],$src\n\t"
11578 "FLD_S [ESP]\n\t"
11579 "FLDCW trunc mode\n\t"
11580 "FISTp [ESP + #0]\n\t"
11581 "FLDCW std/24-bit mode\n\t"
11582 "POP EAX\n\t"
11583 "POP EDX\n\t"
11584 "CMP EDX,0x80000000\n\t"
11585 "JNE,s fast\n\t"
11586 "TEST EAX,EAX\n\t"
11587 "JNE,s fast\n\t"
11588 "SUB ESP,4\t# Convert float to long\n\t"
11589 "MOVSS [ESP],$src\n\t"
11590 "FLD_S [ESP]\n\t"
11591 "ADD ESP,4\n\t"
11592 "CALL d2l_wrapper\n"
11593 "fast:" %}
11594 ins_encode( X2L_encoding(src) );
11595 ins_pipe( pipe_slow );
11596 %}
11597
11598 instruct convI2D_reg(regD dst, stackSlotI src) %{
11599 predicate( UseSSE<=1 );
11600 match(Set dst (ConvI2D src));
11601 format %{ "FILD $src\n\t"
11602 "FSTP $dst" %}
11603 opcode(0xDB, 0x0); /* DB /0 */
11604 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst));
11605 ins_pipe( fpu_reg_mem );
11606 %}
11607
11608 instruct convI2XD_reg(regXD dst, eRegI src) %{
11609 predicate( UseSSE>=2 && !UseXmmI2D );
11610 match(Set dst (ConvI2D src));
11611 format %{ "CVTSI2SD $dst,$src" %}
11612 opcode(0xF2, 0x0F, 0x2A);
11613 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11614 ins_pipe( pipe_slow );
11615 %}
11616
11617 instruct convI2XD_mem(regXD dst, memory mem) %{
11618 predicate( UseSSE>=2 );
11619 match(Set dst (ConvI2D (LoadI mem)));
11620 format %{ "CVTSI2SD $dst,$mem" %}
11621 opcode(0xF2, 0x0F, 0x2A);
11622 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem));
11623 ins_pipe( pipe_slow );
11624 %}
11625
11626 instruct convXI2XD_reg(regXD dst, eRegI src)
11627 %{
11628 predicate( UseSSE>=2 && UseXmmI2D );
11629 match(Set dst (ConvI2D src));
11630
11631 format %{ "MOVD $dst,$src\n\t"
11632 "CVTDQ2PD $dst,$dst\t# i2d" %}
11633 ins_encode %{
11634 __ movdl($dst$$XMMRegister, $src$$Register);
11635 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11636 %}
11637 ins_pipe(pipe_slow); // XXX
11638 %}
11639
11640 instruct convI2D_mem(regD dst, memory mem) %{
11641 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11642 match(Set dst (ConvI2D (LoadI mem)));
11643 format %{ "FILD $mem\n\t"
11644 "FSTP $dst" %}
11645 opcode(0xDB); /* DB /0 */
11646 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11647 Pop_Reg_D(dst));
11648 ins_pipe( fpu_reg_mem );
11649 %}
11650
11651 // Convert a byte to a float; no rounding step needed.
11652 instruct conv24I2F_reg(regF dst, stackSlotI src) %{
11653 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11654 match(Set dst (ConvI2F src));
11655 format %{ "FILD $src\n\t"
11656 "FSTP $dst" %}
11657
11658 opcode(0xDB, 0x0); /* DB /0 */
11659 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst));
11660 ins_pipe( fpu_reg_mem );
11661 %}
11662
11663 // In 24-bit mode, force exponent rounding by storing back out
11664 instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{
11665 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11666 match(Set dst (ConvI2F src));
11667 ins_cost(200);
11668 format %{ "FILD $src\n\t"
11669 "FSTP_S $dst" %}
11670 opcode(0xDB, 0x0); /* DB /0 */
11671 ins_encode( Push_Mem_I(src),
11672 Pop_Mem_F(dst));
11673 ins_pipe( fpu_mem_mem );
11674 %}
11675
11676 // In 24-bit mode, force exponent rounding by storing back out
11677 instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{
11678 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11679 match(Set dst (ConvI2F (LoadI mem)));
11680 ins_cost(200);
11681 format %{ "FILD $mem\n\t"
11682 "FSTP_S $dst" %}
11683 opcode(0xDB); /* DB /0 */
11684 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11685 Pop_Mem_F(dst));
11686 ins_pipe( fpu_mem_mem );
11687 %}
11688
11689 // This instruction does not round to 24-bits
11690 instruct convI2F_reg(regF dst, stackSlotI src) %{
11691 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11692 match(Set dst (ConvI2F src));
11693 format %{ "FILD $src\n\t"
11694 "FSTP $dst" %}
11695 opcode(0xDB, 0x0); /* DB /0 */
11696 ins_encode( Push_Mem_I(src),
11697 Pop_Reg_F(dst));
11698 ins_pipe( fpu_reg_mem );
11699 %}
11700
11701 // This instruction does not round to 24-bits
11702 instruct convI2F_mem(regF dst, memory mem) %{
11703 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11704 match(Set dst (ConvI2F (LoadI mem)));
11705 format %{ "FILD $mem\n\t"
11706 "FSTP $dst" %}
11707 opcode(0xDB); /* DB /0 */
11708 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11709 Pop_Reg_F(dst));
11710 ins_pipe( fpu_reg_mem );
11711 %}
11712
11713 // Convert an int to a float in xmm; no rounding step needed.
11714 instruct convI2X_reg(regX dst, eRegI src) %{
11715 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11716 match(Set dst (ConvI2F src));
11717 format %{ "CVTSI2SS $dst, $src" %}
11718
11719 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */
11720 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src));
11721 ins_pipe( pipe_slow );
11722 %}
11723
11724 instruct convXI2X_reg(regX dst, eRegI src)
11725 %{
11726 predicate( UseSSE>=2 && UseXmmI2F );
11727 match(Set dst (ConvI2F src));
11728
11729 format %{ "MOVD $dst,$src\n\t"
11730 "CVTDQ2PS $dst,$dst\t# i2f" %}
11731 ins_encode %{
11732 __ movdl($dst$$XMMRegister, $src$$Register);
11733 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11734 %}
11735 ins_pipe(pipe_slow); // XXX
11736 %}
11737
11738 instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{
11739 match(Set dst (ConvI2L src));
11740 effect(KILL cr);
11741 format %{ "MOV $dst.lo,$src\n\t"
11742 "MOV $dst.hi,$src\n\t"
11743 "SAR $dst.hi,31" %}
11744 ins_encode(convert_int_long(dst,src));
11745 ins_pipe( ialu_reg_reg_long );
11746 %}
11747
11748 // Zero-extend convert int to long
11749 instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{
11750 match(Set dst (AndL (ConvI2L src) mask) );
11751 effect( KILL flags );
11752 format %{ "MOV $dst.lo,$src\n\t"
11753 "XOR $dst.hi,$dst.hi" %}
11754 opcode(0x33); // XOR
11755 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11756 ins_pipe( ialu_reg_reg_long );
11757 %}
11758
11759 // Zero-extend long
11760 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11761 match(Set dst (AndL src mask) );
11762 effect( KILL flags );
11763 format %{ "MOV $dst.lo,$src.lo\n\t"
11764 "XOR $dst.hi,$dst.hi\n\t" %}
11765 opcode(0x33); // XOR
11766 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11767 ins_pipe( ialu_reg_reg_long );
11768 %}
11769
11770 instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11771 predicate (UseSSE<=1);
11772 match(Set dst (ConvL2D src));
11773 effect( KILL cr );
11774 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11775 "PUSH $src.lo\n\t"
11776 "FILD ST,[ESP + #0]\n\t"
11777 "ADD ESP,8\n\t"
11778 "FSTP_D $dst\t# D-round" %}
11779 opcode(0xDF, 0x5); /* DF /5 */
11780 ins_encode(convert_long_double(src), Pop_Mem_D(dst));
11781 ins_pipe( pipe_slow );
11782 %}
11783
11784 instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{
11785 predicate (UseSSE>=2);
11786 match(Set dst (ConvL2D src));
11787 effect( KILL cr );
11788 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11789 "PUSH $src.lo\n\t"
11790 "FILD_D [ESP]\n\t"
11791 "FSTP_D [ESP]\n\t"
11792 "MOVSD $dst,[ESP]\n\t"
11793 "ADD ESP,8" %}
11794 opcode(0xDF, 0x5); /* DF /5 */
11795 ins_encode(convert_long_double2(src), Push_ResultXD(dst));
11796 ins_pipe( pipe_slow );
11797 %}
11798
11799 instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{
11800 predicate (UseSSE>=1);
11801 match(Set dst (ConvL2F src));
11802 effect( KILL cr );
11803 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11804 "PUSH $src.lo\n\t"
11805 "FILD_D [ESP]\n\t"
11806 "FSTP_S [ESP]\n\t"
11807 "MOVSS $dst,[ESP]\n\t"
11808 "ADD ESP,8" %}
11809 opcode(0xDF, 0x5); /* DF /5 */
11810 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8));
11811 ins_pipe( pipe_slow );
11812 %}
11813
11814 instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11815 match(Set dst (ConvL2F src));
11816 effect( KILL cr );
11817 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11818 "PUSH $src.lo\n\t"
11819 "FILD ST,[ESP + #0]\n\t"
11820 "ADD ESP,8\n\t"
11821 "FSTP_S $dst\t# F-round" %}
11822 opcode(0xDF, 0x5); /* DF /5 */
11823 ins_encode(convert_long_double(src), Pop_Mem_F(dst));
11824 ins_pipe( pipe_slow );
11825 %}
11826
11827 instruct convL2I_reg( eRegI dst, eRegL src ) %{
11828 match(Set dst (ConvL2I src));
11829 effect( DEF dst, USE src );
11830 format %{ "MOV $dst,$src.lo" %}
11831 ins_encode(enc_CopyL_Lo(dst,src));
11832 ins_pipe( ialu_reg_reg );
11833 %}
11834
11835
11836 instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{
11837 match(Set dst (MoveF2I src));
11838 effect( DEF dst, USE src );
11839 ins_cost(100);
11840 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11841 opcode(0x8B);
11842 ins_encode( OpcP, RegMem(dst,src));
11843 ins_pipe( ialu_reg_mem );
11844 %}
11845
11846 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
11847 predicate(UseSSE==0);
11848 match(Set dst (MoveF2I src));
11849 effect( DEF dst, USE src );
11850
11851 ins_cost(125);
11852 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11853 ins_encode( Pop_Mem_Reg_F(dst, src) );
11854 ins_pipe( fpu_mem_reg );
11855 %}
11856
11857 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{
11858 predicate(UseSSE>=1);
11859 match(Set dst (MoveF2I src));
11860 effect( DEF dst, USE src );
11861
11862 ins_cost(95);
11863 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11864 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst));
11865 ins_pipe( pipe_slow );
11866 %}
11867
11868 instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{
11869 predicate(UseSSE>=2);
11870 match(Set dst (MoveF2I src));
11871 effect( DEF dst, USE src );
11872 ins_cost(85);
11873 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11874 ins_encode( MovX2I_reg(dst, src));
11875 ins_pipe( pipe_slow );
11876 %}
11877
11878 instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{
11879 match(Set dst (MoveI2F src));
11880 effect( DEF dst, USE src );
11881
11882 ins_cost(100);
11883 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11884 opcode(0x89);
11885 ins_encode( OpcPRegSS( dst, src ) );
11886 ins_pipe( ialu_mem_reg );
11887 %}
11888
11889
11890 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
11891 predicate(UseSSE==0);
11892 match(Set dst (MoveI2F src));
11893 effect(DEF dst, USE src);
11894
11895 ins_cost(125);
11896 format %{ "FLD_S $src\n\t"
11897 "FSTP $dst\t# MoveI2F_stack_reg" %}
11898 opcode(0xD9); /* D9 /0, FLD m32real */
11899 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11900 Pop_Reg_F(dst) );
11901 ins_pipe( fpu_reg_mem );
11902 %}
11903
11904 instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{
11905 predicate(UseSSE>=1);
11906 match(Set dst (MoveI2F src));
11907 effect( DEF dst, USE src );
11908
11909 ins_cost(95);
11910 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11911 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
11912 ins_pipe( pipe_slow );
11913 %}
11914
11915 instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{
11916 predicate(UseSSE>=2);
11917 match(Set dst (MoveI2F src));
11918 effect( DEF dst, USE src );
11919
11920 ins_cost(85);
11921 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11922 ins_encode( MovI2X_reg(dst, src) );
11923 ins_pipe( pipe_slow );
11924 %}
11925
11926 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11927 match(Set dst (MoveD2L src));
11928 effect(DEF dst, USE src);
11929
11930 ins_cost(250);
11931 format %{ "MOV $dst.lo,$src\n\t"
11932 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11933 opcode(0x8B, 0x8B);
11934 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11935 ins_pipe( ialu_mem_long_reg );
11936 %}
11937
11938 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11939 predicate(UseSSE<=1);
11940 match(Set dst (MoveD2L src));
11941 effect(DEF dst, USE src);
11942
11943 ins_cost(125);
11944 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11945 ins_encode( Pop_Mem_Reg_D(dst, src) );
11946 ins_pipe( fpu_mem_reg );
11947 %}
11948
11949 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{
11950 predicate(UseSSE>=2);
11951 match(Set dst (MoveD2L src));
11952 effect(DEF dst, USE src);
11953 ins_cost(95);
11954
11955 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11956 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst));
11957 ins_pipe( pipe_slow );
11958 %}
11959
11960 instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{
11961 predicate(UseSSE>=2);
11962 match(Set dst (MoveD2L src));
11963 effect(DEF dst, USE src, TEMP tmp);
11964 ins_cost(85);
11965 format %{ "MOVD $dst.lo,$src\n\t"
11966 "PSHUFLW $tmp,$src,0x4E\n\t"
11967 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11968 ins_encode( MovXD2L_reg(dst, src, tmp) );
11969 ins_pipe( pipe_slow );
11970 %}
11971
11972 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11973 match(Set dst (MoveL2D src));
11974 effect(DEF dst, USE src);
11975
11976 ins_cost(200);
11977 format %{ "MOV $dst,$src.lo\n\t"
11978 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11979 opcode(0x89, 0x89);
11980 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11981 ins_pipe( ialu_mem_long_reg );
11982 %}
11983
11984
11985 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
11986 predicate(UseSSE<=1);
11987 match(Set dst (MoveL2D src));
11988 effect(DEF dst, USE src);
11989 ins_cost(125);
11990
11991 format %{ "FLD_D $src\n\t"
11992 "FSTP $dst\t# MoveL2D_stack_reg" %}
11993 opcode(0xDD); /* DD /0, FLD m64real */
11994 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11995 Pop_Reg_D(dst) );
11996 ins_pipe( fpu_reg_mem );
11997 %}
11998
11999
12000 instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{
12001 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
12002 match(Set dst (MoveL2D src));
12003 effect(DEF dst, USE src);
12004
12005 ins_cost(95);
12006 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12007 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src));
12008 ins_pipe( pipe_slow );
12009 %}
12010
12011 instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{
12012 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
12013 match(Set dst (MoveL2D src));
12014 effect(DEF dst, USE src);
12015
12016 ins_cost(95);
12017 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
12018 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src));
12019 ins_pipe( pipe_slow );
12020 %}
12021
12022 instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{
12023 predicate(UseSSE>=2);
12024 match(Set dst (MoveL2D src));
12025 effect(TEMP dst, USE src, TEMP tmp);
12026 ins_cost(85);
12027 format %{ "MOVD $dst,$src.lo\n\t"
12028 "MOVD $tmp,$src.hi\n\t"
12029 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
12030 ins_encode( MovL2XD_reg(dst, src, tmp) );
12031 ins_pipe( pipe_slow );
12032 %}
12033
12034 // Replicate scalar to packed byte (1 byte) values in xmm
12035 instruct Repl8B_reg(regXD dst, regXD src) %{
12036 predicate(UseSSE>=2);
12037 match(Set dst (Replicate8B src));
12038 format %{ "MOVDQA $dst,$src\n\t"
12039 "PUNPCKLBW $dst,$dst\n\t"
12040 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12041 ins_encode( pshufd_8x8(dst, src));
12042 ins_pipe( pipe_slow );
12043 %}
12044
12045 // Replicate scalar to packed byte (1 byte) values in xmm
12046 instruct Repl8B_eRegI(regXD dst, eRegI src) %{
12047 predicate(UseSSE>=2);
12048 match(Set dst (Replicate8B src));
12049 format %{ "MOVD $dst,$src\n\t"
12050 "PUNPCKLBW $dst,$dst\n\t"
12051 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %}
12052 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst));
12053 ins_pipe( pipe_slow );
12054 %}
12055
12056 // Replicate scalar zero to packed byte (1 byte) values in xmm
12057 instruct Repl8B_immI0(regXD dst, immI0 zero) %{
12058 predicate(UseSSE>=2);
12059 match(Set dst (Replicate8B zero));
12060 format %{ "PXOR $dst,$dst\t! replicate8B" %}
12061 ins_encode( pxor(dst, dst));
12062 ins_pipe( fpu_reg_reg );
12063 %}
12064
12065 // Replicate scalar to packed shore (2 byte) values in xmm
12066 instruct Repl4S_reg(regXD dst, regXD src) %{
12067 predicate(UseSSE>=2);
12068 match(Set dst (Replicate4S src));
12069 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %}
12070 ins_encode( pshufd_4x16(dst, src));
12071 ins_pipe( fpu_reg_reg );
12072 %}
12073
12074 // Replicate scalar to packed shore (2 byte) values in xmm
12075 instruct Repl4S_eRegI(regXD dst, eRegI src) %{
12076 predicate(UseSSE>=2);
12077 match(Set dst (Replicate4S src));
12078 format %{ "MOVD $dst,$src\n\t"
12079 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %}
12080 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12081 ins_pipe( fpu_reg_reg );
12082 %}
12083
12084 // Replicate scalar zero to packed short (2 byte) values in xmm
12085 instruct Repl4S_immI0(regXD dst, immI0 zero) %{
12086 predicate(UseSSE>=2);
12087 match(Set dst (Replicate4S zero));
12088 format %{ "PXOR $dst,$dst\t! replicate4S" %}
12089 ins_encode( pxor(dst, dst));
12090 ins_pipe( fpu_reg_reg );
12091 %}
12092
12093 // Replicate scalar to packed char (2 byte) values in xmm
12094 instruct Repl4C_reg(regXD dst, regXD src) %{
12095 predicate(UseSSE>=2);
12096 match(Set dst (Replicate4C src));
12097 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %}
12098 ins_encode( pshufd_4x16(dst, src));
12099 ins_pipe( fpu_reg_reg );
12100 %}
12101
12102 // Replicate scalar to packed char (2 byte) values in xmm
12103 instruct Repl4C_eRegI(regXD dst, eRegI src) %{
12104 predicate(UseSSE>=2);
12105 match(Set dst (Replicate4C src));
12106 format %{ "MOVD $dst,$src\n\t"
12107 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %}
12108 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst));
12109 ins_pipe( fpu_reg_reg );
12110 %}
12111
12112 // Replicate scalar zero to packed char (2 byte) values in xmm
12113 instruct Repl4C_immI0(regXD dst, immI0 zero) %{
12114 predicate(UseSSE>=2);
12115 match(Set dst (Replicate4C zero));
12116 format %{ "PXOR $dst,$dst\t! replicate4C" %}
12117 ins_encode( pxor(dst, dst));
12118 ins_pipe( fpu_reg_reg );
12119 %}
12120
12121 // Replicate scalar to packed integer (4 byte) values in xmm
12122 instruct Repl2I_reg(regXD dst, regXD src) %{
12123 predicate(UseSSE>=2);
12124 match(Set dst (Replicate2I src));
12125 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %}
12126 ins_encode( pshufd(dst, src, 0x00));
12127 ins_pipe( fpu_reg_reg );
12128 %}
12129
12130 // Replicate scalar to packed integer (4 byte) values in xmm
12131 instruct Repl2I_eRegI(regXD dst, eRegI src) %{
12132 predicate(UseSSE>=2);
12133 match(Set dst (Replicate2I src));
12134 format %{ "MOVD $dst,$src\n\t"
12135 "PSHUFD $dst,$dst,0x00\t! replicate2I" %}
12136 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00));
12137 ins_pipe( fpu_reg_reg );
12138 %}
12139
12140 // Replicate scalar zero to packed integer (2 byte) values in xmm
12141 instruct Repl2I_immI0(regXD dst, immI0 zero) %{
12142 predicate(UseSSE>=2);
12143 match(Set dst (Replicate2I zero));
12144 format %{ "PXOR $dst,$dst\t! replicate2I" %}
12145 ins_encode( pxor(dst, dst));
12146 ins_pipe( fpu_reg_reg );
12147 %}
12148
12149 // Replicate scalar to packed single precision floating point values in xmm
12150 instruct Repl2F_reg(regXD dst, regXD src) %{
12151 predicate(UseSSE>=2);
12152 match(Set dst (Replicate2F src));
12153 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12154 ins_encode( pshufd(dst, src, 0xe0));
12155 ins_pipe( fpu_reg_reg );
12156 %}
12157
12158 // Replicate scalar to packed single precision floating point values in xmm
12159 instruct Repl2F_regX(regXD dst, regX src) %{
12160 predicate(UseSSE>=2);
12161 match(Set dst (Replicate2F src));
12162 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %}
12163 ins_encode( pshufd(dst, src, 0xe0));
12164 ins_pipe( fpu_reg_reg );
12165 %}
12166
12167 // Replicate scalar to packed single precision floating point values in xmm
12168 instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{
12169 predicate(UseSSE>=2);
12170 match(Set dst (Replicate2F zero));
12171 format %{ "PXOR $dst,$dst\t! replicate2F" %}
12172 ins_encode( pxor(dst, dst));
12173 ins_pipe( fpu_reg_reg );
12174 %}
12175
12176 // =======================================================================
12177 // fast clearing of an array
12178
12179 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
12180 match(Set dummy (ClearArray cnt base));
12181 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
12182 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t"
12183 "XOR EAX,EAX\n\t"
12184 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
12185 opcode(0,0x4);
12186 ins_encode( Opcode(0xD1), RegOpc(ECX),
12187 OpcRegReg(0x33,EAX,EAX),
12188 Opcode(0xF3), Opcode(0xAB) );
12189 ins_pipe( pipe_slow );
12190 %}
12191
12192 instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, regXD6 tmp3, regXD7 tmp4, eCXRegI result, eFlagsReg cr) %{
12193 match(Set result (StrComp str1 str2));
12194 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12195 //ins_cost(300);
12196
12197 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX, XMM6, XMM7" %}
12198 ins_encode( enc_String_Compare() );
12199 ins_pipe( pipe_slow );
12200 %}
12201
12202 // fast string equals
12203 instruct string_equals(eDIRegP str1, eSIRegP str2, eBXRegI tmp1, eCXRegI tmp2, regXD6 tmp3, regXD7 tmp4, eAXRegI result, eFlagsReg cr) %{
12204 match(Set result (StrEquals str1 str2));
12205 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12206
12207 format %{ "String Equals $str1,$str2 -> $result // KILL EBX, ECX, EDX, XMM6, XMM7" %}
12208 ins_encode( enc_String_Equals() );
12209 ins_pipe( pipe_slow );
12210 %}
12211
12212 instruct string_indexof(eSIRegP str1, eDIRegP str2, eAXRegI tmp1, eCXRegI tmp2, eDXRegI tmp3, regXD6 tmp4, eBXRegI result, eFlagsReg cr) %{
12213 predicate(UseSSE >=4 && UseSSE42Intrinsics);
12214 match(Set result (StrIndexOf str1 str2));
12215 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12216
12217 format %{ "String IndexOf $str1,$str2 -> $result // KILL EAX, ECX, EDX, XMM6" %}
12218 ins_encode( enc_String_IndexOf() );
12219 ins_pipe( pipe_slow );
12220 %}
12221
12222 // fast array equals
12223 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eBXRegI tmp1, eDXRegI tmp2, regXD6 tmp3, regXD7 tmp4, eAXRegI result, eFlagsReg cr) %{
12224 match(Set result (AryEq ary1 ary2));
12225 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL tmp3, KILL tmp4, KILL cr);
12226 //ins_cost(300);
12227
12228 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EBX, EDX, XMM6, XMM7" %}
12229 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, tmp3, tmp4, result) );
12230 ins_pipe( pipe_slow );
12231 %}
12232
12233 //----------Control Flow Instructions------------------------------------------
12234 // Signed compare Instructions
12235 instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{
12236 match(Set cr (CmpI op1 op2));
12237 effect( DEF cr, USE op1, USE op2 );
12238 format %{ "CMP $op1,$op2" %}
12239 opcode(0x3B); /* Opcode 3B /r */
12240 ins_encode( OpcP, RegReg( op1, op2) );
12241 ins_pipe( ialu_cr_reg_reg );
12242 %}
12243
12244 instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{
12245 match(Set cr (CmpI op1 op2));
12246 effect( DEF cr, USE op1 );
12247 format %{ "CMP $op1,$op2" %}
12248 opcode(0x81,0x07); /* Opcode 81 /7 */
12249 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
12250 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12251 ins_pipe( ialu_cr_reg_imm );
12252 %}
12253
12254 // Cisc-spilled version of cmpI_eReg
12255 instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{
12256 match(Set cr (CmpI op1 (LoadI op2)));
12257
12258 format %{ "CMP $op1,$op2" %}
12259 ins_cost(500);
12260 opcode(0x3B); /* Opcode 3B /r */
12261 ins_encode( OpcP, RegMem( op1, op2) );
12262 ins_pipe( ialu_cr_reg_mem );
12263 %}
12264
12265 instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{
12266 match(Set cr (CmpI src zero));
12267 effect( DEF cr, USE src );
12268
12269 format %{ "TEST $src,$src" %}
12270 opcode(0x85);
12271 ins_encode( OpcP, RegReg( src, src ) );
12272 ins_pipe( ialu_cr_reg_imm );
12273 %}
12274
12275 instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{
12276 match(Set cr (CmpI (AndI src con) zero));
12277
12278 format %{ "TEST $src,$con" %}
12279 opcode(0xF7,0x00);
12280 ins_encode( OpcP, RegOpc(src), Con32(con) );
12281 ins_pipe( ialu_cr_reg_imm );
12282 %}
12283
12284 instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{
12285 match(Set cr (CmpI (AndI src mem) zero));
12286
12287 format %{ "TEST $src,$mem" %}
12288 opcode(0x85);
12289 ins_encode( OpcP, RegMem( src, mem ) );
12290 ins_pipe( ialu_cr_reg_mem );
12291 %}
12292
12293 // Unsigned compare Instructions; really, same as signed except they
12294 // produce an eFlagsRegU instead of eFlagsReg.
12295 instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{
12296 match(Set cr (CmpU op1 op2));
12297
12298 format %{ "CMPu $op1,$op2" %}
12299 opcode(0x3B); /* Opcode 3B /r */
12300 ins_encode( OpcP, RegReg( op1, op2) );
12301 ins_pipe( ialu_cr_reg_reg );
12302 %}
12303
12304 instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{
12305 match(Set cr (CmpU op1 op2));
12306
12307 format %{ "CMPu $op1,$op2" %}
12308 opcode(0x81,0x07); /* Opcode 81 /7 */
12309 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12310 ins_pipe( ialu_cr_reg_imm );
12311 %}
12312
12313 // // Cisc-spilled version of cmpU_eReg
12314 instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{
12315 match(Set cr (CmpU op1 (LoadI op2)));
12316
12317 format %{ "CMPu $op1,$op2" %}
12318 ins_cost(500);
12319 opcode(0x3B); /* Opcode 3B /r */
12320 ins_encode( OpcP, RegMem( op1, op2) );
12321 ins_pipe( ialu_cr_reg_mem );
12322 %}
12323
12324 // // Cisc-spilled version of cmpU_eReg
12325 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{
12326 // match(Set cr (CmpU (LoadI op1) op2));
12327 //
12328 // format %{ "CMPu $op1,$op2" %}
12329 // ins_cost(500);
12330 // opcode(0x39); /* Opcode 39 /r */
12331 // ins_encode( OpcP, RegMem( op1, op2) );
12332 //%}
12333
12334 instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{
12335 match(Set cr (CmpU src zero));
12336
12337 format %{ "TESTu $src,$src" %}
12338 opcode(0x85);
12339 ins_encode( OpcP, RegReg( src, src ) );
12340 ins_pipe( ialu_cr_reg_imm );
12341 %}
12342
12343 // Unsigned pointer compare Instructions
12344 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
12345 match(Set cr (CmpP op1 op2));
12346
12347 format %{ "CMPu $op1,$op2" %}
12348 opcode(0x3B); /* Opcode 3B /r */
12349 ins_encode( OpcP, RegReg( op1, op2) );
12350 ins_pipe( ialu_cr_reg_reg );
12351 %}
12352
12353 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
12354 match(Set cr (CmpP op1 op2));
12355
12356 format %{ "CMPu $op1,$op2" %}
12357 opcode(0x81,0x07); /* Opcode 81 /7 */
12358 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
12359 ins_pipe( ialu_cr_reg_imm );
12360 %}
12361
12362 // // Cisc-spilled version of cmpP_eReg
12363 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
12364 match(Set cr (CmpP op1 (LoadP op2)));
12365
12366 format %{ "CMPu $op1,$op2" %}
12367 ins_cost(500);
12368 opcode(0x3B); /* Opcode 3B /r */
12369 ins_encode( OpcP, RegMem( op1, op2) );
12370 ins_pipe( ialu_cr_reg_mem );
12371 %}
12372
12373 // // Cisc-spilled version of cmpP_eReg
12374 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
12375 // match(Set cr (CmpP (LoadP op1) op2));
12376 //
12377 // format %{ "CMPu $op1,$op2" %}
12378 // ins_cost(500);
12379 // opcode(0x39); /* Opcode 39 /r */
12380 // ins_encode( OpcP, RegMem( op1, op2) );
12381 //%}
12382
12383 // Compare raw pointer (used in out-of-heap check).
12384 // Only works because non-oop pointers must be raw pointers
12385 // and raw pointers have no anti-dependencies.
12386 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
12387 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
12388 match(Set cr (CmpP op1 (LoadP op2)));
12389
12390 format %{ "CMPu $op1,$op2" %}
12391 opcode(0x3B); /* Opcode 3B /r */
12392 ins_encode( OpcP, RegMem( op1, op2) );
12393 ins_pipe( ialu_cr_reg_mem );
12394 %}
12395
12396 //
12397 // This will generate a signed flags result. This should be ok
12398 // since any compare to a zero should be eq/neq.
12399 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
12400 match(Set cr (CmpP src zero));
12401
12402 format %{ "TEST $src,$src" %}
12403 opcode(0x85);
12404 ins_encode( OpcP, RegReg( src, src ) );
12405 ins_pipe( ialu_cr_reg_imm );
12406 %}
12407
12408 // Cisc-spilled version of testP_reg
12409 // This will generate a signed flags result. This should be ok
12410 // since any compare to a zero should be eq/neq.
12411 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
12412 match(Set cr (CmpP (LoadP op) zero));
12413
12414 format %{ "TEST $op,0xFFFFFFFF" %}
12415 ins_cost(500);
12416 opcode(0xF7); /* Opcode F7 /0 */
12417 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
12418 ins_pipe( ialu_cr_reg_imm );
12419 %}
12420
12421 // Yanked all unsigned pointer compare operations.
12422 // Pointer compares are done with CmpP which is already unsigned.
12423
12424 //----------Max and Min--------------------------------------------------------
12425 // Min Instructions
12426 ////
12427 // *** Min and Max using the conditional move are slower than the
12428 // *** branch version on a Pentium III.
12429 // // Conditional move for min
12430 //instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12431 // effect( USE_DEF op2, USE op1, USE cr );
12432 // format %{ "CMOVlt $op2,$op1\t! min" %}
12433 // opcode(0x4C,0x0F);
12434 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12435 // ins_pipe( pipe_cmov_reg );
12436 //%}
12437 //
12438 //// Min Register with Register (P6 version)
12439 //instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{
12440 // predicate(VM_Version::supports_cmov() );
12441 // match(Set op2 (MinI op1 op2));
12442 // ins_cost(200);
12443 // expand %{
12444 // eFlagsReg cr;
12445 // compI_eReg(cr,op1,op2);
12446 // cmovI_reg_lt(op2,op1,cr);
12447 // %}
12448 //%}
12449
12450 // Min Register with Register (generic version)
12451 instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12452 match(Set dst (MinI dst src));
12453 effect(KILL flags);
12454 ins_cost(300);
12455
12456 format %{ "MIN $dst,$src" %}
12457 opcode(0xCC);
12458 ins_encode( min_enc(dst,src) );
12459 ins_pipe( pipe_slow );
12460 %}
12461
12462 // Max Register with Register
12463 // *** Min and Max using the conditional move are slower than the
12464 // *** branch version on a Pentium III.
12465 // // Conditional move for max
12466 //instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{
12467 // effect( USE_DEF op2, USE op1, USE cr );
12468 // format %{ "CMOVgt $op2,$op1\t! max" %}
12469 // opcode(0x4F,0x0F);
12470 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12471 // ins_pipe( pipe_cmov_reg );
12472 //%}
12473 //
12474 // // Max Register with Register (P6 version)
12475 //instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{
12476 // predicate(VM_Version::supports_cmov() );
12477 // match(Set op2 (MaxI op1 op2));
12478 // ins_cost(200);
12479 // expand %{
12480 // eFlagsReg cr;
12481 // compI_eReg(cr,op1,op2);
12482 // cmovI_reg_gt(op2,op1,cr);
12483 // %}
12484 //%}
12485
12486 // Max Register with Register (generic version)
12487 instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{
12488 match(Set dst (MaxI dst src));
12489 effect(KILL flags);
12490 ins_cost(300);
12491
12492 format %{ "MAX $dst,$src" %}
12493 opcode(0xCC);
12494 ins_encode( max_enc(dst,src) );
12495 ins_pipe( pipe_slow );
12496 %}
12497
12498 // ============================================================================
12499 // Branch Instructions
12500 // Jump Table
12501 instruct jumpXtnd(eRegI switch_val) %{
12502 match(Jump switch_val);
12503 ins_cost(350);
12504
12505 format %{ "JMP [table_base](,$switch_val,1)\n\t" %}
12506
12507 ins_encode %{
12508 address table_base = __ address_table_constant(_index2label);
12509
12510 // Jump to Address(table_base + switch_reg)
12511 InternalAddress table(table_base);
12512 Address index(noreg, $switch_val$$Register, Address::times_1);
12513 __ jump(ArrayAddress(table, index));
12514 %}
12515 ins_pc_relative(1);
12516 ins_pipe(pipe_jmp);
12517 %}
12518
12519 // Jump Direct - Label defines a relative address from JMP+1
12520 instruct jmpDir(label labl) %{
12521 match(Goto);
12522 effect(USE labl);
12523
12524 ins_cost(300);
12525 format %{ "JMP $labl" %}
12526 size(5);
12527 opcode(0xE9);
12528 ins_encode( OpcP, Lbl( labl ) );
12529 ins_pipe( pipe_jmp );
12530 ins_pc_relative(1);
12531 %}
12532
12533 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12534 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12535 match(If cop cr);
12536 effect(USE labl);
12537
12538 ins_cost(300);
12539 format %{ "J$cop $labl" %}
12540 size(6);
12541 opcode(0x0F, 0x80);
12542 ins_encode( Jcc( cop, labl) );
12543 ins_pipe( pipe_jcc );
12544 ins_pc_relative(1);
12545 %}
12546
12547 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12548 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12549 match(CountedLoopEnd cop cr);
12550 effect(USE labl);
12551
12552 ins_cost(300);
12553 format %{ "J$cop $labl\t# Loop end" %}
12554 size(6);
12555 opcode(0x0F, 0x80);
12556 ins_encode( Jcc( cop, labl) );
12557 ins_pipe( pipe_jcc );
12558 ins_pc_relative(1);
12559 %}
12560
12561 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12562 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12563 match(CountedLoopEnd cop cmp);
12564 effect(USE labl);
12565
12566 ins_cost(300);
12567 format %{ "J$cop,u $labl\t# Loop end" %}
12568 size(6);
12569 opcode(0x0F, 0x80);
12570 ins_encode( Jcc( cop, labl) );
12571 ins_pipe( pipe_jcc );
12572 ins_pc_relative(1);
12573 %}
12574
12575 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12576 match(CountedLoopEnd cop cmp);
12577 effect(USE labl);
12578
12579 ins_cost(200);
12580 format %{ "J$cop,u $labl\t# Loop end" %}
12581 size(6);
12582 opcode(0x0F, 0x80);
12583 ins_encode( Jcc( cop, labl) );
12584 ins_pipe( pipe_jcc );
12585 ins_pc_relative(1);
12586 %}
12587
12588 // Jump Direct Conditional - using unsigned comparison
12589 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12590 match(If cop cmp);
12591 effect(USE labl);
12592
12593 ins_cost(300);
12594 format %{ "J$cop,u $labl" %}
12595 size(6);
12596 opcode(0x0F, 0x80);
12597 ins_encode(Jcc(cop, labl));
12598 ins_pipe(pipe_jcc);
12599 ins_pc_relative(1);
12600 %}
12601
12602 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12603 match(If cop cmp);
12604 effect(USE labl);
12605
12606 ins_cost(200);
12607 format %{ "J$cop,u $labl" %}
12608 size(6);
12609 opcode(0x0F, 0x80);
12610 ins_encode(Jcc(cop, labl));
12611 ins_pipe(pipe_jcc);
12612 ins_pc_relative(1);
12613 %}
12614
12615 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12616 match(If cop cmp);
12617 effect(USE labl);
12618
12619 ins_cost(200);
12620 format %{ $$template
12621 if ($cop$$cmpcode == Assembler::notEqual) {
12622 $$emit$$"JP,u $labl\n\t"
12623 $$emit$$"J$cop,u $labl"
12624 } else {
12625 $$emit$$"JP,u done\n\t"
12626 $$emit$$"J$cop,u $labl\n\t"
12627 $$emit$$"done:"
12628 }
12629 %}
12630 size(12);
12631 opcode(0x0F, 0x80);
12632 ins_encode %{
12633 Label* l = $labl$$label;
12634 $$$emit8$primary;
12635 emit_cc(cbuf, $secondary, Assembler::parity);
12636 int parity_disp = -1;
12637 bool ok = false;
12638 if ($cop$$cmpcode == Assembler::notEqual) {
12639 // the two jumps 6 bytes apart so the jump distances are too
12640 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12641 } else if ($cop$$cmpcode == Assembler::equal) {
12642 parity_disp = 6;
12643 ok = true;
12644 } else {
12645 ShouldNotReachHere();
12646 }
12647 emit_d32(cbuf, parity_disp);
12648 $$$emit8$primary;
12649 emit_cc(cbuf, $secondary, $cop$$cmpcode);
12650 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 4)) : 0;
12651 emit_d32(cbuf, disp);
12652 %}
12653 ins_pipe(pipe_jcc);
12654 ins_pc_relative(1);
12655 %}
12656
12657 // ============================================================================
12658 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12659 // array for an instance of the superklass. Set a hidden internal cache on a
12660 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12661 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12662 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12663 match(Set result (PartialSubtypeCheck sub super));
12664 effect( KILL rcx, KILL cr );
12665
12666 ins_cost(1100); // slightly larger than the next version
12667 format %{ "CMPL EAX,ESI\n\t"
12668 "JEQ,s hit\n\t"
12669 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12670 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12671 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12672 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12673 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12674 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12675 "hit:\n\t"
12676 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12677 "miss:\t" %}
12678
12679 opcode(0x1); // Force a XOR of EDI
12680 ins_encode( enc_PartialSubtypeCheck() );
12681 ins_pipe( pipe_slow );
12682 %}
12683
12684 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12685 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12686 effect( KILL rcx, KILL result );
12687
12688 ins_cost(1000);
12689 format %{ "CMPL EAX,ESI\n\t"
12690 "JEQ,s miss\t# Actually a hit; we are done.\n\t"
12691 "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12692 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12693 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12694 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12695 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12696 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12697 "miss:\t" %}
12698
12699 opcode(0x0); // No need to XOR EDI
12700 ins_encode( enc_PartialSubtypeCheck() );
12701 ins_pipe( pipe_slow );
12702 %}
12703
12704 // ============================================================================
12705 // Branch Instructions -- short offset versions
12706 //
12707 // These instructions are used to replace jumps of a long offset (the default
12708 // match) with jumps of a shorter offset. These instructions are all tagged
12709 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12710 // match rules in general matching. Instead, the ADLC generates a conversion
12711 // method in the MachNode which can be used to do in-place replacement of the
12712 // long variant with the shorter variant. The compiler will determine if a
12713 // branch can be taken by the is_short_branch_offset() predicate in the machine
12714 // specific code section of the file.
12715
12716 // Jump Direct - Label defines a relative address from JMP+1
12717 instruct jmpDir_short(label labl) %{
12718 match(Goto);
12719 effect(USE labl);
12720
12721 ins_cost(300);
12722 format %{ "JMP,s $labl" %}
12723 size(2);
12724 opcode(0xEB);
12725 ins_encode( OpcP, LblShort( labl ) );
12726 ins_pipe( pipe_jmp );
12727 ins_pc_relative(1);
12728 ins_short_branch(1);
12729 %}
12730
12731 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12732 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12733 match(If cop cr);
12734 effect(USE labl);
12735
12736 ins_cost(300);
12737 format %{ "J$cop,s $labl" %}
12738 size(2);
12739 opcode(0x70);
12740 ins_encode( JccShort( cop, labl) );
12741 ins_pipe( pipe_jcc );
12742 ins_pc_relative(1);
12743 ins_short_branch(1);
12744 %}
12745
12746 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12747 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12748 match(CountedLoopEnd cop cr);
12749 effect(USE labl);
12750
12751 ins_cost(300);
12752 format %{ "J$cop,s $labl\t# Loop end" %}
12753 size(2);
12754 opcode(0x70);
12755 ins_encode( JccShort( cop, labl) );
12756 ins_pipe( pipe_jcc );
12757 ins_pc_relative(1);
12758 ins_short_branch(1);
12759 %}
12760
12761 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12762 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12763 match(CountedLoopEnd cop cmp);
12764 effect(USE labl);
12765
12766 ins_cost(300);
12767 format %{ "J$cop,us $labl\t# Loop end" %}
12768 size(2);
12769 opcode(0x70);
12770 ins_encode( JccShort( cop, labl) );
12771 ins_pipe( pipe_jcc );
12772 ins_pc_relative(1);
12773 ins_short_branch(1);
12774 %}
12775
12776 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12777 match(CountedLoopEnd cop cmp);
12778 effect(USE labl);
12779
12780 ins_cost(300);
12781 format %{ "J$cop,us $labl\t# Loop end" %}
12782 size(2);
12783 opcode(0x70);
12784 ins_encode( JccShort( cop, labl) );
12785 ins_pipe( pipe_jcc );
12786 ins_pc_relative(1);
12787 ins_short_branch(1);
12788 %}
12789
12790 // Jump Direct Conditional - using unsigned comparison
12791 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12792 match(If cop cmp);
12793 effect(USE labl);
12794
12795 ins_cost(300);
12796 format %{ "J$cop,us $labl" %}
12797 size(2);
12798 opcode(0x70);
12799 ins_encode( JccShort( cop, labl) );
12800 ins_pipe( pipe_jcc );
12801 ins_pc_relative(1);
12802 ins_short_branch(1);
12803 %}
12804
12805 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12806 match(If cop cmp);
12807 effect(USE labl);
12808
12809 ins_cost(300);
12810 format %{ "J$cop,us $labl" %}
12811 size(2);
12812 opcode(0x70);
12813 ins_encode( JccShort( cop, labl) );
12814 ins_pipe( pipe_jcc );
12815 ins_pc_relative(1);
12816 ins_short_branch(1);
12817 %}
12818
12819 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12820 match(If cop cmp);
12821 effect(USE labl);
12822
12823 ins_cost(300);
12824 format %{ $$template
12825 if ($cop$$cmpcode == Assembler::notEqual) {
12826 $$emit$$"JP,u,s $labl\n\t"
12827 $$emit$$"J$cop,u,s $labl"
12828 } else {
12829 $$emit$$"JP,u,s done\n\t"
12830 $$emit$$"J$cop,u,s $labl\n\t"
12831 $$emit$$"done:"
12832 }
12833 %}
12834 size(4);
12835 opcode(0x70);
12836 ins_encode %{
12837 Label* l = $labl$$label;
12838 emit_cc(cbuf, $primary, Assembler::parity);
12839 int parity_disp = -1;
12840 if ($cop$$cmpcode == Assembler::notEqual) {
12841 parity_disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12842 } else if ($cop$$cmpcode == Assembler::equal) {
12843 parity_disp = 2;
12844 } else {
12845 ShouldNotReachHere();
12846 }
12847 emit_d8(cbuf, parity_disp);
12848 emit_cc(cbuf, $primary, $cop$$cmpcode);
12849 int disp = l ? (l->loc_pos() - (cbuf.code_size() + 1)) : 0;
12850 emit_d8(cbuf, disp);
12851 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp");
12852 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp");
12853 %}
12854 ins_pipe(pipe_jcc);
12855 ins_pc_relative(1);
12856 ins_short_branch(1);
12857 %}
12858
12859 // ============================================================================
12860 // Long Compare
12861 //
12862 // Currently we hold longs in 2 registers. Comparing such values efficiently
12863 // is tricky. The flavor of compare used depends on whether we are testing
12864 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12865 // The GE test is the negated LT test. The LE test can be had by commuting
12866 // the operands (yielding a GE test) and then negating; negate again for the
12867 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12868 // NE test is negated from that.
12869
12870 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12871 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12872 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12873 // are collapsed internally in the ADLC's dfa-gen code. The match for
12874 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12875 // foo match ends up with the wrong leaf. One fix is to not match both
12876 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12877 // both forms beat the trinary form of long-compare and both are very useful
12878 // on Intel which has so few registers.
12879
12880 // Manifest a CmpL result in an integer register. Very painful.
12881 // This is the test to avoid.
12882 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12883 match(Set dst (CmpL3 src1 src2));
12884 effect( KILL flags );
12885 ins_cost(1000);
12886 format %{ "XOR $dst,$dst\n\t"
12887 "CMP $src1.hi,$src2.hi\n\t"
12888 "JLT,s m_one\n\t"
12889 "JGT,s p_one\n\t"
12890 "CMP $src1.lo,$src2.lo\n\t"
12891 "JB,s m_one\n\t"
12892 "JEQ,s done\n"
12893 "p_one:\tINC $dst\n\t"
12894 "JMP,s done\n"
12895 "m_one:\tDEC $dst\n"
12896 "done:" %}
12897 ins_encode %{
12898 Label p_one, m_one, done;
12899 __ xorptr($dst$$Register, $dst$$Register);
12900 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12901 __ jccb(Assembler::less, m_one);
12902 __ jccb(Assembler::greater, p_one);
12903 __ cmpl($src1$$Register, $src2$$Register);
12904 __ jccb(Assembler::below, m_one);
12905 __ jccb(Assembler::equal, done);
12906 __ bind(p_one);
12907 __ incrementl($dst$$Register);
12908 __ jmpb(done);
12909 __ bind(m_one);
12910 __ decrementl($dst$$Register);
12911 __ bind(done);
12912 %}
12913 ins_pipe( pipe_slow );
12914 %}
12915
12916 //======
12917 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12918 // compares. Can be used for LE or GT compares by reversing arguments.
12919 // NOT GOOD FOR EQ/NE tests.
12920 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12921 match( Set flags (CmpL src zero ));
12922 ins_cost(100);
12923 format %{ "TEST $src.hi,$src.hi" %}
12924 opcode(0x85);
12925 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12926 ins_pipe( ialu_cr_reg_reg );
12927 %}
12928
12929 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12930 // compares. Can be used for LE or GT compares by reversing arguments.
12931 // NOT GOOD FOR EQ/NE tests.
12932 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{
12933 match( Set flags (CmpL src1 src2 ));
12934 effect( TEMP tmp );
12935 ins_cost(300);
12936 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12937 "MOV $tmp,$src1.hi\n\t"
12938 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12939 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12940 ins_pipe( ialu_cr_reg_reg );
12941 %}
12942
12943 // Long compares reg < zero/req OR reg >= zero/req.
12944 // Just a wrapper for a normal branch, plus the predicate test.
12945 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12946 match(If cmp flags);
12947 effect(USE labl);
12948 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12949 expand %{
12950 jmpCon(cmp,flags,labl); // JLT or JGE...
12951 %}
12952 %}
12953
12954 // Compare 2 longs and CMOVE longs.
12955 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12956 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12957 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12958 ins_cost(400);
12959 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12960 "CMOV$cmp $dst.hi,$src.hi" %}
12961 opcode(0x0F,0x40);
12962 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12963 ins_pipe( pipe_cmov_reg_long );
12964 %}
12965
12966 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12967 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12968 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12969 ins_cost(500);
12970 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12971 "CMOV$cmp $dst.hi,$src.hi" %}
12972 opcode(0x0F,0x40);
12973 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12974 ins_pipe( pipe_cmov_reg_long );
12975 %}
12976
12977 // Compare 2 longs and CMOVE ints.
12978 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{
12979 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12980 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12981 ins_cost(200);
12982 format %{ "CMOV$cmp $dst,$src" %}
12983 opcode(0x0F,0x40);
12984 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12985 ins_pipe( pipe_cmov_reg );
12986 %}
12987
12988 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{
12989 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12990 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12991 ins_cost(250);
12992 format %{ "CMOV$cmp $dst,$src" %}
12993 opcode(0x0F,0x40);
12994 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12995 ins_pipe( pipe_cmov_mem );
12996 %}
12997
12998 // Compare 2 longs and CMOVE ints.
12999 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
13000 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
13001 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13002 ins_cost(200);
13003 format %{ "CMOV$cmp $dst,$src" %}
13004 opcode(0x0F,0x40);
13005 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13006 ins_pipe( pipe_cmov_reg );
13007 %}
13008
13009 // Compare 2 longs and CMOVE doubles
13010 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
13011 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13012 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13013 ins_cost(200);
13014 expand %{
13015 fcmovD_regS(cmp,flags,dst,src);
13016 %}
13017 %}
13018
13019 // Compare 2 longs and CMOVE doubles
13020 instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{
13021 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13022 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13023 ins_cost(200);
13024 expand %{
13025 fcmovXD_regS(cmp,flags,dst,src);
13026 %}
13027 %}
13028
13029 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
13030 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13031 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13032 ins_cost(200);
13033 expand %{
13034 fcmovF_regS(cmp,flags,dst,src);
13035 %}
13036 %}
13037
13038 instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{
13039 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
13040 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13041 ins_cost(200);
13042 expand %{
13043 fcmovX_regS(cmp,flags,dst,src);
13044 %}
13045 %}
13046
13047 //======
13048 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13049 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{
13050 match( Set flags (CmpL src zero ));
13051 effect(TEMP tmp);
13052 ins_cost(200);
13053 format %{ "MOV $tmp,$src.lo\n\t"
13054 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
13055 ins_encode( long_cmp_flags0( src, tmp ) );
13056 ins_pipe( ialu_reg_reg_long );
13057 %}
13058
13059 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
13060 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
13061 match( Set flags (CmpL src1 src2 ));
13062 ins_cost(200+300);
13063 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
13064 "JNE,s skip\n\t"
13065 "CMP $src1.hi,$src2.hi\n\t"
13066 "skip:\t" %}
13067 ins_encode( long_cmp_flags1( src1, src2 ) );
13068 ins_pipe( ialu_cr_reg_reg );
13069 %}
13070
13071 // Long compare reg == zero/reg OR reg != zero/reg
13072 // Just a wrapper for a normal branch, plus the predicate test.
13073 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
13074 match(If cmp flags);
13075 effect(USE labl);
13076 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13077 expand %{
13078 jmpCon(cmp,flags,labl); // JEQ or JNE...
13079 %}
13080 %}
13081
13082 // Compare 2 longs and CMOVE longs.
13083 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
13084 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13085 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13086 ins_cost(400);
13087 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13088 "CMOV$cmp $dst.hi,$src.hi" %}
13089 opcode(0x0F,0x40);
13090 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13091 ins_pipe( pipe_cmov_reg_long );
13092 %}
13093
13094 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
13095 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13096 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13097 ins_cost(500);
13098 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13099 "CMOV$cmp $dst.hi,$src.hi" %}
13100 opcode(0x0F,0x40);
13101 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13102 ins_pipe( pipe_cmov_reg_long );
13103 %}
13104
13105 // Compare 2 longs and CMOVE ints.
13106 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{
13107 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13108 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13109 ins_cost(200);
13110 format %{ "CMOV$cmp $dst,$src" %}
13111 opcode(0x0F,0x40);
13112 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13113 ins_pipe( pipe_cmov_reg );
13114 %}
13115
13116 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{
13117 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13118 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13119 ins_cost(250);
13120 format %{ "CMOV$cmp $dst,$src" %}
13121 opcode(0x0F,0x40);
13122 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13123 ins_pipe( pipe_cmov_mem );
13124 %}
13125
13126 // Compare 2 longs and CMOVE ints.
13127 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
13128 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
13129 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13130 ins_cost(200);
13131 format %{ "CMOV$cmp $dst,$src" %}
13132 opcode(0x0F,0x40);
13133 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13134 ins_pipe( pipe_cmov_reg );
13135 %}
13136
13137 // Compare 2 longs and CMOVE doubles
13138 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
13139 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13140 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13141 ins_cost(200);
13142 expand %{
13143 fcmovD_regS(cmp,flags,dst,src);
13144 %}
13145 %}
13146
13147 // Compare 2 longs and CMOVE doubles
13148 instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{
13149 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13150 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13151 ins_cost(200);
13152 expand %{
13153 fcmovXD_regS(cmp,flags,dst,src);
13154 %}
13155 %}
13156
13157 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
13158 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13159 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13160 ins_cost(200);
13161 expand %{
13162 fcmovF_regS(cmp,flags,dst,src);
13163 %}
13164 %}
13165
13166 instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{
13167 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
13168 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13169 ins_cost(200);
13170 expand %{
13171 fcmovX_regS(cmp,flags,dst,src);
13172 %}
13173 %}
13174
13175 //======
13176 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13177 // Same as cmpL_reg_flags_LEGT except must negate src
13178 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{
13179 match( Set flags (CmpL src zero ));
13180 effect( TEMP tmp );
13181 ins_cost(300);
13182 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
13183 "CMP $tmp,$src.lo\n\t"
13184 "SBB $tmp,$src.hi\n\t" %}
13185 ins_encode( long_cmp_flags3(src, tmp) );
13186 ins_pipe( ialu_reg_reg_long );
13187 %}
13188
13189 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
13190 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
13191 // requires a commuted test to get the same result.
13192 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{
13193 match( Set flags (CmpL src1 src2 ));
13194 effect( TEMP tmp );
13195 ins_cost(300);
13196 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
13197 "MOV $tmp,$src2.hi\n\t"
13198 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
13199 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
13200 ins_pipe( ialu_cr_reg_reg );
13201 %}
13202
13203 // Long compares reg < zero/req OR reg >= zero/req.
13204 // Just a wrapper for a normal branch, plus the predicate test
13205 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
13206 match(If cmp flags);
13207 effect(USE labl);
13208 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
13209 ins_cost(300);
13210 expand %{
13211 jmpCon(cmp,flags,labl); // JGT or JLE...
13212 %}
13213 %}
13214
13215 // Compare 2 longs and CMOVE longs.
13216 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
13217 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
13218 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13219 ins_cost(400);
13220 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13221 "CMOV$cmp $dst.hi,$src.hi" %}
13222 opcode(0x0F,0x40);
13223 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
13224 ins_pipe( pipe_cmov_reg_long );
13225 %}
13226
13227 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
13228 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
13229 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13230 ins_cost(500);
13231 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
13232 "CMOV$cmp $dst.hi,$src.hi+4" %}
13233 opcode(0x0F,0x40);
13234 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
13235 ins_pipe( pipe_cmov_reg_long );
13236 %}
13237
13238 // Compare 2 longs and CMOVE ints.
13239 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{
13240 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13241 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
13242 ins_cost(200);
13243 format %{ "CMOV$cmp $dst,$src" %}
13244 opcode(0x0F,0x40);
13245 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13246 ins_pipe( pipe_cmov_reg );
13247 %}
13248
13249 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{
13250 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13251 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
13252 ins_cost(250);
13253 format %{ "CMOV$cmp $dst,$src" %}
13254 opcode(0x0F,0x40);
13255 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
13256 ins_pipe( pipe_cmov_mem );
13257 %}
13258
13259 // Compare 2 longs and CMOVE ptrs.
13260 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
13261 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
13262 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
13263 ins_cost(200);
13264 format %{ "CMOV$cmp $dst,$src" %}
13265 opcode(0x0F,0x40);
13266 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
13267 ins_pipe( pipe_cmov_reg );
13268 %}
13269
13270 // Compare 2 longs and CMOVE doubles
13271 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
13272 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13273 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13274 ins_cost(200);
13275 expand %{
13276 fcmovD_regS(cmp,flags,dst,src);
13277 %}
13278 %}
13279
13280 // Compare 2 longs and CMOVE doubles
13281 instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{
13282 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13283 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
13284 ins_cost(200);
13285 expand %{
13286 fcmovXD_regS(cmp,flags,dst,src);
13287 %}
13288 %}
13289
13290 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13291 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13292 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13293 ins_cost(200);
13294 expand %{
13295 fcmovF_regS(cmp,flags,dst,src);
13296 %}
13297 %}
13298
13299
13300 instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{
13301 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13302 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13303 ins_cost(200);
13304 expand %{
13305 fcmovX_regS(cmp,flags,dst,src);
13306 %}
13307 %}
13308
13309
13310 // ============================================================================
13311 // Procedure Call/Return Instructions
13312 // Call Java Static Instruction
13313 // Note: If this code changes, the corresponding ret_addr_offset() and
13314 // compute_padding() functions will have to be adjusted.
13315 instruct CallStaticJavaDirect(method meth) %{
13316 match(CallStaticJava);
13317 effect(USE meth);
13318
13319 ins_cost(300);
13320 format %{ "CALL,static " %}
13321 opcode(0xE8); /* E8 cd */
13322 ins_encode( pre_call_FPU,
13323 Java_Static_Call( meth ),
13324 call_epilog,
13325 post_call_FPU );
13326 ins_pipe( pipe_slow );
13327 ins_pc_relative(1);
13328 ins_alignment(4);
13329 %}
13330
13331 // Call Java Dynamic Instruction
13332 // Note: If this code changes, the corresponding ret_addr_offset() and
13333 // compute_padding() functions will have to be adjusted.
13334 instruct CallDynamicJavaDirect(method meth) %{
13335 match(CallDynamicJava);
13336 effect(USE meth);
13337
13338 ins_cost(300);
13339 format %{ "MOV EAX,(oop)-1\n\t"
13340 "CALL,dynamic" %}
13341 opcode(0xE8); /* E8 cd */
13342 ins_encode( pre_call_FPU,
13343 Java_Dynamic_Call( meth ),
13344 call_epilog,
13345 post_call_FPU );
13346 ins_pipe( pipe_slow );
13347 ins_pc_relative(1);
13348 ins_alignment(4);
13349 %}
13350
13351 // Call Runtime Instruction
13352 instruct CallRuntimeDirect(method meth) %{
13353 match(CallRuntime );
13354 effect(USE meth);
13355
13356 ins_cost(300);
13357 format %{ "CALL,runtime " %}
13358 opcode(0xE8); /* E8 cd */
13359 // Use FFREEs to clear entries in float stack
13360 ins_encode( pre_call_FPU,
13361 FFree_Float_Stack_All,
13362 Java_To_Runtime( meth ),
13363 post_call_FPU );
13364 ins_pipe( pipe_slow );
13365 ins_pc_relative(1);
13366 %}
13367
13368 // Call runtime without safepoint
13369 instruct CallLeafDirect(method meth) %{
13370 match(CallLeaf);
13371 effect(USE meth);
13372
13373 ins_cost(300);
13374 format %{ "CALL_LEAF,runtime " %}
13375 opcode(0xE8); /* E8 cd */
13376 ins_encode( pre_call_FPU,
13377 FFree_Float_Stack_All,
13378 Java_To_Runtime( meth ),
13379 Verify_FPU_For_Leaf, post_call_FPU );
13380 ins_pipe( pipe_slow );
13381 ins_pc_relative(1);
13382 %}
13383
13384 instruct CallLeafNoFPDirect(method meth) %{
13385 match(CallLeafNoFP);
13386 effect(USE meth);
13387
13388 ins_cost(300);
13389 format %{ "CALL_LEAF_NOFP,runtime " %}
13390 opcode(0xE8); /* E8 cd */
13391 ins_encode(Java_To_Runtime(meth));
13392 ins_pipe( pipe_slow );
13393 ins_pc_relative(1);
13394 %}
13395
13396
13397 // Return Instruction
13398 // Remove the return address & jump to it.
13399 instruct Ret() %{
13400 match(Return);
13401 format %{ "RET" %}
13402 opcode(0xC3);
13403 ins_encode(OpcP);
13404 ins_pipe( pipe_jmp );
13405 %}
13406
13407 // Tail Call; Jump from runtime stub to Java code.
13408 // Also known as an 'interprocedural jump'.
13409 // Target of jump will eventually return to caller.
13410 // TailJump below removes the return address.
13411 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13412 match(TailCall jump_target method_oop );
13413 ins_cost(300);
13414 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13415 opcode(0xFF, 0x4); /* Opcode FF /4 */
13416 ins_encode( OpcP, RegOpc(jump_target) );
13417 ins_pipe( pipe_jmp );
13418 %}
13419
13420
13421 // Tail Jump; remove the return address; jump to target.
13422 // TailCall above leaves the return address around.
13423 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13424 match( TailJump jump_target ex_oop );
13425 ins_cost(300);
13426 format %{ "POP EDX\t# pop return address into dummy\n\t"
13427 "JMP $jump_target " %}
13428 opcode(0xFF, 0x4); /* Opcode FF /4 */
13429 ins_encode( enc_pop_rdx,
13430 OpcP, RegOpc(jump_target) );
13431 ins_pipe( pipe_jmp );
13432 %}
13433
13434 // Create exception oop: created by stack-crawling runtime code.
13435 // Created exception is now available to this handler, and is setup
13436 // just prior to jumping to this handler. No code emitted.
13437 instruct CreateException( eAXRegP ex_oop )
13438 %{
13439 match(Set ex_oop (CreateEx));
13440
13441 size(0);
13442 // use the following format syntax
13443 format %{ "# exception oop is in EAX; no code emitted" %}
13444 ins_encode();
13445 ins_pipe( empty );
13446 %}
13447
13448
13449 // Rethrow exception:
13450 // The exception oop will come in the first argument position.
13451 // Then JUMP (not call) to the rethrow stub code.
13452 instruct RethrowException()
13453 %{
13454 match(Rethrow);
13455
13456 // use the following format syntax
13457 format %{ "JMP rethrow_stub" %}
13458 ins_encode(enc_rethrow);
13459 ins_pipe( pipe_jmp );
13460 %}
13461
13462 // inlined locking and unlocking
13463
13464
13465 instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{
13466 match( Set cr (FastLock object box) );
13467 effect( TEMP tmp, TEMP scr );
13468 ins_cost(300);
13469 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %}
13470 ins_encode( Fast_Lock(object,box,tmp,scr) );
13471 ins_pipe( pipe_slow );
13472 ins_pc_relative(1);
13473 %}
13474
13475 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13476 match( Set cr (FastUnlock object box) );
13477 effect( TEMP tmp );
13478 ins_cost(300);
13479 format %{ "FASTUNLOCK $object, $box, $tmp" %}
13480 ins_encode( Fast_Unlock(object,box,tmp) );
13481 ins_pipe( pipe_slow );
13482 ins_pc_relative(1);
13483 %}
13484
13485
13486
13487 // ============================================================================
13488 // Safepoint Instruction
13489 instruct safePoint_poll(eFlagsReg cr) %{
13490 match(SafePoint);
13491 effect(KILL cr);
13492
13493 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13494 // On SPARC that might be acceptable as we can generate the address with
13495 // just a sethi, saving an or. By polling at offset 0 we can end up
13496 // putting additional pressure on the index-0 in the D$. Because of
13497 // alignment (just like the situation at hand) the lower indices tend
13498 // to see more traffic. It'd be better to change the polling address
13499 // to offset 0 of the last $line in the polling page.
13500
13501 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13502 ins_cost(125);
13503 size(6) ;
13504 ins_encode( Safepoint_Poll() );
13505 ins_pipe( ialu_reg_mem );
13506 %}
13507
13508 //----------PEEPHOLE RULES-----------------------------------------------------
13509 // These must follow all instruction definitions as they use the names
13510 // defined in the instructions definitions.
13511 //
13512 // peepmatch ( root_instr_name [preceeding_instruction]* );
13513 //
13514 // peepconstraint %{
13515 // (instruction_number.operand_name relational_op instruction_number.operand_name
13516 // [, ...] );
13517 // // instruction numbers are zero-based using left to right order in peepmatch
13518 //
13519 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13520 // // provide an instruction_number.operand_name for each operand that appears
13521 // // in the replacement instruction's match rule
13522 //
13523 // ---------VM FLAGS---------------------------------------------------------
13524 //
13525 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13526 //
13527 // Each peephole rule is given an identifying number starting with zero and
13528 // increasing by one in the order seen by the parser. An individual peephole
13529 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13530 // on the command-line.
13531 //
13532 // ---------CURRENT LIMITATIONS----------------------------------------------
13533 //
13534 // Only match adjacent instructions in same basic block
13535 // Only equality constraints
13536 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13537 // Only one replacement instruction
13538 //
13539 // ---------EXAMPLE----------------------------------------------------------
13540 //
13541 // // pertinent parts of existing instructions in architecture description
13542 // instruct movI(eRegI dst, eRegI src) %{
13543 // match(Set dst (CopyI src));
13544 // %}
13545 //
13546 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13547 // match(Set dst (AddI dst src));
13548 // effect(KILL cr);
13549 // %}
13550 //
13551 // // Change (inc mov) to lea
13552 // peephole %{
13553 // // increment preceeded by register-register move
13554 // peepmatch ( incI_eReg movI );
13555 // // require that the destination register of the increment
13556 // // match the destination register of the move
13557 // peepconstraint ( 0.dst == 1.dst );
13558 // // construct a replacement instruction that sets
13559 // // the destination to ( move's source register + one )
13560 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13561 // %}
13562 //
13563 // Implementation no longer uses movX instructions since
13564 // machine-independent system no longer uses CopyX nodes.
13565 //
13566 // peephole %{
13567 // peepmatch ( incI_eReg movI );
13568 // peepconstraint ( 0.dst == 1.dst );
13569 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13570 // %}
13571 //
13572 // peephole %{
13573 // peepmatch ( decI_eReg movI );
13574 // peepconstraint ( 0.dst == 1.dst );
13575 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13576 // %}
13577 //
13578 // peephole %{
13579 // peepmatch ( addI_eReg_imm movI );
13580 // peepconstraint ( 0.dst == 1.dst );
13581 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13582 // %}
13583 //
13584 // peephole %{
13585 // peepmatch ( addP_eReg_imm movP );
13586 // peepconstraint ( 0.dst == 1.dst );
13587 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13588 // %}
13589
13590 // // Change load of spilled value to only a spill
13591 // instruct storeI(memory mem, eRegI src) %{
13592 // match(Set mem (StoreI mem src));
13593 // %}
13594 //
13595 // instruct loadI(eRegI dst, memory mem) %{
13596 // match(Set dst (LoadI mem));
13597 // %}
13598 //
13599 peephole %{
13600 peepmatch ( loadI storeI );
13601 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13602 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13603 %}
13604
13605 //----------SMARTSPILL RULES---------------------------------------------------
13606 // These must follow all instruction definitions as they use the names
13607 // defined in the instructions definitions.