307 #ifdef COMPILER2
308 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
309 // For new Intel cpus do the next optimization:
310 // don't align the beginning of a loop if there are enough instructions
311 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
312 // in current fetch line (OptoLoopAlignment) or the padding
313 // is big (> MaxLoopPad).
314 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
315 // generated NOP instructions. 11 is the largest size of one
316 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
317 MaxLoopPad = 11;
318 }
319 #endif // COMPILER2
320 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
321 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
322 }
323 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
324 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
325 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
326 }
327 }
328 }
329 }
330
331 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
332 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
333
334 // set valid Prefetch instruction
335 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
336 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
337 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
338
339 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
340 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
341 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
342
343 // Allocation prefetch settings
344 intx cache_line_size = L1_data_cache_line_size();
345 if( cache_line_size > AllocatePrefetchStepSize )
346 AllocatePrefetchStepSize = cache_line_size;
347 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
348 AllocatePrefetchLines = 3; // Optimistic value
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307 #ifdef COMPILER2
308 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
309 // For new Intel cpus do the next optimization:
310 // don't align the beginning of a loop if there are enough instructions
311 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
312 // in current fetch line (OptoLoopAlignment) or the padding
313 // is big (> MaxLoopPad).
314 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
315 // generated NOP instructions. 11 is the largest size of one
316 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
317 MaxLoopPad = 11;
318 }
319 #endif // COMPILER2
320 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
321 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
322 }
323 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
324 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
325 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
326 }
327 if(FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
328 UseSSE42Intrinsics = true;
329 }
330 }
331 }
332 }
333
334 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
335 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
336
337 // set valid Prefetch instruction
338 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
339 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
340 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
341
342 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
343 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
344 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
345
346 // Allocation prefetch settings
347 intx cache_line_size = L1_data_cache_line_size();
348 if( cache_line_size > AllocatePrefetchStepSize )
349 AllocatePrefetchStepSize = cache_line_size;
350 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) )
351 AllocatePrefetchLines = 3; // Optimistic value
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