368 #ifdef COMPILER2
369 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
370 // For new Intel cpus do the next optimization:
371 // don't align the beginning of a loop if there are enough instructions
372 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
373 // in current fetch line (OptoLoopAlignment) or the padding
374 // is big (> MaxLoopPad).
375 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
376 // generated NOP instructions. 11 is the largest size of one
377 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
378 MaxLoopPad = 11;
379 }
380 #endif // COMPILER2
381 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
382 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
383 }
384 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
385 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
386 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
387 }
388 }
389 }
390 }
391
392 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
393 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
394
395 // set valid Prefetch instruction
396 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
397 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
398 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
399 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
400
401 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
402 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
403 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
404 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
405
406 // Allocation prefetch settings
407 intx cache_line_size = L1_data_cache_line_size();
408 if( cache_line_size > AllocatePrefetchStepSize )
409 AllocatePrefetchStepSize = cache_line_size;
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368 #ifdef COMPILER2
369 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
370 // For new Intel cpus do the next optimization:
371 // don't align the beginning of a loop if there are enough instructions
372 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
373 // in current fetch line (OptoLoopAlignment) or the padding
374 // is big (> MaxLoopPad).
375 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
376 // generated NOP instructions. 11 is the largest size of one
377 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
378 MaxLoopPad = 11;
379 }
380 #endif // COMPILER2
381 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
382 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
383 }
384 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
385 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
386 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
387 }
388 if(FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
389 UseSSE42Intrinsics = true;
390 }
391 }
392 }
393 }
394
395 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
396 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
397
398 // set valid Prefetch instruction
399 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
400 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
401 if( ReadPrefetchInstr == 3 && !supports_3dnow() ) ReadPrefetchInstr = 0;
402 if( !supports_sse() && supports_3dnow() ) ReadPrefetchInstr = 3;
403
404 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
405 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
406 if( AllocatePrefetchInstr == 3 && !supports_3dnow() ) AllocatePrefetchInstr=0;
407 if( !supports_sse() && supports_3dnow() ) AllocatePrefetchInstr = 3;
408
409 // Allocation prefetch settings
410 intx cache_line_size = L1_data_cache_line_size();
411 if( cache_line_size > AllocatePrefetchStepSize )
412 AllocatePrefetchStepSize = cache_line_size;
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